JP4533432B2 - TLB correlation type branch predictor and method of using the same - Google Patents

Description

  Embodiments of the present invention relate to high performance processors, and more particularly to instruction branch predictors that use translation look-aside buffer (TLB) inputs and variable length global branch history.

As branch instruction rates and instruction pipeline depth both increase, accurate branch prediction is becoming increasingly important to realize the potential performance of superscalar out-of-order processors. . Some branch predictors according to the prior art are implemented as either a branch predictor without a global history or a two- level branch predictor with a global history.

  In some branch predictors, the global history consists of m recent branches and is introduced into an m-bit global shift register in which each bit records whether a branch has been taken or not. Unfortunately, current global shift registers only record a fixed-length global history. However, recent studies have shown that separate instructions from separate programs may be predicted more accurately by using different lengths of global history.

  FIG. 1 shows a circuit block diagram of a branch predictor known in the art. In FIG. 1, m-bit history shift register 110 includes a single-bit shift input of bit m and a single-bit shift output of bit 1, where the single-bit shift input is for each instruction. Receives an indication of whether or not a branch has been taken. For example, the value “1” is used to indicate that a branch has been taken, and the value “0” is used to indicate that a branch has not been taken. The history shift register 110 stores a fixed-length (ie m-bit long) global branch prediction history, shifts out the most significant bit value, ie the first bit value, and the m-bit branch to be stored. Used to output the entire prediction history value.

  In FIG. 1, the history shift register 110 is coupled to an exclusive OR (exclusive OR) gate 120, and the history shift register 110 exclusives the m-bit global branch prediction history value stored in the history shift register 110. Output to the first input of the OR gate 120. The exclusive OR gate 120 is also coupled to the branch address register 130, which outputs the m-bit branch address to the second input of the exclusive OR gate 120. The exclusive OR gate 120 outputs the m-bit global history to the pattern history table 140 when the m-bit branch address input from the branch address register 130 matches the m-bit global history input from the history shift register 110. . The m-bit branch address from branch address register 130 is shifted, expanded, or cut off before being output to match the number of bits with the output from history shift register 110. As a result, the length of the global branch prediction history value may change, but the number of bits of the m-bit branch address bit string output from the branch address register 130 is the bit of the global branch prediction value input from the history shift register 110. Always matches the number.

In FIG. 1, the pattern history table 140 is composed of 2 ^m input items, and each input item in this table includes “local history”. Local history information is typically stored in a 2-bit saturated branch predictor. The m-bit global history output from the exclusive OR gate 120 is used to select one input item from the pattern history table 140, and the selected one input item is used to perform the prediction. It is done. This design uses reliable predictive input items and stores valid history information in which separate branch instructions are correlated with each other.

In FIG. 1, the 2-bit branch predictor holds a 2-bit counter. When it is referenced, it outputs a branch prediction based on its contents. For example, when a 2-bit content of a predictor assigned to the branch (that is, an input item of the pattern history table) is “10”, the branch is predicted to be “taken”. . After a while, the actual instructions are found, and the contents are updated. For example, when the branch is “taken”, “10” is updated to “11”, and when the branch is “not taken”, “10” is updated to “01”. In general, it is predicted that a branch will be taken when the 2-bit counter value is 1/2 of its maximum value, ie 2 ^2-1 = 2 or more. Conversely, when the 2-bit counter value is less than 2, it is predicted that no branch will be taken. In other words, if the 2-bit counter contains either “10” (ie, 2) or “11” (ie, 3), the branch is predicted to be taken and the 2-bit counter is set to “00”. It is predicted that no branch will be taken if it contains either (ie 0) or “01” (ie 1).

Local history implies that the output of a branch depends on its own history, while global history implies that the output of a branch depends on the history of other branches. In the following short code example, if the first branch outputs “done”, the second branch also outputs “done”. Then, this information to maintain with this global history and 2 levels (two-level) branch prediction scheme, two independent bits branch predictor (input field branch d == 0 of pattern history with global history Is adopted corresponding to the above).

If (d == 0) // if d = 0
d = 1; // then set d = 1
If (d == 1) // if d = 1
... // If d = 1 conditional instruction is continued, unfortunately, global history register 110 in FIG. 1 only records a fixed-length global history in any case, so a branch based on a fixed-length global history The prediction is not good enough. For example, branch prediction based on a fixed-length global history does not always accurately identify the preceding branch instruction, even if the preceding branch instruction has a correlation with the current branch instruction. Similarly, with fixed-length global history, not only other uncorrelated branch instructions but also some branch instructions that have correlation in some contexts and other contexts that should have no correlation. It is not always predicted accurately. For example, in the following code example, assume that memory operands X, Y have proximity values due to data locality . The branch predictor may function as described above. However, this relationship is compromised by the loss of data locality .

If (d == 0) // if d = 0
d = X; // then set d = X
If (d == Y) // if d = Y
… // If this case continues with a d = Y conditional instruction, this example shows that global correlation may rely on data locality as well as global history or branch addresses. The loss of data locality as shown in the above example occurs when d is set equal to X in the second instruction and d is not equal to Y in the third instruction . As a result, the conditional instruction with d = Y may not be executed. This can also damage the global history. Therefore, it is desirable to provide branch prediction that avoids the aforementioned defects.

  An object of the present invention is to provide branch prediction that avoids the above-described defects.

Embodiments of the present invention relate to a translation look-aside buffer correlation type branch prediction apparatus and method, which are not limited to the following, but do or do not have a dynamically controlled variable length branch history. in both cases, including the global history translation lookaside buffer correlated branch predictor, and / or two-level (two-level) translation lookaside buffer correlated branch predictor. For example, a processor according to an embodiment of the present invention includes a correlated branch predictor having input wiring from a translation index buffer to a global branch history shift register. The input wiring can indicate a state where a mistake has occurred in the conversion index buffer, and can be used to erase (clear) the contents of the global branch history shift register. Since the global branch history stored in the global branch history shift register can be trained by data locality, clearing the global branch history shift register on a translation index buffer miss is caused by missing data from the translation index buffer It may help to disable global branch history which is broken by the non-locality of data.

FIG. 2 is a circuit block diagram of a transform index buffer correlated branch predictor for a processor according to one embodiment of the present invention. In FIG. 2, the processor 200 has an m-bit history shift register 210. The history shift register 210 includes a first single bit shift input (which may be similar to the single bit shift input of FIG. 1), a second single bit shift input, and the single bit shift output of FIG. The first single bit shift input receives a signal indicating whether a branch has been taken for an individual instruction. The history shift register 210 may be used to store a variable length global branch history for the instruction being executed. In general, the most significant bit having the value “1” is used to specify a reasonable history length. For example, if the most significant “1” is in the fifth bit of the m-bit shift register, the global history can be determined to be m-5 bits long. As a result, the most significant “1” value does not indicate whether a branch has taken place. According to one embodiment of the present invention, "1" value of is used as an enable signal indicating that the branch is made, "0" may be used as a non-enable signal indicating that the branch is not made . The history shift register 210 may be used to store a variable length global branch prediction history having a maximum length of m−1 bits and to output the most significant bit value, ie, the m−1th bit value. Thus, the string “0000... 01” may represent a zero-length global history indicating that the global history has been recently erased from the history shift register 210. Similarly, according to one embodiment of the present invention, a string of “0000 ... 00” may be treated as meaningless because it represents a global history length that does not exist, and a “1X ... Y” string (where X and Y are each (Equal to “0” or “1”) may be treated as including the longest global history length that the register may contain, ie, a length of m−1 bits.

  In FIG. 2, the history shift register 210 is coupled to an exclusive OR (exclusive OR) gate 220, and the history shift register 210 stores the value of the m-bit global branch prediction history stored in the history shift register 210. Output to the first input of the exclusive OR gate 220. Further, the exclusive OR gate 220 is coupled to the branch address register 230, and the branch address register 230 outputs the m-bit branch address to the second input of the exclusive OR gate 220. The exclusive OR gate 220 outputs the m-bit global history to the pattern history table 240 when the m-bit branch address input from the branch address register 230 matches the m-bit global history input from the history shift register 210. To do. The m-bit branch address from branch address register 230 can be shifted, expanded, or clipped before being output to match the number of bits with the output from history shift register 210. As a result, the length of the global branch prediction history value may change, but the number of bits of the m-bit branch address bit string output from the branch address register 230 is generally input from the global branch prediction value from the history shift register 210. Always matches the number of bits.

In FIG. 2, the pattern history table 240 is composed of 2 ^m input items, and each input item in this table may include “local history”. Local history information can generally be stored in a 2-bit saturated branch predictor. The m-bit global history output from the exclusive OR gate 220 may be used to select one input item from the pattern history table 240, and the selected one input item performs prediction. May be used for This design uses reliable predictive input items and stores valid history information in which separate branch instructions are correlated with each other.

In general, in FIG. 2, the history shift register 210 has two exceptions: when the global branch history is to be erased, and as X, Y and Z are equal to “0” or “1”, respectively, Shift as described in FIG. 1 except when the value is equal to “1XYZ...”. First, in FIG. 2, when the history shift register 210 is to be erased, the global branch history string in the history shift register 210 is cleared and set to “0000... 01”. Second, when the history shift register 210 contains a global branch history m-1 bits long, which means that the most significant bit (i.e., bit 1) to "1" is stored in the history shift register 210 The value “1” stored in bit 1 is maintained, and the bit value of bit 2 is shifted out.

The history shift register 210 is also coupled to a latch memory 250, such as a tri-state buffer, for example, which may receive a signal from the translation index buffer “TLB” (not shown) indicating whether there has been a TLB miss . The latch memory 250 may receive and store an m-bit input clear value. This m-bit input clear value includes all “0” s except for the rightmost digit “1”. For example, when m = 16, the 16-bit input clear value is “0000000000000001”. When a TLB miss occurs, an enable signal indicating that a TLB miss has occurred is enabled on the TLB miss line 260 by a TLB (not shown) . When an enable signal indicating that a TLB miss has occurred reaches the latch memory 250, the m-bit input clear value stored in the latch memory 250 is read into the history shift register 210. As a result, the history shift register 210 is “cleared”, and the m-bit value stored in the history shift register 210 at that time is overwritten with the m-bit value from the latch memory 250, for example, “0000000000000001”.

  In FIG. 2, a feedback circuit 270 is coupled to the bit 1 and bit 2 positions of the history shift register 210. The feedback circuit 270 includes an AND gate 280, which is coupled to the history shift register 210 to receive the most significant bit of the output and is also coupled to an OR gate 290. Yes. An OR gate 290 is coupled to the bit 1 and bit 2 positions of the history shift register 210. The feedback circuit 270 may be used to maintain the most significant bit value 1 at the m−1 bit position of the history shift register 210. Specifically, the first input 281 of AND gate 280 is coupled to the output of history shift register 210. The second input 283 of the logical product gate 280 receives the value “1”, and the value is multiplied with the output value of the history shift register 210 to obtain a logical product value. It is output to the first input 291 of 290. The second input 293 of the OR gate 290 is coupled to the position of bit 2 of the history shift register 210 and receives the value therefrom. The output 297 of the logical sum gate 290 is coupled to the position of bit 1 of the history shift register 210, and outputs the logical sum value there. Since the second input 283 of the AND gate 280 has a constant input “1”, only two input combinations (0,1) and (1,1) are possible. That is, only two output values can be taken from the AND gate 280, and if the output value at the m-1 bit position of the history shift register 210 is also "1", "1" is output from the AND gate 280. When the output value at the m−1 bit position of the history shift register 210 is “0”, “0” is output from the AND gate 280. Similarly, OR gate 290 also only has the same two possible output values (ie, “0” or “1”), but the result is a combination of four possible inputs, ie, (0, Resulting from (0), (0,1), (1,0) and (1,1). This is because neither the first input 291 nor the second input 293 to the OR gate 290 is limited to a single value.

表１に示された論理和の論理表に見られるように、取り得る４つの入力値の組み合わせのうちの３つの結果として“1”が出力される。故に、履歴シフトレジスタ210のビット1の値が“1”であるとき論理積ゲート280は常に“1”を出力するので、履歴シフトレジスタ210がＴＬＢミスによってクリアされるまで、フィードバック回路はビット1の位置に値“1”を維持することが分かる。

As can be seen from the logical table of the logical sum shown in Table 1, “1” is output as three results of four possible combinations of input values. Therefore, since the logical product gate 280 always outputs “1” when the value of bit 1 of the history shift register 210 is “1”, the feedback circuit is set to bit 1 until the history shift register 210 is cleared by a TLB miss . It can be seen that the value “1” is maintained at the position of.

  Embodiments of the present invention can be implemented in an out-of-order processor in which a fetch / decode unit obtains an instruction, such as a macro instruction, from a storage location, such as an instruction cache, and decodes the instruction. In a multiple instruction set computer (“CISC”) architecture, a fetch / decode unit may decode complex instructions into one or more microinstructions / operations. Typically, these microinstructions define a load storage architecture, and microinstructions involving memory operations are, for example, reduced instruction set computers (“RISC”) or very long instruction words (Very Long Instruction Words); It can be implemented on other architectures, such as the “VLIW” architecture.

  In a typical RISC architecture, instructions are not decoded into microinstructions. Since the present invention can be executed not only in the CISC architecture but also in the RISC architecture, unless otherwise specified, no distinction is made between instructions and microinstructions / operations, and these are simply referred to as instructions.

  FIG. 3 is a flow diagram of a method according to an embodiment of the invention. In FIG. 3, for example, from the pattern history table 240, a prediction input item is selected using an input from the TLB (310), and whether or not a branch can be made based on the selected prediction input item and the TLB input is dynamically determined. (320). The method receives information about whether a branch has actually been taken (330) and updates the prediction input item based on whether the branch has actually been taken (340). For example, the prediction input item is updated in the pattern history table 240 (340). The global history value indicating whether the branch has actually been taken and the pattern history table 240 are updated in the history shift register 210 based on, for example, whether the branch has actually been taken. Then, the next branch instruction is acquired (360). The method generally ends only when the processor is powered down or no further instruction processing is performed.

  In an alternative embodiment of the present invention, although not explicitly shown, the method of FIG. 3 may wait and wait for further branch instructions if no further branch instructions are obtained immediately.

  Although the method of FIG. 3 refers to a particular order in which the method is performed, it should not be construed as limiting embodiments of the present invention to the above order. The present invention also contemplates embodiments in which some or all of the components of the method may actually be performed in any order. For example, but not limited to, it is intended to be executed in parallel on an out-of-order (“OOO”) processor in whole or in part. Similarly, in the illustrated case, the method of FIG. 3 has been simplified to reflect processing one branch at a time, but the present invention is of course limited by existing data dependencies. However, embodiments in which multiple branches can be processed simultaneously are also contemplated.

The following simplified pseudo code portion illustrates the operation of running a TLB correlated global history branch predictor according to one embodiment of the present invention:
check_and_initialize_predictor (argc, argv, & inTrace, &aPredictor);
while (! inTrace-> EndOfTrace ()) {
aPredictor-> SelectPredictionEntry (inTrace-> GetAddress (),
inTrace-> TLBMissOrNot ()); // TLB information here
bool pr-taken = aPredictor-> prediction (inTrace-> ForwardBranchOrNot ());
// Allow static prediction
aPredictor-> UpdatePredictor (inTrace-> TakenOrNot (), pr ~ taken);
// After finding out the actual branch target,
// Update pattern history table and shift global register
inTrace-> read ~ trace (); // Read next branch instruction in simulation
}
aPredictor->ShowAccuracyo;
For example, in the above pseudo code, it can be seen that the predictor operates to predict the result of each branch included in the instruction during execution of the instruction and update the prediction using it after the actual result is known. The pseudocode example above implies serial execution, but this is merely an example of the overall concept, and of course depends on inter-bound data dependencies. However, other embodiments where parallel execution and / or out-of-order execution of branches are contemplated are also contemplated.

  FIG. 4 is a block diagram of a computer system including one or more processors and memory used in accordance with one embodiment of the present invention. In FIG. 4, computer system 400 includes one or more processors 410 (1) -410 (n) coupled to a processor bus 420, which is coupled to system logic 430. . Each of the one or more processors 410 (1) -410 (n) is an N-bit processor and includes a decoder (not shown) and one or more N-bit registers (not shown). Also good. System logic 430 is coupled to system memory 440 via bus 450 and is coupled to non-volatile memory 470 and one or more peripheral devices 480 (1) -480 (m) via peripheral bus 460. Has been. Peripheral bus 460 may be, for example, one or more peripheral component interconnect (PCI) buses, industry standard architecture, as found in PCI local bus specification version 2.2 (published December 18, 1998). (Industry Standard Architecture; ISA) Bus, Extended to ISA (EISA) bus, USB specification version 1.1 (published on September 23, 1998) in EISA specification version 3.12 (1992) of BCPR Service Represents universal serial bus (USB) and similar peripheral buses. The non-volatile memory 470 may be a static memory device such as a read only memory (ROM) or a flash memory, for example. Peripheral devices 480 (1) to 480 (m) are, for example, mass storage devices such as a keyboard, mouse or other pointing device, hard disk drive, compact disk (CD) drive, optical disk, and digital video disk (DVD) drive Devices, displays, and the like may be included.

  Although the invention has been described in detail, it should be understood that various changes, substitutions and modifications can be made. Further, although software and hardware that control specific functions are described, as is well known in the art, such functions may be implemented using software, hardware, or a combination thereof. Good. Similarly, the term “instructions” in the claims can encompass instructions in a RISC architecture or instructions in a CISC architecture, and instructions used in other computer architectures. Other embodiments will be readily apparent to those skilled in the art and may be made without departing from the spirit and scope of the invention as defined by the claims.

It is a circuit block diagram of the conventional branch predictor. FIG. 3 is a circuit block diagram of a transform index buffer correlated branch predictor for a processor according to one embodiment of the present invention. 2 is a flow diagram of a method according to an embodiment of the invention. 1 is a block diagram of a computer system including one or more processors and memory used in accordance with one embodiment of the present invention.

Claims (25)

The branching results in executing instruction a branch predictor having a branch prediction circuit for predicting in processor, the branch prediction circuit:
A pattern history table storing a plurality of branch prediction input items ; and a history shift register coupled to the pattern history table and coupled to the conversion index buffer via a conversion index buffer miss signal line to output a pattern history value And the pattern history value is used to select one branch prediction input item from the pattern history table to execute branch prediction when the pattern history value matches the branch address, and the history shift register includes the conversion index receiving a miss signal from the buffer miss signal line clears the history shift register itself, history shift register;
A branch predictor. The branch prediction circuit:
A memory coupled to the history shift register and receiving a miss signal from the conversion index buffer miss signal line and passing a clear value to the history shift register;
The branch predictor according to claim 1, further comprising:   The branch predictor of claim 2, wherein the memory has a tristate buffer. The branch prediction circuit:
The history shift is coupled feedback loop register, in accordance with the most significant bit value is shifted out of the history shift register, a feedback loop that maintains the most significant bit value of the history shift register;
The branch predictor according to claim 2, further comprising: 5. The branch predictor according to claim 4, wherein the feedback loop maintains the most significant bit value at 1 when the most significant bit value to be shifted out is 1 .   The branch predictor according to claim 4, wherein the bit position of the most significant value 1 in the history shift register determines the length of the global branch history stored in the history shift register.   The branch predictor according to claim 6, wherein the length of the global branch history stored in the history shift register is determined by the bit position of the most significant value 1. The feedback loop is:
An AND gate coupled to the history shift register and receiving an output bit value of the history shift register and an enable signal; and a first input from the AND gate coupled to the AND gate and the history shift register. An OR gate that receives a value and a second input value that is the value of the second most significant bit from the history shift register and outputs a new bit value to the most significant bit of the history shift register;
The branch predictor according to claim 4, comprising:   2. The branch predictor of claim 1, wherein the history shift register includes a variable length global branch history. Further comprising, the history shift register having m bits, and the exclusive pattern historical values of m bits to the pattern history table branch address register for outputting the branch address to the exclusive OR gates The branch predictor according to claim 1, wherein the branch predictor outputs via a gate.   The branch prediction according to claim 10, wherein the exclusive OR gate receives the m-bit pattern history value and the m-bit branch address value, and outputs the m-bit pattern history value to the pattern history table. vessel. A branch prediction circuit ,
Pattern history table that stores multiple branch prediction input items;
An m-bit history shift register coupled to the pattern history table and the translation index buffer for outputting a pattern history value including a global branch history; and
A branch address register that stores an address of each branch represented in the history shift register and outputs a branch address from the stored branch address group;
A branch prediction circuit having:
Coupled to and said branch prediction circuit; said translation lookaside buffer and coupled to said branch prediction circuitry, the memory provides an input clear value of m bits to the branch prediction circuit receives an indication of a mistake of the translation lookaside buffer A feedback loop that maintains the most significant bit value of the m-bit history shift register when the length of the global branch history is equal to m−1;
A branch predictor having
The m-bit history shift register receives the indication of the miss in the conversion index buffer, stores the m-bit input clear value, and
When the output pattern history value matches the output branch address, it is used to select one branch prediction input item from the pattern history table to perform branch prediction.
Branch predictor.   The branch predictor of claim 12, wherein the memory is coupled to the history shift register.   The branch predictor of claim 12, wherein the memory has a tri-state buffer. The feedback loop is:
An AND gate coupled to the history shift register and receiving an output bit value of the history shift register and an enable signal; and a first input from the AND gate coupled to the AND gate and the history shift register. An OR gate that receives a value and a second input value that is the value of the second most significant bit from the history shift register and outputs a new bit value to the most significant bit of the history shift register;
The branch predictor according to claim 12, comprising: Conversion index buffer;
A branch prediction circuit,
Pattern history table that stores multiple branch prediction input items;
An m-bit history shift register coupled to the pattern history table and the translation index buffer for outputting a pattern history value including a global branch history; and
A branch address register that stores an address of each branch represented in the history shift register and outputs a branch address from the stored branch address group;
A branch prediction circuit having:
Coupled to and said branch prediction circuit; said translation lookaside buffer and coupled to said branch prediction circuitry, the memory provides an input clear value of m bits to the branch prediction circuit receives an indication of a mistake of the translation lookaside buffer A feedback loop that maintains the most significant bit value of the m-bit history shift register when the length of the global branch history is equal to m−1;
A processor having:
The m-bit history shift register receives the indication of the miss in the conversion index buffer, stores the m-bit input clear value, and
When the output pattern history value matches the output branch address, it is used to select one branch prediction input item from the pattern history table to perform branch prediction.
Processor.   The processor of claim 16, wherein the memory is coupled to the history shift register.   The processor of claim 16, wherein the memory comprises a tri-state buffer. The feedback loop is:
An AND gate coupled to the history shift register and receiving an output bit value of the history shift register and an enable signal; and a first input from the AND gate coupled to the AND gate and the history shift register. An OR gate that receives a value and a second input value that is the value of the second most significant bit from the history shift register and outputs a new bit value to the most significant bit of the history shift register;
The processor of claim 16, comprising: memory;
A processor coupled to the memory;
Conversion index buffer; and
A branch prediction circuit,
Pattern history table that stores multiple branch prediction input items;
An m-bit history shift register coupled to the pattern history table and the translation index buffer for outputting a pattern history value including a global branch history; and
A branch address register that stores an address of each branch represented in the history shift register and outputs a branch address from the stored branch address group;
A branch prediction circuit having:
A processor having:
A memory coupled to the conversion index buffer and the branch prediction circuit and receiving an indication of a miss in the conversion index buffer and providing an m-bit input clear value to the branch prediction circuit; and coupled to the branch prediction circuit; A feedback loop that maintains the most significant bit value of the m-bit history shift register when the length of the global branch history is equal to m−1;
A computing system comprising:
The m-bit history shift register receives the indication of the miss in the conversion index buffer, stores the m-bit input clear value, and
When the output pattern history value matches the output branch address, it is used to select one branch prediction input item from the pattern history table to perform branch prediction.
Calculation system.   21. The computing system of claim 20, wherein the memory is coupled to the history shift register. The branch result of a plurality of instructions being executed by a method comprising the step of predicting within processor, wherein said step of predicting the branch outcome of a plurality of instructions being executed in a processor comprising:
Predicting a branch result for each of the plurality of executing instructions;
Maintaining a predicted branch result for each of the plurality of executing instructions; and indicating that a translation index buffer miss has occurred with respect to data associated with one of the plurality of executing instructions Receiving and clearing the global branch history;
Having a method. The step of clearing the global branch history in response to an indication that a mistake has occurred in the translation index buffer comprises:
23. The method of claim 22, comprising replacing the global branch history with a predetermined clear value. The branch result of a plurality of instructions being executed by a machine-readable medium having stored thereon executable instructions that cause a processor for execution of the method with a step to predict,
Wherein the step of the branch results to predict a plurality of instructions being executed:
Predicting a branch result for each of the plurality of executing instructions;
Maintaining a predicted branch result for each of the plurality of executing instructions; and indicating that a translation index buffer miss has occurred with respect to data associated with one of the plurality of executing instructions Receiving and clearing the global branch history;
Having,
Machine-readable medium. Receiving the indication that a mistake has occurred in the translation index buffer and clearing the global branch history ;
Replacing the global branch history with a predetermined clear value ;
25. A machine readable medium according to claim 24.

Images