JP4517413B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a pair of transistors having the same characteristics and the same size are provided in a symmetrical arrangement on a semiconductor substrate.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a semiconductor device constituting an analog circuit, for example, a device in which a pair of transistors (pair transistors) having the same characteristics for constituting a mirror circuit or the like are provided symmetrically on a semiconductor substrate is known.
In such an element, it is necessary that the transistors constituting the pair operate with the same characteristics. In particular, in an analog circuit, the characteristics of each transistor must match in absolute value, and the characteristics of each transistor must be matched exactly.
[0003]
FIG. 3 is a partial plan view showing an example of arrangement of the pair transistors on the semiconductor substrate.
As shown in the figure, two field effect transistors 2A, 2B constituting a pair are arranged adjacent to each other via a common source 2C, and drains 2D, 2E that are symmetrical to each other outside each field effect transistor 2A, 2B. have.
Similarly, two field effect transistors 4A and 4B constituting another pair are disposed adjacent to each other via a common source 4C, and symmetrical drains 4D and 4D are disposed outside the field effect transistors 4A and 4B. 4E.
Further, other field effect transistors 6A, 6B, 6C and other elements are arranged around each pair transistor 2A, 2B, 4A, 4B.
[0004]
[Problems to be solved by the invention]
However, since various elements are densely arranged on the semiconductor substrate on which the pair transistors as described above are mounted, due to the difference in density of elements arranged around the pair transistors, process variations, etc. The characteristics were adversely affected, and proper symmetry characteristics could not be obtained, resulting in failure.
In particular, a transistor with a large area that is not individually checked by a 1PC (Pellet Check) monitor is easily affected by adjacent elements in the same chip, and monitoring and control thereof are difficult.
[0005]
FIG. 4 is an explanatory diagram showing an actual measurement example of the difference in characteristics of transistors at each part in the semiconductor wafer.
As shown in FIG. 4B, the positions of 1 to 9 in the vertical direction and 11 to 19 in the horizontal direction of the surface of the semiconductor wafer are taken. As shown in FIG. The value of NMVth (threshold voltage of n-type transistor) of the large area transistor was measured.
The 1PC transistor has a channel width W = 10 μm and a channel length L = 0.5 μm, and each measured value is indicated by a square point. In contrast, a large channel transistor has a channel width W = 10 μm and a channel length L = 6.0 μm, and each measurement value is indicated by a round dot.
[0006]
As shown in the figure, the NMVth of the large area transistor tends to vary slightly in the vertical direction of the semiconductor wafer at the top and bottom. Normally, NMVth depends on the channel length from L = 0.5 μm → 6.0 μm, and ΔVth to 0.1 Vth, so the upper and lower portions of the semiconductor wafer are considered abnormal.
Although parameters that cause Vth abnormalities at the top and bottom of the semiconductor wafer have not been grasped, it is suggested that for a large-area transistor, Vth shifts by 0.1 V with subtle parameters.
[0007]
Therefore, an object of the present invention is to provide a semiconductor device capable of matching the characteristics of a pair transistor.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a pair of transistors disposed on a semiconductor substrate, symmetrical in the channel length direction, having the same characteristics and the same size, and the pair of transistors on the semiconductor substrate. They are arranged symmetrically with respect to said pair of transistors in the peripheral portion, and a dummy pattern for the element pattern arrangement in the peripheral portion of the transistor of the one pair symmetrically. In the semiconductor device of the present invention, since the element pattern arrangement in the peripheral part of each transistor constituting the pair is symmetrical, the influence due to the density difference of the element arrangement pattern in the periphery of each transistor is eliminated, and the characteristics of each transistor Can be kept the same.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor device according to the present invention will be described below.
FIG. 1 is a plan view showing a first example of a semiconductor device according to the present invention.
In the semiconductor device of this example, a pair of field effect transistors 20A and 20B having the same characteristics and the same size are arranged on a semiconductor substrate 10 in a symmetrical shape in the channel length direction to constitute a pair transistor as an analog element. is there.
Each field effect transistor 20A, 20B is a large-area transistor, and has a channel width W = 10 μm and a channel length L = 6.0 μm.
[0010]
The field effect transistors 20A and 20B are arranged adjacent to each other via a common source 20C, and have drains 20D and 20E that are symmetrical to each other outside the channel length direction of the field effect transistors 20A and 20B. ing.
The main body of each field effect transistor 20A, 20B is formed by a laminated structure such as a polysilicon film or a silicon oxide film, and gates 20F, 20G are provided on the upper part thereof.
[0011]
Also, dummy conductive layers 22A and 22B as dummy patterns symmetrical to each other are provided in the vicinity of the outside of the drains 20D and 20E of the field effect transistors 20A and 20B.
The dummy conductive layers 22A and 22B are formed of a polysilicon film or the like, and are formed in parallel with the drains 20D and 20E.
In the semiconductor device of this example, the dummy conductive layers 22A and 22B having symmetrical shapes are provided in the vicinity of the outside of the drains 20D and 20E of the field effect transistors 20A and 20B arranged adjacent to each other via the common source 20C. Therefore, it is possible to eliminate the influence due to the density difference of the element arrangement pattern around the field effect transistors 20A and 20B, and to keep the characteristics of the field effect transistors 20A and 20B the same.
[0012]
As a result, LDD. ET (Lightly Doped Drain. Etching), LDD. II (LDD. Ion Implantation), S / D. Ox (Source / Drain. Oxidtion), S / D. It is possible to equalize the influence of pattern density differences such as II and autodope.
Therefore, the characteristics of the field effect transistors 20A and 20B can be made equal, and a good function as a pair transistor constituting an analog element can be obtained.
[0013]
In the example shown in FIG. 1, the dummy conductive layers 22A and 22B are provided symmetrically in the channel length direction of the field effect transistors 20A and 20B. However, the field effect transistors 20A and 20B are surrounded by the dummy conductive layers 22A and 20B. The dummy conductive layer may be provided in a symmetrical shape in the long direction and the channel width direction.
In the example shown in FIG. 1, conductive layers 22A and 22B made of a polysilicon film or the like are provided as dummy patterns. However, as such a dummy pattern, an insulating layer made of, for example, a silicon oxide film or the like is used instead of the conductive layer. It may be used.
In the example shown in FIG. 1, the configuration in which each field effect transistor 20A, 20B has the common source 20C has been described, but the source may be individually provided.
Further, in the example shown in FIG. 1, the pair transistor is configured by the field effect transistor, but another transistor may be used.
[0014]
FIG. 2 is a plan view showing a second example of the semiconductor device according to the present invention.
The semiconductor device of this example is configured by arranging a pair of field effect transistors 30A and 30B having the same characteristics and the same size on a semiconductor substrate 12 in a symmetrical shape in the channel length direction, thereby forming a pair transistor as an analog element. is there.
Each field effect transistor 30A, 30B is a large area transistor and has a channel width W = 10 μm and a channel length L = 6.0 μm.
[0015]
The field effect transistors 30A and 30B are arranged adjacent to each other via a common source 30C, and have drains 30D and 30E that are symmetrical to each other outside the channel length direction of the field effect transistors 30A and 30B. ing.
Further, the main body of each field effect transistor 30A, 30B is formed by a laminated structure such as a polysilicon film or a silicon oxide film, and gates 30F, 30G are provided thereon.
[0016]
In this example, a space 32 having a predetermined size or more is provided in the periphery of each field effect transistor 30A, 30B, and other elements 34A, 34B, 34C, etc. are provided outside thereof.
The space 32 has a substantially uniform width (for example, 10 μm) over the entire periphery of each field effect transistor 30A, 30B.
In the semiconductor device of this example, the space 32 having a predetermined size or more is provided around each field effect transistor 30A, 30B arranged adjacent to each other via the common source 30C, and thus each field effect transistor 30A, 30B. Thus, the influence of the density difference of the element arrangement pattern in the periphery of the transistor can be eliminated, and the characteristics of the field effect transistors 30A and 30B can be kept the same.
[0017]
As a result, LDD. ET, LDD. II, S / D. Ox, S / D. It is possible to equalize the influence of pattern density differences such as II and autodope.
Therefore, the characteristics of the field effect transistors 30A and 30B can be made equal, and a favorable function as a pair transistor constituting an analog element can be obtained.
[0018]
In the example illustrated in FIG. 2, the configuration in which the field effect transistors 20A and 20B have the common source 20C has been described, but the source may be individually provided.
Further, in the example shown in FIG. 2, the pair transistor is configured by the field effect transistor, but another transistor may be used.
[0019]
【The invention's effect】
As described above, in the semiconductor device of the present invention, in the semiconductor device in which a pair of transistors having the same characteristics and the same size are arranged symmetrically in the channel length direction on the semiconductor substrate, the element pattern in the peripheral part of each transistor The arrangement was symmetrical.
Therefore, according to the present invention, since the element pattern arrangement in the peripheral part of each transistor constituting the pair is made symmetrical, the influence due to the density difference of the element arrangement pattern in the periphery of each transistor is eliminated, and the characteristics of each transistor Can be kept the same, and for example, a good function as a pair transistor constituting an analog element can be obtained.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention;
FIG. 2 is a plan view showing a second embodiment of a semiconductor device according to the present invention.
FIG. 3 is a plan view showing an example of an element arrangement in a semiconductor device.
FIG. 4 is an explanatory diagram showing an example of actual measurement of a difference in characteristics of a transistor at each part in a semiconductor wafer.
[Explanation of symbols]
10, 12 ... Semiconductor substrate, 20A, 20B, 30A, 30B ... Field effect transistor, 20C, 30C ... Common source, 20D, 20E, 30D, 30E ... Drain, 20F, 20G, 30F, 30G ... Gate 22A, 22B ... dummy conductive layer, 32A, 32B, 32C, 32D ... space, 34A, 34B, 34C, 34D ... peripheral elements.

Claims (10)

A pair of transistors disposed on a semiconductor substrate, symmetrical in the channel length direction, having the same characteristics and the same size;
Wherein arranged symmetrically with respect to said pair of transistors in the peripheral portion of the pair of transistors in a semiconductor substrate, a semiconductor device having a dummy pattern for the element pattern disposed symmetrically in the peripheral portion of the transistor of the one pair .   The semiconductor device according to claim 1, wherein the dummy pattern is formed so as to surround each of the transistors.   The semiconductor device according to claim 1, wherein the dummy patterns are formed symmetrically with respect to each other in the vicinity of the outside in the channel length direction of each transistor.   2. The semiconductor device according to claim 1, wherein each of the transistors is disposed adjacent to each other through a common source, and has drains that are symmetrical to each other outside the transistors.   5. The semiconductor device according to claim 4, wherein the dummy pattern is formed in the vicinity of the outside of each drain in parallel with each drain.   The semiconductor device according to claim 1, wherein the dummy pattern is formed of a conductive layer.   The semiconductor device according to claim 6, wherein the conductive layer is formed of a polysilicon element.   The semiconductor device according to claim 1, wherein the dummy pattern is formed of an insulating layer.   9. The semiconductor device according to claim 8, wherein the insulating layer is formed of a silicon oxide element.   2. The semiconductor device according to claim 1, wherein each of the transistors constitutes an analog element.

Images