JP4514867B2 - Thin film transistor, method for manufacturing the same, and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit including an active matrix field effect thin film transistor (hereinafter referred to as a thin film transistor) on a substrate having an insulating surface, and a manufacturing method thereof. A semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device, in which an image display region and a drive circuit for performing image display are provided on the same substrate. The semiconductor device includes in its category the electro-optical device and an electronic device in which the electro-optical device is mounted.
[0002]
[Prior art]
A TFT having a crystalline silicon semiconductor layer represented by polycrystalline silicon (polysilicon), microcrystalline silicon, and single crystalline silicon (hereinafter referred to as crystalline silicon TFT) is a TFT having an amorphous silicon semiconductor layer (hereinafter referred to as crystalline silicon TFT). The field effect mobility is higher than that of an amorphous silicon TFT, and high-speed operation is possible. For this reason, it was inappropriate to use an amorphous silicon TFT for manufacturing a drive circuit for an image area that requires high-speed operation. However, if a crystalline silicon TFT is used, it can be manufactured on the same substrate as the image display area. became.
[0003]
As a technique for obtaining a crystalline film, there is a technique described in JP-A-10-303430. The technology disclosed in this publication performs gettering by introducing a metal that promotes crystallization, causing crystal growth, and moving the metal that promotes crystallization to a region doped with an element typified by P. It is. In this technique, in crystallization of an amorphous film, the crystallization temperature is lowered by the action of a metal that promotes crystallization, and the time required for crystallization is reduced. The metal that promotes crystallization is removed from the crystalline film so as not to adversely affect the characteristics and reliability, or is reduced to such an extent that the metal is not adversely affected. By using this technique, a metal that promotes crystallization can be gettered by low-temperature heat treatment, and the characteristics of the low-temperature process can be utilized in manufacturing a semiconductor device.
[0004]
As a further development of the above-described technique, there is a method of performing gettering by doping an element typified by P into a source / drain region of a transistor. In this method, since the region for removing or reducing the metal that promotes crystallization by gettering is only the region where the channel of the transistor is formed, the heat treatment time required for gettering can be shortened. Moreover, the process for gettering can be reduced by doping an element typified by P when forming the source / drain. As for the p-channel transistor, gettering is performed by doping an element typified by P into the source / drain region. At this time, the source / drain is formed by setting the concentration of an element typified by P doped in the active layer to be equal to or lower than the concentration of the impurity element imparting P-type. These are techniques described in JP-A-10-242475 and JP-A-10-335672.
[0005]
[Problems to be solved by the invention]
When gettering a metal that promotes crystallization using an element typified by P In general, a metal that promotes crystallization is removed from a region to which an element typified by P is added and a metal that promotes crystallization. It is thought that many segregates near the interface with the region to be reduced. Therefore, in the method in which the source / drain region is doped with an element typified by P, the metal that promotes crystallization is easily segregated in the vicinity of the junction region of the transistor. If the metal that promotes crystallization is present in the depletion layer region of the transistor, there is a concern that unnecessary impurity levels may be formed and the transistor characteristics may be adversely affected. It is preferable that no impurity element exists. It is a problem to be solved by the present invention to remove or reduce the impurity element in the vicinity of the junction of the transistor.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the inventor of the present application has a gradient in the concentration distribution of an element typified by P in a region where a source / drain doped with an element typified by P is formed in order to perform gettering. We thought to move the metal that promotes crystallization by attaching. That is, it is represented by P in the source / drain region and away from the junction region with respect to the concentration of the element represented by P in the region where the source / drain is formed and near the junction region. We thought that the metal that promotes crystallization in the vicinity of the source / drain can be moved to a region where there is a lot of P away from the junction region by increasing the concentration of the element.
[0007]
However, for that purpose, in the region where the source / drain doped with the element represented by P is formed, the metal that promotes crystallization moves when the concentration distribution of the element represented by P has a gradient. It was necessary to check whether or not. Figure 2 shows the amorphous silicon film deposited on the glass substrate, introduced metal Ni that promotes crystallization, and heat-treated at 550 ° C for 8 hours to crystallize, and P with a gettering effect of 10 kV 3 is a SIMS analysis result showing the P concentration and Ni concentration of a sample that was ion-implanted at an acceleration voltage of and subjected to heat treatment for gettering at 600 ° C. for 12 hours. When P is ion-implanted, P takes a concentration distribution described by a Gaussian function in the depth direction. Therefore, it was possible to investigate the movement of Ni in the polycrystalline silicon film in which the P concentration gradient was formed in the depth direction. In addition, the Ni concentration distribution in the film of the sample not subjected to gettering treatment for reference is almost uniform and 3 × 10 ¹⁸ atoms / cm ^Three Met.
[0008]
As can be seen from FIG. 2, Ni is present at a high depth in the P concentration, and comparison with a sample not subjected to gettering treatment shows that Ni has moved to a depth at which P is high. Ni moves a lot in the region where P is highly concentrated by heat treatment for gettering, and the shape of the Ni profile in the polycrystalline silicon film follows the shape of the P profile. That is, it was found that Ni can be removed or reduced effectively even in the region where the source / drain doped with P is formed. Therefore, it is possible to effectively remove or reduce the metal that promotes crystallization in the vicinity of the source / drain junction region by using the concentration gradient of an element typified by P. In this SIMS analysis, we investigated the movement of Ni in the depth direction. When an element represented by P has a concentration gradient parallel to the semiconductor film, Ni moves in parallel to the semiconductor film. We can conclude that
[0009]
The configuration of the present invention will be described with reference to FIG. The substrate 103 is a glass substrate or a quartz substrate. A channel forming region 107 is formed on the substrate 103, first impurity regions 101 and 111 are formed outside the channel forming region 107, and second impurity regions 102 and 112 are formed outside the channel forming region 107. An impurity element of one conductivity type is introduced into the first impurity regions 101 and 111 at a first concentration, and an impurity element of the same type as that of the conductivity type is introduced into the second impurity regions 102 and 112 at a second concentration. It is assumed that the channel formation region is crystallized using metal Ni that promotes crystallization. An insulating film 104 is formed on the channel formation region, and a gate electrode 105 is formed to face the channel formation region 107 with the insulating film 104 interposed therebetween. A region obtained by combining the first impurity regions 101 and 111 and the second impurity regions 102 and 112 becomes the whole or a part of the source / drain region. The insulating film 104 may also be formed on the source / drain regions. When the LDD region and the offset region are formed, the first impurity regions 101 and 111 and the second impurity region are sandwiched between the channel formation region and the impurity region so as to sandwich the LDD region and the offset region. 102, 112 are formed.
[0010]
The configuration of the present invention is characterized in that the second concentration in the second impurity regions 102 and 112 is higher than the first concentration in the first impurity regions 101 and 111. In the present invention, specifically, the first concentration is 1 × 10 5. ¹⁹ atoms / cm ^Three ~ 5 × 10 ^{twenty one} atoms / cm ^Three And the second density is 1.2 to 1000 times the first density. The configuration of the present invention may be configured on both sides of the channel formation region as shown in FIG. 1, or may be configured on only one side. That is, for example, when it is desired to getter impurities near the junction of the drain region, the first impurity region and the second impurity region may be formed only on the drain side.
[0011]
In another configuration of the present invention, an impurity element of one conductivity type is introduced into the first impurity regions 101 and 111 at a first concentration, and the second impurity region is introduced into the first impurity region. An impurity element giving the same conductivity type as the impurity element is introduced at the first concentration, and an impurity element having a conductivity type opposite to the one conductivity type is introduced at a second concentration. This configuration is characterized in that the first concentration is larger than the second concentration. The opposite conductivity type impurity element introduced into the second impurity region is introduced not for source / drain formation but for gettering. In the present invention, specifically, the second concentration is 1 × 10 ¹⁹ atoms / cm ^Three ~ 1 × 10 ^{twenty two} atoms / cm ^Three It is characterized by being. For example, in a P-type TFT, if P, which has a large effect of gettering Ni, is introduced into the second impurity region, Ni can be effectively gettered from the vicinity of the junction region. As another example, in an N-type TFT, if B, which has a large effect of gettering Fe, is introduced into the second impurity region, Fe can be effectively gettered from the vicinity of the junction region.
[0012]
Still another configuration of the present invention will be described with reference to FIG. The substrate 303 is a glass substrate or a quartz substrate. A channel formation region 307 and third impurity regions 301 and 311 are formed outside the channel formation region 307 on the substrate 303. According to another configuration of the present invention, the third impurity region includes an impurity element of one conductivity type, and the third concentration is increased as the impurity element concentration contained in the third impurity region is further away from the channel region. To a fourth concentration continuously. The channel formation region is crystallized using metal Ni that promotes crystallization. An insulating film 304 is formed on the channel formation region, and the channel formation is performed via the insulation film 304. A gate electrode 305 is formed facing the region 307. The insulating film 304 may also be formed on the source / drain regions. In addition, an LDD region or an offset region may be formed between the channel formation region and the third impurity region.
[0013]
In another configuration of the present invention, specifically, the third concentration is 1 × 10 ¹⁹ atoms / cm ^Three ~ 5 × 10 ^{twenty one} atoms / cm ^Three The fourth density is 1.2 to 1000 times the third density. The configuration of the present invention may be configured on both sides of the channel formation region as shown in FIG. 3, or may be configured on only one side. That is, for example, when it is desired to getter impurities near the junction of the drain region, the third impurity region may be formed only on the drain side.
[0014]
A strict explanation will be given regarding the concentration. In general, when impurities are introduced by thermal diffusion or ion implantation of impurities, the concentration of impurities in the active layer varies depending on the depth in the active layer and has a non-uniform concentration distribution. Here, the concentration is a value obtained by averaging the concentration distribution in the depth direction in the active layer.
[0015]
The above three configurations describe a method for removing or reducing Ni in the vicinity of the junction by crystallization of the channel formation region using metal Ni that promotes crystallization. It can also be applied to gettering of other metals that promote crystallization, and does not use a metal that promotes crystallization. The present invention is also applied to gettering of an impurity element forming a deep level in the transistor described above. That is, 3d transition metals (FE, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au) can be removed or reduced from the vicinity of the junction region of the transistor.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The present invention can be implemented with respect to an element forming technique of a semiconductor thin film device.
[0017]
The present invention can be implemented by introducing an impurity element imparting one conductivity type into the source / drain region and forming its concentration distribution. This concentration distribution may change continuously or discontinuously. Hereinafter, a method for forming the concentration distribution will be described.
[0018]
First, a method of performing a doping process a plurality of times using a resist mask, an oxide film mask, or the like, or a gate metal mask can be considered. This method increases the number of manufacturing steps, but if the impurity element imparting the one conductivity type is doped in the source / drain region after forming the contact holes, gettering in the vicinity of the junction can be performed without increasing the number of manufacturing steps.
[0019]
As another method, there is a method in which an oxide film mask having a step or inclination is formed on the source / drain, and an impurity element giving the one conductivity type is ion-implanted. This utilizes the difference in concentration distribution of implanted ions in the depth direction, and only one doping step is required. This method will be described later in Examples.
[0020]
[Embodiment 1]
[0021]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for removing the metal Ni that promotes crystallization from the vicinity of the junction using the present invention will be described in the order of steps, taking as an example the case where a pixel matrix circuit and a TFT of a control circuit provided around the pixel matrix circuit are manufactured simultaneously. However, in order to simplify the description, a CMOS circuit that is a basic circuit such as a shift register circuit and a buffer circuit is shown in the control circuit, and an n-channel TFT that forms a sampling circuit.
[0022]
In FIG. 4A, a low alkali glass substrate or a quartz substrate can be used as the substrate 201. In this embodiment, a low alkali glass substrate is used, but when glass is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. In addition, a substrate in which an insulating film is formed on the surface of a silicon substrate, a metal substrate, or a stainless steel substrate may be used. If heat resistance permits, a plastic substrate can be used. In order to prevent impurity diffusion from the substrate 201, a base film 202 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 201 on which a TFT is formed, for example, SiH. _Four , NH _Three , N ₂ A silicon oxynitride film made of O is formed by plasma CVD to 100 nm, and similarly SiH _Four , N ₂ A silicon oxynitride film formed from O is stacked to a thickness of 200 nm.
[0023]
Next, the semiconductor film 203a having an amorphous structure is formed to a thickness of 20 to 150 nm, preferably 30 to 80 nm by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Further, since the base film 202 and the amorphous silicon film 203a can be formed by the same film forming method, both may be continuously formed. In this way, after the formation of the base film, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics of TFTs to be manufactured and fluctuations in threshold voltage. (Fig. 2 (A))
[0024]
Then, using a known crystallization technique, the amorphous silicon film 203a is crystallized to form a crystallized silicon film 203b. As a crystallization technique, for example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied, but here, crystallization is promoted according to the technique disclosed in Japanese Patent Laid-Open No. 7-130652. A crystalline silicon film 203b is formed by a crystallization method using metal Ni. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed at 400 to 500 ° C. for about 1 hour, and the amount of hydrogen contained is reduced to 5 atom% or less for crystallization. desirable. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film is densified. Therefore, the thickness of the produced crystalline silicon film is the thickness of the amorphous silicon film before crystallization (this embodiment Is about 1 to 15% less than 55 nm. (Fig. 2 (B))
[0025]
Then, the crystalline silicon film 203b is divided into island shapes, and island-shaped semiconductor layers 204 to 207 are formed. Thereafter, a mask layer 208 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD or sputtering. (Figure 4 (C))
[0026]
Thereafter, a resist mask 209 is provided, and 1 × 10 6 is used to control the threshold voltage over the entire surface of the island-like semiconductor layers 205 to 207 forming the n-channel TFT. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three B, which is an impurity forming the p-type semiconductor layer, is added at a moderate concentration. B may be added by an ion doping method or may be added at the same time when an amorphous silicon film is formed. The addition of B here is not always necessary, but the semiconductor layers 210 to 212 to which B is added are preferably formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. (Fig. 4 (D))
[0027]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element that forms the n-type semiconductor layer is selectively added to the island-like semiconductor layers 210 and 211. Therefore, resist masks 213 to 216 are formed in advance. P or As may be used as the n-type impurity element. Here, in order to add P, phosphine (PH _Three ) Shall be applied. The impurity concentration of the formed impurity regions 217 to 219 is 2 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It may be in the range. In this specification, the concentration of the n-type impurity element contained in the impurity regions 217 to 218 formed here is (n ^- ). Further, the impurity region 219 is a semiconductor layer for forming a holding procedure for the pixel matrix circuit, and P is added to this region at the same concentration. (Fig. 4 (E))
[0028]
Next, the mask layer 208 is removed with hydrofluoric acid or the like, and a process of activating the impurity element added in FIG. The activation can be performed in a nitrogen atmosphere by a heat treatment at 500 to 600 ° C. for 1 to 4 hours or a laser activation method. Moreover, you may carry out using both together. (Fig. 5 (A))
[0029]
Then, the gate insulating film 220 is formed with an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 5 (A))
[0030]
Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, but may have a laminated structure of two layers or three layers as necessary. In this embodiment, a conductive layer (A) 221 made of a conductive nitride metal film and a conductive layer (B) 222 made of a metal film are stacked. The conductive layer (B) 222 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, the conductive layer (A) 221 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), molybdenum nitride. (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 221 as an alternative material. In the conductive layer (B), it is preferable to reduce the concentration of impurities contained in order to reduce the resistance, and in particular, the oxygen concentration is preferably set to 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0031]
The conductive layer (A) 221 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 222 may be 200 to 400 nm (preferably 250 to 350 nm). In film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and peeling of the film can be prevented. Although not shown, it is effective to form a silicon film doped with P under the conductive layer (A) 221 with a thickness of about 2 to 20 nm. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (Fig. 5 (B))
[0032]
Next, resist masks 223 to 227 are formed, and the conductive layer (A) 221 and the conductive layer (B) 222 are etched together to form gate electrodes 228 to 231 and a capacitor wiring 232. In the gate electrodes 228 to 231 and the capacitor wiring 232, the conductive layer (A) and the conductive layer (B) are integrally formed. At this time, the gate electrodes 229 and 230 formed in the driver circuit are formed so as to overlap with part of the impurity regions 217 and 218 with the gate insulating film 220 interposed therebetween. (Fig. 5 (C))
[0033]
Then, using the gate electrode and the capacitor wiring as a mask, the gate insulating film 220 is etched to leave a part of the island-shaped semiconductor layer so that the gate insulating films 233 to 236 remain at least under the gate electrode. (At this time, the insulating film 237 is also formed under the capacitor wiring.) This is because the impurity element is efficiently added in a step of adding an impurity element for forming a source region or a drain region in a later step. Therefore, this step may be omitted and the gate insulating film may be left on the entire surface of the island-like semiconductor layer. (Fig. 5 (D))
[0034]
Next, in order to form a source region and a drain region of the p-channel TFT of the control circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligning manner using the gate electrode 228 as a mask. At this time, a region where the n-channel TFT is formed is covered with a resist mask 238. And diborane (B ₂ H ₆ The impurity region 239 is formed by an ion doping method using). The B concentration in this region is 3 x 10 ²⁰ ~ 3 × 10 ^{twenty one} atoms / cm ^Three To be. In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 239 formed here is expressed as (p +). (Fig. 6 (A))
[0035]
Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region is formed. Resist masks 240 to 242 are formed so as to cover a region to be a gate electrode and a p-channel TFT, and an impurity element imparting n-type is added to form impurity regions 243 to 247. This is the phosphine (PH _Three ) And the P concentration in this region is 1 × 10 ²⁰ ~ 1 × 10 ^{twenty one} atoms / cm ^Three And In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 217 to 218 formed here is expressed as (n +). (Fig. 6 (B))
[0036]
The impurity regions 243 to 247 already contain P or B added in the previous step, but P is added in a sufficiently higher concentration than that, so that P or boron added in the previous step is added. It is not necessary to consider the influence of B. Further, since the P concentration added to the impurity region 243 is 1/2 to 1/3 of the B concentration added in FIG. 6A, p-type conductivity is ensured, and the TFT characteristics are affected. There is no. The P doping here is performed to form the source / drain and getter the metal Ni existing in the channel formation region and promoting crystallization. In the impurity region 243, the concentration of B is higher, but it has been clarified by the present inventor that metal Ni that promotes crystallization of the channel formation region can be gettered.
[0037]
Next, the resist mask is removed, and an impurity addition step for imparting n-type is performed in order to form an LDD region of the n-channel TFT of the pixel matrix circuit. The concentration of P added here is 1 × 10 ¹⁶ ~ 5 × 10 ¹⁸ atoms / cm ^Three The impurity regions 249 and 250 are formed by adding at a concentration lower than the concentration of the impurity element added in FIGS. 4E, 6A, and 6B. In this specification, the concentration of an impurity element imparting n-type contained in the impurity region formed here is expressed as (n−−). (Fig. 6 (C))
[0038]
Then, a protective insulating film 251 that is part of the first interlayer insulating film is formed. The protective insulating film 251 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 100 to 400 nm.
[0039]
Further, an interlayer insulating film 252 having a thickness of 500 to 1500 nm is formed on the protective insulating film 251. A laminated film composed of the protective insulating film 251 and the interlayer insulating film 252 is defined as a first interlayer insulating film. Thereafter, contact holes reaching the source region or drain region of each TFT are formed. (Figure 7)
[0040]
Next, P is added to the source region or the drain region from which the first interlayer insulating film has been removed by forming the contact hole. Add P to phosphine (PH _Three ) And the P concentration in this region is 4 × 10 ²⁰ ~ 1 × 10 ^{twenty two} atoms / cm ^Three And The ion doping of P is performed to reduce or reduce the metal Ni that promotes crystallization from the vicinity of the junction. In order to efficiently perform gettering, it is better that the position of the contact hole is closer to the junction and the area of the contact hole is larger. (Figure 7)
[0041]
Thereafter, a heat treatment process is performed at a temperature of 450 ° C. to 600 ° C. to activate the impurity element imparting n-type or p-type added at each concentration. By this heat treatment, the metal Ni that promotes crystallization of the channel formation region moves to the source or drain region, and further moves to the P-doped region through the contact hole having a high P concentration. Also, Ni in the junction region moves to the P-doped region through the contact hole, and Ni in the vicinity of the junction region can be reduced or reduced. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method).
[0042]
Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the active layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0043]
When the activation process is completed, source wirings 253 to 256 and drain wirings 257 to 259 are formed in contact holes reaching the source region or the drain region of each TFT.
[0044]
Next, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed as the passivation film 260 with a thickness of 50 to 500 nm (typically 100 to 300 nm). In this state, hydrogenation treatment or plasma hydrogenation may be performed. (Fig. 8 (A))
[0045]
Thereafter, a second interlayer insulating film 261 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Then, a contact hole reaching the drain wiring 259 is formed in the second interlayer insulating film 261, and a pixel electrode 262 is formed. The pixel electrode 262 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. (Fig. 8 (B))
[0046]
Thus, an active matrix substrate having a control circuit and a pixel matrix circuit can be completed on the same substrate. A p-channel TFT 285, a first n-channel TFT 286, and a second n-channel TFT 287 can be formed in the control circuit, and a pixel TFT including an n-channel TFT 288 can be formed in the pixel matrix circuit.
[0047]
The p-channel TFT 285 of the control circuit has a channel formation region 263, a source region 264, and a drain region 265. The first n-channel TFT 286 includes a channel formation region 266, an Lov region 267, a source region 268, and a drain region 269. The second n-channel TFT 287 includes a channel formation region 270, LDD regions 271 and 272, a source region 273, and a drain region 274. The n-channel TFT 288 of the pixel matrix circuit has channel formation regions 275 and 276 and Loff regions 277 to 280. The Loff region is offset with respect to the gate electrode, and the length of the offset region is 0.02 to 0.2 μm. Further, a capacitor wiring 232 formed simultaneously with the gate electrode, an insulating film made of the same material as the gate insulating film, and a semiconductor layer to which an impurity element imparting n-type conductivity connected to the drain region 283 of the n-channel TFT 288 is added A holding capacitor 289 is formed from the H.264. In FIG. 8B, the n-channel TFT 287 of the pixel matrix circuit has a double gate structure; however, a single gate structure or a multi-gate structure provided with a plurality of gate electrodes may be used.
[0048]
Hereinafter, in Examples 1 to 3, only a method of forming an impurity element imparting one conductivity type in a non-uniform concentration distribution in a region where the source / drain is formed will be described. Since formation of LDD and the like has been described in detail in Embodiment 1, it is omitted in the following examples.
[0049]
【Example】
[Example 1]
In Example 1, a method of performing a doping process a plurality of times using a resist mask, an oxide film mask, or the like, or a gate metal mask will be described.
[0050]
In FIG. 9A, a substrate 903 is a glass substrate or a quartz substrate, and a base film 908 is formed of an insulating film containing silicon (silicon). An island-shaped semiconductor layer is formed on the base film. This semiconductor layer is formed by crystallizing an amorphous silicon film formed by plasma CVD according to the technique disclosed in Japanese Patent Laid-Open No. 7-130652. Further, gate insulating films 901 and 904 and gate electrodes 902 and 905 are formed on the island-like semiconductor layer by a known method.
[0051]
Next, a resist mask 922 is formed so as to cover a region to be an n-channel TFT, and an impurity element B imparting p-type is added to form impurity regions 909 and 910. The B concentration in this region is 3 x 10 ²⁰ ~ 3 × 10 ^{twenty one} atoms / cm ^Three To be. (Fig. 9 (A))
[0052]
Next, a resist mask 919 is formed so as to cover a region to be a p-channel TFT, and an impurity element P imparting n-type is added to form impurity regions 912 and 913. P concentration in this area is 1 × 10 ²⁰ ~ 1 × 10 ^{twenty one} atoms / cm ^Three (Fig. 9 (B))
[0053]
Next, resist masks 920 and 921 are formed in part of a region where the gate electrode and the source / drain are to be formed, and an impurity element P imparting n-type is added to form impurity regions 915 to 918. P concentration in this area is 4 × 10 ²⁰ ~ 1 × 10 ^{twenty two} atoms / cm ^Three (Fig. 9 (C))
[0054]
By performing a heat treatment that combines thermal activation and gettering later, the impurity element Ni present in the channel formation regions 911 and 914 can be moved to the source / drain regions, and the impurity element Ni in the vicinity of the junction can be moved. Can be moved to the impurity regions 915 to 918 in which P is most doped.
[0055]
In this method, the impurity regions 915 to 918 doped with a large amount of P can be brought close to the vicinity of the junction. Further, in this method, P doping using a contact hole may be further performed, and gettering may be performed in which the concentration difference is made in three stages.
[0056]
[Example 2]
In Example 2, a method for controlling the amount of impurities to be doped by leaving the gate oxide film partially in the island-like semiconductor layer will be described. This uses a concentration profile in the depth direction in impurity implantation using ion doping, and a source / drain region having a non-uniform concentration distribution can be formed by a single doping process.
[0057]
In FIG. 10A, a substrate 1003 is a glass substrate or a quartz substrate, and a base film 1008 is formed of an insulating film containing silicon (silicon). An island-shaped semiconductor layer is formed on the base film. This semiconductor layer is obtained by crystallizing an amorphous silicon film formed by plasma CVD according to the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. Further, a gate insulating film 1004 is formed on the entire surface of the island-like semiconductor layer by a known method, and gate electrodes 1002 and 1005 etched by a known method are formed thereon. Here, a resist mask 1023 is formed so as to cover the entire gate electrode of the n-channel TFT and leave a part of the island-shaped semiconductor layer, and the gate insulating film is etched. (Fig. 10 (A))
[0058]
Next, a resist mask 1014 is formed so as to cover a region to be an n-channel TFT, and an impurity element B1 that imparts p-type is added to form impurity regions 1011 and 1012. The B concentration in this region is 3 x 10 ²⁰ ~ 3 × 10 ^{twenty one} atoms / cm ^Three To be. (Fig. 10 (B))
[0059]
Next, a resist mask 1022 is formed so as to cover the entire gate electrode of the p-channel TFT and leave a part of the island-like semiconductor layer, and an impurity element P imparting n-type is added to form impurity regions 1015 to 1020. Form. P concentration in this area is 1 × 10 ¹⁹ ~ 1 × 10 ^{twenty two} atoms / cm ^Three (Fig. 10 (C))
[0060]
Therefore, the impurity regions 1015, 1016, 1019, and 1020 are doped with P at a high concentration, and 1017 and 1018 are doped with a low concentration. Therefore, after the heat treatment, the impurity element Ni in the channel formation regions 1013 and 1021 moves to a region doped with P, and Ni in the vicinity of the junction also moves to impurity regions 1015, 1016, 1019, and 1020 doped with P at a high concentration. Therefore, Ni can be effectively removed or reduced from the vicinity of the joint. Here, the low concentration and the high concentration are expressed by comparing the concentrations of the two regions, and the region doped at a low concentration is almost the same as the amount of impurities doped in the normal source / drain. To do.
[0061]
In this method, P-doping using a contact hole may be further performed to perform gettering.
[0062]
[Example 3]
In Example 3, a method of controlling the amount of impurities to be doped by forming a slope in the gate insulating film by using wet etching and performing doping will be described. This method also uses a concentration profile in the depth direction in impurity implantation using ion doping as in the second embodiment. In this example, the concentration distribution of P to be doped changes continuously.
[0063]
In FIG. 11A, a substrate 1103 is a glass substrate or a quartz substrate, and a base film 1108 is formed of an insulating film containing silicon (silicon). An island-like semiconductor layer is formed on the base film. This semiconductor layer is obtained by crystallizing an amorphous silicon film formed by plasma CVD according to the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. Further, a gate insulating film 1104 is formed on the entire surface of the island-like semiconductor layer by a known method, and gate electrodes 1102 and 1105 etched by a known method are formed thereon. Here, resist masks 1111 and 1112 are formed so as to cover the whole gate electrodes of the n-channel TFT and the p-channel TFT and leave all or part of the island-like semiconductor layer, and wet-etch the gate insulating film. (Fig. 11 (A))
[0064]
Next, a resist mask 1115 is formed so as to cover a region to be an n-channel TFT, and an impurity element B imparting p-type is added. The B concentration in this region is 3 x 10 ²⁰ ~ 3 × 10 ^{twenty one} atoms / cm ^Three To be. (Fig. 11 (B))
[0065]
Next, a resist mask 1124 is formed so as to cover the entire gate electrode of the p-channel TFT and leave a part of the island-like semiconductor layer, and an impurity element P imparting n-type is added to form impurity regions 1116 to 1119. Form. P in this region may be ion-implanted so that the doping amount increases as the distance from the gate increases in consideration of the thickness due to the inclination of the gate insulating film. (Fig. 11 (C))
[0066]
Accordingly, the impurity regions 1116 to 1119 have a higher P concentration as they move away from the gate electrode. Therefore, after the heat treatment, the impurity element Ni in the channel formation regions 1122 and 1123 moves to a region doped with P, and Ni near the junction also moves more to a portion farther from the gate than the impurity region doped with P at a high concentration. Therefore, Ni can be effectively removed or reduced from the vicinity of the joint. Here, the low concentration and the high concentration are expressed by comparing the concentrations of the two regions, and the region doped at a low concentration is almost the same as the amount of impurities doped in the normal source / drain. To do.
[0067]
[Example 4]
In this example, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 12, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. 8B that can be manufactured in the first embodiment. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 603, a transparent conductive film 604, and an alignment film 605 were formed on the counter substrate 602 on the counter side. After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. Then, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling process. Thereafter, a liquid crystal material 606 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, an active matrix liquid crystal display device is completed.
[0068]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. 13 and the top view of FIG. 13 and 14 use the same reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. 4 to 8 and FIG. Further, the cross-sectional structure along 1 'shown in FIG. 14 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG. 8B.
[0069]
The active matrix substrate includes a pixel matrix circuit 701, a scanning signal control circuit 702, and an image signal control circuit 703 formed on the glass substrate 201. An n-channel TFT 288 is provided in the pixel matrix circuit, and a driver circuit provided in the periphery is configured based on a CMOS circuit. Each of the scanning signal control circuit 702 and the image signal control circuit 703 includes a gate wiring 231 (represented by the same reference sign in the sense of being connected to a gate electrode and extending) and a source wiring 256. A channel type TFT 288 is connected. Further, the FPC 731 is connected to the external input / output terminal 734.
[0070]
FIG. 14 is a top view showing a part (substantially one pixel) of the pixel matrix circuit 701. The gate wiring 231 intersects with the active layer therebelow through a gate insulating film (not shown). Although not shown, the active layer is formed with a source region, a drain region, and an Loff region composed of an n−− region. Reference numeral 290 denotes a contact portion between the source wiring 256 and the source region 281, 292 denotes a contact portion between the drain wiring 259 and the drain region 283, and 292 denotes a contact portion between the drain wiring 259 and the pixel electrode 262. The storage capacitor 289 is formed in a region where the capacitor wiring 232 overlaps with the semiconductor layer 284 extending from the drain region of the n-channel TFT 288 and the gate insulating film.
[0071]
Note that the active matrix liquid crystal display device of this embodiment can be freely combined with any of the configurations of the following embodiments to manufacture an active matrix liquid crystal display device.
[0072]
[Example 5]
The present invention can be applied to an active matrix EL display device. FIG. 15 is a circuit diagram of an active matrix EL display device. An X direction control circuit 12 and a Y direction control circuit 13 are provided around the pixel matrix circuit 11. Each pixel of the pixel matrix circuit 11 includes a switching TFT 14, a capacitor 15, a current control TFT 16, and an organic EL element 17, and an X direction signal line 18 a and a Y direction signal line 20 a are connected to the switching TFT 14 to control current. A power line 19a is connected to the TFT for use.
[0073]
In the active matrix EL display device of the present invention, TFTs used for the X direction control circuit 12, the Y direction control circuit 13, or the current control TFT 17 are the p-channel TFT 285, the n-channel TFT 286, or the n-channel TFT 286 in FIG. A channel TFT 287 is formed in combination. Further, the switching TFT 14 is formed by the n-channel TFT 288 of FIG. 8B.
[0074]
It should be noted that any of the configurations of Embodiment Mode 1, Embodiments 1 to 3 may be combined with the active matrix EL display device of this embodiment.
[0075]
[Example 6]
An active matrix substrate in which a pixel matrix circuit and a control circuit manufactured according to the present invention are integrally formed on the same substrate is used in various electro-optical devices (active matrix liquid crystal display devices, active matrix EL display devices, active matrix substrates). Matrix type EC display device). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display units.
[0076]
Examples of such electronic devices include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggles type display), a car navigation system, a personal computer, a mobile phone, or an electronic book. Examples of these are shown in FIG.
[0077]
FIG. 16A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display portion 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display portion 9004 provided with an active matrix substrate.
[0078]
FIG. 16B illustrates a video camera which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the display portion 9102 provided with an active matrix substrate.
[0079]
FIG. 16C illustrates a mobile computer, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display portion 9205. The present invention can be applied to the display portion 9205 including an active matrix substrate.
[0080]
FIG. 16D illustrates a goggle type display which includes a main body 9301, a display portion 9302, and an arm portion 9303. The present invention can be applied to the display portion 9302. Although not shown, it can also be used for other signal control circuits.
[0081]
FIG. 16E shows a rear projector, which includes a main body 9401, a light source 9402, a display device 9403, a polarizing beam splitter 9404, reflectors 9405 and 9406, and a screen 9407. The present invention can be applied to the display device 9403.
[0082]
FIG. 16F illustrates a portable book which includes a main body 9501, display portions 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506. The data received by the antenna is displayed. In the present invention, the display portions 9502 and 9503 can be applied to a direct-view display device.
[0083]
Although not shown here, the present invention can also be applied to a display unit of a car navigation system or an image sensor personal computer. Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields. Also, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fifth embodiments.
【The invention's effect】
By using the present invention, impurities in the vicinity of the boundary between the channel formation region of the transistor and the source and drain regions can be removed or reduced, and the operating performance and reliability of the semiconductor device (here, specifically, the electro-optical device) are greatly improved. Can be made.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing means for solving a problem.
FIG. 2 is a diagram showing SIMS analysis results.
FIG. 3 is a diagram schematically showing a means for solving the problem.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel matrix circuit and a control circuit.
FIG. 9 is a diagram illustrating a TFT creation process according to the first embodiment.
10 is a diagram showing a TFT creation process of Example 2. FIG.
FIG. 11 is a diagram illustrating a TFT creation process according to the third embodiment.
FIG. 12 is a cross-sectional structure diagram of an active matrix liquid crystal display device.
FIG. 13 is a perspective view of an active matrix liquid crystal display device.
FIG. 14 is a top view of a pixel matrix circuit.
FIG. 15 is a circuit diagram of an active matrix EL display device.
FIG 16 illustrates an example of a semiconductor device.
[Explanation of symbols]
210 ~ 212,284,301,311 Semiconductor layer
204-207,210,211 Island-like semiconductor layer
209,213-216,223-227,238,240-242,919-922 resist mask
1014,1022,1023,1111,1112,1115,1124 Resist mask
105,305,228 ~ 231,902,905,1002,1005,1102,1105 Gate electrode
104,304,220,233 to 236,901,904,1004,1104 Gate insulation film
107,263,266,270,275,276,911,914,1013,1021,1122,1123 Channel formation region
264,268,273 Source area
265,269,274,283 drain region
101,111 first impurity region
102,112 second impurity region
301,311 Third impurity region
203a Amorphous silicon film
203b Crystallized silicon film
208 Mask layer
221 Conductive layer (A)
222 Conductive layer (B)
232 capacity wiring
237 Insulating film
251 Protective insulating film
252 Interlayer insulation film
260 Passivation membrane
261 Second interlayer insulating film
262 Pixel electrode
267 Lov region
277-280 Loff area
603 Shading film
604 transparent conductive film
606 LCD material
290,292 Contact section
232 capacity wiring

Claims (7)

Forming a semiconductor film having an amorphous structure on the insulating surface;
Crystallizing the semiconductor film having the amorphous structure using a metal that promotes crystallization,
An island-shaped semiconductor layer is formed from the crystallized semiconductor film,
Forming an insulating film on the island-like semiconductor layer;
After forming the gate electrode on the insulating film, the insulating film is inclined by wet etching,
An impurity element is added to the island-like semiconductor layer through the insulating film provided with an inclination ,
A method for manufacturing a thin film transistor, characterized in that heat treatment is performed to move the metal that promotes crystallization to a region where an impurity element is added to the island-shaped semiconductor layer . 2. The method for manufacturing a thin film transistor according to claim 1 , wherein the impurity element added to the island-shaped semiconductor layer increases with distance from the gate electrode. Forming a semiconductor film having an amorphous structure on the insulating surface;
Crystallizing the semiconductor film having the amorphous structure using a metal that promotes crystallization,
An island-shaped semiconductor layer is formed from the crystallized semiconductor film,
Forming an insulating film on the island-like semiconductor layer;
After forming the gate electrode on the insulating film, the insulating film is inclined by wet etching,
An impurity element is added to the island-shaped semiconductor layer through the insulating film provided with an inclination,
An interlayer insulating film is provided on the insulating film and the gate electrode,
After forming a contact hole reaching the island-like semiconductor layer to which the impurity element is added in the interlayer insulating film, the same impurity element as the impurity element is added,
By performing a heat treatment, the metal that promotes crystallization is moved to a region where an impurity element is added to the island-shaped semiconductor layer,
A method for manufacturing a thin film transistor, wherein a wiring electrically connected to the island-shaped semiconductor layer through the contact hole is formed. Forming a semiconductor film having an amorphous structure on the insulating surface;
Crystallizing the semiconductor film having the amorphous structure using a metal that promotes crystallization,
An island-shaped semiconductor layer is formed from the crystallized semiconductor film,
Forming an insulating film on the island-like semiconductor layer;
After forming the gate electrode on the insulating film, the insulating film is inclined by wet etching,
An impurity element is added to the island-like semiconductor layer through the insulating film provided with an inclination, and the impurity element is increased as the distance from the gate electrode increases, and then an interlayer insulating film is formed on the insulating film and the gate electrode. Provided,
After forming a contact hole reaching the island-like semiconductor layer to which the impurity element is added in the interlayer insulating film, the same impurity element as the impurity element is added,
By performing a heat treatment, the metal that promotes crystallization is moved to a region where an impurity element is added to the island-shaped semiconductor layer,
A method for manufacturing a thin film transistor, wherein a wiring electrically connected to the island-shaped semiconductor layer through the contact hole is formed. Forming a semiconductor film having an amorphous structure on the insulating surface;
Crystallizing the semiconductor film having the amorphous structure using a metal that promotes crystallization,
An island-shaped semiconductor layer is formed from the crystallized semiconductor film,
Forming an insulating film on the island-like semiconductor layer;
After forming the gate electrode on the insulating film, the insulating film is inclined by wet etching,
An impurity element is added to the island-like semiconductor layer through the insulating film provided with an inclination, and the impurity element is increased as the distance from the gate electrode increases, and then an interlayer insulating film is formed on the insulating film and the gate electrode. Provided,
After forming a contact hole reaching the island-like semiconductor layer to which the impurity element is added in the interlayer insulating film, the same impurity element as the impurity element is added,
By performing a heat treatment, the metal that promotes crystallization is moved to a region where an impurity element is added to the island-shaped semiconductor layer,
Forming a wiring electrically connected to the island-like semiconductor layer through the contact hole;
A method for manufacturing a thin film transistor, characterized in that the impurity element of 4 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²² atoms / cm ³ is added to a junction between the island-shaped semiconductor layer and the wiring. . The metal that promotes crystallization is removed or reduced from the vicinity of the junction region between the channel region and the source region of the island-shaped semiconductor layer and the junction region between the channel region and the drain region by the heat treatment. Item 6. A method for manufacturing a thin film transistor according to any one of Items 1 to 5. The method for manufacturing a thin film transistor according to any one of claims 1 to 6, wherein the heat treatment is performed at a temperature of 450 ° C to 600 ° C.

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