JP4586492B2 - One-wire data communication method and one-wire data transmitter / receiver using this communication method - Google Patents

Description

  The present invention relates to a one-wire data communication method using multi-levels and a one-wire data transceiver to which this communication method is applied.

Conventionally, there is known a one-wire data communication method for converting a plurality of binary signals into a multi-value signal having a multi-value level and communicating the multi-value signal via a single signal line (for example, (See Patent Document 1 and Patent Document 2). In such a one-line data communication method using multi-levels, for example, as shown in FIG. 4, a plurality of binary signals D101, D102, etc. are sent to the multi-levels “0” to “7” on the transmitter side. Is converted to a multilevel signal D103 having a plurality of binary signals D101, D102 by reversely converting the multilevel signal D103 into a plurality of binary signals D101, D102, etc. Etc. can be communicated via a single signal line.
JP 2003-78576 A JP 2000-47768 A

  By the way, in data communication, in order to correctly receive data sent from a communication partner, the position of each bit and each block of data (units meaningful as data on the transmission side and reception side (for example, one character) )) Start position needs to be detected and synchronized on the receiving side. However, in the signal processing methods and the like described in Patent Document 1 and Patent Document 2 described above, there is no contrivance to reliably detect the start position of each block of the multilevel signal on the receiving side, and the data is erroneously detected. There is a risk of recognition. In general data communication, for example, a predetermined pattern (for example, “01111110” or the like) is added to the start position of each block of data to ensure the identification of each block. There is a risk that synchronization will occur by mistake due to the occurrence of an error on the line, which is not a simple method.

  In data communication, for example, the communication speed is determined by a fixed sampling frequency determined in advance on the transmission side and the reception side, but communication can be performed without making such an arrangement so that the communication environment can be flexibly handled. It may be desirable to be able to change the speed freely.

  The present invention has been made in order to solve the above-described problem, and recognizes each block of a multi-level signal in a single-wire data communication method using a multi-level and a single-wire data transceiver used in the communication method. The first object is to improve the performance and reduce the data error rate, and it is possible to arbitrarily set the communication speed without preliminarily determining the communication speed between the transmission side and the reception side. This is the second purpose.

In order to achieve the above object, the invention of claim 1 is directed to a multilevel signal conversion step for converting a plurality of binary signals into a multilevel signal having a multilevel level on the transmitter side, the transmitter and the receiver. A transmission / reception step for transmitting and receiving the multilevel signal via a single signal line, and a binary for inversely converting the received multilevel signal into the plurality of binary signals on the receiver side A multi-level data communication method with multi-levels comprising a signal conversion step, wherein the transmitter has a level different from the multi-levels constituting the multi-level signal and the pulse width is variable An identification pulse adding step for adding an identification pulse having a long pulse width of one clock to the start position of each block of the multilevel signal, and detecting the identification pulse on the receiver side, Each of the multilevel signals An identification pulse detection step of detecting the starting position of the lock, by detecting the pulse width of the identification pulse, the communication speed of the last one block followed by determining the interval of one clock to each identification pulse in the data transmission and reception A communication speed detecting step for detecting, and the binary signal converting step includes a start position of each block of the multilevel signal detected by the identification pulse detecting step and a communication speed detecting step and a communication speed of each block. Based on this, the multilevel signal is inversely converted into the plurality of binary signals for each block.

The invention of claim 2 is a multi-value signal conversion means for converting a plurality of binary signals into multi-value signals having multi-value levels, and transmits the multi-value signals to a receiver via one signal line. One-line data comprising: a transmitter having a transmitting means; a receiving means for receiving the multilevel signal; and a receiver having a binary signal converting means for inversely converting the multilevel signal into the plurality of binary signals. An identification pulse having a level different from the multilevel levels constituting the multilevel signal, the pulse width being variable , and the pulse width being equivalent to one clock. and further has an identification pulse adding means for adding at the beginning of each block of the multi-level signal, the receiver, along with detecting the identification pulse for detecting the beginning of each block of the multi-level signal By detecting the pulse width of the identification pulse Further has an identification pulse detecting means for detecting the communication speed of the last one block followed by determining the interval of one clock to each identification pulse in the data transmission and reception, and the binary signal converting means, the identification pulse Based on the start position of each block of the multi-level signal detected by the detection unit and the communication speed of each block, the multi-level signal is reversely converted into the plurality of binary signals for each block. Features.

  As described above, according to the one-line data communication method of the first aspect, the transmitter side has a level different from the multilevel level constituting the multilevel signal and the pulse width is one clock. A pulse is added to the start position of each block of the multilevel signal, and the multilevel signal is converted into a plurality of binary signals on the receiver side based on the start position of each block of the multilevel signal detected by this identification pulse. Therefore, the data recognizability can be improved in units of one block, and the data error rate can be reduced. For this reason, for example, it is possible to shorten the data length such that the parity for error detection can be omitted.

  On the transmitter side, an identification pulse having a variable pulse width and a pulse width of one clock is added to the start position of each block of the multilevel signal, and on the receiver side, the pulse of this identification pulse is added. By detecting the width, the communication speed for the most recent block following each identification pulse is detected, so by arbitrarily adjusting the pulse width of the identification pulse, communication can be made arbitrarily for each block of the multilevel signal. The speed can be set.

According to the one-line transmitter / receiver of the second aspect , similarly to the above, it is possible to simply improve the data recognizability in units of one block and to arbitrarily adjust the pulse width of the identification pulse. The communication speed can be arbitrarily set for each block of the multilevel signal.

  Hereinafter, a one-wire data communication method according to the first embodiment of the present invention and a one-wire data transceiver (hereinafter simply referred to as a transceiver) used in the communication method will be described with reference to FIG. 1 and FIG. explain. The transceiver 1 converts a plurality of binary signals D1, D2, etc. into an 8-level signal (multi-level signal) D3 having multi-levels “0” to “7”, and this 8-level signal D3 is converted into one signal. A device that communicates via a signal line, a transmitter 2 that converts a plurality of binary signals D1, D2, and the like input from the outside into an 8-level signal D3 and transmits the signal to the receiver 3, and a transmitter 2 And a receiver 3 that converts the received 8-level signal D3 into binary signals D1 and D2 and outputs them to the outside.

  The transmitter 2 is a binary-to-eight-value conversion circuit that converts two binary signals D1 and D2 and a clock signal CLK input from the outside into an 8-level signal D3 having multilevel levels “0” to “7”. (Multi-value signal conversion means) 21, an identification pulse addition circuit (identification pulse addition means) 22 for adding an identification pulse P to the start position of each block of the 8-level signal D3, and an 8-level signal D3 as one signal line And a transmission circuit (transmission means) 23 for transmitting to the receiver 3 via the.

  The receiver 3 detects a reception circuit (reception means) 31 that receives the 8-level signal D3 from the transmitter 2 and the identification pulse P added by the transmitter 2, and starts each block of the 8-level signal D3. Based on the start position of each block of the 8-value signal D3 detected by the identification pulse detection circuit 32 and the identification pulse detection circuit (identification pulse detection means) 32 for detecting the 8-value signal D3, a plurality of binary signals D1 , D2 and the like, and an 8-value-to-binary conversion circuit (binary signal conversion means) 33 for reverse conversion.

  The one-wire data communication method performed using the transceiver 1 of this embodiment will be described in more detail. First, the binary-to-eight-value conversion circuit 21 converts the two binary signals D1 and D2 and the clock signal CLK input from the outside into an 8-level signal D3 having multilevel levels “0” to “7”. (Multi-value signal conversion step). In FIG. 2, the multilevel levels “0” to “F” are shown in hexadecimal notation, and the binary signals D1 and D2 and the 8-level signal D3 converted from the clock signal CLK are each level “0”. To level “7”. For example, at the point a where the value of the binary signal D1 is “1”, the value of the binary signal D2 is “1”, and the value of the clock signal CLK is “0”, the binary signal D1, the binary signal D2, The level “6” obtained by converting “110” assigned to each digit of the binary number in the order of the clock signal CLK to the hexadecimal number “6” becomes the level of the 8-level signal D3. Similarly, the value of the binary signal D1 is “0”. “At the point b where the value of the binary signal D2 is“ 1 ”and the value of the clock signal CLK is“ 0 ”, the level“ 2 ”obtained by converting the binary number“ 10 ”into the hexadecimal number“ 2 ”is eight values. It becomes the level of the signal D3.

  Next, the identification pulse adding circuit 22 has a level “F” different from the multilevel levels “0” to “7” constituting the 8-level signal D3 at the start position of each block of the 8-level signal D3. In addition, an identification pulse P having a pulse width of one clock is added (identification pulse adding step). Thus, by making the difference between the level of the identification pulse P and the level of the 8-level signal D3 larger, the recognizability of each block of the 8-level signal D3 can be further improved. In the present embodiment, an example in which one block is 8 bytes is shown. The 8-level signal D3 is transmitted / received between the transmitter 2 and the receiver 3 via one signal line (transmission / reception step).

  Next, the identification pulse detection circuit 32 on the receiver 3 side detects the identification pulse P and detects the start position of each block of the 8-level signal D3 (identification pulse detection step). Then, based on the detected start position of each block of the 8-level signal D3, the 8-level signal D3 is inversely converted into a plurality of binary signals D1, D2, etc. (binary signal conversion step).

  According to the transceiver 1 and the one-wire data communication method of this embodiment, the transmitter 2 side has a level “F” different from the multilevel levels “0” to “7” constituting the 8-level signal D3. In addition, an identification pulse P having a pulse width of one clock is added to the start position of each block of the 8-level signal D3, and each of the 8-level signal D3 detected by the identification pulse P is detected on the receiver 3 side. Based on the block start position, the 8-level signal D3 is inversely converted into a plurality of binary signals D1, D2, etc., so that the data recognizability can be easily improved in units of blocks. The error rate can be reduced. For this reason, for example, it is possible to shorten the data length such that the parity for error detection can be omitted.

  A one-wire data communication method according to a second embodiment of the present invention and a transceiver used in this communication method will be described with reference to FIG. The present embodiment is different from the first embodiment in that the identification pulse has a variable length, and the communication speed can be arbitrarily set without preliminarily determining the communication speed between the transmission side and the reception side.

Similarly to the first embodiment, the transmitter 2 includes a binary / eight-value conversion circuit 21, an identification pulse addition circuit 22, and a transmission circuit 23, and the receiver 3 includes a reception circuit 31 and an identification pulse detection circuit. 32 and an 8-value-to-binary conversion circuit 33. As shown in FIG. 3, the identification pulse adding circuit 22 starts identifying blocks P1 and P2 having a variable pulse width and a pulse width of one clock at the start of each block B1 and B2 of the 8-level signal D3. Append to position. On the other hand, the identification pulse detection circuit 32 detects the identification pulses P1 and P2 added by the transmitter 2, detects the start position of each block B1 and B2 of the 8-level signal D3, and also detects the identification pulses P1 and P2. By detecting the pulse widths T ₁ and T ₂ , the interval of one clock is determined, and the communication speed for the latest one block following each identification pulse P 1 and P 2 is detected.

  The one-wire data communication method performed using the transceiver 1 of this embodiment will be described in more detail. First, the binary-to-eight-value conversion circuit 21 converts the two binary signals D1 and D2 and the clock signal CLK input from the outside into an 8-level signal D3 having multilevel levels “0” to “7”. (Multi-value signal conversion step).

Next, in the identification pulse addition circuit 22, at the start position of each of the blocks B1 and B2 of the 8-level signal D3, a level “F” different from the multilevel levels “0” to “7” constituting the 8-level signal D3. Identification pulses P1 and P2 having a variable pulse width and a pulse width of one clock are added (identification pulse adding step). In the present embodiment, by adding the identification pulse P1 that the pulse width is _{T 1} to the start of the block B1, the identification pulse P2 having a pulse width in the starting position of the block B2 is _{T 2 (T 2 = 2T 1} ) An added example is shown. In this embodiment, an example in which one block is composed of 8 bytes is shown. The 8-level signal D3 to which the identification pulses P1, P2 are added is transmitted / received between the transmitter 2 and the receiver 3 via one signal line (transmission / reception step).

Next, the identification pulse detection circuit 32 on the receiver 3 side detects the identification pulses P1 and P2 to detect the start positions of the respective blocks B1 and B2 of the 8-level signal D3, and the pulse width T of the identification pulses P1 and P2 ₁ and T ₂ are detected to detect the communication speed (identification pulse detection step, communication speed detection step). Then, based on the start position and the communication speed of each block B1, B2 of the detected 8 value signal D3, a plurality of binary signal 8 value signal D3 the period of one clock as _{T 1} for block B1 D1, D2 and converted back to an equal, for block B2 to inverse transform the 8-value signal D3 the period of one clock as T ₂ to a plurality of binary signals D1, D2, etc. (binary signal converting step).

As described above, according to the transceiver 1 and the one-wire data communication method of the present embodiment, the same effect as the first embodiment can be obtained, and the pulse width is variable on the transmitter 2 side. Identification pulses P1 and P2 having a pulse width of one clock are added to the start positions of the respective blocks B1 and B2 of the 8-level signal D3. On the receiver 3 side, the pulse widths T ₁ and P 2 of the identification pulses P1 and P2 are added. by detecting the T _2, and detects the communication speed of the last one block following each identification pulse P1, P2, by arbitrarily adjusting the pulse width T _1, T ₂ of the identification pulse P1, P2, It is possible to arbitrarily set the communication speed for each block of the 8-level signal D3.

  The present invention is not limited to the configuration of the above embodiment, and various modifications can be made. For example, the number of binary signals to be converted and the number of levels of multilevel levels are not particularly limited, and an arbitrary number of 2 can be set by setting the number of levels according to the number of binary signals to be converted. A value signal can be converted into a multi-value signal. Further, each block of the multilevel signal may not be composed of 1 byte.

1 is a block diagram showing a configuration of a one-wire data transceiver according to a first embodiment of the present invention. Explanatory drawing of the multi-value signal transmitted / received in the transmitter / receiver. Explanatory drawing of the multi-value signal transmitted / received in the 1 wire type data transmitter / receiver which concerns on the 2nd Embodiment of this invention. Explanatory drawing of the one-wire data communication method by the multi-value level in a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1-line | wire type data transmitter / receiver 2 Transmitter 3 Receiver 21 Binary-eight-value conversion circuit (multi-value signal conversion means)
22 Identification pulse addition circuit (recognition pulse addition means)
23 Transmission circuit (transmission means)
31 Receiving circuit (receiving means)
32 Identification pulse detection circuit (identification pulse detection means)
33 8-value-2 value conversion circuit (binary signal conversion means)

Claims (2)

On the transmitter side, a multilevel signal conversion step of converting a plurality of binary signals into a multilevel signal having a multilevel level;
A transmission / reception step of transmitting / receiving the multilevel signal via a single signal line between the transmitter and the receiver;
On the receiver side, a multi-level level one-line data communication method comprising: a binary signal conversion step of inversely converting the received multi-level signal into the plurality of binary signals,
On the transmitter side,
An identification pulse having a level different from the multi-levels constituting the multi-level signal and having a variable pulse width and a pulse width of one clock is started at each block of the multi-level signal. An identification pulse adding step to add to the position;
On the receiver side,
An identification pulse detecting step of detecting the identification pulse and detecting a start position of each block of the multi-value signal;
Detecting a pulse width of the identification pulse to determine an interval of one clock in data transmission and reception , and detecting a communication speed for the latest one block following each identification pulse; and
In the binary signal conversion step, the multilevel signal is determined for each block based on the start position of each block of the multilevel signal and the communication speed of each block detected by the identification pulse detection step and the communication speed detection step. Is converted back to the plurality of binary signals. A multi-level signal converting means for converting a plurality of binary signals into a multi-level signal having a multi-level level, and a transmitter having a transmitting means for transmitting the multi-level signal to a receiver via one signal line; ,
A one-line data transmitter / receiver comprising: receiving means for receiving the multilevel signal; and a receiver having binary signal converting means for inversely converting the multilevel signal into the plurality of binary signals,
The transmitter has an identification pulse having a level different from the multilevel level constituting the multilevel signal and having a variable pulse width and a pulse width of one clock. Further comprising identification pulse adding means for adding to the start position of each block of
The receiver detects the identification pulse to detect the start position of each block of the multilevel signal, and also detects the pulse width of the identification pulse to determine the interval of one clock in data transmission / reception. It further comprises an identification pulse detecting means for detecting the communication speed of the most recent block following each identification pulse , and the binary signal converting means is configured to detect each of the multilevel signals detected by the identification pulse detecting means. A one-line data transmitter / receiver comprising means for inversely converting the multilevel signal into the plurality of binary signals for each block based on a block start position and a communication speed of each block .

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