JP4558172B2 - Power consumption reduction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power control technique, and more particularly to a power consumption reduction circuit for reducing power consumption during clock operation and power consumption when the clock is stopped.
[0002]
[Prior art]
Semiconductor design is progressing year by year with higher speed and higher integration. For this reason, the power consumption of the block, particularly the power consumption of the clock line that operates at high speed, is very large, and there are many problems due to restrictions on package selection due to power consumption restrictions and heat generation.
[0003]
FIG. 16 is a block diagram of the first prior art described in Japanese Patent Laid-Open No. 5-326866. Referring to FIG. 16, this is achieved by operating the entire mesh clock line 44 with a small amplitude signal 42 supplied from the outside, thereby reducing the charge / discharge current of the mesh clock line 44 and entering the logic. By passing through the level conversion circuit 45 immediately before, a full swing signal such as the full swing clock 43 is supplied to the logic itself to reduce the power consumption of the mesh clock line 44. With this method, power consumption can be reduced by reducing the amplitude of the mesh-like clock line 44.
[0004]
FIG. 17 is a configuration diagram of a gated clock disclosed in the second prior art. Referring to FIG. 17, in the second prior art, when there is no need to operate the subsequent stage clock, an enable signal (clock stop signal 2) of the AND (logical product) gate 7 to which clock 1 is input is used. The operation of the clock line of the flip-flop 10 is stopped to reduce the power consumption of the clock line.
[0005]
[Problems to be solved by the invention]
However, the first prior art has a problem that power consumption in the level conversion circuit 45 is large. Further, since the level conversion circuit 45 has a large area, there is a problem that an increase in the area of the level conversion circuit 45 cannot be ignored.
Furthermore, since a current due to the generation of an intermediate potential is generated between the small amplitude portion and the level conversion circuit 45 when the clock is stopped, there is a problem that it is difficult to reduce power consumption as a whole circuit.
[0006]
In the case of the second prior art, it is possible to reduce power consumption when the clock may be stopped, but when the operating rate of the clock line is high, the same as the normal clock line. There was a problem of becoming.
[0007]
The present invention has been made in view of such problems, and an object thereof is to provide a power consumption reduction circuit capable of reducing power consumption during clock operation and power consumption when the clock is stopped.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a gated buffer circuit including an AND gate that outputs a logical product of a clock signal and a clock stop signal in an LSI chip, and a small amplitude that is a circuit that does not perform a full swing. The present invention resides in a power consumption reduction circuit including a buffer circuit and a leak prevention buffer circuit which is a circuit for stopping leakage when the clock is stopped.
According to a second aspect of the present invention, there is provided a circuit configuration in which an enable terminal of the gated buffer circuit is connected to an enable terminal of the leak prevention buffer circuit. It exists in the described power consumption reduction circuit.
According to a third aspect of the present invention, the small amplitude buffer circuit performs level conversion on an output signal of an AND gate that performs a logical product of a clock and a clock stop signal, and the small amplitude buffer circuit and 3. The power consumption reduction circuit according to claim 2, wherein the power consumption reduction circuit has a circuit configuration for outputting as an output signal of the leak prevention buffer circuit.
According to a fourth aspect of the present invention, the leak prevention buffer circuit is configured such that when the clock stop signal is at "L" level, the output signal of the AND gate is directly used as the small amplitude buffer circuit and 4. The power consumption reduction circuit according to claim 3, wherein the power consumption reduction circuit has a circuit configuration for outputting as an output signal of the leak prevention buffer circuit.
According to a fifth aspect of the present invention, the buffer circuit for leak prevention makes the output high impedance when the clock stop signal is at "H" level. The power consumption reduction circuit described in the above.
According to a sixth aspect of the present invention, the output signals of the small amplitude buffer circuit and the leak prevention buffer circuit are the output signal of the small amplitude buffer circuit and the output of the leak prevention buffer circuit. 6. The power consumption reduction circuit according to claim 5, wherein the circuit is a wired OR with a signal.
According to a seventh aspect of the present invention, the output signals of the small amplitude buffer circuit and the leak prevention buffer circuit are connected to the clock input terminal, and the data input signal is connected to the data input terminal. 7. A power consumption reduction circuit according to claim 6, further comprising a D flip-flop.
The gist of the invention described in claim 8 is that the D flip-flop takes in the data input terminal at the rising edge of the clock input terminal, and always holds the held value as the output of the D flip-flop. 8. The power consumption reduction circuit according to claim 7, wherein the power consumption reduction circuit has a circuit configuration for outputting the signal from an output terminal.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The present invention includes a clock circuit having a clock stop circuit in an LSI chip (not shown) clock signal and logical AND gates (hereinafter referred to as a gated buffer circuits working) for outputting a signal of a clock stop signal from By providing a circuit that does not fully swing (hereinafter referred to as a small amplitude buffer circuit) and a circuit that stops leakage when the clock is stopped (hereinafter referred to as a buffer circuit for preventing leakage), power consumption and clock stop during clock operation are provided. It is characterized by reducing power consumption at the time. Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.
[0010]
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram for explaining a power consumption reduction circuit according to the first embodiment of the present invention. In FIG. 1, 1 is a clock, 2 is a clock stop signal, 7 is an AND (logical product) gate, 8 is a small amplitude buffer circuit, 9 is a buffer circuit for preventing leakage, 10 is a D flip-flop, and 13 is an AND (logical product). The output signal of the gate, 14 is the output signal of the small amplitude buffer circuit and the leak prevention buffer circuit, 17 is the data input signal of the D flip-flop, 18 is the output signal of the D flip-flop, and 28 is the circuit of the characteristic part of the present invention. It is.
[0011]
Referring to FIG. 1, the power consumption reduction circuit of the present embodiment has a current gated buffer circuit (AND gate 7) having a clock circuit (not shown) having a clock stop circuit and an intermediate potential when the clock is stopped. provided with a small-amplitude buffer circuit 8 for preventing leakage current of the next stage gate, the enable terminal of the gated buffer circuits working, has a circuit configuration connected to the enable terminal of the leakage preventing buffer circuit 9.
[0012]
Referring to FIG. 1, the signal (clock 1) is a clock signal supplied from the outside. The signal (clock stop signal 2) is a signal for permitting the clock output signal (the output signal 13 of the AND (logical product) gate 7), and means “permit” when it is “H” level, and “L” level. Means prohibition.
[0013]
The AND gate 7 outputs a logical product (output signal 13 of the AND gate 7) of the signal (clock 1) and the signal (clock stop signal 2).
[0014]
The small amplitude buffer circuit 8 converts the level of the signal (the output signal 13 of the AND gate 7) and outputs it as the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9.
[0015]
When the signal (clock stop signal 2) is at "L" level, the leak prevention buffer circuit 9 outputs the signal (the output signal 13 of the AND gate 7) as it is (the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9). To output signal 14). When the signal (clock stop signal 2) is at “H” level, the output is set to Hi-Z (high impedance).
[0016]
The signal (the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9) is a wired OR of the output signal of the small amplitude buffer circuit 8 and the output signal of the leak prevention buffer circuit 9.
[0017]
In the D flip-flop 10, the signal (the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9) is connected to the clock input terminal C, and the signal (the data input signal 17 of the D flip-flop 10) is connected to the data input terminal. Connected to D.
[0018]
The D flip-flop 10 takes in the data input terminal D at the rising edge of the clock input terminal C (“L” level → “H” level), and always holds the held value as a signal (the output signal 18 of the D flip-flop 10). As output from the output terminal Q.
[0019]
FIG. 2 is a configuration example of the small amplitude buffer circuit 8 of FIG. Referring to FIG. 2, the small amplitude buffer circuit 8 includes an inverter (first inverter 15) composed of a P channel transistor 3 and an N channel transistor 4, a P channel transistor 5, a P channel transistor 11, and an N channel transistor 6. And an inverter constituted by an N-channel transistor 12 (second inverter 16 constituting the small amplitude buffer circuit 8). In FIG. 2, reference numeral 36 denotes a first power source.
[0020]
Here, since the gate input of the P-channel transistor 5 and the N-channel transistor 6 is drain-connected, the signals (the output signals 14 of the small amplitude buffer circuit 8 and the leakage prevention buffer circuit 9) are as shown in FIG. The signal is not full swing. The operation of the small amplitude buffer circuit 8 is shown in the timing chart of FIG.
[0021]
FIG. 3 is a configuration example of the leak prevention buffer circuit 9 of FIG. Referring to FIG. 3, the leak preventing buffer circuit 9 includes a fourth inverter 26 including a P-channel transistor 19 and an N-channel transistor 20, a P-channel transistor 21, a P-channel transistor 22, an N-channel transistor 23, and an N-channel transistor 23. A three-state inverter (fifth inverter 27) including a channel transistor 24 and a third inverter 25 is formed.
[0022]
Hereinafter, the operation of the present embodiment will be described. 5 is a timing chart when clock output is permitted in the first embodiment, FIG. 6 is a timing chart when clock output is prohibited in the first embodiment, and FIG. 7 is a clock line. It is explanatory drawing of this shield wiring. FIG. 8 shows an example in which the clock line is used for wiring of the leak prevention buffer circuit 9.
[0023]
First, the operation when the signal (the output signal 13 of the AND gate 7) is permitted will be described.
[0024]
Since the output of the signal (the output signal 13 of the AND gate 7) is in the permitted state, the signal (clock stop signal 2) is at the “H” level.
[0025]
At this time, as shown in the timing chart of FIG. 5, the signal (clock 1) propagates as it is from the AND gate 7 and becomes a signal (the output signal 13 of the AND gate 7).
[0026]
Since the output of the leak prevention buffer circuit 9 is “Hi-Z” (high impedance), the output signal of the small amplitude buffer circuit 8 remains as it is (the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9). Thus, a signal that does not fully swing is input to the clock input terminal C of the D flip-flop 10.
[0027]
If the voltage does not fully swing, an intermediate level potential is applied to the clock input terminal C of the D flip-flop 10, so that the power consumption due to the through current is larger than that during the full swing. However, since the power consumption P due to the charge / discharge current is determined by P = C · f · V ^{2 when the} load capacity C, frequency f, and amplitude voltage V are used, the power consumption due to the charge / discharge current is dominant as the frequency increases. It becomes.
[0028]
Thus, according to the first embodiment, since the voltage is suppressed by a small amplitude, power consumption due to charging / discharging is reduced, and power consumption is reduced as a whole circuit.
[0029]
Next, the operation when the signal (the output signal 13 of the AND gate 7) is prohibited will be described.
[0030]
As described above, since the output of the leak prevention buffer circuit 9 is “Hi-Z” (high impedance), the output signal of the small amplitude buffer circuit 8 is the signal (the small amplitude buffer circuit 8 and the leak prevention buffer circuit). 9, and a signal that does not fully swing is input to the clock input terminal C of the D flip-flop 10.
[0031]
At this time, as shown in the timing chart of FIG. 6, when the clock is stopped, the signal (clock stop signal 2) is at the “L” level.
[0032]
At this time, the AND gate 7 outputs the “L” level to the signal (the output signal 13 of the AND gate 7) regardless of the state of the signal (clock 1). Therefore, the “L” level is input to the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9.
[0033]
Here, since the signal (clock stop signal 2) of the leak prevention buffer circuit 9 is "L" level, the signal (output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9) is set to "L" level. Output.
[0034]
The small amplitude buffer circuit 8 also outputs an intermediate voltage that does not completely become “L” level to the signal (the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9). As a result of the output, the signal (the output signal 14 of the small amplitude buffer circuit 8 and the leak prevention buffer circuit 9) becomes “L” level.
[0035]
As a result, when the signal (the output signal 13 of the AND gate 7) is permitted, it is possible to stop a through current due to generation of an intermediate potential that is likely to increase compared to the conventional gated clock configuration.
[0036]
In this embodiment, since the leak prevention buffer circuit 9 is added to the gated clock, there is a concern that the wiring property is extremely lowered as compared with the conventional technique. However, in recent years, when a circuit is operated at a high frequency, a problem such as crosstalk becomes remarkable in the clock line. As a countermeasure, the clock line is set to the “L” level or “H” level called shield wiring as shown in FIG. Many methods are used to reduce the influence of crosstalk by running wiring with fixed levels in parallel with clock lines. Further, if the shield wiring is used as an enable signal as shown in FIG. 8 for the enable signal line of the leak prevention buffer circuit 9 of the present embodiment, a large wiring is required in the layout even if this embodiment is adopted. It can be realized without causing a decrease in sex.
[0037]
The effects of this embodiment will be described below. As described above, in the present embodiment, the leakage prevention buffer circuit 9 having the buffer circuit by the small amplitude buffer circuit 8 is provided in the clock circuit having the clock stop circuit, thereby reducing the power consumption particularly during high-speed operation. It becomes possible to do.
[0038]
First, the current consumption of the clock buffer of the prior art will be described. FIG. 9 shows a circuit configuration of a conventional clock buffer. FIG. 11 shows the result of comparison between the conventional configuration and the Spice waveform (output waveform from Spice (trademark), which is one of simulation software for electronic circuits) in the present embodiment.
[0039]
Referring to FIGS. 9 and 11, when an input signal (clock 29 supplied from the outside) is input, the output waveform (prior art output signal 30) changes and current (current consumption 32 in the prior art) is generated. To do.
[0040]
Next, current consumption of this embodiment will be described. FIG. 10 shows a circuit configuration of the clock buffer 38 of the present embodiment.
[0041]
Referring to FIGS. 10 and 11, when an input signal (clock 29 supplied from the outside) is input, the output waveform (the output signal 31 of the present embodiment) changes, and the consumption current (the consumption of the present embodiment) is changed. A current 33) is generated. As can be seen from FIG. 11, in this embodiment, since the output waveform does not fully swing, the charge / discharge current decreases. The through current is larger in the present embodiment, but it can be seen that the through current is sufficiently small as compared with the charge / discharge current.
[0042]
This also increases the through current. However, since the effect of reducing the charge / discharge current is greater, the power consumption of the entire circuit is reduced.
[0043]
FIG. 12 shows the relationship between the present invention and a known configuration regarding the relationship between frequency and average current.
Referring to FIG. 12, for example, when comparing 250 MHz, the present embodiment is reduced by about 20% compared to the conventional configuration. Further, the power consumption can be reduced as compared with a method in which the output waveform using the known compare method level conversion circuit 45 (see FIG. 16) does not perform a full swing. Furthermore, since the leak prevention buffer circuit 9 only needs to be able to output the level at the time of clock stop, a large area is not required.
[0044]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description is omitted. FIG. 13 is a functional block diagram for explaining a power consumption reduction circuit according to the second embodiment of the present invention. In FIG. 13, reference numeral 38 denotes a clock buffer.
[0045]
As shown in FIG. 1, the first embodiment is configured by a single power source. On the other hand, in the second embodiment, a leak prevention buffer circuit 9 to which a potential is supplied from a first power supply 36 (see FIGS. 2 and 3) and a second power supply 37 (see FIG. 18 described later). It is characterized in that it comprises a conventional clock buffer to which a higher potential is supplied.
[0046]
FIG. 18 shows a configuration example of a conventional clock buffer. Referring to FIG. 18, the clock buffer includes an inverter composed of a P-channel transistor 47 and an N-channel transistor 48 (an inverter 51 constituting the clock buffer 38), and an inverter composed of a P-channel transistor 49 and an N-channel transistor 50. (Inverter 52 constituting clock buffer 38 (see FIG. 13)).
[0047]
It should be noted that blocks other than the clock buffer (in the case of the present embodiment, the AND gate 7 and the D flip-flop 10) are supplied with a potential from the first power supply 36. Further, the second power source 37 is set lower than the first power source 36.
[0048]
In the present embodiment, the small amplitude buffer circuit 8 is used. However, since the power supply voltage of the conventional clock buffer is low, the output signal (the clock buffer 38 and the leakage prevention buffer circuit 9) can be used even if a normal buffer is used. The output signal 46) has a small amplitude, and the power consumption can be reduced as in the first embodiment.
[0049]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description is omitted. 14 and 15 are operation explanatory diagrams of the power consumption reduction circuit according to the third embodiment of the present invention.
[0050]
In this embodiment, as shown in FIG. 15, a plurality of parallel circuits of a small amplitude buffer circuit 8 and a leak prevention buffer circuit 9 are connected in series. The enable terminal of the leak prevention buffer circuit 9 inputs "H" level when the frequency is high and "L" level when the frequency is low.
[0051]
In the present embodiment, as shown in FIG. 14, the high level is supplied to the enable terminal of the leak prevention buffer circuit 9 at high speed, and the path (clock path 40 at high speed operation) is used as the clock line. So, we tried to reduce power consumption by charging and discharging current.
[0052]
However, as shown in FIG. 12, since the through current of the next stage due to the intermediate potential becomes large at low speed, the conventional configuration as shown in FIG. 9 consumes less power. However, as shown in FIG. 15, the clock is operated at the “L” level at the enable terminal of the leak prevention buffer circuit 9, and the path (the clock path 41 at the low speed in the third embodiment) is set to the clock line. Thus, as in the conventional case, a full-swinged waveform (output signal 13 of the AND gate 7) is output, so that the problem due to the through current is equivalent to the conventional case.
[0053]
As described above, by using this embodiment, it is possible to provide an optimal clock line with the same configuration even in a clock line whose frequency changes from a low frequency to a high frequency.
[0054]
Note that the present invention is not limited to the above-described embodiments, and it is obvious that the above-described embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above embodiments, and can be set to a number, position, shape, and the like that are suitable for carrying out the present invention. Moreover, in each figure, the same code | symbol is attached | subjected to the same component.
[0055]
【The invention's effect】
Since the present invention is configured as described above, the power consumption during the clock operation and the power consumption when the clock is stopped can be reduced.
[Brief description of the drawings]
FIG. 1 is a functional block diagram for explaining a power consumption reduction circuit according to a first embodiment of the present invention.
FIG. 2 is a configuration example of the small amplitude buffer circuit of FIG. 1;
FIG. 3 is a configuration example of the leak prevention buffer circuit of FIG. 1;
FIG. 4 is a timing chart showing the operation of the buffer.
FIG. 5 is a timing chart when clock output is permitted in the first embodiment;
FIG. 6 is a timing chart when clock output is prohibited in the first embodiment;
FIG. 7 is an explanatory diagram of shield wiring of a clock line.
FIG. 8 is an example in which a clock line is used for wiring of a buffer circuit for preventing leakage.
FIG. 9 is a circuit configuration of a conventional clock buffer.
FIG. 10 is a circuit configuration of a clock buffer according to the present embodiment.
11 is a graph comparing the characteristics of FIG. 9 and FIG.
12 is a graph showing the frequency dependence of the average current in FIGS. 9 and 10. FIG.
FIG. 13 is a functional block diagram for explaining a power consumption reduction circuit according to a second embodiment of the present invention.
FIG. 14 is an operation explanatory diagram of a power consumption reduction circuit according to a third embodiment of the present invention.
FIG. 15 is an operation explanatory diagram of the power consumption reduction circuit according to the third embodiment of the present invention.
FIG. 16 is a block diagram of the first prior art described in Japanese Patent Laid-Open No. 5-326866.
FIG. 17 is a configuration diagram of a gated clock disclosed in the second prior art.
FIG. 18 is a configuration example of a conventional clock buffer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Clock 2 ... Clock stop signal 3, 5, 11, 19, 21, 22, 47, 49 ... P channel transistor 4, 6, 12, 20, 23, 24, 48, 50 ... N channel transistor 7 ... AND ( AND gate 8... Small amplitude buffer circuit 9... Leakage prevention buffer circuit 10... D flip-flop 13... AND (logical product) gate output signal 14... Small amplitude buffer circuit and leak prevention buffer circuit output signal 15. First inverter 16 ... second inverter 17 ... data input signal 18 of D flip-flop ... output signal 25 of D flip-flop ... third inverter 26 ... fourth inverter 27 ... fifth inverter 28 ... of the present invention The circuit 29 of the characteristic part ... The clock 30 supplied from the outside ... The output signal 31 of the prior art ... The output signal 32 of the present embodiment ... Current consumption 33 in the next technology Current consumption 36 ... First power supply 37 ... Second power supply 38 ... Clock buffer 40 ... Clock path 41 during high-speed operation ... Clock speed at low speed in the third embodiment Path 42 ... Small amplitude signal 43 supplied from outside ... Full swing clock 44 ... Mesh-like clock line 45 ... Level conversion circuit 46 ... Output signals 51 and 52 of clock buffer and leak prevention buffer circuit Configured inverter C ... clock input terminal D ... data input terminal Q ... output terminal

Claims (8)

A gated buffer circuit composed of an AND gate that outputs a logical product of a clock signal and a clock stop signal in an LSI chip;
A small-amplitude buffer circuit that does not fully swing, and
What is claimed is: 1. A power consumption reduction circuit comprising a leak prevention buffer circuit which is a circuit for stopping leakage when a clock is stopped.  2. The power consumption reduction circuit according to claim 1, further comprising a circuit configuration in which an enable terminal of the gated buffer circuit is connected to an enable terminal of the leak prevention buffer circuit.  The small amplitude buffer circuit has a circuit configuration in which an output signal of an AND gate that performs a logical product of a clock and a clock stop signal is level-converted and output as an output signal of the small amplitude buffer circuit and the leak prevention buffer circuit. The power consumption reduction circuit according to claim 2.  The leak prevention buffer circuit has a circuit configuration that outputs the output signal of the AND gate as it is as an output signal of the small amplitude buffer circuit and the leak prevention buffer circuit when the clock stop signal is at "L" level. The power consumption reduction circuit according to claim 3.  5. The power consumption reduction circuit according to claim 4, wherein the leak prevention buffer circuit sets the output to high impedance when the clock stop signal is at "H" level.  The output signal of the small amplitude buffer circuit and the leak prevention buffer circuit is a wired OR of the output signal of the small amplitude buffer circuit and the output signal of the leak prevention buffer circuit. 5. The power consumption reduction circuit according to 5.  7. The D flip-flop according to claim 6, further comprising: a D flip-flop in which output signals of the small amplitude buffer circuit and the leak prevention buffer circuit are connected to a clock input terminal, and a data input signal is connected to the data input terminal. Power consumption reduction circuit.  The D flip-flop has a circuit configuration in which the data input terminal is fetched at a rising edge of the clock input terminal, and a held value is always output from the output terminal as an output signal of the D flip-flop. The power consumption reduction circuit according to claim 7.

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