JP4541980B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a transistor element that operates at a low power supply voltage by dynamically changing a threshold value, and a semiconductor device including the transistor element. The present invention also relates to a contact formation technique for the transistor element and an element isolation technique suitable for integration of the transistor element.

The power consumption of a circuit (CMOS circuit) in which MOS transistors of different conductivity types are complementarily connected is proportional to the square of the power supply voltage. For this reason, in order to reduce the power consumption of a large scale integrated circuit (LSI) formed by a CMOS circuit, it is effective to reduce the power supply voltage. However, when the power supply voltage is reduced, the driving force of the transistor is reduced, so that an increase in circuit delay time becomes a problem. This problem increases as the power supply voltage is reduced. In particular, it is known that when the power supply voltage drops below three times the threshold voltage (3 × V _th ), the delay time increases significantly.

  One method for improving this is to set the threshold voltage of the transistor low. However, if the threshold value is lowered, there is a problem that the leakage current at the time of gate off increases. For this reason, the lower limit of the threshold voltage is defined by the allowable off-current (leakage current).

  In order to alleviate this problem, a dynamic threshold voltage transistor (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra) has been proposed that effectively lowers the threshold voltage when the gate is turned on. -Low Voltage Operation, F. Assaderaghi et al, IEDM94 Ext. Abst. Pp.809).

  A conventional structure of such a transistor is shown in FIG. FIG. 54 shows an N-channel MOS transistor (NMOS), but it is also possible to configure a P-channel MOS transistor (PMOS) by making the polarity symmetrical. This transistor uses an SOI substrate, and an oversized metal wiring is used to short-circuit the gate electrode and the substrate (silicon layer portion) with a local wiring. In such a structure in which the gate electrode and the substrate are short-circuited, when a bias (gate bias) is applied to the gate electrode, a forward bias having the same magnitude as the gate bias is applied to the active region of the substrate.

  However, in order to suppress the standby current with such a structure, it is necessary to limit the voltage applied to the gate electrode to 0.6 V or less, which is a voltage for turning on the lateral parasitic bipolar transistor. In this way, when the gate is turned off, a bias state similar to that of a normal transistor is formed. When the gate is turned on, the substrate is biased forward as the gate bias increases. As a result, the threshold decreases when the gate is turned on.

As a result, the leakage current when the gate = substrate bias is off is equivalent to that of a normal SOI transistor in the same channel state. When the transistor is on, the threshold voltage further decreases as the gate = substrate bias increases. For this reason, the gate overdrive effect is increased and the driving force is remarkably increased. Suppression of mobility degradation by suppressing the vertical electric field on the substrate surface also contributes to an increase in driving force. Further, since the lateral parasitic bipolar is off, a significant increase in standby current is suppressed.
A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F. Assaderaghi et al, IEDM94 Ext. Abst. Pp.809

  Since the above prior art uses an SOI substrate, the active layer substrate is electrically completely insulated. For this reason, holes generated in the channel (electrons in the case of PMOS) are more likely to accumulate than devices formed on a bulk substrate. As a result, the generation of drain current kinks due to the substrate floating effect and the characteristic history effect become problems. Similarly, since the active layer substrate is electrically insulated, charge-up and ESD (electrostatic damage) that occur during the manufacturing process also become problems. In addition, when using a SIMOX substrate, which has the best crystallinity currently available for SOI, the buried oxide film / substrate interface is more disturbed than the channel side gate oxide / substrate interface. Therefore, characteristic deterioration due to carrier injection and capture to the back surface interface becomes a problem. Further, in the SOI substrate, the film thickness (channel region) of the body is very thin (50 nm to 200 nm) and has a very high resistance. Therefore, even if the gate and the body are short-circuited via the contact, the potential is not easily transmitted to the body as the distance from the contact increases, and the effect as a DTMOS is suppressed.

The semiconductor device of the present invention includes a semiconductor substrate, a first conductivity type deep well region formed in the semiconductor substrate, and a plurality of second conductivity type shallow well regions formed in the deep well region. A source region and a drain region of a first conductivity type formed in each of the plurality of shallow well regions; a channel region formed between the source region and the drain region; and a channel region formed on the channel region. A semiconductor device comprising a gate insulating film and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to the corresponding shallow well region, and the shallow well region is , is electrically isolated from the other shallow well region adjacent the other shallow well region in contact該隣is deeper than the shallow well region said gate electrode corresponding, the deep well region the shallow trench element than Are electrically separated by the child separation structure, the field oxide film so as to cover a portion of the region surrounded by the said groove type element separation structure which is formed, electrical and said gate electrode and said shallow well region The contact region for connection is surrounded by the field oxide film, thereby achieving the above object.

In a preferred embodiment, the gate electrode includes a polycrystalline silicon film formed on the gate insulating film and a metal silicide film formed on the polycrystalline silicon film, and the metal silicide film includes: through the contact region of the shallow well region is electrically connected to the shallow well, the in the contact area, other impurities shallow well region of the same conductivity type as the conductivity type of the shallow well region A high-concentration impurity diffusion region is formed which is diffused with an impurity concentration higher than the impurity concentration of the portion of the portion, and the metal silicide film and the shallow well region are in ohmic contact via the high-concentration impurity diffusion region. .

In a preferred embodiment, the semiconductor device includes an interlayer insulating film provided on the semiconductor substrate and an upper wiring provided on the interlayer insulating film. The interlayer insulating film includes the gate electrode and the gate insulating film. wherein which the contact hole reaching the contact region is formed of the shallow well region through the other portions of the contact area, shallow have shallow impurities of the same conductivity type as the conductivity type of the well region well regions A high-concentration impurity diffusion region is formed which is diffused with an impurity concentration higher than the impurity concentration of the first electrode, and the upper wiring and the shallow well region are ohmic at the bottom of the contact hole via the high-concentration impurity diffusion region. The gate electrode and the upper wiring are ohmically connected at the side wall portion of the contact hole.

In a preferred embodiment, in operation, a potential difference is formed between the potential difference formed between the shallow well region and the source region, and shallow well region and the drain region, both, the semiconductor It is set smaller than the built-in potential of the pn junction in the device.

  In one embodiment, the junction of the source and drain regions and the shallow well region is doped with nitrogen ions or carbon ions.

  In one embodiment, a power supply voltage cut-off circuit is provided between a circuit block constituted by the semiconductor device and a power supply voltage supply source, and the supply of the power supply voltage is cut off when the circuit block is in a standby state.

  In one embodiment, a cutoff circuit is provided between a circuit block configured by the semiconductor device and a power supply voltage supply source, and between the circuit block and a ground voltage supply source, and when the circuit block is in a standby state, Shut off supply of power supply voltage and supply of ground voltage.

  As described above, the present invention provides the following effects.

According to the semiconductor device of the first aspect, it is possible to achieve a high driving force at a low power supply voltage, which is an advantage of the dynamic threshold transistor, while avoiding the above-described problems associated with the SOI substrate.
In addition, since it is possible to efficiently isolate the elements without increasing the size of the isolation region between the transistor elements, the exclusive area per element can be reduced, and the degree of integration can be improved. Effects such as reduction of wiring capacitance and wiring delay time can be obtained.

  According to another aspect of the present invention, there is a bird's beak of the field oxide film in the region where the gate electrode and the element isolation region overlap. Therefore, in the region where the gate electrode overlaps the groove edge, Source region / drain leakage due to the edge portion can be suppressed. Thus, the off-state current of the transistor can be reduced.

  According to the semiconductor device of the second and third aspects, the p-type semiconductor and the n-type semiconductor are connected via the metal silicide film or the metal film. For this reason, it is possible to reliably perform ohmic connection, and it is possible to transmit the potential of the gate electrode to the shallow well region without delay time. The threshold value can be changed dynamically without delay time.

  According to the semiconductor device of the fourth aspect, the PN junction forward current can be reduced as much as possible, the leakage current unrelated to the drive current can be suppressed, and the power consumption can be reduced.

  According to the semiconductor device of the fifth aspect, since the PN junction forward current can be further suppressed by increasing the value of the built-in potential, the power consumption can be further reduced.

  According to the semiconductor devices of the sixth and seventh aspects, since the power supply during standby can be shut off, the power consumption can be further reduced.

  The present invention has the greatest feature in that a shallow well region is formed and the shallow well region is electrically connected to the gate electrode in order to dynamically change the threshold voltage Vt of the transistor in accordance with the gate potential. have.

  In general, when polycrystalline silicon doped with an impurity is used as the material of the gate electrode, the conductivity type of the impurity is opposite to the conductivity type of the impurity doped in the shallow well region. Therefore, to realize the present invention, a technique for forming a low-resistance ohmic contact between the gate electrode and the shallow well region is required. In the present invention, such a contact is formed mainly by using silicide.

  Further, when considering a plurality of transistor elements that are in a relationship in which different voltages can be applied to the gate electrode at a certain time, the shallow well regions of these transistor elements need to be electrically isolated from each other. Typically, one shallow well region is assigned to one transistor element, and the shallow well regions are separated. For this reason, in order to integrate the transistor elements of the present invention at a high density, a technique for efficiently separating adjacent shallow well regions is required. In the present invention, the shallow well region is isolated by the trench isolation structure.

  In this specification, the “shallow well region” refers to a well region in which a source region / drain region is formed and is electrically connected to a gate electrode. In contrast, the “deep well region” is a well region having a pn junction deeper than the pn junction of the “shallow well region”, and has a conductivity type opposite to that of the shallow well region, and has at least one conductivity type. A well region having two shallow well regions therein is called.

  Reference Example 1 A first reference example (an example having a LOCOS isolation structure) of a semiconductor device of the present invention will be described with reference to FIGS. 1 (a) to 1 (d). 1A is a plan view of the present reference example, and FIGS. 1B, 1C and 1D are cross-sectional views taken along line bb ′ and line cc ′ of FIG. 1A, respectively. It is sectional drawing and dd 'line sectional drawing.

  In the semiconductor device of this reference example, a “deep well region 102” is provided in the semiconductor substrate 101, and a “shallow well region 103” is provided in the deep well region 102. The conductivity type of the shallow well region 103 is opposite to that of the deep well region and is the same as the conductivity type of the semiconductor substrate 101.

  In this reference example, the MOS transistor according to the present invention is formed in the shallow well region 103. More specifically, this MOS transistor includes a source region / drain region 107 formed in a shallow well region, a channel region formed between the source region / drain region 107, and a gate insulating film 105 covering the channel region. And a gate electrode 106 formed on the gate insulating film 105. A part of the gate electrode 106 is electrically connected to the shallow well region 103 through a contact hole 108 formed in the gate insulating film 105.

  In the drawing, for the sake of simplicity, one MOS transistor is shown, but actually, a plurality of MOS transistors are formed in one semiconductor substrate 101. The illustrated shallow well region 103 is electrically isolated from a shallow well region (not shown) of another adjacent MOS transistor by an element isolation oxide film 104.

  With the above structure, a variable threshold transistor can be realized without using an SOI (Silicon On Insulator) substrate.

Here, the relation between the inversion threshold voltage V _th (hereinafter sometimes abbreviated as “threshold”) of the MOS transistor and the bias (V _S-well ) of the shallow well region is a simplified expression. This is expressed by the following formula (1).

Here, Φ _b is Fermi potential, N _S-well is the impurity concentration of the shallow well region, ε _S is the dielectric constant of the shallow well region, q is the charge amount of electrons, C _OX is the gate insulating film capacitance per unit area, V _FB is a flat band voltage. From the above equation (1), it can be seen that the absolute value of the threshold voltage is small when the shallow well region is biased in the forward direction.

The simplified driving current equation is expressed by the following equation (2) in the linear region.

Further, in the saturation region, it is expressed by the following formula (3).

Here, I _D is the drain current, W is the gate width, L is the gate length, μ _eff is the effective mobility, and V _G is the gate voltage.

  The graph of FIG. 3 shows the relationship between the gate voltage and the drain current when the potential of the shallow well region is changed. Here, the “gate voltage” refers to the potential of the gate electrode with respect to the potential of the source region.

Since the drive current is expressed as in equations (2) and (3), if the absolute value of the threshold voltage (V _th ) is reduced, a large drive current can be obtained with a dramatically lower power supply voltage. Become.

  In this structure, since the gate electrode and the shallow well region are connected, the potential of the shallow well region is displaced as the gate potential is displaced. Therefore, as is apparent from the above equation, the gate potential increases, the shallow well region is forward-biased with respect to the source region / drain region, and the apparent threshold voltage decreases. As a result, a large drive current can be obtained even with a low power supply voltage.

  Thus, in this structure, since the gate potential and the potential of the shallow well region match, a forward bias is applied to the pn junction formed between the shallow well region and the source region (and drain region). More specifically, in the case of an n-channel transistor, the potential of the source region is equal to the GND potential, and the potential of the shallow well region is equal to the gate potential. On the other hand, in the case of a p-channel transistor, the potential of the source region is equal to the power supply voltage, and the potential of the shallow well region is equal to the gate potential. In order not to increase the forward current, it is necessary to keep the voltage between the well region and the source region (or the voltage between the well region and the drain) below the built-in potential of the pn junction. When these voltages exceed the built-in potential, a pn junction diode forward current flows between the shallow well region and the source region (or drain region). When the potential of the shallow well region is raised to the vicinity of the built-in potential, a pn junction diode forward current of a level that cannot be ignored flows, so that the potential of the well region is lowered by about 0.1 to 0.3 V with respect to the built-in potential. It is desirable to set the power supply voltage.

  FIG. 4 shows the relationship between the gate potential of the transistor having this structure and the drive current. From this figure, it can be seen that the slope S value of the curve in the subthreshold region (the amount of displacement of the gate potential required to increase the drive current by one digit) is about 60 mV / dec. According to this structure, a large driving current can be obtained by a small change in the gate potential as compared with the S value (80 mV / dec to 100 mV / dec) of a transistor having a normal structure.

In this reference example, the impurity concentration of the deep well region is set to about 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁷ / cm ^3, and the impurity concentration of the shallow well region is 5 × 10 ¹⁶ / cm ^{3 to} 5 It is set to × 10 ¹⁷ / cm ^3. The depth of the shallow well region is set to 250 nm to 1000 nm. The impurity concentration of the source region / drain region is set to about 1 × 10 ²⁰ / cm ³ or more, and the junction depth is set to 50 nm to 300 nm. In order to suppress the short channel effect of the transistor, it is better to make the junction depth of the source region / drain region as shallow as possible and to make the gate oxide film thinner.

  Next, an improved example of the reference example of FIGS. 1 (a) to (d) will be described with reference to FIGS. 2 (a) to 2 (d). In this improved example, a “deep well region 102 ′” is provided in the semiconductor substrate 101 ′, and a “shallow well region 103 ′” is provided in the deep well region. The conductivity type of the shallow well region 103 ′ is opposite to that of the deep well region, and is the same as the conductivity type of the semiconductor substrate 101 ′.

  More specifically, this MOS transistor includes a source region / drain region 107 ′ formed in a shallow well region, a channel region formed between the source region / drain region 107 ′, and gate insulation covering the channel region. A film 105 ′ and a gate electrode 106 ′ formed on the gate insulating film 105 ′ are provided. The gate electrode 106 ′ is electrically connected to the shallow well region 103 ′ through a contact hole 108 ′ formed in the gate insulating film 105.

  The illustrated shallow well region 103 ′ is electrically isolated from a shallow well region (not shown) of an adjacent MOS transistor by an element isolation oxide film 104 ′.

  In this improved example, the element isolation oxide film 104 ′ is also present between the region where the contact between the gate electrode and the shallow well region is formed and the region where the source region / drain region is formed. Yes.

  Reference Example 2 A second reference example of the semiconductor device according to the present invention will be described below. Here, an example in which a parasitic bipolar transistor contributes to the operation of the transistor will be described.

  FIG. 5 is a diagram schematically showing the wiring of the transistor element and the parasitic bipolar transistor in this reference example. Here, an n-channel MOS transistor and a parasitic npn transistor will be described, but by making the polarity symmetric (reverse), an equivalent can be considered for a p-channel MOS transistor and a parasitic pnp bipolar.

In this reference example, the source region of the MOS transistor is connected to GND, the gate electrode is connected to the input V _IN , and the drain region is connected to the output V _OUT . The potential of the shallow well region is V _s-well and the potential of the deep well region is V _d-well .

In the semiconductor device of this reference example, as shown in FIG. 2, three parasitic bipolar transistors indicated by Tr1, Tr2, and Tr3 are formed separately from the MOS type transistors. The direction of the operating current of these parasitic bipolar transistors is shown in Table 1 below.

  The direction of the arrow indicating “current direction” in Table 1 corresponds to the direction of the arrow in FIG. 5. The symbol ◯ in Table 1 indicates a case where the MOS type transistor of this reference example operates to assist its operation, and the symbol Δ indicates a case where a leakage current unrelated to the operation of the MOS type transistor is generated. The symbol x indicates a case where the operation is performed so as to hinder the operation of the MOS transistor.

For example, when the potential of the deep well region (V _d-well ) is fixed at the level of the power supply voltage (V _DD ) and the voltage of V _DD is input to the gate electrode, the parasitic bipolar transistor Tr3 operates as an MOS transistor. Try to work to hinder. In other words, the MOS-type transistor tries to keep (maintain) the output (V _out ) as GND, whereas the parasitic bipolar transistor Tr3 tries to maintain (maintain) the output (V _out ) as the power supply voltage V _DD. Behave. In this case, the parasitic bipolar transistor Tr2 operates so as to generate a leakage current unrelated to the element operation.

Therefore, when the potential (V _d-well ) of the deep well region is fixed to the power supply voltage (V _DD ), it is necessary to design the parasitic bipolar transistors Tr2 and Tr3 so that they do not flow much current. According to the experiments of the present inventor, if the base width of the parasitic bipolar transistors Tr2 and Tr3 is set to 200 nm or more and the impurity concentration of the pace portion is set to 2 × 10 ¹⁷ cm ³ or less, the on-current of the MOS transistor is reduced. The current of the parasitic bipolar transistor could be suppressed to a negligible level. Here, the “base width” means a distance from the lower end of the source / drain region to the lower end of the shallow well region.

When the potential (V _d-well ) applied to the deep well region is set to the GND level, the parasitic bipolar transistor works in the direction of assisting the MOS transistor in all input / output relationships. At this time, the semiconductor element of FIG. 5 can flow a current that is a sum of the dynamic threshold transistor current and the parasitic bipolar transistor current. For this reason, when the configuration that positively operates the operation of the parasitic bipolar transistor is adopted, it is possible to obtain a larger driving force than a single dynamic threshold transistor element that does not exhibit the parasitic bipolar operation. .

  Reference Example 3 In the semiconductor device of Reference Example 1, the element isolation structure is formed of a field oxide film. When the element isolation structure is formed of a field oxide film, a very large element isolation region is required to isolate adjacent shallow well regions. For this reason, element isolation using a field oxide film causes an increase in the area occupied by each transistor element on the silicon substrate, and is not suitable for high integration of elements.

  Hereinafter, a reference example having a groove type element isolation structure will be described with reference to FIGS. 6A is a plan view of the present reference example, FIGS. 6B, 6C, and 6D are cross-sectional views taken along line bb ′ and line cc ′ of FIG. 6A, respectively. It is sectional drawing and dd 'line sectional drawing.

  In the semiconductor device of this reference example, the “deep well region 302” is provided in the semiconductor substrate 301, and the “shallow well region 303” is provided in the deep well region. The conductivity type of the shallow well region 303 is opposite to that of the deep well region, and is the same as the conductivity type of the semiconductor substrate 301.

  The MOS transistor of this reference example is formed in the shallow well region 303. More specifically, this MOS transistor includes a source region / drain region 307 formed in a shallow well region, a channel region formed between the source region / drain region 307, and a gate insulating film 305 covering the channel region. And a gate electrode 306 formed on the gate insulating film 305. The gate electrode 306 is electrically connected to the shallow well region 303 through a contact hole 308 formed in the gate insulating film 305.

  At least the shallow well region is electrically isolated from the shallow well region of the adjacent transistor element by the trench type element isolation structure 304.

  The lateral size of the region necessary for forming the grooved element isolation structure is about the minimum processing dimension. Therefore, it is possible to perform separation between adjacent transistor elements only in a small region of the minimum processing dimension, and without using an SOI substrate and without sacrificing the degree of integration, the variable threshold value can be obtained. A type MOS transistor can be realized.

  (Embodiment 1) FIGS. 7A to 7D show an improved example of the reference example 3. FIG. In this improved example, a field oxide film 3041 is formed on an inactive region on a trench type element isolation structure type silicon substrate. The illustrated structure is covered with an interlayer insulating film (not shown), and an upper wiring is formed thereon. By providing the field oxide film 3041, the parasitic capacitance between the upper wiring and the semiconductor substrate can be reduced.

  Hereinafter, this improved example will be described. In this improved semiconductor device, a “deep well region 302 ′” is provided in the semiconductor substrate 301 ′, and a “shallow well region 303 ′” is provided in the deep well region. The conductivity type of the shallow well region 303 'is opposite to that of the deep well region and is the same as that of the semiconductor substrate 301'.

  The MOS transistor of this embodiment is formed in the shallow well region 303 '. More specifically, this MOS transistor includes a source region / drain region 307 ′ formed in a shallow well region, a channel region formed between the source region / drain region 307 ′, and gate insulation covering the channel region. A film 305 ′ and a gate electrode 306 ′ formed on the gate insulating film 305 ′ are provided. The gate electrode 306 ′ is electrically connected to the shallow well region 303 ′ through a contact hole 308 ′ formed in the gate insulating film 315 ′.

  At least the shallow well region is electrically isolated from the shallow well region of the adjacent transistor element by the trench type element isolation structure 304 ′ and the field oxide film 3041.

  (Embodiment 2) In order to reduce the capacitance formed between the upper wiring formed on the interlayer insulating film and the semiconductor substrate, in the semiconductor device of Embodiment 1, oxidation is performed on the inactive region on the silicon substrate. A film 3041 is formed. In the present embodiment, a case will be described in which another configuration that achieves the same object is provided.

  Hereinafter, this embodiment will be described with reference to FIGS. 8A is a plan view of the present embodiment, FIGS. 8B, 8C, and 8D are cross-sectional views taken along line bb ′ and line cc ′ of FIG. 8A, respectively. It is sectional drawing and dd 'line sectional drawing.

  In the semiconductor device of this embodiment, the “deep well region 402” is provided in the semiconductor substrate 401, and the “shallow well region 403” is provided in the deep well region. The conductivity type of the shallow well region 403 is opposite to that of the deep well region and is the same as the conductivity type of the semiconductor substrate 401.

  The MOS transistor of this embodiment is formed in the shallow well region 403. More specifically, this MOS transistor includes a source region / drain region 407 formed in a shallow well region, a channel region formed between the source region / drain region 407, and a gate insulating film 405 covering the channel region. And a gate electrode 406 formed on the gate insulating film 405. The gate electrode 406 is electrically connected to the shallow well region 403 through a contact hole 408 formed in the gate insulating film 405. At least the shallow well region is electrically isolated from the shallow well region of the adjacent transistor element by the grooved element isolation structure 404.

  In this embodiment, the field oxide film 4041 extends partially also on the region surrounded by the trench type element isolation structure 404. Therefore, the channel width (W) of this embodiment is determined not by the trench type element isolation structure 404 but by the field oxide film 4041. More specifically, the channel width (W) of the transistor is determined by the distance d of the field oxide film. In the embodiment shown in FIGS. 7A to 7D, when misalignment occurs between the element isolation trench and the gate electrode, the channel width (W) of the transistor is shifted from the design value. However, in this embodiment, even if such misalignment occurs, the channel width (W) of the transistor does not shift from the design value. For this reason, the transistor characteristics are hardly changed by the manufacturing process.

  In addition, a bird's beak is present in the overlap region of the gate electrode and the element isolation region (region A in FIG. 8D) instead of the edge portion of the trench. For this reason, it is possible to suppress the leakage between the source region and the drain caused by the edge portion of the groove.

  However, it is disadvantageous for high integration. A method for suppressing bird's beaks will be described in Examples 28 and later.

  (Embodiment 3) A contact structure for ohmic connection between a gate electrode and a shallow well region in a transistor element according to the present invention will be described below.

  In a MOS transistor having a buried channel, the gate electrode (semiconductor layer) and the shallow well region have the same conductivity type, and therefore a contact hole is formed in the gate oxide film to form the gate electrode (semiconductor layer). An ohmic contact is formed even if the shallow well region is directly connected. However, in the surface channel type MOS transistor, the gate electrode (semiconductor layer constituting the gate electrode) and the shallow well region are of opposite conductivity type, so that the gate electrode (semiconductor layer constituting the gate electrode) is directly used as the shallow well region. Even if connected, a PN junction is formed and no ohmic contact is formed.

Therefore, in the present invention, when the gate electrode and the shallow well region are connected, the metal silicide film and the shallow well region are connected between the gate electrode and the shallow well region so that the gate electrode and the shallow well region can be ohmic connected to any conductivity type. A region having the same conductivity type as the well region and a high impurity concentration is provided. In other words, the gate electrode is electrically connected to the shallow well region in the order of “gate electrode” → “metal silicide layer” → “region with high impurity concentration and the same conductivity type as the shallow well region” → “shallow well region”. is doing. Here, if the impurity concentration of the “region having the same impurity type as that of the shallow well region having a high impurity concentration” is set to 1 × 10 ²⁰ / cm ³ or more, the “metal silicide layer” and the “shallow well region” are ohmic. It becomes possible to connect. Since the impurity concentration of the “gate electrode” is originally high (usually 1 × 10 ²⁰ / cm ³ or more), it can be directly connected to the metal silicide film by ohmic contact.

  If a silicide film is directly connected to a shallow well region without providing a region having the same impurity type as that of a shallow well region having a high impurity concentration, a metal semiconductor Schottky junction is formed. No longer formed.

  FIG. 9A is a cross-sectional view showing the basic structure of the ohmic contact structure according to the present invention. 9B to 9E are application examples of the ohmic contact structure, and various element isolation structures are shown. However, the element isolation structure is not limited to the groove type element isolation and the field oxide film as in this embodiment.

  Here, 51, 510, 511, 512, 513 are deep well regions, 52, 520, 521, 522, 523 are shallow well regions, 53, 530, 531, 532, 533 are gate oxide films, 54, 540, 541, 542, 543 are gate electrodes, 55, 550, 551, 552, 553 are gate electrode side wall oxide films, 56, 560, 561, 562, 563 are metal silicide films, 57, 570, 571, 572 and 573 are regions having the same conductivity type as a shallow well region having a high impurity concentration, 580, 592 and 593 are field oxide films, and 581, 582 and 583 are groove type isolation structures.

  (Embodiment 4) A contact structure for ohmic connection between a gate electrode and a shallow well region in the present invention will be described with reference to FIG.

  As described above, in the surface channel type MOS transistor, since the gate electrode and the shallow well region are of the reverse conductivity type, even if they are connected as they are, a PN junction is formed and no ohmic contact is formed. Therefore, in the present invention, the gate electrode and the shallow well region can be connected in any ohmic manner. Specifically, an upper metal wiring 619 is provided on the upper portion of the semiconductor device via an interlayer insulating film 616, and the interlayer insulating film 616 penetrates through the gate electrode 614 and the gate oxide film 613 to reach the shallow well region 612. A hole 618 is provided. The gate electrode 614 and the upper metal wiring 619 are ohmically connected at the side wall of the contact hole 618. At the bottom of the contact hole 618, the upper metal wiring 619 and the shallow well region 612 are ohmically connected through a region 617 of the same conductivity type and high impurity concentration as the shallow well region.

  Here, 611 is a deep well region having a conductivity type opposite to that of the shallow well region, and 615 is a gate side wall oxide film.

According to this structure, the upper metal wiring 619 and the shallow well region 617 are ohmically connected by setting the impurity concentration of the high conductivity region 617 of the same conductivity type as that of the shallow well region to 1 × 10 ²⁰ / cm ³ or more. It becomes possible to do. Since the gate electrode 614 originally needs to have an impurity concentration of 1 × 10 ²⁰ / cm ³ or more in order to prevent the gate electrode from being depleted, the upper metal wiring 619 and the gate electrode 614 can be connected to each other directly to make an ohmic connection. Accordingly, the gate electrode 614 and the shallow well region 612 can be ohmically connected via the upper metal wiring 619.

  As an application example of this embodiment, there is a method as shown in FIG. In this method, for example, when it is desired to form the upper wiring metal 629 using an aluminum-based material that does not contain silicon (not limited to the aluminum-based material, any metal that reacts with silicon) may be used. For example, the silicon substrate and the aluminum-based material react vigorously due to, for example, sintering, and a spike 6291 is generated. For this reason, the shallow well region and the upper metal wiring 629 can be ohmic-connected. In this case, the region 627 having the same conductivity type and high impurity concentration as that of the shallow well region may be omitted, but the presence thereof can more reliably form the ohmic contact. Further, by forming the gate electrode with a two-layer polycide film of a polycrystalline silicon film 624 and a metal silicide film 6241, the contact resistance between the upper metal wiring 629 and the gate electrode can be further reduced.

  As a more general method, there is a method shown in FIG. In this method, after a structure having a polycide structure gate electrode (in this embodiment, a two-layer structure of a titanium silicide film 6341 and a polycrystalline silicon film 634) is formed, an interlayer insulating film 636 is deposited. After a contact hole 638 reaching the silicon substrate is opened in the interlayer insulating film 636, titanium 6391, titanium nitride 6392, and upper metal wiring 6393 are sequentially deposited. In this embodiment, titanium 6391 (thickness: 30 to 50 nm) and titanium nitride (thickness: about 500 to 1000 nm) are deposited. Thereafter, annealing in a nitrogen atmosphere is performed at 700 ° C. for about 20 seconds. By this annealing treatment, the titanium film 6391 reacts with the titanium silicide film 6341 and the polycrystalline silicon film 634 of the polycide gate electrode, and reacts with the silicon substrate (the region 637 having the same conductivity type as the shallow well region). To do. In this way, since the titanium silicide film 63911 is formed, the gate electrode and the shallow well region 632 can be ohmically connected with low resistance. In this embodiment, Al—Si (1%) — Cu (0.5%) is used as the material of the upper metal wiring 6393, but the metal wiring material is not limited to this. The silicide film of the gate electrode having a polycide structure is not limited to the titanium silicide film, but may be another refractory metal silicide film such as cobalt silicide. In FIGS. 11D to 11F, an element isolation structure is combined with the structure of FIG. 10C. However, this element isolation structure is not limited to the groove type element isolation and / or the field oxide film as in this embodiment.

  Here, 621, 631, 641, 651, 661, and 671 are deep well regions, 622, 632, 642, 652, 662, and 672 are shallow well regions, and 623, 633, 643, 653, 663, and 673 are gate oxide films. 624, 634, 644, 654, 664 and 674 are polycrystalline silicon films, 6241, 6341, 6441, 6541, 6641 and 6741 are titanium silicide films, and 625, 635, 645, 655, 665 and 675 are gate electrode side wall oxides. 626, 636, 646, 656, 666, 676 are interlayer insulating films, 621, 631, 641, 651, 661, 671 are regions having the same conductivity type as a shallow well region having a high impurity concentration, 628, 638, 648, 658, 668, and 678 are contact holes, 629 is Al-Cu (0.5%) wiring, 6 91 is an aluminum alloy spike, 6391, 6491, 6591, 6691, and 6791 are titanium films, 63911, 64911, 65911, 66911, and 67911 are titanium silicide films, 6392, 6492, 6592, 6692, and 6792 are titanium nitride films, 6393, 6493 , 6593, 6693 and 6793 are Al-Si (1%)-Cu (0.5%) wirings, 6400, 6601 and 6701 are field oxide films, and 6500, 6600 and 6700 are groove-type isolation structures.

  (Embodiment 5) A method for forming a contact structure in Embodiment 3 will be described in detail with reference to FIGS. 12 (a) to 12 (e). A case where the structure shown in FIG. 9E is adopted as the element isolation structure will be described.

  First, as shown in FIG. 12A, after forming a shallow well region 702, a groove-type element isolation structure 703, and a field oxide film region 704 in a semiconductor substrate in which a deep well region 701 is formed, the shallow well region is formed. Impurity ion implantation or the like for threshold control is performed on the surface 702. Thereafter, a gate oxide film 705, a gate electrode 706, and a gate sidewall oxide film 707 are formed by a known method.

In this embodiment, the impurity concentration in the deep well region is set to 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ , and the impurity concentration in the shallow well region is set to 1 to 2 × 10 ¹⁷ / cm ³ . did. The depth of the shallow well region was set to 300 to 700 nm.

A source / drain region (not shown) was formed to have a diffusion depth of 50 to 70 nm so as to have an impurity concentration of 1 × 10 ²⁰ / cm ³ or more. The thickness of the gate oxide film 705 is 3 nm. The gate electrode 705 was formed from a polycrystalline silicon film, and the impurity concentration was set to 1 × 10 ²⁰ / cm ³ or more. The trench element isolation structure 703 needs to be set sufficiently deep with respect to the shallow well region 702, and is desirably shallower than the deep well region. In this embodiment, the depth of the deep well region 701 is set to 2 μm or more, and the depth of the trench element isolation structure 703 is set to 1 to 2 μm.

  The above numerical values are only examples used in the present embodiment, and the present invention is not limited to this. These values such as impurity concentration and diffusion depth vary depending on the transistor design.

  In the transistor of this example, the gate length (channel length) is set to 0.18 μm. The deep well region 701, the source / drain regions (not shown), and the gate electrode 706 are of the same conductivity type, and are of the opposite conductivity type to the shallow well region 702.

Next, as shown in FIG. 12B, a desired portion of the gate electrode 705 is etched by RIE using a resist 708 formed by lithography as a mask, and a contact hole 709 reaching the shallow well region 702 is formed in this portion. Form. Thereafter, an impurity having the same conductivity type as that of the shallow well region 702 is implanted by an ion implantation process, so that a region 710 having a higher concentration than the shallow well region 702 is formed. In this ion implantation process, for example, when the shallow well region 702 is a p-type semiconductor, boron ions are implanted at an acceleration voltage of 5 to 10 keV with an implantation amount of 1 to 5 × 10 ¹⁵ / cm ² to form a shallow well. When the region 702 is an n-type semiconductor, arsenic ions are implanted at an accelerating voltage of 10 to 30 keV with an implantation amount of 1 to 5 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 12C, titanium metal 711 is deposited. In this example, a film thickness of 20 nm to 50 nm was deposited in an argon gas by sputtering.

  Next, as shown in FIG. 12 (d), a first rapid heat treatment is performed for about 10 to 20 seconds in a nitrogen atmosphere in the range of 600 ° C. to 700 ° C. to react the titanium metal 711 with silicon to form titanium. A silicide film 712 is formed. At this time, part of the impurity implanted into the contact portion is activated by the first rapid heating process.

  As shown in FIG. 12 (e), after selectively removing the unreacted and nitrided titanium metal film, the second rapid heat treatment in a nitrogen atmosphere in the range of 800 ° C. to 1000 ° C. for about 10 to 20 seconds. The silicide film 712 is changed to a low-resistance C54 crystal structure and the impurities implanted in the contact portion are activated.

  According to the method of this embodiment, the gate electrode 706 and the shallow well region 702 can be easily connected by the silicide film 712. The process for forming the silicide film 712 is basically the same as the salicide process. Therefore, when a salicide transistor is formed, as a special process, a process for forming a contact hole 709 and a process for forming a high-concentration region 710 are only added, and the number of processes as a whole does not increase greatly.

  In the above embodiment, impurity ions are implanted into the contact with the surface of the silicon substrate (the surface of the shallow well region 702) exposed, so that contaminants from the resist contaminate the surface of the silicon substrate (the shallow well region 702). there's a possibility that. However, it is not for forming a junction (at the time of ion implantation for forming a junction, contaminants form deep levels and act as recombination centers, so junction leakage increases, which is not good). So you do n’t have to worry too much.

  Further, when the silicon substrate surface (shallow well region 702) is damaged by contact etching, the gate oxide film at the bottom of the contact hole is exposed by RIE with a high etching selectivity between the polycrystalline silicon film and the silicon oxide film. The etching may be terminated, and the gate oxide film 705 may be removed with a hydrofluoric acid solution or an oxide film etching system RIE.

  If contamination from the resist is a concern, etching for contact formation is performed at the stage where the gate oxide film 705 at the bottom of the contact hole is exposed by RIE with a high etching selectivity between the polycrystalline silicon film and the silicon oxide film. The etching may be terminated and the gate oxide film 705 may be left, and impurity ions may be implanted into the contact through the gate oxide film 705. However, in this method, oxygen is knocked on from the gate oxide film 705 to the surface of the shallow well region 702 at the time of ion implantation, so that this knock-on oxygen has an adverse effect at the time of silicidation reaction, and the film quality of the silicide film is deteriorated.

  (Embodiment 6) Another method for forming a contact structure for connecting a gate electrode and a shallow well region will be described with reference to FIGS. 13 (a) to 13 (e) and FIGS. 14 (a) to 14 (c). Here, a method will be described in which there is no resist contamination and no knock-on oxygen contamination in silicidation compared to Example 5.

First, as shown in FIG. 13A, as in FIG. 12A, a shallow well region 802, a trench type element isolation structure 803, a field oxide film region are formed in a semiconductor substrate in which a deep well region 801 is formed. After forming 804, impurity ion implantation or the like for threshold control is performed. Thereafter, a gate oxide film 805, a gate electrode 806, and a gate sidewall oxide film 807 are formed by a known method. In this embodiment, the impurity concentration in the deep well region is set to 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ , and the impurity concentration in the shallow well region is set to 1 to 2 × 10 ¹⁷ / cm ³ . The depth of the shallow well region was set to 300 to 700 nm. The impurity concentration of the source / drain region (not shown) is set to 1 × 10 ²⁰ / cm ³ or more, and the junction depth is set to 50 to 70 nm.

The gate oxide film is 3 nm, and the gate electrode is formed from a polycrystalline silicon film. The concentration of is set to 1 × 10 ²⁰ / cm ³ or more. Further, the trench type element isolation structure 803 needs to be set sufficiently deep with respect to the shallow well region 802 and is desirably shallower than the deep well region. In this embodiment, the depth of the deep well region 801 is set to 2 μm or more, and the depth of the trench element isolation structure 803 is set to 1 to 2 μm.

  These numerical values are values that we used for trial manufacture in the examples, and are not limited thereto. These numerical values of concentration and depth vary depending on the transistor design. In our transistor, the gate length is set to 0.18 μm. Note that the deep well region 801, the source / drain regions (not shown in the drawing), and the gate electrode 806 have the same conductivity type, and the shallow well region 802 has the opposite conductivity type.

  Next, as shown in FIG. 13B, using the photoresist 808 as a mask, a contact hole 809 reaching the shallow well region 802 to a desired region of the gate electrode is formed by RIE. When the surface of the silicon substrate (shallow well region 802) is damaged by contact etching, the etching is performed when the gate oxide film at the bottom of the contact hole is exposed by RIE with a high etching selectivity between the polycrystalline silicon film and the silicon oxide film. Then, the gate oxide film 805 may be removed with a hydrofluoric acid solution or an oxide film etching system RIE.

  Next, as shown in FIG. 13C, the photoresist 808 is removed and a silicon nitride film 810 is deposited. In this embodiment, a film thickness of about 2 to 5 nm is deposited by the LPCVD method.

Next, as shown in FIG. 13D, masking is performed with a photoresist 811 and ion implantation is performed at the bottom of the contact hole 809 (in this embodiment, when the shallow well region 802 is a p-type semiconductor, 1 boron ion is used. When the implantation dose is ˜5 × 10 ¹⁵ / cm ² and the energy is an acceleration voltage of 5 to 10 keV, and the shallow well region 802 is an n-type semiconductor, arsenic ions are implanted at 1 to 5 × 10 ¹⁵ / cm ^2. A region 812 having a higher concentration than that of the shallow well region 802 and the shallow well region 802 of the same conductivity type is formed. In the ion implantation through the silicon nitride film 810, not oxygen but nitrogen is knocked on, so that the silicidation reaction in the subsequent process can be controlled well.

  As for the relationship between the photoresist 811 (ion implantation mask) and the contact hole 809, the photoresist 811 needs to be widened with respect to the contact hole 809 by a margin (distance d) of misalignment. At this time, since an impurity having the same conductivity type as that of the shallow well region 802 is implanted into a part of the gate electrode, the gate electrode 806 originally has a conductivity type opposite to that of the shallow well region 802 in the case of a surface channel MOS transistor. Therefore, depending on the original impurity concentration of the gate electrode, only the region where the gate electrode is contact-implanted is close to the intrinsic semiconductor or has the same conductivity type as the shallow well region 802, and the PN junction is connected to the worst gate electrode. Is formed. However, since the gate electrode is silicided in a later process, there is no problem in ohmic connection.

  Next, as shown in FIG. 13E, after the photoresist 811 is removed, titanium metal 813 is deposited as shown in FIG. 14A. In this example, a film thickness of 20 nm to 50 nm was deposited in an argon gas by a sputtering method.

  Next, as shown in FIG. 14B, a first rapid heat treatment is performed for about 10 to 20 seconds in a nitrogen atmosphere in the range of 600 ° C. to 700 ° C. to react the titanium metal 813 with silicon to form titanium. A silicide film 814 is formed. At this time, part of the impurities implanted into the contact portion is activated by the first rapid heating process.

  As shown in FIG. 14 (c), after selectively removing the unreacted and nitrided titanium metal film, a second rapid heat treatment in a nitrogen atmosphere at a temperature of 800 ° C. to 1000 ° C. for about 10 to 20 seconds. The silicide film 814 is changed to a low-resistance C54 crystal structure and the impurities implanted in the contact portion are activated. In this embodiment, nitrogen, not oxygen, is knocked on in silicon, so that nitrogen, not oxygen, segregates at the grain boundary of the silicide film in the silicidation reaction, and the heat resistance of the silicide film is improved. In addition, entry of contaminants from the photoresist can be prevented by the silicon nitride film 810 which is an implantation protective film, so that contamination is small.

  Further, when priority is given to process simplification, impurity ions may be directly implanted without depositing the silicon nitride film 810. However, as described above in the fifth embodiment, contamination is caused at the time of implantation.

  In this embodiment, the implantation mask formation process for selectively implanting impurity ions into the contact formation region is increased once compared to the fifth embodiment. However, when a complementary MOS structure is formed, it is necessary to perform ion implantation separately for an n-channel transistor and a p-channel transistor. Therefore, in total, an implantation mask forming process is performed at least twice. . For this reason, when ion implantation is performed to the contact formation region using the contact formation implantation mask as in the fifth embodiment, separate contact holes are opened for the contact of the n-channel transistor and the contact of the p-channel transistor, respectively. Need to occur.

  Considering these points, in the case of the complementary MOS structure, the method of this embodiment does not make the process so complicated as compared with the case of the fifth embodiment.

  In order to form the fifth embodiment in a complementary type, n channel (p channel) contact photolithography → n channel (p channel) contact opening → contact implantation into p well region (n well region) → p channel ( n channel) contact photolithography → p channel (n channel) contact opening → contact implantation into an n well region (p well region). In the sixth embodiment, contact photolithography → n channel and p channel simultaneous contact opening → n channel (p channel) contact injection photolithography → p well region (n well region) contact injection → p channel (n channel) contact injection photolithography → n well region (p well region) contact injection. For this reason, in the fifth embodiment, the contact opening process is increased once instead of the photolithography process being decreased once.

  In the case of forming a complementary MOS structure as in the embodiment (embodiment 11) described later, when the source / drain implantation mask and the contact implantation mask are used together, this embodiment is different from the fifth embodiment. In comparison, the photolithography process is reduced once. This is because the contact mask photolithography process and the source / drain implantation photolithography process cannot be combined. This is to prevent the source / drain regions from being damaged by contact etching.

  (Embodiment 7) In this embodiment, a refractory metal silicide film is formed in a self-aligned manner with respect to the embodiment 6, and then an impurity ion having the same conductivity type as that of the shallow well region is implanted by an ion implantation method. A method for forming a high concentration diffusion layer in the well region at the bottom of the hole will be described.

  FIGS. 15A to 15F are simplified process-order cross-sectional views of the present embodiment.

First, as shown in FIG. 15A, as in FIG. 12A, a shallow well region 902, a trench type element isolation structure 903, a field oxide film region are formed in a semiconductor substrate in which a deep well region 901 is formed. 904, and impurity ion implantation for threshold control is performed, and then a gate oxide film 905, a gate electrode 906, and a gate sidewall oxide film 907 are formed by a known method. In this embodiment, the deep well region concentration is set to 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ , and the shallow well region is set to 1 to 2 × 10 ¹⁷ / cm ³ and the depth thereof is set. Was set to 300-700 nm. Although not shown, the source region and the drain region have a concentration of 1 × 10 ²⁰ / cm ³ or more and a depth of 50 to 70 nm. The gate oxide film is 3 nm, the gate electrode is made of a polycrystalline silicon film, and its concentration is set to 1 × 10 ²⁰ / cm ³ or more. Further, the trench type element isolation structure 903 needs to be set sufficiently deep with respect to the shallow well region 902 and is desirably shallower than the deep well region. In this embodiment, the depth of the deep well region 901 is set to 2 μm or more, and the depth of the trench element isolation structure 903 is set to 1 to 2 μm. However, these numerical values are values that we used for trial manufacture in the examples, and are not limited thereto. These numerical values of concentration and depth vary depending on the transistor design. In our transistor, the gate length is set to 0.18 μm. Note that the deep well region 901, the source / drain regions (not shown in the drawing), and the gate electrode 906 are of the same conductivity type and the shallow well region 902 is of the opposite conductivity type.

  Next, as shown in FIG. 15B, using the photoresist 909 as a mask, a contact hole 909 reaching the shallow well region 902 to a desired region of the gate electrode is formed by RIE. If the surface of the silicon substrate (shallow well region 902) is damaged by contact etching, etching is performed when the gate oxide film at the bottom of the contact hole is exposed by RIE with a high etching selectivity between the polycrystalline silicon film and the silicon oxide film. Then, the gate oxide film 905 may be removed with a hydrofluoric acid solution or an oxide film etching system RIE.

  Next, as shown in FIG. 15C, titanium metal 910 is deposited. (In this example, a film thickness of 20 nm to 50 nm was deposited in an argon gas by sputtering).

  Next, as shown in FIG. 15 (d), a first rapid heat treatment is performed in a nitrogen atmosphere in a range of 600 ° C. to 700 ° C. for about 10 to 20 seconds to react the titanium metal 910 with silicon to form titanium. A silicide film 911 is formed.

Next, as shown in FIG. 15E, an implantation mask is formed with a photoresist 912 and ion implantation is performed on the bottom of the contact hole 909 (in this embodiment, when the shallow well region 902 is a p-type semiconductor, boron is used. When ions are implanted with an energy of 1 to 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 5 to 10 keV, and the shallow well region 902 is an n-type semiconductor, arsenic ions are implanted with 1 to 5 × 10 ^15. / were implanted at an energy of accelerating voltage 10~30kev in injection volume cm ^2), to form a high concentration of region 913 than the shallow well region 902 of the shallow well region 902 and the same conductivity type.

  As for the relationship between the photoresist 912 (ion implantation mask) and the contact hole 909, it is necessary to extend the photoresist 912 with respect to the contact hole 909 by a misalignment margin (distance d). At this time, since an impurity having the same conductivity type as that of the shallow well region 902 is implanted into a part of the gate electrode, the gate electrode 906 originally has a conductivity type opposite to that of the shallow well region 902 in the case of a surface channel MOS type transistor. Therefore, depending on the original impurity concentration of the gate electrode, only the region where the gate electrode is contact-implanted is close to the intrinsic semiconductor or has the same conductivity type as the shallow well region 902, and the PN junction is connected to the worst gate electrode. However, since the gate electrode is made polycide, there is no problem in ohmic connection.

  Next, as shown in FIG. 15 (f), the photoresist 912 and the unreacted and nitrided titanium metal film are selectively removed, and in a nitrogen atmosphere in the range of 800 ° C. to 1000 ° C. for about 10 to 20 seconds. The second rapid heat treatment is performed to change the silicide film 911 into a low-resistance C54 crystal structure and activate the impurities implanted into the contact portion. In this embodiment, since not titanium but oxygen is knocked on in silicon, oxygen does not accumulate on the grain boundary of the silicide film in the silicidation reaction, and the heat resistance of the silicide film is improved. In addition, contaminants from the photoresist can be prevented by the unreacted and nitrided titanium metal film 910 which is an implantation protective film, so that the contamination is small.

  (Embodiment 8) An embodiment of a semiconductor device having a complementary MOS structure according to the present invention will be described below with reference to FIGS. FIG. 16 shows the structure of this embodiment, and FIG. 17 is an equivalent circuit diagram thereof. FIG. 16 shows a CMOS inverter in which the potential level of the output OUT changes between the power supply voltage VDD and the ground voltage GND in response to the potential level of the input IN. In the present embodiment, the transistor elements of Reference Examples 1 to 3 and Examples 1 and 2 are complementarily connected with different conductivity types and formed on the same semiconductor substrate.

  As shown in FIG. 16, a semiconductor substrate 1001 is provided with a deep n-well region 1002 and a deep p-well region 1003. The deep well region includes a shallow p-well region 1006 and a shallow n-well region 1007, respectively. Is provided. Although FIG. 16 shows a set of complementary MOS transistors, in practice, a large number of sets of MOS transistors are integrated on the same substrate.

  An n channel type MOS transistor element is formed in the shallow p well region 1006, and a p channel type MOS transistor element is formed in the shallow n well region 1007.

  An n-channel MOS transistor element includes an n-type source / drain region 1015 formed near the upper surface of a shallow p-well region 1006, an n-type overhang junction region 1013, and a channel region formed between the source / drain regions. A gate insulating film 1008 formed thereon and an n-type gate electrode 1009 formed on the gate insulating film 1008 are provided. The n-type gate electrode 1009 is electrically connected to the shallow p well region 1006.

  A p-channel MOS transistor element includes a p-type source / drain region 1016 formed near the upper surface of a shallow n-well region 1007, a p-type extended junction region 1014, and a channel region formed between the source / drain regions. A gate insulating film 1008 formed thereon and a p-type gate electrode 1010 formed on the gate insulating film 1008 are provided. The p-type gate electrode 1009 is electrically connected to the shallow n-well region 1007.

  In any of the transistors, a refractory metal silicide film 1012 is formed on the gate electrodes 1009 and 1010, and a sidewall insulating film (sidewall spacer) 1011 is formed on the side surfaces of the gate electrodes 1009 and 1010. ing.

Note that the overhang junction regions 1013 and 1014 are provided to increase the transistor driving force while suppressing the short channel effect. The junction depth is, for example, about 20 nm to 70 nm, and the impurity concentration is set within a range of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ .

  The size, impurity concentration, and the like of each part are in accordance with the contents described in Reference Example 2. The operation of each transistor is as described in Reference Examples 1 and 2.

  A trench type element isolation structure 1004 is provided around each of the shallow p-well region 1006 and the shallow n-well region 1007. A field element isolation region 1005 is formed on an inactive region (field region) on the substrate surface.

  Although not shown in FIG. 16, for example, a plurality of shallow p-well regions 1006 can be formed in one deep n-well region 1002. Each shallow p-well region 1006 needs to be electrically isolated from the other shallow p-well region 1006, but the deep n-well region 1002 can be shared by multiple transistors. Therefore, the trench type element isolation structure 1004 is formed deeper than the shallow well region, but is shallower than the lower end of the deep well region.

  By configuring the complementary dynamic threshold transistor, there is an effect that it is easy to configure a circuit with low power consumption.

  The problem with the complementary type is that the PN junction forward current always flows in either the n-channel type MOS transistor element or the p-channel type MOS transistor element. The “PN junction forward current” in this case is not only the current flowing through the PN junction formed between the shallow well region and the source / drain region, but depending on the bias of the deep well region, A current flowing through a PN junction formed between the well region and the well region is included.

  Details will be described with reference to FIG.

In the standby state, the level of the input IN is fixed to High (power supply voltage V _DD level) or Low (GND level). In this standby state, either the parasitic bipolar (PNPTr1, PNPTr2, PNPTr3) on the P-channel MOS transistor side or the parasitic bipolar (NPNTr1, NPNTr2, NPNTr3) on the N-channel MOS transistor side is always on. And the parasitic bipolar current continues to flow. Even if the parasitic bipolar current is negligible, the PN junction forward current continues to flow.

Regarding the potential of the deep well region, as described in Table 1 of Reference Example 2, when the deep n-well region is fixed to GND and the deep p-well region is fixed to V _DD (power supply voltage), Is effective because the parasitic bipolar transistor operates in a direction to help the MOS transistor. However, in this case, a forward bias is applied to the diode connection formed between the deep p-well region and the deep n-well region. For this reason, a forward current always flows through this diode connection. Care must be taken during design.

In order to prevent forward current from flowing through the diode connection between the deep p-well region and the deep n-well region, the deep p-well region and the deep n-well region have the same potential, for example 1 / 2V _DD (power supply The potential of the deep n-well region may be fixed at the VDD level and the potential of the deep p-well region may be fixed at the GND level.

In this case, as described in Reference Example 2, since the parasitic bipolar PNPTr3 and NPNTr3 operate in a direction that hinders the operation of the transistor, the capability of the parasitic bipolar transistor is increased by increasing the base width and decreasing the impurity concentration of the base. Must be reduced as much as possible so as to be negligible for the operation of the MOS transistor. For example, in order to reduce the capability of the parasitic bipolar transistor, for example, a shallow well region is formed deeply so as to have a base width of 200 nm or more, and the shallow well region concentration is reduced to 2 × 10 ¹⁷ in order to reduce the impurity concentration of the base. / Cm ³ or less.

(Example 9) As described above, regarding the potential of the deep well region, as described in Table 1 of Reference Example 2, the potential of the deep n well region is fixed at the GND level, and the potential of the deep p well region is set to V _DD When fixed at the (power supply voltage) level, the parasitic bipolar transistor operates in the direction of helping the MOS transistor. However, according to the configuration of the eighth embodiment, since a forward bias is applied to the diode connection formed between the deep p well region and the deep n well region, there is a problem that the forward current always flows.

  In this embodiment, a deeper well region having a conductivity type opposite to the conductivity type of each deep well region is provided, and the groove type isolation is deeper than the deep well region at the boundary between the deep p well region and the deep n well region. A structure is provided.

  The present embodiment will be described with reference to FIGS. FIG. 18 is a cross-sectional view of the structure of this example, and FIG. 19 is a circuit diagram of this element.

Here, 1101 semiconductor substrate, 1102 deeper p-well region, 1103 deeper n-well region, 1104 deeper trench region isolation structure than shallower deep well region, 1105 deep n-well region, 1106 deep p-well region Well region, 1107 shallower than deep well region, deeper than shallow well region, 1108 field device isolation region, 1109 shallow p-well region, 1110 shallow n-well region, 1111 gate oxide film, 1112 n-type gate electrode 1113p type gate electrode, 1114 gate sidewall insulating film, 1115 refractory metal silicide film, 1116n type overhang junction, 1117p type overhang junction, 1118n type source / drain region, and 1119p type source / drain region. The concentration of the deeper well region than that of the deep well region was 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ² , and the depth was set to 5 μm or more. The depth of the deep well region is 2 to 4 μm, and other conditions are the same as in Example 8. However, it is not restricted to the conditions of a present Example.

  According to the present embodiment, as shown in FIGS. 18 and 19, PN junctions are not directly formed between deep well regions but are separated by deeper well regions, and PN junctions between deeper well regions are reversed. Since it is biased, the PN junction forward current does not flow between deep well regions as in the eighth embodiment.

  (Embodiment 10) In this embodiment, an example of setting guidelines for the threshold voltage of a MOS transistor when the bipolar effect is suppressed as much as possible and the MOS transistor is operated as a MOS transistor will be described.

  Considering portable devices in the future, low power consumption technology will become increasingly important. In a normal CMOS, when the power supply voltage is lowered from the device side, it is the most effective means for reducing power consumption. In normal CMOS, standby leakage is determined by the off-state current of the transistor.

  However, in the complementary semiconductor device according to the present invention, the standby leak is determined by the current obtained by adding the off current of the MOS transistor portion and the current of the bipolar transistor portion. When the amplification function of the bipolar transistor portion is small, the “current of the bipolar transistor portion” is equivalent to the base current and coincides with the PN junction forward current. For this reason, since either NPN or PNP is always in the ON state even in the standby state, the bipolar current of either NPN or PNP (PN junction forward current when the amplification function is small) always continues to flow. Therefore, even if the off-state current of the MOS transistor portion is set several orders of magnitude lower than the bipolar current, the bipolar current becomes dominant for the standby leak, which is not very meaningful.

  For this reason, in the semiconductor device according to the present invention, it is desirable to set the off-current value of the MOS type transistor portion from a level one digit smaller than the bipolar current to almost the same level. The reason is as follows.

  In order to set the off-state current of the MOS transistor so that the off-state current of the MOS transistor is about one digit smaller than the bipolar current, the apparent threshold voltage of the MOS transistor may be lowered. As a rule of thumb, the “apparent threshold voltage” is equal to the gate voltage when the drain current flows about 1 A when the gate width is 10 μm. Here, the “apparent” threshold voltage is described because the original threshold voltage varies depending on the gate voltage (the potential of the shallow well region).

The graph of FIG. 20 shows a straight line indicating a bipolar current (Tr3 bipolar current in Reference Example 2, Examples 8 and 9) and a gate voltage (V _G ) -drain current (I _D ) characteristic in a MOS transistor. Two types of curves are shown. The two types of curves for MOS transistors correspond to two different thresholds.

  Here, since the base region (shallow well region) and the gate electrode are short-circuited, the gate voltage and the base voltage are equal. In this embodiment, since the parasitic bipolar is suppressed as much as possible, the amplification factor is about 1. For this reason, the base current and the bipolar current substantially coincide.

  The off current of the MOS transistor is a drain current when the gate voltage is 0V. In order to adjust this off-current so that it is equal to or lower by an order of magnitude than the bipolar current in the power supply voltage used, the “apparent threshold voltage” of the MOS transistor can be lowered as shown in FIG. That's fine.

  As described in Reference Example 1, when the semiconductor devices (transistor elements) of Examples 8 and 9 are used as low power consumption elements, how to suppress the bipolar current (minimum PN junction even without an amplification function) The forward current flows) is the key. Therefore, in reality, it is necessary to set the power supply voltage below the built-in potential of the PN junction. The forward current of the PN junction increases exponentially with respect to the bias value when a bias is applied in the forward direction of the PN junction. Therefore, it is preferable to reduce the bias value, and it is desirable to design an element that operates around a power supply voltage of 0.3 V to 0.6 V.

In summary, the base current decreases exponentially by lowering the power supply voltage, and the MOS type transistor is configured so that the off-state current of the MOS type transistor portion is about the base current (or one digit drop level) at a certain power supply voltage. The threshold voltage is set on the appearance of the part. Then, the on-current of the MOS transistor portion at the power supply voltage is determined. If the on-state current is more than enough to charge the gate capacitance of the next stage within a predetermined time (in order to operate the circuit at the design value frequency), the power supply voltage is further lowered. If the amount is insufficient to charge the gate capacity of the next stage within a predetermined time (in order to operate the circuit at the designed frequency), the power supply voltage may be increased. Our device prototyped according to this design guideline has a stand-by leakage (current which is the sum of the off-state current of the MOS transistor and the base current of the bipolar part) per 10 μm of gate power of 0.55 V on the order of 10 ⁻¹⁰ A. On-state current of 0.2 to 0.25 mA (NMOS) and 0.1 to 0.13 mA (PMOS) are realized, and the apparent threshold voltage is 0.18V.

  Further, the propagation delay time per stage of the ring oscillator constituted by the complementary inverter was 30 picoseconds (psec).

The gate oxide film is 3 nm, the impurity concentration of the source / drain region is 1 × 10 ²⁰ / cm ³ or more, and the junction depth of the source / drain region is 0.1 μm (in the case of NMOS) to 0.15 μm (in the case of PMOS). ), The impurity concentration of the shallow well region is 9 × 10 ¹⁶ / cm ³ , the junction depth is 0.8 to 1.0 μm, the depth of the isolation groove is 1.5 to 2 μm, and the impurity concentration of the deep well region is The gate length was 4 × 10 ¹⁶ / cm ³ and the gate length was 0.15 μm. The potential of the deep n-well region is fixed at VDD, and the potential of the deep p-well region is fixed at GND.

  (Embodiment 11) In Embodiments 6 and 7, the method for ohmic connection between the gate electrode and the shallow well region has been described. In the case where the manufacturing steps of the sixth and seventh embodiments are applied to the complementary elements of the eighth and ninth embodiments, the source / drain implantation mask and the contact implantation mask are used as described in the section of the sixth embodiment. I can do it.

  FIGS. 21A and 21B are plan views of an implantation mask (formed from a photoresist) that serves both as a contact formation mask and a source / drain implantation mask in this embodiment.

  The opening of this implantation mask corresponds to the hatched regions (donor impurity implantation region 1305 and acceptor impurity implantation region 1306). Here, reference numeral 1301 denotes a field oxide film region, 1302 denotes a trench type element isolation structure, 1303 denotes polycrystalline silicon serving as a gate electrode, and 1304 denotes a contact hole for connecting the shallow well region and the gate electrode.

  According to the implantation mask of FIG. 21A, contact implantation for a P-channel MOS transistor, source / drain implantation for an N-channel MOS transistor, and implantation into a gate electrode are performed in one mask. The process can be simplified. Similarly, according to the implantation mask of FIG. 21B, contact implantation for an N-channel type MOS transistor, source / drain implantation for a P-channel type MOS transistor, and introduction into a gate electrode are performed. Implantation can be performed with one mask, and the process can be simplified.

  For this reason, when a complementary MOS structure is formed by the manufacturing methods of Examples 6 and 7, it is preferable to use an implantation mask having a layout pattern as shown in FIGS.

  Here, the difference from Embodiments 6 and 7 is that the impurity doping to the polycrystalline silicon serving as the gate electrode is performed simultaneously with the impurity doping for forming the source region and the drain region. In Examples 6 and 7, the process was performed on the assumption that the impurity doping of the gate had already been completed.

  Since the upper surface of the source / drain region and the upper surface of the gate electrode are salicided in a self-aligned manner by the methods of Embodiments 6 and 7, the transistor parasitic resistance is also very small. In the present manufacturing method, a PN junction is formed around the region a of the gate electrode, but there is no problem because the gate electrode has a polycide structure.

  Also, source / drain implantation on the N-channel MOS transistor side (contact implantation on the P-channel MOS transistor side) and source / drain implantation on the P-channel MOS transistor side (N-channel MOS type) Either step of transistor side contact injection) may be performed first.

  However, if the activation heat treatment for the source / drain implantation on the N-channel MOS transistor side and the source / drain implantation on the P-channel MOS transistor side are not performed at the same time, the ion that is not strict to the heat treatment It is better to perform the seed injection step first. For example, arsenic is used as the source / drain implanted ion species on the N-channel MOS transistor side, and boron ions are used as the source / drain implanted ion species on the P-channel MOS transistor side, so that the short channel effect of the transistor can be prevented. Therefore, when it is desired to suppress the annealing annealing of boron (boron is light, the diffusion rate in silicon is high), arsenic is implanted, and after annealing (for example, 850 ° C., about 30 minutes) Implantation and additional annealing (for example, 1000 ° C., about 20 seconds) may be performed.

  (Embodiment 12) In the reference example 1, the case where the gate electrode and the shallow well region are directly electrically connected has been described. In the semiconductor device of Reference Example 1, when the parasitic bipolar effect is negligibly small, the equivalent circuit is as shown in FIGS. 22 (a) and 22 (b). FIG. 22A shows the case of an N-channel MOS transistor, and FIG. 22B shows the case of a P-channel MOS transistor.

  As shown, PN junctions are formed between the shallow well region and the source / drain region, and between the deep well region and the shallow well region. When these PN junctions are biased in the forward direction, a forward current flows through the PN junction as described in Reference Example 1. In order to prevent this, it is desirable to set the power supply voltage so that the potential of the well region is about 0.1 to 0.3 V lower than the built-in potential (see the description of Example 10). Therefore, when the gate electrode and the shallow well region are directly electrically connected, the power supply voltage that can be practically used is about 0.6 V or less.

  In this embodiment, a method of using the power supply voltage without any limitation will be described. FIGS. 22C and 22D show examples in which an n-channel transistor Trn2 and a p-channel transistor Trp2 are arranged between the gate electrode and the shallow well region, respectively.

Here, if the gate potential of the transistor _Trn2 is fixed to Vspwell _MAX + V _thn2 with respect to GND, no matter how much the gate potential (V _G ) becomes, the voltage can be applied to the deep well region only up to the maximum Vspwell _MAX. Not.

Similarly, in the case of the transistor Trp2, if the gate potential is fixed to Vsnwell _MIN + V _thp2 with respect to GND, no matter what the gate potential (V _G ) becomes, the deep well region has a maximum Vsnwell _MIN + V _thp2 Only voltage is applied.

  FIGS. 23A and 23B show the relationship between the potential of the shallow p-well region (Vspwell) and the potential of the shallow n-well region (Vsnwell) with respect to the potentials of the gate electrodes of the transistors Trn1 and Trp1.

Here, Vspwell _MAX is the maximum potential applied to the shallow p-well region, Vsnwell _MIN is the minimum potential applied to the shallow n-well region, V _thn2 is the threshold voltage of _Trn2 , and V _thp2 is the threshold voltage of Trp2. It is.

More specifically, when the potential of the source region of the transistor Trn2 is GND and the potential of the source region of the transistor Trp2 is 3V (power supply voltage), Vspwell _{MAX is set} to 0.6V, Vsnwell _MIN to suppress forward leakage. Is set to 2.4V. In this case, for example, if the threshold voltage of the transistor Trn2 is 0.4V and the threshold voltage of the transistor Trp2 is -0.4V, the gate voltage of the transistor Trn2 is 1V and the gate voltage of the transistor Trp2 is 2V. You only have to set it.

  According to the above method, the maximum value (minimum value) of the potential of the shallow well region can be arbitrarily set regardless of how much the power supply voltage is set, and the limitation of the power supply voltage can be avoided.

  (Embodiment 13) In Embodiment 12, the method of using the equivalent circuit when the parasitic bipolar effect is negligibly small without limiting the power supply voltage has been described. With reference to FIGS. 24 and 25, an embodiment in which a parasitic bipolar transistor is considered will be described. 24 and 25 show an equivalent circuit in the case where parasitic bipolar is considered.

  FIG. 24 shows a case where a semiconductor device is constituted by an n-channel transistor and an npn-type bipolar, and FIG. 25 shows a case where a semiconductor device is constituted by a p-channel transistor and a pnp-type bipolar.

  Since the roles of NMOS2 and PNOS2 are the same as those of Trn1 (n-channel transistor) or Trp1 (p-channel transistor) of the twelfth embodiment, the basic operation is omitted.

  Thus, even when the parasitic bipolar transistor cannot be ignored, the base current can be arbitrarily designed by the gate voltages of the NMOS 2 and the PNOS 2, so that there is an advantage that the degree of freedom of design is increased compared to the reference example 2.

  (Embodiment 14) In Embodiments 12 and 13, the configuration for arbitrarily setting the maximum value (minimum value) of the potential of the shallow well region has been described. However, the N-channel MOS transistor side when the input state (gate potential) is in the high state and the standby state, or the P-channel MOS transistor side when the standby state is in the low state. In the twelfth and thirteenth embodiments, the PN junction forward current continues to flow.

  In this embodiment, when the input value changes from High → Low or Low → High, the PN junction forward current flows only during the period when the output value changes from Low → High or High → Low, and does not flow in the standby state ( A configuration in which PN junction is not forward biased will be described.

  As shown in FIG. 26, the gate electrode of the MOS transistor in Reference Example 1 (NMOS1 in this embodiment) is the source of a second MOS transistor of the same type as NMOS1 (NMOS2 in this embodiment). When the NMOS 1 is connected to the shallow well region through the drain region and the gate electrode of the NMOS 2 is connected to the drain of the NMOS 1, the PN junction forward current flows only when the output changes in response to the input change. Does not flow in standby mode.

  As shown in FIG. 27, the same applies to the p-channel, and the gate electrode of the MOS transistor in Reference Example 1 (referred to as PMOS 1 in this embodiment) is used as a second MOS transistor of the same type as PMOS 1 (this embodiment). Only when the output changes with respect to the input change if the PMOS 1 is connected to the shallow well region of the PMOS 1 through the source region and drain of the PMOS 1 and the gate electrode of the PMOS 2 is connected to the drain region of the PMOS 1. A PN junction forward current flows and does not flow in the standby state.

The operation principle will be described using an n-channel transistor as an example. Assume that the node G (the gate potential of the NMOS 1 and the input potential) is fixed at Low and is in a standby state. At this time, since the node D (the drain potential of the NMOS 1 and the output potential) is in the high state, the NMOS 2 is in the on state, and the node sp (the potential of the shallow well region) becomes the same potential as the node G and is fixed low. Therefore, the same potential between the node sp (Low) and the node S (Low), the reverse bias between the node sp (Low) and the node D (High), and the same potential between the node sp (Low) and the node VDnwell (Low or High). It becomes a potential or reverse bias state, and PN junction forward current does not flow. Here, consider a case where the node G changes from Low to High and enters the standby state again. First, at the moment when the node G changes from low to high, the node D is in the high state, so the NMOS 2 remains on. Therefore, the potential of the node sp similarly changes from Low to High as the node G changes from Low to High. Since the node G and the node sp similarly change from Low to High, the operation of the NMOS 1 is the same as that of the reference example 1, and the threshold value dynamically changes according to the potential of the node G. Here, since the NMOS 1 is turned on, electrons are supplied from the node S to the node D, and the potential of the node D gradually approaches Low. When the potential of the node D drops below the threshold voltage of the NMOS 2, the node sp is turned off, the node sp is in a floating state, and the charge supply source is cut off from the node sp (strictly speaking, the NMOS 2 off current component). PN junction forward current does not continue to flow in the standby state (strictly speaking, a current corresponding to the off current of the NMOS 2 flows). At the beginning when the node sp is in a floating state, the potential of the node sp is still high with respect to the node S (ground), and the substrate bias effect on the NMOS 1 still remains. The node sp in a floating state with respect to the node S (ground), the node D (Low), and the deep well region (when V _dnwell is grounded) is forward biased, so that the charge of the node sp is gradually released over time. The potential of the node sp is close to Low (GND).

  That is, even if the input (node G) is high and in a standby state, the PN junction forward current does not flow even if the input (node G) is in a standby state when low.

  Further, when the potential of the node G changes from Low to High, the maximum potential of the node sp becomes VD−Vthn2 when the threshold voltage of the NMOS 2 is Vthn2 and the potential of the node D is VD. That is, the maximum potential of the node sp is determined depending on the setting of Vthn2.

  Since the p-channel type has exactly the same operation principle, the description is omitted.

  (Embodiment 15) In Embodiment 14, a method of using an equivalent circuit when the parasitic bipolar effect is so small as to be negligible has been described without limiting the power supply voltage. Depending on the value obtained by subtracting the depth of the source / drain region), when a power supply voltage higher than the built-in potential is used, the bipolar current is likely to be dominant. In this embodiment, a case where bipolar is considered will be described. An equivalent circuit in consideration of bipolar is shown in FIGS.

  In FIG. 28, an n-channel transistor and an npn bipolar are described. In FIG. 29, a p-channel transistor and a pnp bipolar are described. Since the roles of the NMOS 2 and the PNOS 2 are the same as those of the NMOS 2 and the PNOS 2 of the fourteenth embodiment, the basic operation is omitted.

  Thus, even if the parasitic bipolar transistor cannot be ignored, a mixed element of the bipolar transistor and the MOS type transistor is formed so that the base current can be cut off in the standby state (actually, the off current of NMOS2 and PNOS2 flows). I can do it.

In this embodiment, a power supply voltage below the built-in potential (actually, a power supply voltage at which the maximum difference between the base potential (the potential of the shallow well region) and the potential of the source region and the drain is less than the built-in potential: the base potential. VB = VD−V _th2 ; VB: base potential at node sp or node Sn, VD: output potential at node D, V _th2 : threshold voltage of NMOS2 or PNOS2) In this case, the current of the MOS transistor becomes dominant with respect to the device operation, and the maximum potential difference between the source voltage / drain region and the power source voltage (actually the base potential, that is, the potential of the shallow well region) higher than the built-in potential. When used at a power supply voltage whose value is greater than or equal to the built-in potential, the bipolar current becomes dominant. In order to use under the condition where the bipolar current is dominant, V _dnwell (FIG. 28) or V _dpwell (FIG. 29), which is the potential of the deep well region, is set to V _dnwell = GND and V _dpwell = V _DD (power supply voltage). (Ie, the deep well region is used as the emitter of NPN3 and PNP3).

  In summary, the low power supply voltage side is a MOS transistor having a low voltage and high driving capability, and the high power supply voltage side is a bipolar transistor in which a base current does not flow in a standby state.

  (Embodiment 16) In Embodiments 12 to 15, the configuration for eliminating the limitation of the power supply voltage and the configuration for suppressing the PN junction forward current in the standby state have been described for the elements of Reference Examples 1 and 2. It has been described using an equivalent circuit that such a configuration can be realized by adding a transistor.

  NMOS 1 in FIG. 22C, PMOS 1 in FIG. 22D, NMOS 1 in FIG. 15-1, PMOS 1 in FIG. 25, NMOS 1 in FIG. 26, PMOS 1 in FIG. 27, NMOS 1 in FIG. 28, PMOS 1 in FIG. The structure is the structure of the switching element as shown in Reference Examples 1 and 2, and the adjacent shallow well regions are preferably separated by the groove type separation structure as in Example 1. By forming the groove-type isolation structure, the distance between transistors can be reduced, and high integration can be achieved.

  (Embodiment 17) In Embodiments 12 to 15, a transistor is added with respect to the method of eliminating the limitation of the power supply voltage and the method of suppressing the PN junction forward current in the standby state in the elements of Reference Examples 1 and 2. It was explained using an equivalent circuit that However, the above description is not a complementary type, and a through current always flows when the MOS transistor portion is on. In particular, in the fourteenth and fifteenth embodiments, even if the PN junction forward current (bipolar current) is lost in the standby state, the NMOS transistor side when the standby state is entered in the input high state or the standby state in the input low state. Since the through current continues to flow on the PNOS side at the time of becoming, it is not suitable for low power consumption. Therefore, in this embodiment, the case where the elements of Embodiments 12 to 15 are formed in a complementary type will be described.

  30 to 33 are circuit diagrams when the elements of Examples 12 to 15 are formed in a complementary type. Since the operation of each transistor has been described in Examples 12 to 15, description thereof will be omitted.

  When the elements of the twelfth and thirteenth embodiments are made complementary, it is possible to eliminate the limitation of the power supply voltage with respect to the complementary elements of the eighth embodiment. However, there is the same problem as in the eighth embodiment. That is, the PN junction forward current always flows. In the standby state, the input value is fixed to High (power supply voltage) or Low (GND), and the parasitic bipolar (PNPTr1, PNPTr2, PNPTr3 in FIG. 31) on the P channel type MOS transistor side or N channel One of the parasitic bipolar transistors (NPTNr1, NPNTr2, and NPNTr3 in FIG. 31) on the MOS transistor side of the type is always in the ON state. For this reason, the parasitic bipolar current continues to flow. Even when the parasitic bipolar current can be ignored, the PN junction forward current (the PN junction forward current flowing between the shallow well region and the source region, drain, and deep well region depending on the bias) continues to flow. Therefore, as a design policy, the shallow well region concentration, depth, and deep well region are set so that the capability of the parasitic bipolar is minimized and the collector current is almost equal to the base current (that is, the parasitic bipolar is almost negligible). Set the density. Then, under the condition that collector current = base current = PN junction forward current, as shown in the tenth embodiment, the MOS transistor has an off-current equal to the PN junction forward current. What is necessary is just to set a threshold voltage.

When the elements of Examples 14 and 15 are made complementary, the parasitic bipolar is turned off in the standby state as described in Examples 14 and 15 (the base is floating in the standby state). However, in order to prevent forward current against diode connection between the deep p-well region and the deep n-well region, the deep p-well region and the deep n-well region have the same potential (for example, 1 / 2V _DD : half of the power supply voltage). Alternatively, it is necessary to fix the deep n-well region to V _DD and the deep p-well region to GND. In this case, since the parasitic bipolar PNPTr3 and NPNTr3 operate in a direction that hinders the operation of the transistor as described in Reference Example 2, the base width is increased (the shallow well region is deepened: the base width is 200 nm or more), and the base concentration is increased. The parasitic bipolar transistor capability may be reduced as much as possible (as in Reference Example 1) as much as possible by thinning (shallow well region concentration: 2 × 10 ¹⁷ / cm ³ or less) with respect to the operation of the MOS transistor.

Conversely, with respect to the potential of the deep well region, when the deep n-well region is fixed to GND and the deep p-well region is fixed to V _DD (power supply voltage), as described in Table 1 of Reference Example 2, Is effective because the parasitic bipolar transistor operates in the direction of helping the MOS type transistor, but since it becomes a forward bias with respect to the diode connection of the deep p-well region and the deep n-well region, how much of the bipolar in the standby state is turned off. However, since a forward current always flows between deep well regions, it is preferable to use the circuits and structures of Examples 18 and 19 shown below as in Example 9.

(Embodiment 18) In Embodiment 17, when the bipolar transistors of Embodiments 14 and 15 are positively used as active elements, the deep n-well region is fixed to GND and the deep p-well region is fixed to V _DD (power supply voltage). I explained what I should do. That is, the deep well region (n-type) of the NPNTr3 bipolar transistor may be used as the emitter, the emitter grounded, the deep well region (P-type) of the PNPTr3 bipolar transistor may be used as the emitter, and the emitter may be used as the power supply voltage. In this case, since the forward current always flows between the deep well regions as described above, it is necessary to separate the deep well regions. That is, a deeper well region is formed than the deep well region, the n-type deep well region is formed in the p-type deeper well region, and the p-type deep well region is formed in the n-type deeper well region. The deep well region and the deeper well region may be set to the same potential. By forming in this way, the deep well region becomes a PN reverse bias, and forward current does not flow. FIG. 34 shows a circuit diagram thereof. In the complementary device of the present embodiment, the power supply voltage is not limited, the drive current in the active state is the sum of the drain current of the MOS transistor and the bipolar current, and the leakage in the standby state is NMOS1, NMOS2, It is determined only by the off currents of PMOS1 and PMOS2.

  In other words, when the power supply voltage is used in the vicinity of the built-in potential, the normal CMOS has a driving current and the speed is too slow to withstand use, but according to this embodiment, an ultra-low power consumption circuit is configured. It becomes possible to do. When used at a built-in potential or higher, it is possible to construct an ultra-high speed and low power consumption circuit whose power consumption is similar to that of a CMOS circuit and whose speed is similar to that of a bipolar circuit.

  (Embodiment 19) In order to separate the deep well regions of NMOS 1 and PMOS 1 of Embodiment 18, NMOS 1 and PMOS 1 may be formed with the same structure as that shown in FIG. In other words, the isolation may be performed with a trench type isolation structure deeper than the “deep well region” and shallower than the “deeper well region”.

  (Embodiment 20) As described above, since a forward bias is applied to the source / drain region with respect to the shallow well region, when an electric field higher than the built-in potential is applied between the shallow well region and the source / drain region, An undesirable leakage current (forward current) flows between the shallow well region and the source / drain regions.

  The magnitude of this built-in potential is determined by the material, and in the case of silicon, it is about 0.9 V at room temperature. Therefore, in order to suppress the PN junction forward current, the built-in potential may be increased. One method is to introduce carbon or nitrogen impurities into the junction between the source / drain region and the shallow well region.

In the present embodiment, an impurity of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² with an acceleration energy such that an implantation projection range (Rp center) is located at the junction between the source / drain region and the shallow well region. Ions were implanted. By this ion implantation, Si—C and Si—N are formed in the vicinity of the junction, and as a result, the built-in potential is increased.

  (Embodiment 21) In Embodiments 12 to 15, a transistor is added regarding the method of eliminating the limitation of the power supply voltage and the method of suppressing the PN junction forward current in the standby state in the elements of Reference Examples 1 and 2. It was explained using an equivalent circuit that Moreover, in Examples 17-18, the case where it comprised by the complementary type demonstrated.

  With reference to FIGS. 35 to 36, an embodiment having another configuration for suppressing the leakage current during standby will be described.

  In this embodiment, as shown in FIGS. 35 to 36, the power supply voltage cutoff circuit and / or the GND line cutoff for each unit circuit block (FIG. 35) or for each unit circuit block assembly (FIG. 36). A circuit is provided. Only when the circuit block is activated, power is supplied to the circuit block. The operation of the cutoff circuit is controlled by a sleep signal. By doing so, it is possible to reduce leakage during standby.

  (Embodiment 22) In this embodiment, the relationship between the trench type isolation structure and the field oxide film and the shallow well region will be described.

  FIGS. 37A to 37D are cross-sectional views in order of the processes of this example.

  Here, 2401 semiconductor substrate, 2402 deep n-well region, 2403 deep p-well region, 2404 groove type isolation structure, 2405 field oxide region, 2406 ion implantation protective film, 2407 photoresist, 2408 donor impurity implantation, 2409 photoresist, 2410 acceptor impurities, 2411 shallow n-well region, 2412 shallow p-well region.

First, as shown in FIG. 37A, a deep n-well region 2402, a deep p-well region 2403, a trench-type isolation structure 2404, and a field oxide film region 2405 are formed on a semiconductor substrate 2401. Here, the depth of the deep n-well region 2402 and the deep p-well region 2403 is about 2 to 4 m, and the impurity concentration is set to about 1 × 10 ¹⁶ / cm ^{3 to} 1 × 10 ¹⁷ / cm ³ . The trench type element isolation structure is formed to a depth of 1 to 2 μm. The field oxide film thickness is about 200 to 600 nm.

  Next, as shown in FIGS. 37B and 37C, ion implantation is performed using photoresists 2407 and 2409 as masks, donor 2408 is implanted into the deep p-well region, and acceptor 2410 is implanted into the deep n-well region. inject. The order of injection may be from either. At this time, it is possible to prevent impurity ions from being implanted under the field oxide film 2405 by the field oxide film 2405 even if a slight misalignment occurs in the photoresists 2407 and 2409.

Next, as shown in FIG. 37D, a shallow n-well region 2411 and a shallow p-well region 2412 are formed by performing drive annealing. Here, the depth of the shallow n-well region 2411 and the shallow p-well region 2412 is shallower than that of the trench type isolation structure, and is about 0.5 to 1.0 μm, and the concentration thereof is 5 × 10 ¹⁶ / cm ^{3 to} 1 × 10 ¹⁸ / It was set to about cm ³ .

  By forming the shallow well region after forming the trench type isolation structure and the field oxide film as in this embodiment, the shallow n well region and the deep n well region, and the shallow p well region and the deep p well region are formed. The field oxide film can be separated in a self-aligned manner.

  However, in the manufacturing method of this example, as shown in FIG. 8D in Example 2, the structure in which the field oxide film extends around the contact region between the gate electrode and the shallow well region is Since ion implantation is performed after oxidation, it is difficult to apply. Further, even if it is applied, the effect of this embodiment cannot be obtained. This is because, in order to make the shallow well region under the channel region and the shallow well region under the contact region between the gate and the shallow well region conductive, high energy injection enough to penetrate the field oxide film is necessary. This is because the field oxide film makes it impossible to separate in a self-aligned manner.

  (Embodiment 23) FIG. 38 is a sectional view of a grooved element isolation structure according to the present invention. FIG. 39A is an enlarged view of a portion A in FIG.

  FIG. 39B shows a conventional example in which a groove type separation structure is formed. In this conventional example, after forming a groove in the semiconductor substrate 2511, the groove is filled with a silicon oxide film 2512, and the silicon oxide film 2512 is left only in the groove portion by chemical mechanical polishing (CMP). A gate insulating film 2505 is formed in the active region of the semiconductor substrate.

  As shown in FIG. 38, in the trench type element isolation structure of this embodiment, a silicon oxide film 2502 is formed on the inner wall of the trench, but the silicon oxide film 2502 does not completely fill the inside of the trench. The inside of the trench is filled with a polycrystalline silicon film 2503. A thin gate insulating film 2505 is formed in the active region on the surface of the semiconductor 2501, but a relatively thick field oxide film 2504 is formed in the inactive region (field region). This field oxide film 2504 is also present on the trench. The field oxide film 2504 is formed by in-situ thermal oxidation, and a bird's beak is formed at the end of the field oxide film 2504. Therefore, in this embodiment, the edge of the groove opening is not sharp.

  For this reason, as shown in FIG. 39A, electric field concentration does not occur at the edge (A ′) portion of the groove opening, and it is possible to prevent an increase in leakage current at the edge portion. On the other hand, in the groove type separation formed by the conventional CMP method, the edge (B) of the groove opening is sharp as shown in FIG. For this reason, the electric field is concentrated at the edge (B), and the leakage current at this portion increases.

  The groove-type element isolation structure is effective not only for isolating transistors whose threshold values in FIG. 1 are dynamically changed, but also for isolating normal transistors.

  FIG. 51 shows an arrangement relationship in which the gate electrode and the trench type element isolation structure of a normal MOS transistor overlap. Such an arrangement relationship may affect the transistor characteristics.

  52A and 52B are cross-sectional views taken along line AA in FIG.

  In the conventional manufacturing method, the buried oxide film at the groove edge portion is easily etched by the hydrofluoric acid cleaning process performed before the step of forming the gate insulating film. For this reason, constriction is likely to occur in the groove edge portion. FIG. 52A shows a state in which such “necking” occurs. Due to the electric field concentration at the groove edge portion, as shown in FIG. 53A, a kink occurs in the sub-threshold characteristic curve of the MOS transistor.

  When the grooved element isolation structure according to the present invention is employed, the groove edge portion is rounded as shown in FIG. 52 (b), and the electric field concentration at that portion is alleviated. For this reason, according to the MOS type transistor having such a trench type element isolation structure, no kink occurs in the subthreshold characteristic curve as shown in FIG. 53 (a) and 53 (b) show the gate voltage dependence of the drain current in the transistors of FIGS. 52 (a) and 52 (b), respectively. Note that the graphs of FIGS. 53A and 53B are created based on the measurement results when the source voltage is 0V and the drain voltage is 0.1V.

(Embodiment 24) FIG. 40 shows the relationship between a trench type isolation structure 2603, a shallow well region 2602, and a deep well region 2601 when the semiconductor device of Example 1 is isolated using the trench type isolation structure of FIG. FIG. Here, since the concentration of the shallow well region 2602 is about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ and the concentration of the deep well region is about 1 × 10 ¹⁶ to × 10 ¹⁷ / cm ³ , the depletion layer width is small. Increased (several hundred nanometers). Therefore, when the distance d between the junction formed between the shallow well region 2602 and the deep well region 2601 and the groove bottom is short, punch-through may occur between adjacent shallow well regions. Therefore, it is preferable to provide a region 2604 in which impurities having the same conductivity type as the deep well region are diffused at a high concentration at the bottom of the groove. In this embodiment, the impurity concentration of the region 2604 is set within a range of about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ .

  Although the relationship between the shallow well region, the deep well region, and the trench type isolation structure is described, the present invention is not limited to this. For example, the present invention can be applied to the case where the source / drain regions of adjacent transistors formed in a shallow well region are separated. In this case, the shallow well region 2602 is replaced with a source region / drain region, and the deep well region 2601 is replaced with a shallow well region.

  (Embodiment 25) With reference to FIGS. 41 (a) to 41 (h), an embodiment of a groove type separation structure forming process according to the present invention will be described.

  First, as shown in FIG. 41A, a silicon oxide film 2702 (thickness of 10 to 20 nm in this embodiment) and a silicon nitride film 2703 (thickness of 100 to 200 nm in this embodiment) are formed on a semiconductor substrate 2701. Sequentially formed.

  Next, as shown in FIG. 41B, the silicon nitride film 2703 and the silicon oxide film 2702 located in the region 2704 where the trench isolation structure is to be formed are selectively removed using photolithography and etching techniques. Then, the surface of the semiconductor substrate 2701 is partially exposed. In this embodiment, the width of the exposed region is set to 0.1 to 0.3 μm.

  Next, as shown in FIG. 41C, the silicon substrate 2701 is etched using the silicon nitride film 2703 as a mask to form a groove 2705 in the semiconductor substrate 2701, and then the inner wall of the groove 2705 is oxidized in an oxidizing atmosphere. In this embodiment, after forming a groove having a depth of about 1 to 2 μm, a silicon oxide film 2706 of about 10 to 50 nm is formed on the inner wall of the groove 2705.

  Next, as shown in FIG. 41 (d), a polycrystalline silicon film 2707 (in this embodiment, about 200 nm to 600 nm is deposited) is deposited, and the trench 2705 is filled with the polycrystalline silicon film 2707.

  Next, as shown in FIG. 41E, the polycrystalline silicon film 2707 is etched back, leaving the polycrystalline silicon film 2707 only in the trench 2705.

  Next, as shown in FIG. 41F, in order to form a field oxide film in the field region 2709 other than the active region (element formation region) 2708, a photolithography process is performed on the silicon nitride film 2703 other than the active region 2708. After that, it is removed by etching. At this time, there is no silicon nitride film 2703 on the trench type isolation structure 2704, and the alignment margin of the photolithography process for forming the field oxide film can be set to the width of the trench type region 2704.

  Next, as shown in FIG. 41G, the field oxide film 2710 is formed by oxidizing using the silicon nitride film 2703 on the active region 2708 as a mask. In this embodiment, an oxide film having a thickness of about 200 nm to 400 nm is formed. At this time, the surface of the silicon nitride film 2703 is also oxidized, and a silicon oxide film 2711 is formed.

  Next, as shown in FIG. 41H, the silicon oxide film 2711 on the surface of the silicon nitride film 2703 and the silicon nitride film 2703 on the active region formed by the field oxidation process are removed.

  According to this embodiment, there is no misalignment between the field oxide film and the groove type separation (there is an alignment margin corresponding to the width of the groove type separation structure), and it can be formed at the same time, so that the process can be simplified. In addition, regarding the leakage at the groove edge, which is the most problematic in the formation of the groove type separation structure, in this method, bird's beaks are formed at the groove edge portion A, and the leakage current is suppressed.

  (Embodiment 26) Another embodiment of the grooved separation structure forming process according to the present invention will be described with reference to FIGS.

  First, as shown in FIG. 42A, it is formed by the same method up to the step of FIG. Here, 2801 is a semiconductor substrate, 2802 is a silicon oxide film, 2803 is a silicon nitride film, 2804 is a groove type isolation structure, 2805 is a groove, 2806 is a silicon oxide film, and 2807 is a polycrystalline silicon film.

  Next, as shown in FIG. 42B, a silicon nitride film 2808 is deposited. In this example, a film thickness of about 1 to 5 nm was deposited.

  Next, as shown in FIG. 42C, in order to form a field oxide film in a field region 2810 other than the active region (element formation region) 2809, silicon nitride films 2808 and 2803 other than the active region 2809 are formed by photolithography. Etching is removed through a process. At this time, it is preferable to process the silicon nitride film 2808 on the groove type isolation structure 2804 so as to remain about half on the groove type isolation structure 2804 as shown in the drawing.

  Next, as shown in FIG. 42D, the field oxide film 2811 is formed by oxidizing using the silicon nitride films 2803 and 2808 on the active region 2809 as a mask. In this embodiment, an oxide film having a thickness of about 200 nm to 400 nm is formed. At this time, since the silicon nitride film 2808 is very thin, all of the silicon nitride film 2808 is changed to the silicon oxide film 2812, and the surface of the polycrystalline silicon film 2807 embedded in the groove 2805 is also oxidized.

  Next, as shown in FIG. 42E, the silicon oxide film 2812 on the silicon nitride film 2803 and the silicon nitride film 2803 on the active region are removed.

  According to the present embodiment, it is possible to reduce the bird's beak of the groove edge portion B as compared with the embodiment 25, and a grooved element isolation width close to the design dimension can be obtained.

  FIG. 43 shows the application of the method for forming the groove type isolation structure of this embodiment to the element of the first embodiment. FIG. 44 shows the application of the method for forming the groove type isolation structure of the 25th embodiment to the element of the first embodiment.

  Here, 28001 and 28101 are semiconductor substrates, 28002 and 28102 are deep well regions, 28003 and 28103 are trench-type element isolation structures, 28004 and 28104 are shallow well regions, 28005 and 28105 are gate electrodes, and 28006 and 28106 are source / drains. Regions 28007 and 28107 indicate refractory silicide films.

  In this embodiment, when both sides of the trench isolation structure are active regions, the surface of the polycrystalline silicon film 2807 filling the trench of the trench isolation structure is formed by a thin silicon nitride film 2808 in the state before the field oxidation process. Covered. Therefore, the polycrystalline silicon film 2807 is suppressed from being oxidized during the field oxidation, and the polycrystalline silicon film 2807 is not oxidized until the silicon nitride film 2808 is entirely oxidized and changed into the silicon oxide film 2812. The upper silicon oxide film thickness b is reduced, the level difference is reduced, and the amount of over-etching at the time of processing the gate polycrystalline silicon film can be reduced.

  Further, since the amount of oxidation of the polycrystalline silicon film is small, bird's beak is suppressed, and the area of the active region close to the design dimension can be secured (dimension a can be brought close to the design value). In particular, the smaller the minimum processing dimension and the thinner the gate oxide film, the more advantageous. In this embodiment, the gate width and the groove type separation width are both 0.18 μm in design dimensions, and the groove depth is 1 μm.

  When the twenty-fifth embodiment is applied, since the polycrystalline silicon film is exposed before the field oxidation, the silicon oxide film thickness b ′ on the polycrystalline silicon becomes thick and the step becomes large. In addition, the bird's beak becomes larger. However, the process of the twenty-fifth embodiment is simpler than that of the present embodiment.

  (Embodiment 27) FIGS. 47 (a) to 47 (f) are cross-sectional views in order of steps in forming a groove type isolation structure and a field oxide film of the present invention.

In Examples 25 and 26, etch back was performed to embed a polycrystalline silicon film in the trench. In the etch back, etching is performed with a gas such as Cl ₂ , O ₂ , HBr, and SF ₆ , but it is necessary to perform over-etching in order to eliminate an etching residual.

  At this time, when the amount of over-etching is large, it becomes as shown in FIGS. 45 (a) and (b) (in the case of Example 25) and FIGS. 46 (a) and (b) (in the case of Example 26). The polycrystalline silicon film recedes from the groove opening. When the field oxidation process is performed in this state, the groove side wall is considerably oxidized, resulting in a shape as shown in FIG. 45 (b) (in the case of Example 25) and FIG. 46 (b) (in the case of Example 26). The width of the mold element isolation structure is greatly different from the design dimension, and the step becomes severe, and a polycrystalline silicon film residue is generated in the subsequent gate processing step. Here, 29101, 29201 semiconductor substrate, 29102, 29104, 29106, 29202, 29204, 29207 silicon oxide film, 29103, 29203, 29206 silicon nitride film, 29105, 29205 polycrystalline silicon film, 29107, 29208 field oxide film. In order to provide a margin for the amount of overetching, the height d may be increased as shown in FIG.

  This will be described in detail below in the order of steps. First, as shown in FIG. 47A, a silicon oxide film 2902 (10 to 20 nm in this embodiment), a silicon nitride film 2903 (100 to 200 nm in this embodiment), and a silicon oxide film 2904 are formed on a semiconductor substrate 2901. (In this embodiment, 30 to 150 nm is deposited, and a film thickness of 50 to 70 nm is more preferable).

  Next, as shown in FIG. 47B, through a photolithography process, a silicon oxide film 2904 having a desired groove type isolation structure 2905 (in this embodiment, a width of 0.1 to 0.3 μm), a silicon nitride film 2903 and the silicon oxide film 2902 are etched.

  Next, as shown in FIG. 47 (c), the silicon substrate 2901 is etched using the silicon nitride film 2903 as a mask to form grooves 2906 in the groove type isolation structure 2904, and then the inner walls of the grooves 2906 are oxidized in an oxidizing atmosphere. To do. In this example, a groove having a depth of about 1 to 2 μm was formed, and a silicon oxide film 2907 of about 20 to 100 nm was formed on the inner wall of the groove 2905.

  Next, as shown in FIG. 47D, a polycrystalline silicon film 2908 (deposited in the range of about 200 nm to 600 nm in this embodiment) is deposited, and the trench 2906 is filled with the polycrystalline silicon film 2908.

  Next, as shown in FIG. 47E, the polycrystalline silicon film 2908 is etched back, leaving the polycrystalline silicon film 2908 only in the trench 2906. At this time, although depending on the etching selectivity between the silicon oxide film and the polycrystalline silicon film, the silicon oxide film 2904 becomes thin at the time of etching back the polycrystalline silicon film.

  Although depending on the amount of over-etching, if the film pressure of the silicon oxide film 2904 is too thick, the convex step after field oxidation becomes large, and if it is too thin, the concave step after field oxidation becomes large. The height of the surface of the polycrystalline silicon film after the etch back may be within a range of about 100 nm above (B) from the silicon substrate surface (A).

  Next, as shown in FIG. 47F, after the silicon oxide film 2904 on the surface of the silicon nitride film 2903 is removed by etching, the active region portion 2909 is masked by a photolithography process to form the silicon nitride film 2903 in the field region 2910. Remove. Thereafter, the desired groove type element isolation structure is formed through the same steps as those of the 27th or 26th embodiments.

  Since the etch back is highly accurate and the height of the polycrystalline silicon film surface after the etch back is within the range of about 100 nm above (B) from the silicon substrate surface (A) even without the silicon oxide film 2904. If so, it is better to perform the method of the 27th or 26th embodiment because the process is simpler.

  (Embodiment 28) In the present embodiment described above, as shown in FIG. 47 (f), the silicon oxide film 2904 is entirely removed and then the silicon nitride film 2903 in the field region is etched away through a photolithography process. ing. In this case, the silicon oxide film 2907 in the region of the groove opening is also etched during the etching of the silicon oxide film 2904. For this reason, the diffusion time of oxygen during field oxidation reaches the silicon quickly, resulting in an increase in bird's beak.

  The above points will be described in detail with reference to FIGS. 48 (a) to 48 (d).

  In Example 27, after the polycrystalline silicon film 30106 is etched back as shown in FIG. 48A, the entire surface of the polycrystalline silicon film 30104 is etched as shown in FIG. 48B. Therefore, the silicon oxide film 30105 in the groove opening A region is also etched and thinned when the silicon oxide film 30104 is etched. In this state, the silicon nitride film 30103 in the field region is removed by etching (see FIG. 48C) through a photolithography process using the photoresist 30107 as a mask. Therefore, the bird's beak is slightly larger in the shape after field oxidation as shown in FIG.

  In this embodiment, a method for suppressing bird's beak will be described.

  As in the embodiment 27, after the polycrystalline silicon film 30206 is etched back as shown in FIG. 49A, a photoresist process is performed while leaving the silicon oxide film 30204 as shown in FIG. 49B. . Next, the silicon oxide film 30204 and the silicon nitride film 30203 on the field region are removed by etching using the photoresist 30207 as a mask. For this reason, the bird's beak is suppressed in the shape after field oxidation as shown in FIG. However, it is necessary to remove the silicon oxide film 30208 (which is thicker than the silicon oxide film 30204 before the field oxidation by the field oxidation process) after the field oxidation. The film thickness of the silicon oxide film 30208 is the same as that in Example 27. Since it is thicker than the oxide film 30108, the field oxide film thickness after removal of the silicon oxide film 30208 and the silicon nitride film 30203 is consequently thinner than that of the embodiment 27.

  That is, in this embodiment, compared to the embodiment 27, there is a trade-off relationship that the bird's beak is suppressed but the field oxide film is thin.

  (Embodiment 29) FIGS. 50A to 50E are cross-sectional views in order of steps in forming a groove type isolation structure and a field oxide film according to the present invention.

  First, as shown in FIG. 50A, a silicon oxide film 3102 (10 to 20 nm in this embodiment) and a silicon nitride film 3103 (100 to 200 nm in this embodiment) are sequentially formed on a semiconductor substrate 3101.

  Next, as shown in FIG. 50B, through a photolithography process, a silicon nitride film 3103 having a desired groove-type isolation structure 3104 (in this embodiment, a width of 0.1 to 0.3 μm), a silicon oxide film 3102 is etched.

  Next, as shown in FIG. 50C, the silicon substrate 3101 is etched using the silicon nitride film 3103 as a mask to form a groove 3105 in the groove type isolation structure 3104, and then the inner wall of the groove 3105 is oxidized in an oxidizing atmosphere. To do. In this embodiment, a groove having a depth of about 1 to 2 μm is formed, and a silicon oxide film 3106 of about 10 to 50 nm is formed on the inner wall of the groove 3105. Next, a silicon oxide film 3107 is deposited by chemical vapor deposition (CVD). (In this embodiment, a silicon oxide film having a thickness of about 10 to 70 nm is deposited) Next, as shown in FIG. 50D, a polycrystalline silicon film 3108 (in this embodiment, about 200 nm to 600 nm is deposited). The trench 3105 is filled with a polycrystalline silicon film 3108.

  Next, as shown in FIG. 50E, the polycrystalline silicon film 3108 is etched back, leaving the polycrystalline silicon film 3108 only in the trench 3105. At this time, the silicon oxide film 3107 on the silicon nitride film 3103 is thinned by over-etching of the polycrystalline silicon film. (Although it depends on the etching selectivity, it can be almost eliminated). Thereafter, a desired groove type element isolation structure is formed through the same steps as those in Example 27 or 28.

  According to the present embodiment, the distance between the polycrystalline silicon film embedded in the groove and the silicon substrate can be removed through the silicon oxide film in the groove opening, and the bird's beak is formed as in Examples 27 and 28. In comparison, it becomes possible to further suppress.

  (Embodiment 30) In order to obtain the structure of Embodiment 24, in the manufacturing method of Embodiments 25 to 29, the step of oxidizing the groove inner wall, depositing a polycrystalline silicon film, and filling the interior of the groove with the polycrystalline silicon film It is necessary to add a step of doping impurity ions by an ion implantation method between the steps.

In this example, although it depends on the aspect ratio of the groove, the rotational injection was performed in the range of the injection angle of about 0 to 10 degrees with respect to the vertical direction. The dose was in the range of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² .

(A) is a plan view of Reference Example 1, and (b), (c), and (d) are cross-sectional views taken along lines b-b ′, c-c ′, and d-d ′, respectively, of (a). (A) is a plan view of an improved example of Reference Example 1, and (b), (c) and (d) are the bb ′ line, cc ′ line and dd ′ line of (a), respectively. Sectional drawing. The graph which shows the relationship between the gate voltage and drain current when changing the electric potential of the shallow well area | region of a MOS type transistor. The graph which shows the relationship between the gate voltage in the MOS type transistor of the reference example 1, and a drive current (drain current). The schematic diagram which shows the connection relation of each part in the semiconductor element of the reference example 2, and the parasitic bipolar transistor inside the element. (A) is a plan view of Reference Example 3, and (b), (c), and (d) are cross-sectional views taken along lines b-b ′, c-c ′, and d-d ′, respectively, of (a). (A) is a plan view of an improved example of the reference example 3 (Example 1 of the present invention), (b), (c) and (d) are respectively the bb ′ line and cc of (a). 'Line, dd' line sectional view. (A) is a top view of Example 2, (b), (c), and (d) are the b-b 'line, c-c' line, and d-d 'line sectional drawing of (a), respectively. (A) is a schematic diagram of the ohmic contact structure of Example 3, and (b) to (e) are applied examples of the ohmic contact structure of Example 3, and a cross section showing a combination of element isolation regions Figure. FIG. 6 is a schematic diagram of an ohmic contact structure of Example 4. FIGS. 5A to 5F are cross-sectional views showing application examples of the ohmic contact structure of Example 4. FIGS. (A)-(e) is process order sectional drawing of Example 5. FIG. (A)-(e) is process order sectional drawing of Example 6. FIG. (A)-(c) is process order sectional drawing of Example 6 following the process of FIG. (A) to (f) are cross-sectional views in order of steps of Example 7. Sectional drawing of the structure of the element of Example 8. FIG. FIG. 10 is a circuit diagram of an element of Example 8. Sectional drawing of the structure of the element of Example 9. FIG. FIG. 10 is a circuit diagram of an element of Example 9. The relationship between the bipolar current with respect to the power supply voltage of the element of Example 10, the drain current of the MOS transistor, the base voltage, and the gate voltage. (A) And (b) is the layout top view of the mask which combines the mask for contact formation of Example 11, and the mask for source / drain implantation. (A) And (b) is a figure for demonstrating the equivalent circuit regarding the reference example 1 in Example 12, (c) And (d) is a circuit diagram of the element of Example 12. FIG. (A) And (b) shows the relationship between the potential of the shallow p-well region (Vspwell) and the potential of the shallow n-well region (Vsnwell) with respect to the gate voltages of the transistors Trn1 and Trp1 constituting the device of Example 12. Graph. FIG. 22 is a circuit diagram of an element according to Example 13. FIG. 34 is another circuit diagram of the element in Example 13; The circuit diagram of the element of Example 14. FIG. FIG. 34 is another circuit diagram of the element in Example 14; FIG. 25 is a circuit diagram of an element according to Example 15. FIG. 26 is another circuit diagram of the element in Example 15. FIG. 18 is a circuit diagram of an element according to Example 17; FIG. 28 is another circuit diagram of the device according to the seventeenth embodiment. FIG. 28 is another circuit diagram of the device according to the seventeenth embodiment. FIG. 28 is another circuit diagram of the device according to the seventeenth embodiment. FIG. 19 is a circuit diagram of an element according to Example 18. FIG. 25 is a configuration diagram of a circuit block according to a twenty-first embodiment. FIG. 25 is another configuration diagram of the circuit block according to the twenty-first embodiment. (A)-(d) is process order sectional drawing of the element of Example 22. FIG. 24 is a cross-sectional view of a grooved element isolation structure in Example 23. FIG. (A) is an enlarged view of the A part in FIG. 38, (b) is sectional drawing of the conventional groove type element isolation structure. Sectional drawing of the groove type element isolation | separation structure of Example 24. FIG. (A)-(h) is process order sectional drawing in formation of the groove type isolation structure of Example 25, and a field oxide film. (A)-(e) is process order sectional drawing in formation of the groove type isolation | separation structure of Example 26, and a field oxide film. Sectional drawing which applied the formation method of the groove type isolation structure of Example 26 to the element of the 1st Example. Sectional drawing which applied the formation method of the groove type isolation | separation structure of Example 25 to the element of 1st Example in order to compare with the method of Example 26 in description of Example 26. FIG. (A) is sectional drawing in the process before the field oxidation by the method of Example 25, 26 quoted in description of Example 27, (b) is quoted in description of Example 27. Sectional drawing in the process after the field oxidation by the method of Example 25, 26. (A) is sectional drawing in the process before field oxidation by the method of Example 25, 26 quoted in description of Example 27, (b) is quoted in description of Example 29. Sectional drawing in the process after the field oxidation by the method of Example 25, 26. (A)-(f) is process order sectional drawing in formation of the groove type isolation structure of Example 27, and a field oxide film. (A)-(d) is process order sectional drawing of Example 28. FIG. (A)-(d) is process order sectional drawing by the manufacturing method of Example 27 corresponding to (a)-(d) of FIG. (A)-(e) is process order sectional drawing in formation of the groove type isolation structure of Example 29, and a field oxide film. The top view which shows the arrangement | positioning relationship with which the gate electrode and groove | channel type element isolation structure of a normal MOS type transistor overlap. 51A is a cross-sectional view taken along the line AA ′ in FIG. 51 when the grooved element isolation structure is conventional, and FIG. 51B is a line AA ′ line in FIG. 51 when the grooved element isolation structure is according to the present invention. Sectional drawing. (A) is a graph showing the transistor characteristics when the groove type element isolation structure is conventional, and (b) is a graph showing the transistor characteristics when the groove type element isolation structure is according to the present invention. The figure which shows the conventional dynamic threshold type MOS transistor.

101, 101 ′, 301, 301 ′, 401 Semiconductor substrate 102, 102 ′, 302, 302 ′, 402 Deep well region 103, 103 ′, 303, 303 ′, 403 Shallow well region 104, 104 ′, 304, 304 ′ , 404 Field insulating film 105, 105 ′, 305, 305 ′, 405 Gate insulating film 106, 106 ′, 306, 306 ′, 406 Gate electrode 107, 107 ′, 307, 307 ′, 407 Source region / drain region 108, 108 ', 308, 308', 408 Contact hole 3041, 4041 Field insulating film 51, 510, 511, 512, 513 Deep well region 52, 520, 521, 522, 523 Shallow well region 53, 530, 531, 532, 533 Gate oxide film 54, 540, 541, 542, 543 Electrode 55, 550, 551, 552, 553 Gate electrode side wall oxide film 56, 560, 561, 562, 563 Metal silicide film 57, 570, 571, 572, 573 Region 580 having the same conductivity type as a shallow well region having a high impurity concentration , 592, 593 Field oxide film 581, 582, 583 Groove type isolation structure 621, 631, 641, 651, 661, 671 Deep well region 622, 632, 642, 652, 662, 672 Shallow well region 623, 633, 643, 653, 663, 673 Gate oxide film 624, 634, 644, 654, 664, 674 Polycrystalline silicon film 6241, 6341, 6441, 6541, 6641, 6741 Titanium silicide films 625, 635, 645, 655, 665, 675 Gate electrode Side wall oxide film 6 6, 636, 646, 656, 666, 676 Interlayer insulating film 628, 638, 648, 658, 668, 678 Contact hole 629 Al-Cu (0.5%) wiring 6291 Aluminum alloy spike 6391, 6491, 6591, 6691, 6791 Titanium films 63911, 64911, 65911, 66911, 67911 Titanium silicide films 6392, 6492, 6592, 6692, 6792 Titanium nitride films 6393, 6493, 6593, 6693, 6793 Al-Si (1%)-Cu (0.5%) ) Wiring 6400, 6601, 6701 Field oxide film 6500, 6600, 6700 Groove-type isolation structure

Claims (7)

A semiconductor substrate;
A deep well region of a first conductivity type formed in the semiconductor substrate;
A plurality of second conductivity type shallow well regions formed in the deep well region;
A source region and a drain region of a first conductivity type formed in each of the plurality of shallow well regions;
A channel region formed between the source region and the drain region;
A gate insulating film formed on the channel region;
A gate electrode formed on the gate insulating film;
A semiconductor device comprising:
The gate electrode is electrically connected to the corresponding shallow well region, and the shallow well region is electrically isolated from other adjacent shallow well regions;
Other shallow well region said adjacent is deeper than the shallow well region said gate electrode corresponding are electrically isolated by a shallow trench isolation structure than the deep well region,
Field oxide film so as to cover a portion of the region surrounded by the said groove type element separation structure which is formed, a contact region for electrically connecting the said gate electrode and said shallow well region, said field A semiconductor device surrounded by an oxide film. The gate electrode is
A polycrystalline silicon film formed on the gate insulating film;
A metal silicide film formed on the polycrystalline silicon film,
The metal silicide film via the contact region of the shallow well region is electrically connected to the shallow well,
In the contact region , a high concentration impurity diffusion region is formed in which impurities of the same conductivity type as the conductivity type of the shallow well region are diffused with an impurity concentration higher than the impurity concentration of other portions of the shallow well region. ,
The semiconductor device according to claim 1, wherein the metal silicide film and the shallow well region are in ohmic contact with each other through the high concentration impurity diffusion region. An interlayer insulating film provided on the semiconductor substrate;
An upper wiring provided on the interlayer insulating film,
The interlayer insulating film, wherein which the contact hole reaching the contact regions are formed of the gate electrode and the shallow well region through said gate insulating film,
In the contact region , a high concentration impurity diffusion region is formed in which impurities of the same conductivity type as the conductivity type of the shallow well region are diffused with an impurity concentration higher than the impurity concentration of other portions of the shallow well region. ,
At the bottom of the contact hole, the upper wiring and the shallow well region are ohmically connected via the high-concentration impurity diffusion region,
In the side wall portion of the contact hole, a semiconductor device according to claim 1 wherein said gate electrode and the upper wiring and is ohmically connected. In operation, a potential difference is formed between the potential difference formed between the shallow well region and the source region, and shallow well region and the drain region are both, pn junction in the semiconductor device The semiconductor device according to claim 1, wherein the semiconductor device is set to be smaller than the built-in potential. 4. The semiconductor device according to claim 1, wherein nitrogen ions or carbon ions are doped at a junction between the source region and the drain region and the shallow well region. A power supply voltage cutoff circuit is provided between a circuit block configured by the semiconductor device according to claim 1 and a power supply voltage supply source,
A semiconductor device that cuts off supply of power supply voltage when the circuit block is in a standby state. A cutoff circuit is provided between the circuit block configured by the semiconductor device according to any one of claims 1 to 3 and a power supply voltage supply source, and between the circuit block and the ground voltage supply source,
A semiconductor device that cuts off supply of power supply voltage and supply of ground voltage when the circuit block is in a standby state.

Images