JP4541220B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device having a non-volatile memory cell transistor (non-volatile memory element) and a method for manufacturing the same. For example, a non-volatile memory using a non-conductive charge trap film as an information holding region is used as a CPU. The present invention relates to a technology effective when applied to a semiconductor integrated circuit device provided on-chip together with (Central Processing Unit).

  In recent years, as a memory device that stores data and data constituting a program, a nonvolatile storage device that can electrically erase stored data in a predetermined unit and can write data electrically has been adopted. Flash EEPROM (hereinafter referred to as flash memory) is attracting attention. In flash memory, memory cells are composed of electrically erasable and writable non-volatile memory elements. Data written in the memory cells and data constituting the program are erased, and new data and data constituting the program are erased. Can be rewritten (programmed) into the memory cell.

  Conventionally, charge accumulation in a flash memory has been performed by accumulating electrons in a floating gate made of a polysilicon film and electrically insulated from the surroundings. This conventional memory cell is called a floating gate type flash. This electron storage operation, so-called write operation, is generally hot electron injection, and the erase operation for releasing the stored electrons to the outside of the floating gate is performed by a tunnel current passing through the gate oxide film. When writing and erasing are repeated, charge traps are formed inside the gate oxide film, and the surface state density increases at the interface between the substrate and the gate oxide film. In particular, the former has an essential problem of deteriorating charge retention characteristics, that is, retention characteristics after rewriting.

  As a method for solving this problem, in recent years, a memory cell system using a non-conductive charge trapping film has been proposed for charge accumulation in an EEPROM. For example, US Patent Publication No. 5,768,192, US Patent Publication No. 5,966,603, US Patent Publication No. 6,011,725, US Patent Publication No. 6,180,538, and B. Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell International Conference on Solid State Devices and Materials, Tokyo, 1999. For example, US Patent Publication No. No. 5,768,192 discloses a silicon nitride film 183 sandwiched between insulating films 182 and 184 such as a silicon oxide film, that is, a so-called ONO (Oxide / Nitride / Oxide) structure as shown in the sectional view of FIG. The stacked film is used as a gate insulating film, and the transistor is turned on by applying 0 V to the source 187, 5 V to the drain 186, and 9 V to the control gate 185, and hot electrons generated near the drain 186 are generated. Is written by trapping electrons into the silicon nitride film 183. This first conventional memory cell has a charge storage method in which polysilicon is a continuous conductive film. Compared to the method of storing charge in the film, since the electron traps in the silicon nitride film 183 are discontinuous and discrete, even when a charge leakage path such as a pinhole occurs in a part of the oxide film 182, All of the accumulated charges are not lost, and the retention characteristic is essentially strong, and the erase operation of this memory cell is 3 V at the source 187 as shown in FIG. 5V is applied to the drain 186 and -3V is applied to the control gate 185 to strongly invert the vicinity of the silicon surface of the drain 186 and change significantly due to the strong electric field. By injecting hot holes into the silicon nitride film 183 in that occur interband tunneling caused by the energy band, it is carried out by neutralizing the electrons already trapped.

  Further, in US Pat. No. 5,408,115 and US Pat. No. 5,969,383, side spacers are provided as shown in FIGS. 60 and 61 for its memory cell structure and write / erase method. A memory cell system is disclosed that has a split gate utilized and stores charge in the ONO film. In the conventional second memory cell, as shown in FIG. 60, a select gate 163 is arranged via a gate oxide film 162 on the surface of the substrate 161, and a lower oxide film 165 and silicon nitride are formed around the select gate 163. After the film 166 and the upper oxide film 167 are stacked, a side spacer-shaped control gate 168 is disposed. Since the source 164 of the conventional second memory cell is formed immediately after the processing of the select gate 163 and the drain 169 is formed after the processing of the control gate 168, only the control gate 168 on the drain 169 side is used as the gate electrode. Function.

  In the conventional write operation to the second memory cell, 5V is applied to the drain 169, 1V is applied to the select gate 163, and 10V is applied to the control gate 168 to turn on the channel, and electrons traveling from the source 165 are transferred to the select gate 163. Accelerates in a strong horizontal electric field generated in the channel region below the boundary between the gate and the control gate 168 to form hot electrons, penetrates through the lower oxide film 165, and is injected into the silicon nitride film 167 for trapping. Is called. This operation is generally called a source-side injection (SSI) method because the hot electron injection position is not near the drain. In the conventional erase operation of the second memory cell, as shown in FIG. 61, 14V is applied only to the control gate 168, and the electrons trapped in the silicon nitride film 166 flow through the upper oxide film 167. This is done by drawing it out to the control gate 168 side as a current. In this erasing operation, electron injection from the substrate 161 side also occurs due to the tunnel current through the lower oxide film 165, so that the lower oxide film 165 needs to be set thicker than the upper oxide film 167.

  Further, in the conventional read operation of the second memory cell, as shown in FIG. 62, 2V is applied to the drain 169, 5V is applied to the select gate 163, the channel is turned on, and 2V is applied to the control gate 168. The threshold voltage level based on the presence or absence of trapped electrons in the silicon nitride film is determined from the magnitude of the drain current. Compared to the conventional first memory cell, the conventional second memory cell has an advantage that the drain current required for the write operation is small and the power can be reduced. This is because the conventional second memory cell includes the select gate 163, so that the channel current at the time of writing can be controlled low, and can be reduced to 1/100 or less of the conventional first memory cell. is there.

  Further, US Pat. No. 5,408,115 discloses a conventional third memory cell whose structure is shown in FIG. This conventional third memory cell has a structure in which the structural positions of the select gate and the control gate in the conventional second memory cell are exchanged, and includes a lower oxide film 172, a silicon nitride film 173, and an upper oxide film. After the control gate 175 is formed on the top of the stacked 174, a gate oxide film 177 and a side spacer-shaped select gate 178 are formed. The voltage setting in the write, erase and read operations of the conventional third memory cell is the same as that of the conventional second memory cell.

  In addition, I. Fujiwara et al., “High speed program / erase sub 100 nm MONOS memory Nonvolatile Semiconductor Memory Workshop, August, 2001, p75” shows a conventional fourth memory cell system whose cross-sectional views are shown in FIGS. It is disclosed. As shown in FIG. 64, an ONO (Oxide / Nitride / Oxide) laminated film composed of an insulating film 192 such as a silicon oxide film and a silicon nitride film 193 sandwiched between 194 is used as a gate insulating film, and 12 V is applied to the control gate 195. And an electron injection from the semiconductor substrate 191 side by a tunnel current to trap electrons in the silicon nitride film 193 to bring them into a high threshold voltage state, and 6V to the source 197 and the drain 196, the control gate -6 V is applied to 195 to strongly invert the silicon surface in the vicinity of the source / drain, and hot holes generated by an interband tunnel phenomenon caused by an energy band significantly deformed by a strong electric field are injected into the silicon nitride film 193. By neutralizing the already trapped electrons, write to a low threshold voltage state Work is carried out.

US Pat. No. 5,768,192 US Pat. No. 5,408,115 High speed program / erase sub 100nm MONOS memory, I. Fujiwara, Nonvolatile Semiconductor Memory Workshop, August, 2001, p75

  The present inventor has found the following problems as a result of examining the above-described conventional technology.

  The first problem is that the drain current at the time of reading in the low threshold voltage state is small. This problem is a major drawback in a flash memory module for mixed logic that requires high-speed reading of about 100 MHz, for example. In the first conventional memory cell, the gate insulating film is formed by B. Eitan et al. “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell International Conference on Solid State Devices. and Materials, Tokyo, 1999, the insulating films 182 and 184 such as silicon oxide films shown in FIGS. 58 and 59 are set to 5 nm, and the silicon nitride film 183 is set to 10 nm. The electrical equivalent effective film thickness is about 15 nm, which is 1.5 times thicker than the conventional floating gate type memory cell designed with a gate oxide film thickness of about 10 nm. Compared with memory cells having effective channel width / effective channel length, the read drain current is reduced to about 1 / 1.5.

  In the conventional second memory cell shown in FIGS. 60 to 62, the gate oxide film 163 below the select gate 163 can be designed independently without depending on the write / erase characteristics of the memory cell. For example, it can be designed to be about 5 nm. In addition, even when the lower part of the control gate 168 and the upper oxide films 165 and 167 are designed to be 5 nm, the silicon nitride film 166 is 10 nm, and the effective film thickness is 15 nm, the effective channel length can be adjusted by the side spacer length. The design can be shorter than the select gate length defined by the minimum processing dimension. As a result, the effective channel length of the conventional second memory cell is two series lengths of the select gate 163 and the control gate 168, but the read current in the low threshold voltage state is the same as the conventional first memory cell. Larger designs are possible. In this respect, the number of gate electrodes to be controlled increases, but the conventional second memory cell is superior.

  The second problem relates to the reliability of the second conventional memory cell. As described above, this write / erase operation is performed by hot-electron source-side injection write and tunnel electron emission erase to the control gate side. The inventors of the present invention conducted a rewriting test using this operation method, and obtained a result that the erasing time was significantly deteriorated when the number of rewriting exceeded 10,000. When this cause is analyzed, as shown in FIG. 61, electrons trapped in the corner portion of the silicon nitride film 166, which is an electron trap film arranged in an L shape, are difficult to be emitted to the control gate 168 side. It turned out to be. When the rewrite operation is repeated, the amount of trapped electrons in the corner portion of the silicon nitride film 166 gradually increases. However, the effective film thickness of the silicon nitride film 166 viewed from the control gate 168 is √2 times that of the flat portion (approximately 1.. 4 times), it was considered that the in-film electric field strength at the time of erasing was lowered.

  Further, if the gate oxide film 163 shown in FIG. 60 is set to 4 nm or less in order to design the read current in the low threshold voltage state to be larger, a breakdown failure of the gate oxide film 163 may occur during the write operation. found. As described above, at the time of the write operation, 10V is applied to the control gate 168 and a channel is formed immediately below the control gate 168. Is transmitted to the gate oxide film 162. At this time, the maximum voltage applied to the gate oxide film 162 is (drain 169 voltage = 5V) − (select gate 163 voltage = 1V) = 4V. Therefore, the conventional second memory cell has a lower limit on the thickness of the gate oxide film 163, which limits the read current. In the flash memory module for mixed logic, it is desirable from the viewpoint of simplifying the manufacturing process that the gate oxide film 163 is designed to have the same film thickness as the gate oxide film of the power supply voltage transistor. For example, the gate oxide film thickness of the logic transistor in the 0.13 μm technology generation is 2.5 to 3.0 nm. However, in the conventional second memory cell, the gate oxide film film is used in terms of the gate oxide film breakdown voltage. It was difficult to make the thickness common.

  The third problem relates to the reliability of the above-described conventional fourth memory cell. This write operation depends on hot hole injection from the source / drain junction, as described above. Since the reach distance in the lateral direction in the silicon nitride film 193 of hot holes generated only in the vicinity of the source / drain junction is about 50 nm, the effective channel length of the conventional fourth memory cell is designed to be 100 nm or less. There is a need. Therefore, the single channel effect is remarkable, the stable control of the initial threshold voltage is difficult, the leakage current of the bit line when performing NOR type array connection, the so-called off-leakage current increases, and the variation becomes large, There was a problem such as.

  The fourth problem is that a conventional memory cell performs a gate electrode for performing a write / erase operation and a read operation as shown in FIGS. 58, 59, 60 to 62, 63, 64, and 65. Since the gate electrodes are the same, for example, in the conventional fourth memory cell shown in FIGS. 64 and 65, a weak electric field is applied to the insulating film 192 by applying the power supply voltage to the control gate 195 in the read operation. As a result, weak hot electron injection occurs from a low threshold voltage state in which holes are trapped in the silicon nitride film 193, and the threshold voltage gradually rises, so-called read disturb life is short. As a result, when continuous reading is performed for 10 years, the threshold voltage rises above the power supply voltage applied to the control gate 195, and a defect in which data is inverted occurs.

  An object of the present invention is to provide a technique capable of reading out stored information at high speed from a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device.

  Another object of the present invention is to reduce a parasitic resistance value in a channel portion of a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device.

  Still another object of the present invention is to provide a semiconductor integrated circuit device capable of preventing a charge of one polarity from being permanently trapped in a nonvolatile memory cell transistor formed in the semiconductor integrated circuit device, and It is to provide a manufacturing method.

  Still another object of the present invention is to prevent deterioration of data retention characteristics due to undesired leakage of charges accumulated in a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device.

  Still another object of the present invention is to eliminate a thick high voltage MIS transistor that impairs high speed from a signal path for reading stored information from a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] << Split Gate, Opposite Polarity Charge Injection, Negative Substrate Potential >> A semiconductor integrated circuit device according to the present invention has a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor has a pair of memory electrodes, one of which is a source electrode and the other of which is a drain electrode, and a channel region sandwiched between the pair of memory electrodes in a first well region of the semiconductor substrate. On the channel region, a first gate electrode (3, 123) disposed near the memory electrode via an insulating film (2, 122), an insulating film (4, 7, 124, 126), and A second gate electrode (8, 127) disposed through the charge storage region (6, 125) and electrically separated from the first gate electrode; The access circuit applies a first negative voltage to the first well region to form a reverse voltage application state between the first well region and the memory electrode near the second gate electrode, and accumulates the first polarity charge from the well region side. A first state can be selected that creates an electric field directed to the region. The access circuit can select a second state in which an electric field for directing the second polarity charge from the well region to the charge storage region is formed. Here, the first polarity charge means a positive charge represented by holes or a negative charge represented by electrons, and the second polarity charge means a charge having a polarity opposite to that of the first polarity charge.

  According to the above-described means, the first negative voltage is applied to the first well region to form a reverse voltage application state (reverse bias state) with the memory electrode near the second gate electrode. Tunneling makes it possible to generate hot holes and hot electrons, and an electric field that directs the first polar charge, for example, hot holes, from the well region side to the charge storage region is generated, resulting in hot hole avalanche, Hot holes are injected into the charge storage region.

  Further, in the first state, a larger reverse bias state is formed between the memory electrode near the second gate electrode than when a hot hole or the like is generated by the band-to-band tunneling. Avalanche hot holes can be generated, more avalanche hot holes are injected into the charge storage region, the time for hole injection can be shortened, and the time for writing or erasing information can be shortened.

  Here, the reverse bias between the reverse bias voltage of the pn junction when a hot hole or the like is generated by the band-to-band tunneling and the reverse bias voltage of the pn junction when more avalanche hot holes are generated. The voltage is referred to as a junction breakdown voltage (junction breakdown voltage). Therefore, a reverse bias state that is larger than when a hot hole or the like is generated by the band-to-band tunneling may be grasped as a reverse voltage application state in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage. If the junction breakdown voltage is to be defined quantitatively, a reverse current of an allowable leakage current that is allowed to flow through a channel of an off-state MIS (Metal Insulate Semiconductor) transistor is generated in a pn junction (also simply referred to as a junction). The reverse bias voltage when flowing can be defined as the junction breakdown voltage. In this specification, the junction breakdown voltage does not mean a junction breakdown voltage.

  When forming a reverse bias state in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage, the well region is set to a negative voltage, so the voltage to be applied to the memory electrode should be lower than when the well region voltage is set to the circuit ground voltage. Is possible. Therefore, even when a readout system circuit such as a sense amplifier is connected to the memory electrode, it is not necessary to configure the readout system circuit with a high voltage MIS transistor.

  Further, since the second gate electrode is electrically separated from the first gate electrode (so-called split gate structure), a high voltage is applied to the second gate electrode to form the first state or the second state. However, the withstand voltage of the first gate electrode is not affected by it. Therefore, it is not necessary to form the insulating film of the first gate electrode with a high breakdown voltage thick film. For example, the insulating film of the first gate electrode can be made relatively thin like the logic MIS transistor. Therefore, Gm in the MIS transistor portion of the first gate electrode portion in the memory cell transistor can be made relatively large, and in the read operation of the stored information, the first gate can be applied without particularly increasing the voltage applied to the first gate electrode. The amount of signal current passing through the channel portion directly under the electrode can be increased.

  When the insulating film of the first gate electrode is made relatively thin like the logic MIS transistor, and when a negative voltage is applied to the well region at the time of hot hole injection, the insulating film is formed relatively thin like the logic MIS transistor. In order to prevent the insulating film of the first gate electrode from being destroyed, it is desirable to apply a negative voltage lower than the circuit ground voltage to the first gate electrode within the breakdown voltage range.

  When the memory cell transistor is configured as a memory cell for storing binary information, n one first gate electrode is provided near one memory electrode, and the second gate electrode and the charge storage region are provided in the other memory. One memory cell transistor is provided near the electrode. The memory cell transistor can store binary information according to a difference in charge amount between the first polarity charge and the second polarity charge injected into the charge storage region. For example, electrons are injected into the charge storage region to form a high threshold voltage state (for example, an erased state), and hot electrons are injected into the charge storage region into which electrons are injected to neutralize the electrons, thereby lowering the threshold voltage. A state (for example, a write state) is formed.

  When the memory cell transistor is configured as a memory cell for storing quaternary information, the second gate electrode and the charge storage region are provided close to each memory electrode, and the first gate electrode is a pair of second gate electrodes. One is provided in the area between. The memory cell transistor can store quaternary information according to the difference in charge amount between the first polarity charge and the second polarity charge injected into the pair of charge storage regions. For example, in the case of an n-channel memory cell transistor, a read operation for a memory cell transistor that stores quaternary information is widely spread to the drain side when the logical value of the stored information is determined based on the presence or absence of a current flowing from the drain electrode to the source electrode. Considering the depletion layer, the MIS transistor portion in the charge storage region located on the source electrode side has a conductance according to the threshold voltage state. The MIS transistor portion in the charge storage region located on the drain side does not substantially function as a switch regardless of the threshold voltage. Therefore, four-value determination of stored information is possible based on the presence / absence of current flowing in the channel region when one memory electrode is a drain and the presence / absence of current flowing in the channel region when the other memory electrode is a drain. Become.

  [2] << Split Gate, Opposite Polarity Charge Injection, Negative Substrate Potential >> A semiconductor integrated circuit device according to a specific embodiment of the present invention has a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor has a pair of memory electrodes, one of which is a source electrode and the other of which is a drain electrode, and a channel region sandwiched between the pair of memory electrodes in a first well region of the semiconductor substrate. On the channel region, a first gate electrode disposed near the one memory electrode via an insulating film and a first gate electrode disposed near the other memory electrode via an insulating film and a charge storage region. A second gate electrode electrically separated from the gate electrode; The access circuit applies a first negative voltage to the first well region to apply a reverse voltage between the memory electrode near the second gate electrode and the first well region, and applies a first polarity charge to the first well region. A first state in which a voltage for forming an electric field directed from the well region side toward the charge accumulation region is applied to the second gate electrode can be selected. The access circuit can select a second state in which a voltage for forming an electric field for directing the second polarity charge to the charge storage region is applied to the second gate electrode and the first well region.

  In the first state, a reverse voltage application state (reverse bias state) near the junction breakdown voltage or higher than the junction breakdown voltage may be formed with the memory electrode near the second gate electrode.

  According to the above-described means, the first negative voltage is applied to the first well region to form a reverse voltage application state (reverse bias state) with the memory electrode near the second gate electrode. Tunneling makes it possible to generate hot holes and hot electrons, and an electric field that directs the first polar charge, for example, hot holes, from the well region side to the charge storage region is generated, resulting in hot hole avalanche, Hot holes are injected into the charge storage region.

  Further, in the first state, a reverse voltage application state (reverse bias state) near the junction withstand voltage or higher than the junction withstand voltage is formed between the memory electrode close to the second gate electrode and more. Balancing hot holes can be generated and more balancing hot holes are injected into the charge storage region, so that the time for hole injection can be shortened and the time for writing or erasing information can be shortened.

  When a reverse bias state equal to or higher than the junction breakdown voltage is formed, the voltage to be applied to the memory electrode can be made lower than when the well region voltage is set to the circuit ground voltage because the well region is set to a negative voltage. . For example, when the access circuit includes a first MIS transistor having a relatively thin gate insulating film and a second MIS transistor having a relatively thick gate insulating film, the access circuit is configured to form the first state in order to form the first state. The voltage applied to the memory electrode near the second gate electrode can be the first operating power supply voltage (Vdd) of the circuit configured by the first MIS transistor. Therefore, even when a readout system circuit such as a sense amplifier is connected to the memory electrode, it is not necessary to configure the readout system circuit with a high voltage MIS transistor.

  In addition, since the electric field for injecting the second polar charge, for example, electrons, is formed between the well region and the second gate electrode, the electric field intensity is not biased or extremely biased at each of the opposing bottom surfaces of the charge storage region. Therefore, it is easy to uniformly inject the second polarity charge into the charge storage region, and it is possible to prevent the occurrence of partial erasure or unwritten writing. The possibility of partial unerasing or unwriting becomes obvious when a non-conductive trap film or the like is employed in the charge storage region.

  Further, since the second gate electrode is electrically separated from the first gate electrode (so-called split gate structure), a high voltage is applied to the second gate electrode to form the first state or the second state. However, the withstand voltage of the first gate electrode is not affected by it. Therefore, it is not necessary to form the insulating film of the first gate electrode with a high breakdown voltage thick film. For example, the insulating film of the first gate electrode can be made relatively thin like the logic MIS transistor. Therefore, Gm in the MIS transistor portion of the first gate electrode portion in the memory cell transistor can be made relatively large, and in the read operation of the stored information, the first gate can be applied without particularly increasing the voltage applied to the first gate electrode. The amount of signal current passing through the channel portion directly under the electrode can be increased.

  When the insulating film of the first gate electrode is made relatively thin like the logic MIS transistor, and when a negative voltage is applied to the well region at the time of hot hole injection, the insulating film is formed relatively thin like the logic MIS transistor. In order to prevent the insulating film of the first gate electrode from being destroyed, a negative voltage lower than the circuit ground voltage is applied to the first gate electrode, for example, a second negative voltage having an absolute value smaller than the first negative voltage. May be applied. For example, the second negative voltage is optimally a voltage (−Vcc) whose absolute value is equal to the first operating power supply voltage. Accordingly, the first negative voltage may be set to a voltage (−nVcc) whose absolute value is several times the first operating power supply voltage, for example.

  If the electric field formed in the second state is an electric field in which the second polarity charge is directed from the well region to the charge accumulation region, so-called write / erase can be performed by injecting charges having opposite polarities from the well region. it can. For example, in the second state, a positive voltage is applied to the second gate electrode, and a circuit ground voltage is applied to the first well region. As a result, it is not necessary to consider the trade-off between prevention of undesired charge leakage for the insulating film between the second gate electrode and the charge storage region and good charge extraction performance when rewriting stored information. Therefore, when the charge storage region is formed by, for example, an ONO structure, there is no problem if the upper (near the second gate electrode) oxide film (insulating film) is formed thicker than the lower (well region side). It becomes easy to reduce undesired charge leakage through the second gate electrode.

  In the second state, a ground voltage of the circuit is preferably supplied to the memory electrode near the second gate electrode.

  Paying attention to the read operation of stored information, the access circuit further allows a current to flow in the channel region with the second gate electrode as the ground voltage of the circuit and the first gate electrode as the first power supply voltage. It is sufficient if the state can be selected.

  For the charge storage region, a nonconductive charge trap film, an insulating film having conductive fine particles, a conductive floating gate electrode covered with an insulating film, or the like can be used.

  When the access circuit includes a first MIS transistor having a relatively thin gate insulating film and a second MIS transistor having a relatively thick gate insulating film, the insulating film of the first gate electrode is more than the insulating film of the second gate electrode. Can also be made thinner. For example, the insulating film of the first gate electrode may be made equal to the gate insulating film thickness of the first MIS transistor.

  The semiconductor number product circuit device may further include a logic circuit connected to the access circuit and including the first MIS transistor. The logic circuit may include a CPU and a RAM, for example.

  [3] << Split Gate / Inverse Polarity Charge Injection / Negative Substrate Potential> A semiconductor integrated circuit device according to another specific embodiment of the present invention has a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor is sandwiched between a pair of memory electrodes (10, 11), one of which is a source electrode and the other is a drain electrode, and the pair of memory electrodes, in a first well region of the semiconductor substrate. A first gate electrode (3) disposed via an insulating film (2) near the one memory electrode region, and near the other memory electrode region. The semiconductor device includes a second gate electrode (8) disposed via the insulating films (5, 7) and the charge storage region (6) and electrically separated from the first gate electrode. The access circuit applies a negative voltage that forms a reverse bias state to the memory electrode near the second gate electrode to the first well region and injects a first polarity charge into the charge storage region. Can be selected. The access circuit can select a second operation in which a positive voltage is applied to the second gate electrode to inject a second polarity charge into the charge storage region.

  In the first operation, a reverse bias state in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage may be formed between the memory electrode near the second gate electrode and the first well region by the negative voltage.

  When the access circuit includes a first MIS transistor having a relatively thin gate insulating film and a second MIS transistor having a relatively thick gate insulating film, the access circuit is close to the second gate electrode in the first operation. The voltage applied to the memory electrode may be the first operating power supply voltage of the circuit configured by the first MIS transistor.

  The access circuit may apply a second negative voltage having an absolute value smaller than the first negative voltage to the first gate electrode in the first operation. The second negative voltage may be a voltage whose absolute value is equal to the first operating power supply voltage. The first negative voltage may be a voltage whose absolute value is several times the first operating power supply voltage.

  The access circuit can inject hot electrons into the charge storage region by applying a second negative voltage that is larger in absolute value than the first negative voltage to the second gate electrode in the first operation.

  The access circuit applies a ground voltage of the circuit to the well region in the second operation, and also applies a ground voltage of the circuit to the memory electrode near the second gate electrode, so that the charge accumulation region is transferred from the well region to the well region. Electrons can be injected.

  Focusing on the read operation of the stored information, the access circuit further allows a current to flow in the channel region with the second gate electrode as the circuit ground voltage and the first gate electrode as the first power supply voltage. It is sufficient that the operation can be selected.

  In the access circuit, more hot holes are formed by forming a reverse bias state, for example, near the junction breakdown voltage or higher than the junction breakdown voltage with the memory electrode near the second gate electrode in the first operation. Thus, more hot holes are injected into the charge storage region, the hole injection time can be shortened, and the information writing or erasing time can be shortened.

  [4] << Split Gate, Opposite Polarity Charge Injection, Negative Substrate Potential >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention includes a memory cell transistor and a gate insulating film that are relatively thin on a semiconductor substrate. The first MIS transistor and the second MIS transistor having a relatively thick gate insulating film are included. The memory cell transistor is sandwiched between a pair of memory electrodes (10, 11), one of which is a source electrode and the other is a drain electrode, and the pair of memory electrodes, in a first well region of the semiconductor substrate. A first gate electrode (3) disposed via an insulating film (2) near the one memory electrode region, and near the other memory electrode region. A second gate electrode (8) disposed through the insulating films (5, 7) and the charge storage region (6) and electrically separated from the first gate electrode is injected into the charge storage region. Different information can be stored in accordance with the difference in charge amount between the first polarity charge and the second polarity charge. The insulating film under the first gate electrode has the same thickness as the gate insulating film of the first MIS transistor. When the first polarity charge is injected into the charge storage region, the well region forms, for example, a negative voltage that forms a reverse bias state in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage with the memory electrode near the second gate electrode. Is given. The second gate electrode is given a positive voltage when a second polarity charge is injected into the charge storage region.

  [5] << Multilevel Memory Cell >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention has a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor has a first well region of the semiconductor substrate, a pair of memory electrodes (128), one of which is a source electrode and the other of which is a drain electrode, and a channel region sandwiched between the pair of memory electrodes And on the channel region, the memory gate electrode (127) separately disposed through the insulating films (124, 126) and the charge storage region (125) near the respective memory electrodes, A control gate electrode (123) disposed between the memory gate electrodes via an insulating film (122) and electrically isolated from the memory gate electrode is provided. The access circuit applies a negative voltage to the first well region to form a reverse bias state, for example, in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage with respect to one of the memory electrodes, and the first polarity charge from the well region side A first state in which an electric field directed to the charge storage region on the memory electrode side of the first electrode is formed; a second state in which an electric field is directed from the well region toward the charge storage region of both memory gate electrodes; And a third state in which a current can flow from one memory electrode to the other memory electrode.

  << Multi-Value Memory Cell Perspective >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention has a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor has a first well region of the semiconductor substrate, a pair of memory electrodes (128), one of which is a source electrode and the other of which is a drain electrode, and a channel region sandwiched between the pair of memory electrodes And on the channel region, the memory gate electrode (127) separately disposed through the insulating films (124, 126) and the charge storage region (125) near the respective memory electrodes, A control gate electrode (123) disposed between the memory gate electrodes via an insulating film (122) and electrically isolated from the memory gate electrode is provided. The access circuit applies a negative voltage to the first well region to form a reverse bias state, for example, in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage with respect to one of the memory electrodes, so that the first polarity charge is transferred to the one charge storage region. A second operation in which a positive voltage is applied to both memory gate electrodes to inject a second polarity charge into both charge storage regions from the well region, and one of the two operations is performed via the channel region. A third operation in which a current can flow from the memory electrode to the other memory electrode can be selected.

  [6] << Split Gate, Opposite Polarity Charge Injection, Negative Substrate Potential >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention includes a semiconductor substrate on which a memory cell transistor and a gate insulating film are relatively thin. 1 MIS transistor and a second MIS transistor having a relatively thick gate insulating film. The memory cell transistor has a source region, a drain region, and a channel region sandwiched between the source region and the drain region in a first well region of the semiconductor substrate, and the channel region is over the channel region, A first gate electrode (CG) disposed on one side of the source region and drain region; a second gate electrode disposed on the other side of the source region and drain region; the channel region; and the first gate electrode. A first gate insulating film (46, 129) formed between the first gate electrode, a charge storage region (6, 125) formed between the channel region and the second gate electrode, and the first gate electrode. And an insulating film for electrically separating the second gate electrode. In the write or erase operation of the memory cell transistor, the first well region has a negative voltage or a circuit whose absolute value is smaller than several times the power supply voltage (Vcc) of the circuit constituted by the first MIS transistor. The ground voltage is applied to inject carriers into the charge storage region.

  << Applying Negative Voltage (-Vcc) to CG >> In the write or erase operation of the memory cell transistor, for example, the negative first voltage is applied to the second gate electrode, and the negative first voltage is applied to the first gate electrode. It is possible to apply a negative second voltage having a smaller absolute value to inject holes into the charge storage region.

  [7] << Negative Voltage to MG> Negative Voltage to CG, Hole Injection >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention includes a memory cell transistor. The memory cell transistor has a source region, a drain region, and a channel region sandwiched between the source region and the drain region in a first well region of the semiconductor substrate, and the channel region is over the channel region, A first gate electrode (CG); a second gate electrode (MG); a first gate insulating film (46, 129) formed between the channel region and the first gate electrode; A charge storage region (6, 125) formed between the second gate electrode and an insulating film for electrically separating the first gate electrode and the second gate electrode; In the programming or erasing operation of the memory cell, a negative first voltage is applied to the second gate electrode, and a negative second voltage having an absolute value smaller than the negative first voltage is applied to the first gate electrode. Then, holes are injected into the charge storage region.

  In the above, if the second voltage applied to CG is set to a low voltage such as −Vcc, the control system of the first gate electrode can be formed by a low withstand voltage MIS circuit. For example, the first gate electrode is electrically connected to a first driver circuit that drives the gate control line through a gate control line. The first driver circuit is composed of a low breakdown voltage transistor (power supply voltage MIS transistor). The first gate insulating film is formed in a gate insulating film forming step of the low breakdown voltage transistor.

  The charge storage region is composed of a non-conductive charge trap film. The charge storage region is formed on the channel region via a first insulating film. The first gate electrode constitutes a control gate electrode. The second gate electrode constitutes a memory gate electrode.

  [8] << Vcc for source or drain, negative voltage for well, hole injection >> In a semiconductor integrated circuit device according to still another specific embodiment of the present invention, a memory cell transistor and a gate insulating film are relatively disposed on a semiconductor substrate. A thin first MIS transistor and a second MIS transistor having a relatively thick gate insulating film are provided. The memory cell transistor includes a source region, a drain region, a channel region sandwiched between the source region and the drain region in a first well region of a semiconductor substrate, a gate electrode, the channel region, and the gate electrode. Charge storage regions (6, 125) formed between the two. In the write or erase operation of the memory cell transistor, a negative first voltage is applied to the gate electrode, and a negative second voltage whose absolute value is less than or equal to the first voltage is applied to the first well region, A third voltage (Vcc) whose absolute value is equal to or lower than the power supply voltage (Vcc) of the circuit constituted by the first MIS transistor is applied to the source or drain region, and holes are injected into the charge storage region.

  << Hole Generation with Applied Voltage ≧ Junction Withstand Voltage >> In the write or erase operation of the memory cell, the potential difference between the third voltage (Vcc) and the second voltage (−2 Vcc) is the junction voltage of the source or drain region. Close to breakdown voltage, holes can be generated by band-to-band tunneling.

  If the third voltage applied to the drain is a low voltage such as Vcc, a bit line system circuit connected to the drain can be formed by a low withstand voltage MIS circuit. For example, the source region or the drain region is electrically connected to a first driver circuit that drives the bit control line via a bit control line. The first driver circuit is composed of a low breakdown voltage transistor (power supply voltage MIS transistor). The charge storage region is formed of a non-conductive charge trap film on the channel region via a first insulating film.

  [9] << A gate of a peripheral MOS transistor is a stacked structure of CG and MG, FIG. 24, FIG. 55> Have. The memory cell transistor includes a source region, a drain region, a channel region sandwiched between the source region and the drain region, and a first gate disposed on the channel region in a memory cell formation region of a semiconductor substrate. An electrode and a second gate electrode; a first gate insulating film (46, 129) formed between the channel region and the first gate electrode; and formed between the channel region and the second gate electrode. Charge storage regions (6, 125), and an insulating film for electrically separating the first gate electrode and the second gate electrode. The peripheral circuit transistor (power supply voltage MIS transistor, high voltage MIS transistor) has a gate electrode on the peripheral circuit transistor formation region of the semiconductor substrate. The gate electrode of the peripheral circuit transistor is formed of a stacked film in which a first conductive film in the same layer as the first gate electrode and a second conductive film in the same layer as the second gate electrode are stacked.

  The charge storage region is formed of, for example, a non-conductive charge trap film. The first gate electrode constitutes the control gate electrode. The second gate electrode constitutes a memory gate electrode, and is formed in a sidewall spacer shape (8, 62, 98, 127) on the side wall of the control gate electrode via an insulating film. The second conductive film is formed on the first conductive film.

  The peripheral circuit transistors include a low breakdown voltage transistor (power supply voltage MIS transistor) that operates at a power supply voltage (Vcc) and a high breakdown voltage transistor (high voltage system MIS transistor) that operates at a voltage higher than the power supply voltage.

  The first gate insulating film (46, 129) is formed in the gate insulating film forming step of the low breakdown voltage transistor.

  [10] << Manufacturing Process of Item [9] >> A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a first conductive film on a memory cell formation region and a peripheral circuit transistor formation region of a semiconductor substrate. And patterning the first conductive film on the memory cell formation region to form a first conductive pattern that acts as a first gate electrode of the memory cell, and forming the first conductive pattern on the peripheral circuit transistor formation region. Leaving a film; forming a second conductive film on the memory cell formation region; and on the first conductive film in the peripheral circuit transistor formation region; and etching the second conductive film to at least the first A second gate electrode of the memory cell is formed on a side wall of the conductive pattern, and a peripheral portion including a second conductive film and a first conductive film is formed on the peripheral circuit transistor formation region. And forming a gate electrode of the road transistor.

  The memory cell includes a memory cell formation region of a semiconductor substrate, a source region, a drain region, a channel region sandwiched between the source region and the drain region, a control gate electrode and a memory disposed on the channel region. A gate electrode, a first gate insulating film (46, 129) formed between the channel region and the control gate electrode, and a charge storage region (between the channel region and the memory gate electrode). 6, 125). The first gate electrode constitutes the control gate electrode. The second gate electrode constitutes the memory gate electrode.

  The peripheral circuit transistor includes a low breakdown voltage transistor (power supply voltage MIS transistor) that operates at a power supply voltage and a high breakdown voltage transistor (high voltage MIS transistor) that operates at a voltage higher than the power supply voltage. The first gate insulating film is formed in a gate insulating film forming step of the low breakdown voltage transistor.

  The second gate electrode is formed in a side wall spacer shape (8, 62, 98, 127) via an insulating film on the side wall of the first gate electrode.

  In the step of forming the second gate electrode, an electrode extraction part (200) of the second gate electrode is formed.

  After forming the second gate electrode, the method further includes a step of patterning the first conductive pattern to form the first gate electrode.

  [11] << Separation of Silicide Layer 14 by Spacers 12 and 13 >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention has a memory cell, and the memory cell has a source region in the semiconductor region. A drain region, a channel region sandwiched between the source region and the drain region, a first gate electrode (CG), a second gate electrode (MG), and the first region on the channel region. An insulating film for electrically separating the gate electrode and the second gate electrode; The channel region includes a first channel region and a second channel region. A first gate insulating film is provided between the first channel region and the first gate electrode. A second gate insulating film is provided between the second channel region and the second gate electrode. The second gate electrode is formed higher than the first gate electrode. The silicide layer (14) of the second gate electrode and the silicide layer (14) of the first gate electrode are formed by a sidewall spacer (13) made of an insulating film formed in a self-aligned manner on the sidewall of the second gate electrode. Are electrically separated. It is easy and reliable to prevent undesired short-circuiting of both silicide layers.

  [12] << Height CG <MG, MG small resistance >> A semiconductor integrated circuit device according to still another specific embodiment of the present invention includes a memory cell, and the memory cell includes a source region in the semiconductor region. , A drain region, and a channel region sandwiched between the source region and the drain region, and a first gate electrode (CG), a second gate electrode (MG), and the first region on the channel region. An insulating film for electrically separating the gate electrode and the second gate electrode; The channel region includes a first channel region and a second channel region. A first gate insulating film is provided between the first channel region and the first gate electrode. A second gate insulating film is provided between the second channel region and the second gate electrode. The second gate electrode is formed in a sidewall spacer shape (8, 62, 98, 127) on the side wall of the first gate electrode via an insulating film. The film thickness of the second gate electrode is larger than the film thickness of the first gate electrode, and the height of the second gate electrode on the substrate surface is higher than the height of the first gate electrode on the substrate surface. The When the first and second gate electrodes are salicided, it is easy and reliable to prevent undesired short-circuiting of both silicide layers.

  In order to reduce the resistance value of the second gate electrode, a silicide layer (14) may be formed on the second gate electrode. More specifically, sidewall spacers (12, 13) made of an insulating film formed in a self-aligned manner on the sidewalls on both sides of the second gate electrode are formed. The silicide layer (14) of the second gate electrode and the silicide layer (14) of the first gate electrode are electrically separated by the side wall spacer (13) on one side. The silicide layer (14) of the second gate electrode and the silicide layer (14) of the source region or the drain region are electrically separated by the sidewall spacer (12) on the other side. The silicide layer (14) of the first gate electrode and the silicide layer (of the source region or the drain region) are formed by a sidewall spacer (12) made of an insulating film formed in a self-aligned manner on the sidewall of the first gate electrode. 14) is electrically isolated.

  The second gate insulating film includes a non-conductive charge trapping film that is, for example, a charge storage region (6, 125). The first gate electrode (CG) constitutes a control gate electrode of the memory cell. The second gate electrode (MG) constitutes a memory gate electrode of the memory cell, and is formed in a sidewall spacer shape (8, 62, 98, 127) on the side wall of the control gate electrode via an insulating film.

  [13] << Manufacturing Process of Item [11] >> A semiconductor integrated circuit device manufacturing method includes a first conductive film (51) above a memory cell formation region of a semiconductor substrate and an insulating film (on the first conductive film). 50) (FIG. 19), a step of etching the insulating film and the first conductive film to form a first conductive pattern acting as a first gate electrode (CG) of the memory cell (FIG. 20). ), Forming a second gate electrode (62) of the memory cell on the side wall of the first conductive pattern, removing the insulating film (50) on the first conductive pattern (FIG. 24), Forming a sidewall spacer (69) made of an insulating film on the side wall of the second gate electrode (62) in a self-aligning manner (FIG. 26), and in a self-aligning manner with respect to the sidewall spacer (69); Said first conductive pattern and front Second gate electrode (62) forming a silicide layer (77) (FIG. 27), including.

  More specifically, in the side wall spacer (69) formation step (FIG. 26), the side wall spacer (69) is formed on the side walls on both sides of the second gate electrode and the side walls of the first gate electrode. . The silicide layer (77) of the second gate electrode and the silicide layer (77) of the first gate electrode are electrically separated by the sidewall spacer (69) on one side of the both sides. The silicide layer (77) of the second gate electrode and the silicide layer (77) of the source region or the drain region are electrically separated from each other by the sidewall spacer (69) on the other side. The silicide layer (77) of the first gate electrode and the silicide layer (77) of the source region or the drain region are electrically separated by a sidewall spacer (69) formed on the sidewall of the first gate electrode. The

  More specifically, the gate electrode of the peripheral circuit transistor is formed of a stacked film in which a conductive film in the same layer as the first conductive film and a second conductive film in the same layer as the memory gate electrode are stacked.

  The silicide layer forming step can be combined with the silicide layer forming step of the peripheral MIS transistor. That is, a sidewall spacer is formed on the sidewall of the gate electrode of the peripheral circuit transistor in the sidewall spacer (69) formation step. In the silicide layer (77) formation step, a silicide layer is formed on the gate electrode of the peripheral circuit transistor.

  More specifically, the memory cell includes a source region, a drain region, a channel region sandwiched between the source region and the drain region, and one of the source and drain regions in a memory cell formation region of a semiconductor substrate. A first gate insulating film formed between the channel region and the control gate electrode; a control gate electrode disposed near the memory gate electrode disposed near the other of the source and drain regions; 129) and a charge storage region (6, 125) formed between the channel region and the memory gate electrode. The first gate electrode constitutes the control gate electrode. The second gate electrode constitutes the memory gate electrode.

  [14] << Memory cell structure in which the memory gate electrode is self-aligned with the spacer (100) (FIGS. 35 to 39) >> The semiconductor integrated circuit device has a memory cell, and the memory cell has a source region in the semiconductor region. And a drain region and a channel region sandwiched between the source region and the drain region, and a first gate electrode (101) on the channel region sandwiched between the source region and the drain region, A second gate electrode (98) and an insulating film for electrically separating the first gate electrode and the second gate electrode are provided. The channel region includes a first channel region and a second channel region. A first gate insulating layer (92) is provided between the first channel region and the first gate electrode. A second gate insulating layer (95, 96, 97) is provided between the second channel region and the second gate electrode. The second gate electrode (98) is formed higher than the first gate electrode (101). The first gate electrode (101) is formed in a self-aligned manner on a sidewall spacer (100) made of an insulating film formed in a self-aligned manner on the side wall of the second gate electrode (98).

  More specifically, sidewall spacers (100) made of an insulating film formed in a self-aligned manner on the sidewalls on both sides of the second gate electrode are formed (FIG. 36), and the second gate insulating film (95, 95, 96, 97) are formed in self-alignment with the side wall spacer (100) on one side (FIG. 38), and the first gate electrode (101) is self-aligned with the side wall spacer (100) on the other side. It is formed consistently.

  More specifically, the second gate insulating film includes a non-conductive charge trapping film that is a charge storage region (96), the first gate electrode (101) constitutes a control gate electrode, The gate electrode (98) constitutes a memory gate electrode, and is formed in a sidewall spacer shape (98) on the side wall of the control gate electrode via an insulating film.

  [15] << Manufacturing Method of Item [14] >> A manufacturing method of a semiconductor integrated circuit device includes a first conductive film (93) above a memory cell formation region of a semiconductor substrate, and an insulating film ( 94) (FIGS. 19 and 35), and etching the insulating film and the first conductive film to form a first conductive pattern that functions as a first gate electrode of the memory cell (FIG. 20). 35), forming a second gate electrode (98) of the memory cell on the sidewall of the first conductive pattern (FIG. 35), and removing the insulating film on the first conductive pattern (FIG. 35). 36), forming a sidewall spacer (100) made of an insulating film on the side wall of the second gate electrode (98) in a self-aligned manner (FIG. 36), and self-aligning with the sidewall spacer (100). The first conductive pattern is consistently etched. And forming a first gate electrode (100) by etching (FIG. 38).

  More specifically, a second gate insulating film (96) is formed between the second gate electrode (98) and the semiconductor substrate, and the sidewall spacer (100) is formed of the second gate electrode. The second gate insulating film is formed in a self-aligned manner on the side wall spacers on one side (FIG. 38), and is formed on the side walls on both sides (FIG. 36), and the first gate electrode (101). Is formed in a self-aligned manner on the sidewall spacer (100) on the other side.

  More specifically, the gate electrode of the peripheral circuit transistor is formed of a stacked film in which a conductive film in the same layer as the first conductive film and a second conductive film in the same layer as the memory gate electrode are stacked.

  More specifically, the second gate insulating film includes a non-conductive charge trapping film which is a charge storage region (96), the first gate electrode (101) constitutes the control gate electrode, The two-gate electrode (98) constitutes a memory gate electrode, and is formed in a sidewall spacer shape (98) on the side wall of the control gate electrode via an insulating film.

  [16] << Threshold Control >> A semiconductor integrated circuit device according to still another aspect of the present invention has the same basic structure as described above, that is, a memory cell transistor and its access circuit on a semiconductor substrate. The memory cell transistor has a pair of memory electrodes, one of which is a source electrode and the other of which is a drain electrode, and a channel region sandwiched between the pair of memory electrodes in a first well region of the semiconductor substrate. On the channel region, a first gate electrode disposed near the memory electrode via a first gate insulating film, a first gate electrode disposed via a second gate insulating film and a charge storage region, A second gate electrode that is electrically isolated. Then, the conductivity type of the first gate electrode and the conductivity type of the second gate electrode are made different so that the initial threshold voltage viewed from the first gate electrode and the initial view viewed from the second gate electrode are preferable for the read operation. The threshold voltage is determined. For example, the initial threshold voltage viewed from the second gate electrode during the read operation is lowered, and the voltage applied to the second gate electrode during the read operation is set to a low voltage such as a circuit ground voltage. It becomes possible to prevent it from dropping.

  More specifically, the first gate insulating film is made thinner than the second gate insulating film, the first gate electrode is p-type, and the second gate electrode is n. It may be a type. At this time, the channel region becomes n-type.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, stored information can be read from a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device at high speed.

  The parasitic resistance value in the channel portion of the nonvolatile memory cell transistor formed in the semiconductor integrated circuit device can be reduced.

  It is possible to prevent the charge of one polarity from being constantly trapped in the nonvolatile memory cell transistor formed in the semiconductor integrated circuit device.

  Deterioration of data retention characteristics due to undesired leakage of charges accumulated in a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device can be suppressed.

  A thick high voltage MOS transistor that impairs high speed can be eliminated from a signal path for reading stored information from a nonvolatile memory cell transistor formed in a semiconductor integrated circuit device.

    Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following description, a MOS (Metal Oxide Semiconductor) transistor (also simply referred to as a MOS) is used as an example of a MIS transistor (or MISFET) that is a generic term for an insulated gate field effect transistor.

《Memory cell transistor》
FIG. 1 illustrates, in a vertical cross section, a nonvolatile memory cell transistor (also simply referred to as a memory cell) applied to a semiconductor integrated circuit device according to the present invention. The first structural point of view for the memory cell transistor is writing and erasing by electron and hot hole injection and a split gate structure. That is, the memory cell transistor shown in the figure has a control gate (control gate electrode or first gate electrode) 3 on a surface region of a semiconductor substrate (or well region) 1 via a gate insulating film 2 made of, for example, a silicon oxide film. And a lower silicon oxide film 5, which is a gate insulating film, a charge storage region 6, and an insulating film, on the surface region of the semiconductor substrate 1 at least on the drain side of the control gate 3. An upper silicon oxide film 7 is stacked, and a memory transistor portion having a memory gate (memory gate electrode or second gate electrode) 8 formed thereon is formed. The charge storage area 6 is an information holding area, and for example, can hold charges in a discontinuous and discrete manner. The holding region is formed of, for example, a nonconductive charge trapping film, and an example of the nonconductive charge trapping film is a silicon nitride film. Since the silicon nitride film has non-continuous charge traps and is discrete, even if a charge leakage path such as a pinhole occurs in a part of the lower silicon oxide film 5 which is a gate insulating film, All are not lost, and the retention characteristics can be improved. Further, the upper silicon oxide film 7 is configured to be thicker than the lower silicon oxide film 5, and the gate insulating film 2 is configured to be thinner than the stacked films 5, 6, and 7. A drain (memory electrode which is a drain electrode (region)) 10 is formed on the surface region of the semiconductor substrate 1 overlapping the memory gate 8, and a source (source electrode ( A memory electrode) 11 that is a region) is formed. In general, a source and a drain in a MOS transistor are a relative concept based on an applied voltage. Here, for convenience, a memory electrode connected to an upstream side of a current path during a read operation is referred to as a drain. Insulating films 5, 6, and 7 are formed between the control gate 3 and the memory gate 8 to electrically isolate them.

  As described above, the memory cell transistor includes a control gate 3 formed on the channel region (semiconductor substrate or well region) 1 sandwiched between the source 11 and the drain 10 via the gate insulating film 2, the gate insulating film, and the like. 5 and the charge storage region 6, and insulating films 5, 6, and 7 that electrically isolate the control gate 3 and the memory gate 8.

  The memory cell of FIG. 1 is obtained, for example, by applying a positive voltage only to the memory gate 8, injecting electrons (electrons) 20 from the semiconductor substrate 1 side by a tunnel current, and trapping into the silicon nitride film 6. A high threshold voltage state (for example, an erase state), a positive voltage is applied to the drain 10 and a negative voltage is applied to at least the memory gate 8 to inject hot holes generated near the junction surface of the drain 10 into the silicon nitride film 6. And a low threshold voltage state (written state) obtained by neutralizing trapped electrons. If one of the negative charge represented by electrons or the positive charge represented by holes is the first polarity charge, the charge having the opposite polarity to the first polarity charge is called the second polarity charge.

  The second viewpoint regarding the memory cell transistor is that a large read current, in other words, a common structure with the logic transistor (power supply voltage MOS transistor) is possible. FIG. 2 illustrates a vertical cross section when a memory cell transistor according to the present invention is manufactured by a process of mounting together with a logic transistor (power supply voltage MOS transistor). FIG. 3 illustrates a plan view thereof. 2 is a cross-sectional view along the A-A ′ direction in FIG. 3, and the left side of FIG. 2 corresponds to A, and the right side of FIG. 2 corresponds to A ′. 2 and 3 show only the memory cell transistors, and the process of mounting them will be described later. Also, a MOS transistor that operates at the power supply voltage Vdd is abbreviated as a power supply voltage MOS transistor.

  In FIG. 2, for example, the logic transistor (relatively) is formed on the surface region of the semiconductor substrate 1 made of silicon, for example, on the gate insulating film 2 formed in the same manufacturing process as the gate insulating film of the logic transistor operating with the power supply voltage. A control gate (control gate electrode or first gate electrode) 3 formed in the same manufacturing process as the gate electrode of the first MOS transistor having a thin insulating film), a lower oxide film 5 which is a gate insulating film, and a charge storage region A memory gate (memory gate electrode or second gate electrode) 8 is formed on the laminated film of a silicon nitride film 6 and an upper oxide film 7 which is an insulating film. Note that the thickness of the upper silicon oxide film 7 is larger than that of the lower silicon oxide film 5. A drain (memory electrode which is a drain electrode) 10 is arranged so as to overlap the memory gate 8 in a surface region of the semiconductor substrate 1, and a source (memory electrode which is a source electrode) 11 is arranged so as to overlap the control gate 3. Is done. The control gate 3 and the memory gate 8 are made of, for example, a silicon film. Since the lower oxide film 5 is formed by, for example, a thermal oxidation process, a silicon oxide film 4 that is a sidewall insulating film is grown on the side surface of the control gate 3. Thereby, the thickness of the silicon oxide film 4 is configured to be thicker than that of the lower oxide film 5, and the withstand voltage between the control gate 3 and the memory gate 8 can be improved.

  In FIG. 2, a metal silicide film 14 made of, for example, cobalt silicide (CoSi) or nickel silicide (NiSi) is formed on the control gate 8, the memory gate 8, the drain 10 and the source 11. Are electrically insulated (separated) by side spacers 12 and 13 made of an insulating film. Since the side spacers 12 and 13 are formed in the same process in the manufacturing process without using a photolithography technique as will be described later, the manufacturing process can be reduced. An interlayer insulating film 15 is formed so as to cover the memory cell transistor and the logic transistor, and the surface of the interlayer insulating film 15 is planarized. Connection holes 197 and 198 that open the drain 10 and the source 11 are formed in the interlayer insulating film 15, and metal plugs 16 are embedded in the connection holes. An interlayer insulating film 17 whose surface is planarized is formed on the interlayer insulating film 15, and a bit line 19 is formed on the interlayer insulating film 17. A connection hole 197 that opens the metal plug 16 on the drain 10 is formed in the interlayer insulating film 17, and the metal plug 18 is embedded in the connection hole 197. The connection holes 197 and 198 will be described later with reference to FIG. Thus, the metal plug 16 is electrically connected to the drain 10 and the source 11, and the metal plug 16 formed on the drain 10 is electrically connected to the bit line 19 via the metal plug 18.

  In the plan view of the memory cell shown in FIG. 3, the active region 22 surrounded by the element isolation region, the direction (second direction: the horizontal direction in the figure) perpendicular to the direction in which the active region 22 extends (second direction: second direction: The control gate 23 (corresponding to the control gate 3), the oxide film 24 (corresponding to the oxide film 5), the silicon nitride film 25 (corresponding to the silicon nitride film 6), and the upper oxide film so as to extend in the vertical direction in the figure. 26 (corresponding to the upper oxide film 7), a memory gate 27 (corresponding to the memory gate 8), an insulating film side spacer 28 (corresponding to the side spacer 12) are arranged, and a metal plug 29 (on the drain 10 and the source 11) ( A bit line 30 (corresponding to the bit line 19) connected only to the metal plug on the drain) is disposed. The metal plug 18 formed on the metal plug 29 on the drain 10 is formed in the same position and in the same shape as the metal plug 29 in the interlayer insulating film 17, so that it is illustrated for easy understanding of the drawing. Is omitted. Further, the metal plug 29 (corresponding to the metal plug 16) formed on the source 11 is in the same direction as the extending direction of the control gate 23 (corresponding to the control gate 3) and the memory gate 27 (corresponding to the memory gate 8). The common source line is configured to extend.

  FIG. 4 shows a processing mask pattern arrangement for forming the memory gates 8 and 27 only on the side surfaces on the drain 10 side of the control gates 3 and 23 as shown in FIGS. 1 and 2 in the memory cell of the present invention. Is illustrated. In FIG. 4, reference numeral 191 denotes an active region pattern that defines an active region surrounded by the element isolation region of the memory cell, and the active region 22 is formed to extend in the first direction (the horizontal direction in the figure). 192 is a first gate film pattern for defining the drain side end of the control gate, and 193 is a second gate film for defining the second gate film in the step of forming side spacers in order to extract the electrodes of the memory gates 8 and 27. It is a gate film pattern. Further, in FIG. 4, the first gate film and the second gate film are cut to define a source side end portion, and a control gate 199 (corresponding to the control gates 3 and 23) and a memory gate 200 (memory gates 8 and 27). A gate film isolation pattern 194 for completing the above is shown. That is, the gate film isolation pattern 194 forms a hatched portion of the first gate film pattern 192 as a control gate 199 (corresponding to the control gates 3 and 23), and a high-density pattern of the second gate film pattern 193. The portion shown is formed as a memory gate 200 (corresponding to the memory gates 8 and 27). Further, FIG. 4 shows a contact hole pattern 195 on the memory gate 200, a contact hole pattern 196 on the control gate 199, a drain contact hole pattern 197, and a slit-like contact hole pattern 198 on the source. Connection holes 195, 196, 197, and 198 are formed in the contact holes. Metal plugs 16 and 29 are formed in the contact hole pattern 198, and a common source line extending in the second direction (vertical direction in the figure) is formed integrally with the metal plugs 16 and 29. Although not shown, a bit line pattern is arranged in parallel to the active region pattern, and the bit lines 19 and 30 are formed to extend in the first direction (lateral direction in the figure).

  The electrode extraction of the memory gates 8, 27, and 200 was formed in the metal plugs 16 and 29 formed in the connection hole 195 of the interlayer insulating film 15 and the connection hole 195 of the interlayer insulating film 17, similarly to the drain 10. The metal plug 18 is electrically connected to a wiring or via wiring formed in the same layer as the bit lines 19 and 30. Further, the electrode extraction of the control gates 3, 23, and 199 was formed in the metal plugs 16 and 29 formed in the connection hole 196 of the interlayer insulating film 15 and the connection hole 196 of the interlayer insulating film 17, similarly to the drain 10. The metal plug 18 is electrically connected to a wiring or via wiring formed in the same layer as the bit lines 19 and 30.

  In the manufacturing process of the memory cell of the present invention using the max pattern shown in FIG. 4, the element isolation region 32 defining the active region 22 is formed in the substrate 1 by the active region pattern 191 as described later, and then the substrate 1 A gate insulating film 2 of a logic transistor (power supply voltage MOS transistor) and a memory transistor that operates with a power supply voltage is grown thereon, and a first gate film (first conductive film) made of, for example, a silicon film is formed on the gate insulating film 2. After the deposition, the first gate film is patterned into the shape of the first gate film pattern 192 using the resist film pattern having the shape of the first gate film pattern 192, for example. Thereafter, for example, the gate insulating film 2 other than the lower part of the first gate film is removed, and the lower oxide film 5 shown in FIGS. 1 and 2 and the silicon nitride film 6 are formed on the substrate 1 including the upper part of the first gate film. 25, a stacked film of the upper oxide films 7 and 26, and a second gate film (second conductive film) made of, for example, a silicon film are deposited. The upper silicon oxide films 7 and 26 are formed thicker than the lower silicon oxide film 5. Thereafter, for example, a resist film pattern in the shape of the second gate film pattern 193 is formed, the second gate film is processed by anisotropic dry etching, and a second side spacer-like second is formed around the first gate film. A gate film is formed. Thereafter, the first gate film and the second gate film are cut by patterning the first gate film and the second gate film using a resist film pattern in the shape of the gate film separation pattern 194, for example. , The processing of the control gates 2, 23, 199 and the memory gates 8, 27, 200 is completed. Thereafter, formation of source / drain regions 10 and 11 of the memory cell, formation of source / drain regions of a logic transistor operating with a power supply voltage, formation of a metal silicide film 14, formation of an interlayer insulating film 15, and connection holes 195 and 196 After the formation of 197 and 198, the formation of the interlayer insulating film 17, and the formation of the connection holes 195, 196 and 197, the semiconductor device in which the flash memory is embedded is completed through the formation process of the metal wirings 19 and 30. Although not shown in FIG. 4, for example, the slit-shaped contact hole pattern 198 is formed to extend toward a position below the contact hole pattern 196 in the drawing in the second direction (vertical direction in the drawing). Therefore, it is electrically connected to the wiring or via wiring formed in the same layer as the bit lines 19 and 30 through the metal plug formed in the connection hole of the interlayer insulating film 17 (not shown).

  5, 6 and 7 show the basic operation of the memory cell of the present invention. VD is a drain voltage, VS is a source voltage, and VCG is a control gate voltage. VMG is a memory gate voltage.

  FIG. 5 illustrates a voltage application state in the erase operation. In the erasing operation, an appropriate positive voltage (for example, VMG = 10 V) is applied only to the memory gate 8, and all other terminals are set to 0 V (ground potential) which is a reference voltage. In the erase operation, electrons are injected from the semiconductor substrate (well region) 1 side and trapped in the silicon nitride film 6 by a Fowler-Nordheim (FN) type tunnel current flowing through the lower oxide film 5 immediately below the memory gate 8. Then, the threshold voltage measured from the memory gate 8 is increased (for example, VTE = 2V). That is, electrons are injected from the semiconductor substrate 1 side into the silicon nitride film 6 that is a charge storage region by electron tunneling through the lower oxide film 5 that is a gate insulating film, and electrons are injected into traps in the silicon nitride film 6. Let it be trapped. Therefore, electrons are trapped only in the silicon nitride film 6 immediately below the memory gate 8 because of electron injection by the tunnel current through the lower oxide film 5 immediately below the memory gate 8, and the second problem of the conventional memory cell. The electron traps at the corners were not generated. As a result, the problem of deterioration of the erase time due to trapped electrons at the corner of the silicon nitride film 6 in the rewrite operation is solved. In this erasing operation, the high voltage is applied only to the memory gate 8, and the high voltage is not applied to the gate oxide film 2 of the read transistor portion. The erase time depends on the erase voltage applied to the memory gate 8 and the effective electric field strength determined by the ratio of the lower oxide thickness and the lower oxide thickness / silicon nitride thickness / upper oxide thickness effective oxide thickness. . For example, if the thickness of the lower oxide film 5 is set to 3 nm, the thickness of the silicon nitride film 6 is set to 5 nm, and the thickness of the upper oxide film 7 is set to 5 nm, the effective oxide thickness of the three-layer film is 10.5 nm. In order to obtain an electric field strength of 10 MV / cm through which the FN tunnel current flows in the lower oxide film, the erase voltage to be applied to the memory gate 8 is about 10.5V. In addition, since the upper silicon oxide film 7 is thicker than the lower silicon oxide film 5, electrons trapped in the silicon nitride film 6 are emitted from the silicon nitride film 6 to the memory gate 8 by tunneling. Can be prevented.

  FIG. 6 illustrates the voltage application state in the write operation of the memory cell. In the write operation, the power supply voltage Vdd (for example, VD = 1.5 V) is applied to the drain 10, an appropriate negative voltage (for example, twice the power supply voltage = −2 Vdd = −3 V) is applied to the semiconductor substrate (well region) 1, and the control gate 3 is applied. An appropriate negative voltage (for example, -Vdd = -1.5V) is applied. In this state, an appropriate negative voltage (for example, VMG = −7 V) is applied to the desired memory gate 8 that performs writing for the duration of the writing time. Since the potential difference between the drain 10 and the semiconductor substrate (well region) 1 is the junction voltage, if the device design is performed so that VD−VPW = Vdd − (= 2Vdd) = 3Vdd is near the junction breakdown voltage, the memory gate 8 The surface of the junction is strongly inverted by the applied negative voltage, and a large amount of hot holes are generated starting from the band-to-band tunnel phenomenon, and injected into the silicon nitride film by the negative voltage of the memory gate 8. That is, a large number of hot holes can be injected into the silicon nitride film by forming a reverse voltage application state (reverse bias state).

  Here, the reverse bias between the reverse bias voltage of the pn junction when a hot hole or the like is generated by the band-to-band tunneling and the reverse bias voltage of the pn junction when more avalanche hot holes are generated. The voltage is referred to as a junction breakdown voltage (junction breakdown voltage). Therefore, a reverse bias state that is larger than when a hot hole or the like is generated by the band-to-band tunneling may be grasped as a reverse voltage application state in the vicinity of the junction breakdown voltage or higher than the junction breakdown voltage. If the junction breakdown voltage is to be defined quantitatively, a reverse current of an allowable leakage current that is allowed to flow through a channel of an off-state MIS (Metal Insulate Semiconductor) transistor is generated in a pn junction (also simply referred to as a junction). The reverse bias voltage when flowing can be defined as the junction breakdown voltage. In this specification, the junction breakdown voltage does not mean a junction breakdown voltage.

  The junction withstand voltage is defined as a reverse bias voltage when a reverse current of an allowable leak current that is allowed to flow through a channel of an off-state MOS transistor flows through a pn junction (also simply referred to as a junction) as described above. Therefore, according to this, when such an allowable leakage current is 10 nA, a leakage current of 10 nA is generated between the drain 10 and the semiconductor substrate (well region) 1 with the reverse bias of 3 Vdd. Device design should be done. As a result, a large number of hot holes are generated by setting the junction voltage, which is the potential difference between the drain 10 and the semiconductor substrate 1 during the write operation, to the vicinity of the junction breakdown voltage, and the holes enter the silicon nitride film due to the negative voltage of the memory gate 8. Injected.

  If the device design is made so that the junction breakdown voltage is smaller than 3 Vdd, more avalanche hot holes are generated, more hot holes are injected into the silicon nitride film, and the injection time can be further reduced. That is, by making the junction voltage, which is the potential difference between the drain 10 and the semiconductor substrate 1 during the write operation, equal to or higher than the junction breakdown voltage, many banlanche hot holes are generated, more hot holes are injected into the silicon nitride film, and the injection time is increased. Can be reduced.

  The injected hot holes neutralize the already trapped electrons and lower the threshold voltage measured from the memory gate 8 (for example, VTP = −2 V). Since the drain current required for this write operation is only the drain junction leakage current, the leakage current value in the vicinity of the junction breakdown voltage is about 5 to 10 μA / bit, and writing by hot electron injection in the conventional first memory cell is performed. Compared to 200 μA / bit at 1/10 or less. In writing by this hot hole injection, the hot hole generation region is localized at the drain junction end where electric field concentration occurs, and the distance that the hot hole can reach from the generation point is about 50 nm. The width of the memory gate 8 is set so that the effective channel length of the portion is 50 nm or less. The memory transistor portion alone has inherent disadvantages such as difficulty in stable control of the initial threshold voltage and large off-leakage current, which are the third problems of the conventional memory cell. By providing the readout transistor portion (selection transistor portion), instability of readout characteristics can be eliminated.

  In this write operation, a high voltage is applied to the memory gate 8 and the semiconductor substrate (well region) 1, and is applied to the semiconductor substrate (well region) 1 at most to the gate insulating film 2 of the read transistor portion. A voltage, for example, −2 Vdd is applied, but if an appropriate negative voltage (for example, VCG = −Vdd) is applied to the control gate 3, the applied voltage of the gate insulating film 2 becomes Vdd. As a result, the gate insulating film 2 can be designed to be as thin as the gate oxide film of a logic transistor (power supply voltage MOS transistor) that operates with a power supply voltage. Therefore, the small drain current at the time of reading, which is the first problem of the conventional memory cell, can be solved. Further, since the maximum voltage applied to the control gate 3 and the drain 10 is the power supply voltage (Vdd), the read circuit such as the word driver circuit connected to the control gate 3 and the sense amplifier circuit connected to the drain 10 is A peripheral transistor (power supply voltage MOS transistor) that operates with a power supply voltage having a gate insulating film having the same film thickness as the gate insulating film 2 can be formed, and high-speed reading can be realized. As will be described later, the gate insulating film 2 is formed with a film thickness of 2.7 nm, for example, and is formed thinner than the film thickness of the stacked films 5, 6, and 7.

  FIG. 7 illustrates the read operation state of the memory cell of the present invention. In the read operation, a power supply voltage (for example, VD = Vdd = 1.5V) is applied to the drain 10, a power supply voltage (for example, VCG = Vdd = 1.5V) is applied to the control gate 3, and the other terminals are set to 0V. Since the voltage applied to the memory gate 8 is also 0V, the drain current is turned off or on depending on whether the threshold voltage of the memory transistor is in the erased state (VTE = 2V) or in the written state (VTP = -2V). Is done. Therefore, the problem of deterioration of the read disturb life due to the voltage application to the memory gate 8, which is the fourth problem of the conventional memory cell, is solved. The read drain current in the write state has a high current drive capability (Gm is large) because the thickness of the gate insulating film 2 of the read transistor portion is equal to that of the logic transistor (power supply voltage MOS transistor), and the memory transistor portion Since the effective channel length is less than 50 nm, the parasitic resistance of this portion is small, and thus a large current value can be obtained. For example, when compared with a logic transistor in which the read transistor portion has the same effective channel width / effective channel length, a drain current value of about 70 to 80% of the logic transistor can be achieved. As a result, the above-described read circuit can be constituted by a peripheral transistor (power supply voltage MOS transistor) that operates with a power supply voltage, and the read current of the memory cell is large, so that a flash memory with an extremely high read speed (for example, read frequency 200 MHz). Can be embedded in a logic LSI.

<Data processor>
FIG. 8 illustrates a data processor that on-chips a flash memory module that employs the memory cell having the structure described in FIGS. 2 and 3. Although not particularly limited, the data processor 200 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a 0.13 μm semiconductor integrated circuit manufacturing technique. Although not particularly limited, a large number of bonding pads are arranged around the semiconductor substrate. The data processor 200 includes a CPU (Central Processing Unit) 201 composed of a logic MOS transistor (power supply voltage MOS transistor) having a gate insulating film thickness of 2.7 nm and operating at a power supply voltage Vdd = 1.2 V, an SCI (Serial Communication Interface) 202, FRT (Free Running Timer) 214, DSP unit 203, DMAC (Direct Memory Access Controller) 204, FLC (Flash Controller) 205, UBC (User Break Controller) 206 having a debugging support function, CPG (Clock Pulse) Generator) 207, SYSC (System Controller) 208, BSC (Bus State Controller) 215, RAM (Random Access Memory) 209 having a memory capacity of, for example, 16 kB, and JTAG 211 circuit modules used for self-test and the like. Further, for example, a logic transistor (power supply voltage MOS transistor) having a gate insulating film thickness of 2.7 nm, a high breakdown voltage transistor having a gate insulating film thickness of 15 nm, and the memory cell transistor of the present invention has a memory capacity. A 256 kB flash memory (FLSH) 212 and an I / O (Input / Output) circuit 216 are provided. The high breakdown voltage transistor is a transistor having a gate insulating film thicker than the gate insulating film of the power supply voltage MOS transistor.

  Although not particularly limited, the external power supply voltage supplied to the external power supply terminal of the data processor 200 is 3 V, and the power supply voltage Vdd (= 1.2 V) of the logic MOS transistor (power supply voltage MOS transistor) is the external power supply voltage. It is formed by stepping down. The MOS transistors constituting the I / O circuit 216 have a breakdown voltage exceeding 3V. The high breakdown voltage MOS transistors of the flash memories 212 and 213 have a breakdown voltage that does not cause gate breakdown with respect to a high voltage necessary for writing and erasing operations on the memory cells.

  FIG. 9 shows a detailed example of the flash memory 212. The flash memory 212 has a memory cell block in which the large number of memory cells MC described in FIGS. 2 and 3 are arranged in a matrix. The memory cell MC is divided into a read transistor portion (RTr) and a memory transistor portion (MTr). A large number of memory cells MC are not particularly limited, but common to the source line SL, and n bit lines BL1 to BLn, m control gate lines CG1 to CGm, and m memory gate lines MG1 to MGm are arranged. It is configured as a NOR type memory cell block. The memory cell block is not particularly limited, but has a common well region in which memory cell transistors are formed. In practice, a flash memory may be configured by arranging a large number of memory cell blocks in the front and back direction of the drawing.

  The control gate lines CG1 to CGm are driven by a read word driver 225. The memory gate lines MG1 to MGm, the source line SL, and the well region PW are driven by a write word driver and well driver 226. The X decoder 227 selects a control gate line and a memory gate line to be driven. The bit lines are connected to a sense latch circuit and a column switch circuit 228. The sense latch can be connected to the data buffers 221 and 222 by a column switch. . The power supply circuit 230 generates an internal voltage necessary for the memory operation.

  The flash memory 212 is subjected to access control of the FLC 205 in response to access requests from the CPU 201 and DMAC. The FLC 205 is connected to the flash memory 212 via address lines ADR1 to ADRi, data lines DAT1 to DATj, and control lines ACS1 to ACSk. An address input buffer (AIBUF) 220 inputs an address signal through an address line. The input address signal is supplied to the X decoder 227 and the Y decoder 229 via the predecoder 231. A data input buffer (DIBUF) 221 inputs an access command and write data via data lines DAT1 to DATj. A data output buffer (DOBUF) 222 outputs read data from the memory cell. The control circuit 223 inputs strobe signals such as a read signal, a write signal, a command enable signal, and an address enable signal via the control lines ACS1 to ACSk to control input / output operations with the outside, and also controls the data input buffer 221. An access command is input via the control terminal, and the memory operation specified by the input command is controlled.

  In FIG. 9, the write word driver / well driver 226 and the power supply circuit 230 are composed of, for example, a high breakdown voltage transistor having a gate insulating film thickness of 15 nm. The other element circuit is composed of, for example, a logic MOS transistor (power supply voltage MOS transistor) with a gate insulating film having a relatively thin gate insulating film thickness of 2.7 nm. For example, the initial threshold voltage of the read transistor portion (RTr) of the memory cell is designed to be 0.5V, the initial threshold of the memory transistor portion (MTr) is set to −0.5V, and the drain junction breakdown voltage is designed to be 3.6V.

  FIG. 10 illustrates a state at the time of erasing operation with respect to the flash memory. Erase is performed in units of memory cell blocks, that is, in units of well regions of memory cells. That is, for example, an erase voltage of 10 V is applied to all the memory gates (MG1 to MGm) in the erase block and an erase time of 100 ms is applied to all the other terminals, and a ground potential (Vss) of 0 V is applied to all the other terminals. Electrons are trapped in the silicon nitride film by a tunnel current passing through the film, and the erase threshold voltage (VTE) of the memory transistor portion MTr is raised to 1.2 V to complete the erase operation.

  FIG. 11 illustrates a state at the time of writing operation to the flash memory. For example, −2 Vdd (−2.4 V) is written to the well region PW in the write block, −1.2 V (−Vdd) is written to all the control gate lines CG1 to CGm, and the memory gate lines (for example, MG2, MGm) are written. After applying -7V only to the bit line, 1.2V (Vdd) is applied to the bit line (for example, BL2, BLn) to be written for 10 μs for the write time, and hot holes generated near the drain are injected into the silicon nitride film. Then, the threshold voltage (VTP) of the memory transistor portion Mtr is lowered to -1.2 V, and the write operation is completed.

  FIG. 12 illustrates a state at the time of a read operation with respect to the flash memory. For example, after a bit line (for example, BL2) to be read is selected and precharged to 1.2V (Vdd), 1.2V (Vdd) is applied to the selected control gate (for example, CG2), and the read target bit line A change in the potential of BL2 is detected by a sense amplifier circuit, and data is read out. At this time, the memory cell to be read connected to the bit line BL2 and the control gate line CG2 is in the write state, and the threshold voltage of the memory transistor is VTP = −1.5V, so the on-current of the memory cell is about 50 μA. To be. This current change or a voltage change caused thereby is detected by a sense amplifier circuit.

  FIG. 13 illustrates another bit line structure in the memory cell block. In the configuration shown in the figure, the bit lines are hierarchized into a main bit line GL and a sub bit line SBL, and only the sub bit line SBL to which the memory cell MC to be selected for operation is connected is selected to the main bit line GL. This is a structure that realizes a high-speed read operation by connecting and apparently reducing the parasitic capacitance of the bit line by the memory cell. As described above, since it is not necessary to apply a high voltage to the bit lines BL and GL even during writing, the MOS transistor 233 and its driver (Z driver) for selectively connecting the sub bit line SBL to the main bit line GL. ) It is not necessary to increase the breakdown voltage even for 234. That is, the gate insulating film is constituted by a relatively thin MOS transistor (power supply voltage MOS transistor) having a thickness of 2.7 nm. In this respect as well, the Gm of the storage information read path is further reduced, and it is possible to sufficiently function the speeding up by the hierarchical bit line structure using the main and sub bit lines.

<< Memory cell transistor; Threshold control >>
FIG. 14 shows another example of a nonvolatile memory cell transistor. The memory cell shown in the figure is an example in which a desired initial threshold voltage is obtained with the same channel structure by changing the doping of impurities into the control gate and the memory gate of the memory cell shown in FIG. That is, the entire surface of the channel region of the semiconductor substrate (well region) 1 is depleted by channel implantation, and the threshold values between the selection transistor portion (read transistor portion) and the memory transistor portion are changed by changing the conductivity types of the control gate 21 and the memory gate 8. Different voltages.

Specifically, according to the longitudinal cross-sectional structure illustrated in FIG. 14, the gate insulating film 2 made of a silicon oxide film having a thickness of 2.7 nm on the surface region of the p-type semiconductor substrate (well region) 1 having a resistivity of 10 Ωcm. And a read transistor portion in which a control gate (CG) 21 having a gate length of 150 nm made of a p-type polysilicon film having a thickness of 150 nm doped with a boron concentration of 2 × 10 ²⁰ cm ⁻³ is formed. A lower oxide film 5 having a thickness of 3 nm, a silicon nitride film 6 having a thickness of 5 nm, and an upper oxide film 7 having a thickness of 5 nm are formed on the surface region of the p-type semiconductor substrate (well region) 1 on the drain side of the gate (CG) 21. are stacked, the memory gate having a gate length of 50nm phosphorus concentration 4 × ¹⁰ 20 ^{cm -3} in the upper part made of n-type polysilicon film doped film thickness 150 nm (MG) 8 Configured with a memory transistor portion formed. Note that the memory gate (MG) 8 and the control gate (CG) 21 are electrically separated by the stacked films 5, 6, and 7.

A drain region having a maximum arsenic concentration of 1.5 × 10 ²⁰ cm ⁻³ , a junction depth of 40 nm, and a junction breakdown voltage of 4.5 V is formed on the surface region of the semiconductor substrate (well region) 1 overlapping the memory gate (MG) 8. 10 is the surface region of the semiconductor substrate (well region) 1 that overlaps the control gate (CG) 21. The maximum arsenic concentration is 1.5 × 10 ²⁰ cm ⁻³ , the junction depth is 40 nm, and the junction breakdown voltage is 4.5V. Source region 11 is formed. That is, the read transistor portion and the memory transistor portion are formed on the channel region 20 between the drain region 10 and the source region 11.

The initial threshold voltage of the read transistor portion and the memory transistor portion of the memory cell illustrated in FIG. 14 is determined by the n-type channel region 20 formed in the surface region of the semiconductor substrate (well region) 1. For example, the n-type channel region 20 is set so that the threshold voltage of the read transistor portion composed of the control gate (CG) 21 of the p-type polysilicon film is 0.5 V, and the average arsenic concentration is 5 V. × 10 ¹⁷ cm ^-3 and junction depth 30 nm. At this time, the initial threshold voltage of the memory transistor portion including the memory gate (MG) 8 of the polysilicon film having the n-type conductivity was −0.5V. Therefore, according to the memory cell of the present embodiment, it is possible to optimize the initial threshold voltages of the read transistor portion and the memory transistor portion only by forming the n-type channel region 20.

  The write / erase operation to the memory cell of this embodiment is basically the same as the operation of the memory cell shown in FIG. In the erasing operation, 10 V is applied only to the memory gate (MG) 8 and electrons are injected from the semiconductor substrate 1 side by a tunnel current to be trapped in the silicon nitride film 6 to be in a high threshold voltage state. In the write operation, 1.2 V (Vdd) is applied to the drain 10, −2.4 V (−2 Vdd) to the semiconductor substrate 1, −1.2 V (−Vdd) to the control gate (CG) 21, and the memory gate 8. A low threshold voltage state is obtained by applying −7 V to inject hot holes generated in the vicinity of the junction surface of the drain 10 into the silicon nitride film 6 to neutralize trapped electrons.

"Production method"
For example, a manufacturing process in which the nonvolatile memory cell is mixedly mounted on a logic LSI using 0.13 μm process technology will be described with reference to cross-sectional views (FIGS. 15 to 30) of the LSI for each manufacturing process. In the description here, although not particularly limited, the mask pattern arrangement shown in FIG. 4 is used as a mask pattern for processing a memory cell. In the cross-sectional views (FIGS. 15 to 30), the left side of the figure is a memory cell formation region (memory cell), the center is a power supply voltage MOS transistor formation region (power supply voltage MOS), and the right is a high breakdown voltage system. A MOS transistor formation region (high breakdown voltage MOS) is shown. In addition, in FIG. 15 etc., XX has shown the cutting | disconnection site | part of the part which cut | disconnected left and right for convenience.

  As shown in FIG. 15, for example, a groove having a depth of about 250 nm is formed in the surface region of a p-type semiconductor substrate 31 (corresponding to the semiconductor substrate (well region) 1) having a resistivity of 10 Ωcm, and then an oxide film is deposited. Next, the oxide film is polished by a CMP (Chemical Mechanical Polishing) method so that the oxide film is buried in the groove, and a planarized trench type element isolation region 32 is formed by the CMP method. A film 33 is grown. Although the trench type element isolation region 32 is formed so as to define the active region 22, a dummy active region may be formed in the trench type element isolation region in order to facilitate embedding by the CMP method.

Next, as shown in FIG. 16, for example, the through surface oxide film 33, the desired to the area phosphorous ions of acceleration energy 1MeV implantation amount 1 × ¹⁰ 13 / cm ^2, injection volume 3 × ^{10 12} phosphorous ions of acceleration energy 500keV An n-type buried region 34 is formed by implanting / cm ² . Thereafter, phosphorus ions having an acceleration energy of 150 keV are implanted into the region where the high voltage PMOS transistor is to be formed by implanting 1 × 10 ¹² / cm ² to form the high voltage n-type well region 35. Furthermore, boron ions with an acceleration energy of 500 keV are implanted in an amount of 1 × 10 ¹³ / cm ² and an acceleration energy using a resist pattern 36 having a thickness of 3 μm opening only the memory cell region and the region where the high voltage NMOS transistor is formed. A high breakdown voltage p-type well region 38 is formed by implanting boron ions of 150 keV at an implantation amount of 5 × 10 ¹² / cm ² and boron ions 37 at an acceleration energy of 50 keV at an implantation amount of 1 × 10 ¹² / cm ² .

Next, as shown in FIG. 17, for example, phosphorus ions with an acceleration energy of 100 keV are implanted into a region where a PNOS transistor operated with a power supply voltage is formed at an injection amount of 1 × 10 ¹² / cm ² and phosphorus ions with an acceleration energy of 40 keV are implanted at an amount of 5 ×. The power supply voltage n-type well region 39 is formed by inputting 10 ¹¹ / cm ² . Thereafter, boron ions with an acceleration energy of 200 keV are implanted at a dose of 1 × 10 ¹³ / cm ² and an acceleration energy of 100 keV with a resist pattern 40 having a thickness of 3 μm opening only a region where an NMOS transistor for power supply voltage operation is formed as a mask. The source voltage p-type well region 42 is formed by implanting boron ions 41 with an implantation amount of 5 × 10 ¹² / cm ² and boron ions 41 with an acceleration energy of 30 keV at an implantation amount of 2 × 10 ¹² / cm ² .

Next, as shown in FIG. 18, for example, boron difluoride (BF ₂ ) ions 44 having an acceleration energy of 50 keV are implanted by using a resist pattern 43 having a film thickness of 1.5 μm opened only in the memory cell region as a mask. A memory enhanced implant region 45 is formed by implanting × 10 ¹² / cm ² .

Thereafter, as shown in FIG. 19, the resist mask 43 and the surface oxide film 33 are removed, and a high breakdown voltage gate having a thickness of about 15 nm made of a silicon oxide film is formed in a region where a high breakdown voltage transistor is formed by thermal oxidation, for example. A power supply voltage gate insulating film 46 (about 2.7 nm thick) made of a silicon oxide film is formed on the insulating film 47 in a region where a power supply voltage operation transistor (power supply voltage MOS transistor) is formed and a region where a memory cell is formed. After depositing (corresponding to the gate insulating film 2), it is deposited by chemical vapor deposition (CVD). Then, depositing a non-doped polysilicon film 48 having a thickness of about 150 nm, non-doped polysilicon film supply phosphorus ions of voltage acceleration energy 5keV to regions other than the region where a PMOS transistor is formed of operating injection volume 2 × 10 ¹⁵ out of 48 An n-type polysilicon film 49 is formed by implanting / cm ² . A silicon nitride film 50 having a thickness of about 100 nm is deposited on the upper portion by CVD.

Next, as shown in FIG. 20, the first gate film pattern 192 for defining the drain side of the control gate in the memory cell of the present invention shown in FIG. The film 49 and the silicon nitride film 50 are processed to form first gate film patterns 50 and 51 having the shape of the first gate film pattern 192. By using this first gate film pattern as a mask, arsenic ions 52 having an acceleration energy of 10 keV are implanted at an implantation amount of 3 × 10 ¹² / cm ² to form a memory depletion implant region 53. FIG. 31 shows a planar pattern of the memory cell portion corresponding to FIG.

  The polysilicon films 48 and 49 left in the power supply voltage MOS transistor formation region and the high voltage MOS transistor formation region are configured as gate electrodes of the power supply voltage MOS transistor and the high voltage MOS transistor as will be described later. The That is, since it is not necessary to form the gate insulating film 47 of the high voltage MOS transistor in the subsequent steps, the memory cell can be formed after the thick gate insulating film 47 is formed. Thereby, the heat treatment for forming the thick gate insulating film 47 is not burdened on the formation of the memory cell, the degree of freedom in device design of the memory cell can be improved, and the burden of the formation process is reduced. be able to.

  Next, as shown in FIG. 21, for example, on the surface region of the semiconductor substrate 31 in the memory cell region, a lower oxide film (corresponding to the lower oxide film 5) having a film thickness of about 3 nm and a film that is a charge storage region A stacked film 54 composed of a silicon nitride film (corresponding to the silicon nitride films 6 and 25) having a thickness of about 5 nm and an upper oxide film (corresponding to the upper oxide films 7 and 26) of a CVD oxide film having a thickness of about 5 nm is deposited, The stacked film 54 and the silicon nitride film 50 in the peripheral transistor region are removed by dry etching using a 2 μm-thick resist pattern 55 covering only the cell region as a mask. An insulating film made of the silicon oxide film 4 is formed on the side wall of the first gate film pattern 51 made of the n-type polysilicon film to be thicker than the film thickness of the lower oxide film 5 by thermal oxidation for forming the lower oxide film 5. Is done.

Next, as shown in FIG. 22, after removing the resist film 55, a non-doped polysilicon film having a film thickness of about 50 nm is deposited on the entire surface of the substrate including the polysilicon films 48 and 49 by, for example, CVD. A p-type polysilicon film 57 is implanted by implanting boron difluoride (BF ₂ ) ions having an acceleration energy of 15 keV into the region where the PMOS transistor operating at the power supply voltage in the peripheral portion is formed, and injecting 5 × 10 ¹⁵ / cm ^2. An n-type polysilicon film 56 is formed by implanting phosphorus ions with an acceleration energy of 5 keV into the entire region other than the region where the PMOS transistor operating at power supply voltage is formed, at an injection amount of 5 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 23, for example, the n-type polysilicon film 56 and the p-type polysilicon film 57 are anisotropically etched by using the gate electrode pattern of the peripheral transistor to perform a PMOS transistor gate 61 that operates with a power supply voltage. Then, an NMOS transistor gate 58, a high breakdown voltage PMOS transistor gate 59, and a high breakdown voltage NMOS transistor gate 60 are formed. At this time, the memory cell portion is simultaneously etched using the second gate film pattern 193 shown in FIG. The contact extraction region 193 is formed in the region covered with the second gate film pattern 193, and the insulating film 4 is formed on the sidewalls of the first gate film patterns 50 and 51 in the region not covered with the second gate film pattern 193. Side silicon through the silicon nitride film 6 and the CVD oxide film 7 Formed in self-alignment to the a p o shaped memory gate 62 the first gate layer pattern 50 and 51. FIG. 32 shows a planar pattern of the memory cell portion at this time. A region surrounded by a thick line 193 is covered with a resist pattern and becomes a contact extraction region 193. The portion not covered with the resist pattern becomes the side wall spacer 62 and is formed on the side walls of the first gate film patterns 50 and 51 having the shape of the first gate film pattern 192.

Next, as shown in FIG. 24, the silicon nitride film 50 on the first gate film pattern 51 is removed by dry etching using, for example, a resist film 63 having a thickness of 2 μm opening only the memory cell region as a mask. Thereafter, using the resist film 63 as a mask, arsenic ions 64 having an acceleration energy of 20 keV are implanted at a dose of 5 × 10 ¹⁴ / cm ² to form a memory drain 65. As shown in FIG. 24, a height difference is formed between the side spacer-shaped memory gate 62 and the control gate formed by the first gate film pattern 51. That is, the height of the side spacer-shaped memory gate 62 is formed higher than the height of the control gate formed by the first gate film pattern 51.

Next, as shown in FIG. 25, by dry etching using a resist film 66 with a film thickness of 0.8 μm formed to etch the shape portion of the gate film isolation pattern 194 of the memory cell shown in FIG. The first gate film pattern 51 is cut by patterning to pattern the control gate of the memory cell. Subsequently, arsenic ions 67 having an acceleration energy of 20 keV are implanted at a dose of 5 × 10 ¹⁴ / cm ^{2 using} the resist film 66 as a mask. Thus, the source (region) 68 of the memory cell is formed. FIG. 33 shows a planar pattern of the memory cell portion corresponding to FIG. When the portion indicated by the gate film isolation pattern 194 among the portions indicated by the first gate film pattern 192, the contact extraction region 193, and the memory gate 62 is removed by patterning, the region of the first gate film pattern 192 becomes a region of 199. And the control gate 51 (199, 2, 23) of each memory cell is formed. The contact extraction region 193 and the region indicated by the memory gate 62 are formed on the side walls of the control gate 51 (199, 2, 23) and separated from each other to form the memory gate 62 (8, 27, 200) of each memory cell. Is done.

Next, as shown in FIG. 26, for example, boron difluoride ions with an acceleration energy of 20 keV are implanted only into a PMOS transistor portion operating at a power supply voltage, and an implantation amount of 2 × 10 ¹⁴ / cm ² and phosphorus ions with an acceleration energy of 10 keV are implanted at 3 ×. 10 ¹³ / cm ^{2 is} implanted, p-type extension 70, arsenic ions with an acceleration energy of 10 keV are implanted only into the NMOS transistor portion operating at the power supply voltage, 2 × 10 ¹⁴ / cm ² and boron ions with an acceleration energy of 10 keV are implanted. × 10 ¹³ / cm ^{2 is} implanted to form an n-type extension 71, and boron ions having an acceleration energy of 20 keV are implanted only into the high breakdown voltage PMOS transistor part by an implantation amount of 1 × 10 ¹³ / cm ² and a low concentration p-type source / drain 72. Phosphorus ions with acceleration energy of 30 keV are applied only to the high voltage NMOS transistor part. A low-concentration n-type source / drain 73 is formed by implanting an implantation amount of 2 × 10 ¹³ / cm ² , and then deposited by a CVD method and processed by an etch-back method using anisotropic dry etching. A certain oxide film side spacer 69 is formed on both side walls of the memory gate 62 (8, 27, 200) and the side wall of the control gate 51 (199, 2, 23) in a self-aligning manner. An oxide film side spacer 69 formed on one side wall of the memory gate 62 (8, 27, 200) is formed on the control gate 51 (199, 2, 23), and an oxide film side spacer formed on the other side wall. 69 is formed on the drain region 65 side. The oxide film side spacer 69 formed on the side wall of the control gate 51 (199, 2, 23) is formed on the source region 68 side.

Next, as shown in FIG. 27, for example, boron difluoride ions with an acceleration energy of 20 keV are implanted only into the peripheral PMOS transistor portion by an implantation amount of 3 × 10 ¹⁵ / cm ² to form a high concentration p-type source / drain 90, and 75, after forming the arsenic ions observed acceleration energy 30keV to NMOS transistor of the peripheral portion implantation amount 3 × ¹⁰ 15 / cm ² injected into the high-concentration n-type source and drain 74, and 76, a salicide technique Cobalt having a film thickness of 40 nm on all the gates 58, 59, 60, 61 and the source / drains 70 to 76, 90 and on the gates 51, 62 and the source / drains 65, 68 of the memory cell. A silicide (CoSi) film 77 is grown, and as shown in FIG. 28, as an insulating film, an acid film having a film thickness of about 30 nm is formed by CVD, for example. An oxide film 78 and a silicon nitride film 79 having a thickness of about 50 nm are deposited. The cobalt silicide (CoSi) film 77 is formed by, for example, depositing a cobalt (Co) film on the entire main surface of the substrate, reacting the cobalt with silicon by heat treatment, and then forming an unreacted cobalt (Co) film. It is formed by removing. A cobalt silicide (CoSi) film 77 is selectively formed on the gate and the source / drain made of silicon without being cobalt silicide on an insulating film such as a silicon oxide film. As described above, a height difference is formed between the side spacer-shaped memory gate 62 and the control gate of the first gate film pattern 51, and the insulating film side spacer 69 is formed on the side wall of the memory gate 62 therebetween. Therefore, there is no possibility that the cobalt silicide film 77 on the memory gate 62 and the cobalt silicide film 77 on the control gate 51 are short-circuited. Between the side spacer-shaped memory gate 62 and the drain 65, an insulating film side spacer 69 is formed on the side wall of the memory gate 62 on the drain 65 side, so that the cobalt silicide film 77 on the memory gate 62 and the drain 65 are formed. There is no possibility that the cobalt silicide film 77 is short-circuited. Since the insulating film side spacer 69 is formed on the side wall on the source 68 side of the control gate 51 between the side spacer-shaped control gate 51 and the source 68, the cobalt silicide film 77 on the memory gate 62 and the source 68 are There is no possibility that the cobalt silicide film 77 is short-circuited.

Next, as shown in FIG. 29, for example, after an ozone (O ₃ ) -TEOS (silicon oxide film) film 80 having a film thickness of about 700 nm is deposited as an interlayer insulating film by a CVD method, the interlayer insulating film 80 is formed by a CMP method. Polish to flatten the surface. Next, plug holes (connection holes) are opened on all the gates to be connected and the source / drain, and, for example, tungsten (W) is buried to form plugs 81. The common source lines of the memory cells are connected to each other by the plug 81.

  Finally, as shown in FIG. 30, an interlayer insulating film 82 having a film thickness of about 300 nm is deposited on the plug 81 by, for example, the CVD method, and directly above all the plugs 81 in the peripheral portion and on the drain of the memory cell. A contact hole (connection hole) is opened immediately above the plug 81, and a contact plug 83 made of tungsten (W) is embedded in the contact hole (connection hole) in the same manner as the plug 81, and is made of a tungsten film having a film thickness of about 200 nm. The first metal wiring 84 is formed, and the main manufacturing process of the flash-embedded logic LSI of this embodiment is completed. Further, although not shown in the drawing, a step of adding a desired metal wiring by a multilayer wiring structure, a deposition of a passivation film and an opening of a bonding hole are performed, and the process is completed up to the final step.

In the example of the manufacturing method described above, the gate length of the peripheral logic transistor (power supply voltage MOS transistor) is 100 nm, the gate length of the high breakdown voltage transistor is 0.5 μm, the control gate length of the memory cell is 150 nm, and the memory gate length is The memory channel width was 50 nm, the memory channel width was 180 nm, the bit line pitch was 0.3 μm, the word line pitch was 0.5 μm, and the memory cell area was 0.15 μm ² . The read current of the memory cell was about 50 μA / cell when the power supply voltage was 1.2 V.

<Another manufacturing method>
Next, a manufacturing method in which a memory cell in which the electrode structure of the memory cell is partially changed is adopted in the manufacturing process of mounting the nonvolatile memory cell on the logic LSI based on the 0.13 μm process technology described in the above manufacturing method. Will be described. In this case, the basic steps of the manufacturing method are almost the same as those described with reference to FIGS. The change will be described with reference to FIG.

  As shown in FIG. 34, the common source line of the memory cell is a first metal wiring 85 made of an aluminum film having a thickness of about 400 nm, and is configured in common with the first metal wiring 85 of the peripheral transistor. An interlayer insulating film 86 whose surface is planarized by the CMP method is formed above the first metal wiring 85, and a contact plug 87 made of tungsten (W) is formed in the interlayer insulating film 86. A contact plug 87 is directly connected immediately above the plug 81 on the drain of the memory cell, and a second metal wiring 88 made of an aluminum film having a film thickness of about 400 nm used as a bit line is formed on the contact plug 87 above the second metal wiring 88 of the peripheral transistor. And is configured in common. The interlayer insulating film 86 of the contact plug 87 has a thickness of about 700 nm. Thus, by configuring the wiring connecting the common source line and the peripheral transistors using the first metal wiring 85 made of an aluminum film, the wiring resistance can be reduced and the operation speed can be improved.

<Another manufacturing method>
Here, a method for processing a control cell and a memory gate in a self-aligned manner in the memory cell of the present invention without depending on processing by lithography will be described. Description will be made with reference to FIGS. 35 to 39 showing the cross-sectional structure of the memory cell part in each manufacturing process.

In FIG. 35, for example, a gate oxide film 92 (corresponding to the gate insulating film 2) having a thickness of 2 nm is grown in a desired region where a memory cell of a p-type silicon substrate (well region) 91 having a resistivity of 10 Ωcm is formed. After processing a laminated film of a first gate film pattern 93 made of a silicon film doped with phosphorus at a concentration of 2 × 10 ²⁰ / cm ³ at 100 nm and a cap nitride film 94 having a thickness of 200 nm, the film thickness is 3 nm by a thermal oxidation method. A lower oxide film 95 (corresponding to the lower oxide film 5) is grown, and a silicon nitride film 96 (corresponding to the silicon nitride film 6) having a thickness of 5 nm and an upper oxide film 97 (corresponding to the upper oxide film 7) having a thickness of 5 nm are grown. depositing a further concentration 2 × 10 20 ^/ cm ³ of the side spacer-shaped memory gate 98 to which phosphorus was formed by etching back the doped polysilicon film with a thickness of 70 nm (Memorige It shows a state in which a corresponding) to 8.

Next, as shown in FIG. 36, for example, arsenic ions having an acceleration energy of 30 keV are implanted into the memory gate 98 from the outside by an implantation amount of 4 × 10 ¹⁴ / cm ² to form a drain 99 (corresponding to the drain 10). After removing the cap nitride film 94 by wet etching using the silicon nitride film 96 as a mask, an oxide film having a film thickness of 150 nm is deposited and etched back to form an oxide film side spacer 100 (insulating film having a spacer length of 150 nm). Oxide film side spacers 12, 13, and 69) are formed.

  Next, as shown in FIG. 37, for example, a resist pattern having an opening only in the region of the first gate film pattern 93 to be cut is formed, and the first film is formed by dry etching using the oxide film side spacer 100 as a mask. One gate film pattern 93 is processed in a self-aligned manner with respect to the oxide film side spacer 100, and a control gate 101 (corresponding to the control gate 3) is formed in a self-aligned manner with respect to the oxide film side spacer 100.

Then, as shown in FIG. 38, for example, arsenic ions with an acceleration energy of 30 keV are implanted into the source region between the control gates 101 and 101 from the vertical direction at an injection amount of 4 × 10 ¹⁴ / cm ² to form the source 103 ( A p-type halo region 102 having an impurity concentration higher than the impurity concentration of the channel region by implanting boron ions with an acceleration energy of 20 keV in an implantation amount of 2 × 10 ¹³ cm ² from an oblique direction of 30 °. Form. At this time, the length of the completed control gate is 130 nm, and the upper portion of the memory gate 98 is etched by 120 nm to a height of 150 nm.

  Finally, as shown in FIG. 39, an insulating film 104 having a film thickness of 700 nm is deposited, a tongue hole plug 105 for connecting the plug hole to the common source line is embedded, and a contact interlayer film 106 having a film thickness of 300 nm is deposited. After the contact plug 107 made of the contact hole opening and the tungsten is buried, the bit line 108 made of the tungsten film having a film thickness of 300 nm is formed to complete the main part of the memory cell.

  In the memory cell manufactured by this method, the gate length of the control gate 101 is 120 nm and the gate length of the memory gate 98 is 60 nm. Both gate lengths are processed on the basis of the film thickness deposited by the CVD method. It is determined by the spacer length (the width in the channel length direction of the oxide film side spacer 100, the width in the channel length direction of the side spacer-shaped memory gate), and the variation of the gate length in the wafer surface is within ± 10%, that is, The gate length of the control gate 101 was 120 ± 12 nm, and the gate length of the memory gate 98 was 60 ± 6 nm. This variation in the gate length is difficult to achieve because the alignment accuracy in the lithography technology in the 0.13 μm process technology is about ± 30 nm, and the effectiveness of this embodiment was confirmed.

40 to 43 show an example in which a tungsten polycide (WSi ₂ / poly Si) film is applied to the control gate 101. For example, as shown in FIG. 40, the first gate film pattern 93 can be changed from a polysilicon film (poly Si) to a structure in which a silicide such as tungsten silicide (WSi) is provided on poly Si, as shown in FIG. It is. In addition, it is good also as a polymetal structure which provided metals, such as W, on not only silicide but poly Si via barrier metal films, such as WN. It is also possible to form a silicide film such as a cobalt silicide (CoSi ₂ ) film on the memory gate 98 using the salicide technique. In this case, the process cross section of FIG. 36 is as shown in FIG. 41, and the process cross section of FIG. 37 is as shown in FIG. Thereby, the wiring resistance of the control gate 101 can be reduced as compared with the case where the control gate 101 is formed of a silicon film, and the operation speed can be improved. Further, by forming a cobalt silicide (CoSi ₂ ) film on the memory gate 98, the wiring resistance of the memory gate 98 can be reduced, and the operation speed can be improved.

43 and 44 show a salicide modification. After the step of FIG. 37, as shown in FIG. 43, an oxide film (SiO ₂ ) side wall which is an insulating film is formed on the side wall of the control gate 101 in a self-aligned manner, and then the source / drain is formed by salicide technology. It is also possible to form a CoSi salicide layer on the diffusion layers 99 and 103 and the memory gate 98. Even in the case of FIG. 42, thereafter, as illustrated in FIG. 44, an oxide film (SiO ₂ ) side wall which is an insulating film is formed on the side wall of the control gate 101 in a self-aligned manner, and then salicide is formed. It is also possible to form a CoSi salicide salicide layer on the diffusion layer which is the source / drain 99, 103 by a technique. By forming a SiO ₂ sidewall in a self-aligned manner on the side wall of the control gate 101, the drain 103 and the CoSi salicide layer can be electrically separated, and the resistance of the source / drain 99, 103 and the memory gate 98 can be obtained. The wiring resistance can be reduced, and the operation speed can be improved.

<Multi-valued memory cell>
Next, an application example to a so-called multilevel memory cell of 2 bits / cell having a virtual ground array configuration will be described.

FIG. 45 illustrates a planar layout of a multilevel memory cell. In FIG. 45, 110 is a zigzag active region surrounded by an element isolation region, 111 is a control gate (corresponding to the control gate 3), and 115 is a data line made of metal wiring arranged in a direction orthogonal thereto. A lower oxide film (corresponding to the lower oxide film 5), a silicon nitride film (corresponding to the silicon nitride film 6), and an upper oxide film (corresponding to the lower oxide film 5) are formed below the memory gate 113 (corresponding to the memory gate 8). A stacked film 112 is formed, and a memory gate 113 is disposed on the side wall of the control gate 111 via the stacked film 112. Metal plugs 114 for connecting the active region and the data lines 115 are disposed at the corners of the zigzag active region 110. The arrangement pitch of the data lines 115 is designed to be twice the minimum processing dimension F (2F), the arrangement pitch of the control gate 111 is 4F, and the physical cell area is 8F ² . Accordingly, the arrangement angle θ of the zigzag active region 110 with respect to the data line 115 is tan θ = (data line pitch) / (control gate pitch) = 2F / 4F = 0.5, and θ is about 26.6 °. It is.

FIG. 46 exemplifies a planar layout of a contact extraction portion for the control gate 111 and the memory gate 113 of the multilevel memory cell. Before the memory gate 113 formed in a side spacer shape is processed by an etch back method using anisotropic dry etching, a resist pattern to which the second gate processing pattern 116 is transferred is arranged at the end of the control gate 111 and is etched. Do. Next, in order to take out the memory gates 113 on both sides of the control gate 111 independently, a resist film in which a separation hole pattern 117 (shaded portion) is transferred to a polysilicon film processed into the shape of the second gate processing pattern 116 As a mask, the memory gate 113 is taken out by the contact hole 114 and the first metal wiring 118 for the memory gate. At this time, in the extraction portion of the control gate 111, the contact hole 114 and the first metal wiring for the control gate 119 are connected. However, the end portion of the control gate 111 also has a side spacer-like shape by the separation hole pattern 117 (shaded portion). The memory gate 113 is disconnected. Thereby, the separation hole pattern 117 (shaded portion) is removed from the second gate processing pattern 116 and the side spacer-like memory gate 113, and the memory gates 113 on both sides of the control gate 111 are formed independently. The arrangement pitch of the first metal wiring 118 for the memory gate is twice (2F) the minimum processing dimension F, the arrangement pitch of the first metal wiring 119 for the control gate is 4F, and the arrangement pitch of the data line 115 is 2F. . Memory cell of the present embodiment is applied to processing techniques F = 0.2 [mu] m, physical memory cell area is ^{2F × 4F = 0.4 × 0.8μm 2} = 0.32μm 2, 2 Since the bit / cell operation is performed, the effective cell area is 0.16 μm ² .

FIG. 47 illustrates a vertical cross section of the multilevel memory cell. The multilevel memory cell has a gate oxide film 122 (corresponding to the gate insulating film 2) having a thickness of 4.5 nm on the surface of a p-type well region 121 formed in a surface region of a p-type silicon substrate having a resistivity of 10 Ωcm. Thus, a control gate 123 having a gate length of 200 nm made of a polysilicon film having a thickness of 200 nm and doped with phosphorus at a concentration of 2 × 10 ²⁰ / cm ³ is disposed. A lower oxide film 124 having a thickness of 3 nm, a silicon nitride film 125 having a thickness of 5 nm, and an upper oxide film 126 having a thickness of 5 nm are stacked on the surface region of the left and right p-type wells of the control gate 123, and a film is formed thereon. A side spacer-shaped memory gate 127 made of a polysilicon film having a thickness of 70 nm and doped with phosphorus at a concentration of 2 × 10 ²⁰ / cm ³ is disposed. Arsenic ions having an acceleration energy of 30 keV are implanted from the outside of the memory gate 127 in an amount of 4 × 10 ¹⁴ / cm ^{2 from} the vertical direction, and a source / drain electrode having a junction breakdown voltage of 5 V (one is a source electrode and the other is a drain electrode) Memory electrode) 128 to be formed. The left source / drain electrode 128 is also referred to as a left source / drain SDL, and the right source / drain electrode 128 is also referred to as a right source / drain SDR. The gate electrodes to be controlled in the multi-level memory cell shown in the figure are a control gate 123 (also referred to as control gate CG), a left memory gate 127 (also referred to as left memory gate MGL), and a right memory gate 127 (right side). Memory gate MGR).

  In FIG. 47, the multilevel memory cell can store four-level information. In the erased state (for example, storage information “00”), 10 V is applied to the left memory gate MGL and the right memory gate MGR, electrons are injected from the p-type well 121, and the electrons are trapped in the silicon nitride film 125. This is realized by setting the threshold voltage measured from the memory gate 127 to 1.5V. In the first write state (for example, storage information “10”), as illustrated in FIG. 47, 5 V is applied to the left source / drain SDL and −8 V is applied to the left memory gate MGL, so that the hot hole is left silicon nitride film. This is realized by setting only the threshold voltage measured from the left memory gate MGL to −1.5 V by injecting only into 125. Although not shown, in the second writing state (for example, storage information “01”), 5 V is applied to the right source / drain SDR and −8 V is applied to the right memory gate MGR, and the hot hole is applied only to the right silicon nitride film 125. This is realized by setting the threshold voltage measured from the right memory gate MGR to −1.5 V after implantation. Although not shown, the third write state (for example, storage information “11”) is realized by performing both the write operation for obtaining the first write state and the write operation for obtaining the second write acquisition state. Is done.

  FIG. 48 illustrates a memory array in which multilevel memory cells are arranged in a matrix. Typically, 12 memory cells are arranged in a matrix in the memory array. CG1 to CG4 are representatively shown control gate lines, MG1L to MG4L are left memory gate lines, MG1R to MG4R are right memory gate lines, and DL1 to DL4 are data lines. The data line is shared by the right source / drain SDR and the left source / drain SDL of the adjacent memory cell.

  The erase operation of the memory cell will be described based on FIG. 47. All the left and right memory gates MG1L to MGL4L and MG1R to MG4R in the erase block are selected, 10V is applied for an erase time of 100 ms, electrons are injected by a tunnel current, and the silicon nitride film 125 shown in FIG. The threshold voltage measured from the memory gate is VTE = 1.5V by trapping.

  Here, the erase state is described as “0”, the write state is described as “1”, and the threshold voltage states of the left memory gate and the right memory gate in one memory cell are set as “L, R” (L, R = “ 0 ”or“ 1 ”). After the erasing operation, all the memory cells are grasped as a state storing erasing data “0, 0”.

  FIG. 49 illustrates the write operation. First, -8V is applied to a selected memory gate to be programmed, for example, MG1R, MG2L, MG3R, MG4L, and then 5V, which is a source / drain junction breakdown voltage, is applied to the selected data line DL2 for a period of 10 μs. Hot holes due to interband current generated at the drain junction surface are injected into the silicon nitride film 125 already having electron traps to neutralize the electron traps, and the threshold voltage measured from the memory gate is VTP = −1. The write operation is completed by reducing the voltage to 5V. In this write state, the memory cells MCa and MCb store data “0, 1”, and the memory cells MCc and MCd store data “1, 0”.

  In the above-described operation, a data disturb voltage of 5 V is applied only to the source and drain, or a word disturb voltage of -8 V is applied only to the memory gate, to a memory cell that is not selected for writing. The time required for the slight fluctuation of the threshold voltage (ΔVTE = 0.1 V) due to the voltage, the so-called disturb life is 1 s or more, and there is an operation margin of 5 digits or more for the writing time of 10 μs. In the write operation, 5 V, which is a source / drain junction breakdown voltage, is applied to the selected data line DL2 for a write time of 10 μs. However, 1.8 V of the power supply voltage is applied to the selected data line DL2 on the semiconductor substrate side. The effective source / drain applied voltage may be set to 5V by applying -3.2V. Thereby, including the read operation described below, the maximum voltage applied to the data line and the control gate can be set to the power supply voltage 1.8 V. As a result, the word driver circuit connected to the control gate, and The sense amplifier circuit connected to the data line can be formed of a transistor having a thin film gate oxide film that operates with a power supply voltage, thereby achieving high-speed reading.

  50 and 51 illustrate the read operation. A read operation for one memory cell includes a forward read operation and a reverse read operation. The forward reading operation is an operation for determining whether or not a current path is formed when one of the left source / drain and the right source / drain of the memory cell is used as a drain electrode. Contrary to the above, the reverse read operation is an operation for determining whether or not a current path is formed when the other of the left source / drain and the right source / drain of the memory cell is the drain electrode.

  FIG. 50 illustrates the forward direction read operation. A case where the memory cell MCc in which the data “1, 0” is written is to be read is illustrated. First, in FIG. 50, after precharging the data line DL2 and the data line DL1 higher than the data line DL1 to the power supply voltage 1.8V, the control gate CG2 is raised to the power supply voltage 1.8V to change the potential of the data line DL2. Detect with sense amplifier. At this time, the data line DL2 operates as a drain and the data line DL3 operates as a source. However, since the memory gate MG2R in the vicinity of the source is in an erased state, the drain current is cut off and the potential of the data line DL2 does not change. That is, erase data “0” is read. Subsequently, reverse reading is performed. In FIG. 51, after precharging the data line DL3 and the lower data line DL4 to the power supply voltage 1.8V, the control gate CG2 is raised to the power supply voltage 1.8V to detect the potential change of the data line DL3 as a sense amplifier. To detect. At this time, contrary to the above, the data line DL3 operates as a drain and the data line DL2 operates as a source. However, since the memory gate MG2L in the vicinity of the source is in a write state, a drain current flows and the potential of the data line DL3 decreases. That is, the write data “1” is read. The memory cell in which the data “0, 0”, the data “0, 1”, and the data “1, 1” are written can be read by the same forward reading and reverse reading procedures.

  Although not particularly illustrated, the relationship between the selection control of the data line, the control gate line, the memory gate line and the access address in the write operation and the read operation is arbitrarily determined by the logic of the X decoder and the Y decoder described in FIG. I can do things. For example, assuming a byte address, select a total of eight memory transistor parts on the data line side of eight memory cells sharing one data line as a target for writing or reading for one byte address. do it. The write operation may be performed on the eight memory cells in parallel. The read operation may be performed by performing forward read and reverse read separately for the eight memory cells. If eight memory cells whose operation is selected by one byte address are configured by different memory mats or memory blocks, eight read operations for the eight memory cells can be performed in parallel.

  A method for manufacturing the multilevel memory cell will be described with reference to FIGS.

First, as illustrated in FIG. 52, a trench type in which an oxide film is buried in a trench having a depth of 250 nm in a surface region of a p-type semiconductor substrate 121 having a resistivity of 10 Ωcm and planarized by a CMP (Chemical Mechanical Polishing) method. after forming an isolation region 122, through the surface oxide film with a thickness of 10 nm, the amount of implanted phosphorus ions of acceleration energy 1MeV to a desired region 1 × ¹⁰ 13 / cm ^2, injection volume 3 × ¹⁰ phosphorus ions of acceleration energy 500 keV ¹² An n-type well region 125 is formed by implanting phosphorus ions having a dose of 1 × 10 ¹² / cm ² / cm ² and an acceleration energy of 150 keV. A high breakdown voltage p-type well region 124 is formed by implanting boron ions with an acceleration energy of 500 keV at an implantation amount of 1 × 10 ¹³ / cm ² and boron ions at an acceleration energy of 150 keV at an implantation amount of 5 × 10 ¹² / cm ² . Boron ions with an acceleration energy of 500 keV are implanted at 1 × 10 ¹³ / cm ² , boron ions at an acceleration energy of 150 keV are implanted at 5 × 10 ¹² / cm ² , and boron ions at an acceleration energy of 50 keV are implanted at 1 × 10 ¹² / cm ^2. The memory p-type well region 123 is formed by implantation. Thereafter, boron difluoride (BF ₂ ) ions having an acceleration energy of 50 keV are implanted into the memory cell region at a dose of 7 × 10 ¹² / cm ² , thereby forming the memory channel implantation region 126. A p-type channel enhancement implant region 128 is formed by implanting phosphorus ions having an acceleration energy of 50 keV into the PMOS transistor region operating at power supply voltage at an injection amount of 4 × 10 ¹² / cm ² . An n-type channel enhancement implant region 127 is formed by implanting boron difluoride (BF ₂ ) ions having an acceleration energy of 50 keV into the high-breakdown-voltage NMOS transistor region at an injection amount of 3 × 10 ¹² / cm ² . Thereafter, a thin gate oxide film 129 with a film thickness of 4.5 nm is grown in the memory cell region and the transistor region for power supply voltage operation, and a thick gate oxide film 130 with a film thickness of 15 nm is grown in the high breakdown voltage transistor region. Then, a 200 nm-thick non-doped polysilicon film 131 is deposited by the CVD method, and phosphorus ions having an acceleration energy of 10 keV are implanted into the memory cell region and the NMOS transistor region at an injection amount of 4 × 10 ¹⁵ / cm ² to form the first n-type gate film 132. Form. Thereafter, the control gate 133 is formed by processing the n-type gate film 132 only in the memory cell region.

  Next, as shown in FIG. 53, a lower oxide film 134 having a thickness of 3 nm is grown by a thermal oxidation method, and a silicon nitride film 135 having a thickness of 5 nm is deposited thereon by a CVD method. Further, after depositing an upper oxide film 136 having a thickness of 5 nm, the lower oxide film 134, silicon nitride film 135, and upper oxide film 136 in the peripheral region other than the memory cell region are removed.

Next, as shown in FIG. 54, a 50 nm-thick non-doped polysilicon film is deposited by the CVD method, and phosphorus ions with an acceleration energy of 10 keV are implanted into the memory cell region and the NMOS transistor region at a dose of 2 × 10 ¹⁵ / cm ^2. Then, a second n-type gate film 137 is formed. A p-type gate film 138 is formed by implanting boron difluoride (BF ₂ ) ions having an acceleration energy of 10 keV into the PMOS transistor region by an implantation amount of 5 × 10 ¹⁵ / cm ² .

  Further, as shown in FIG. 55, the stacked film of the first n-type gate film and the second n-type gate film and the p-type gate film are processed to form the p-type gate electrode 140 and the n-type gate electrode 139. Then, in the same gate processing step, the memory cell 141 is formed by processing the second n-type gate film 137 in the memory cell region into a side spacer shape.

Next, as shown in FIG. 56, boron difluoride ions with an acceleration energy of 20 keV are implanted only into the PMOS transistor portion operating at a power supply voltage, and the implantation amount is 2 × 10 ¹⁴ / cm ² and phosphorus ions with an acceleration energy of 10 keV are implanted at 3 ×. A p-type extension 142 is formed by implanting 10 ¹³ / cm ² . Low-concentration n-type source / drain 143 is formed by implanting phosphorus ions with an acceleration energy of 30 keV only into the high-breakdown-voltage NMOS transistor portion at an injection amount of 6 × 10 ¹² / cm ² . The memory source / drain 144 is formed by implanting arsenic ions having an acceleration energy of 10 keV only into the memory cell region at an injection amount of 5 × 10 ¹⁴ / cm ² . Thereafter, an oxide film side spacer 145 having a film thickness of 80 nm deposited by the CVD method and processed by the etch back method is formed, and boron difluoride ions having an acceleration energy of 20 keV are implanted into the peripheral PMOS transistor region at a dose of 3 × 10 ¹⁵ / cm ^2. Are implanted to form high-concentration p-type source / drain, and 30 keV arsenic ions are implanted into the peripheral NMOS transistor region at a dose of 3 × 10 ¹⁵ / cm ² to form high-concentration n-type source / drain. Thereafter, the oxide film 146 having a film thickness of 30 nm deposited by the CVD method is removed by wet etching leaving only the memory cell region, and a cobalt silicide film having a film thickness of 40 nm is formed on all the gate electrodes and the source / drain of the peripheral transistor. A film 147 is formed.

Finally, as illustrated in FIG. 57, a silicon nitride film 148 having a thickness of 50 nm is deposited by the CVD method, and an O ₃ -TEOS film 149 having a thickness of 700 nm is further deposited by the CVD method. In this embodiment, a plug hole is opened on the gate, source / drain, and tungsten 150 is buried to form a plug 150 to form a first metal wiring 151 made of a tungsten film having a thickness of 200 nm. The main manufacturing process of the 2-bit / cell flash memory is completed. Further, although not shown, a process of adding a desired metal wiring, a passivation film deposition and a bonding hole opening are performed, and the process is completed up to the final process.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above description, the best mode of the nonvolatile memory cell transistor according to the present invention is an example in which information is stored by injecting hot holes from the drain side and injecting electrons from the well region. However, the principle is not limited thereto. It is possible to inject electrons from the memory gate side, inject hot electrons instead of the FN tunnel, adopt a combination of hot hole injection and hot electron injection by the FN tunnel, and the like. Further, the concept of writing and erasing may be an overall concept, and a state with a high threshold voltage may be defined as writing and a state with a low threshold voltage may be defined as erasing. Various applied voltages for writing and erasing can be variously changed depending on the relationship between the power supply voltage of the LSI that on-chips the memory cell, the generation of the manufacturing process, and other circuits that are on-chip.

  The charge storage region is not limited to being composed of a silicon nitride film. For the charge storage region, a conductive floating gate electrode (for example, a polysilicon electrode) covered with an insulating film, a conductive fine particle layer covered with an insulating film, or the like may be employed. The conductive fine particle layer can be composed of, for example, nanodots having a polysilicon dot shape.

  The semiconductor integrated circuit device according to the present invention is not limited to a data processor such as a microcomputer, and can be widely applied to a system LSI having a relatively large logical scale, which is a system-on-chip.

1 is a longitudinal sectional view illustrating a nonvolatile memory cell transistor applied to a semiconductor integrated circuit device according to the present invention. It is a longitudinal cross-sectional view in the case of manufacturing the memory cell based on this invention with the process of carrying out mounting together with a logic transistor. FIG. 3 is a plan view of the memory cell of FIG. 2. FIG. 5 is a plan view illustrating a processing mask pattern arrangement for forming a memory gate only on the side surface portion on the drain side of the control gate in the memory cell according to the present invention. It is sectional drawing which illustrates the voltage application state in the erase operation of a memory cell. It is sectional drawing which illustrates the voltage application state in the write-in operation | movement of a memory cell. FIG. 10 is a cross-sectional view illustrating the read operation state of the memory cell. It is a block diagram which illustrates the data processor which carries out a flash memory on-chip. It is a block diagram which illustrates the detail of flash memory. FIG. 3 is a circuit diagram illustrating a state of a memory array during an erase operation for a flash memory. 3 is a circuit diagram illustrating a state of a memory array during a write operation to a flash memory. FIG. 3 is a circuit diagram illustrating a state of a memory array during a read operation with respect to a flash memory. FIG. It is explanatory drawing which illustrates another bit line structure in a memory cell block. It is a longitudinal cross-sectional view which shows another example of a memory cell transistor. FIG. 3 is a longitudinal sectional view of an essential part of an LSI during a manufacturing process when a nonvolatile memory cell as described in FIG. 2 is mixedly mounted on a logic LSI using a 0.13 μm process technology. FIG. 16 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 15; FIG. 17 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 16; FIG. 18 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 17; FIG. 19 is a longitudinal sectional view of an essential part of an LSI in the manufacturing process following FIG. 18; FIG. 20 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 19; FIG. 21 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 20; 22 is a fragmentary longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 21; FIG. FIG. 23 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 22; FIG. 24 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process following FIG. 23; FIG. 25 is an essential part longitudinal cross sectional view of the LSI during a manufacturing step subsequent to FIG. 24; FIG. 26 is an essential part longitudinal cross sectional view of the LSI during a manufacturing step following FIG. 25; FIG. 27 is an essential part longitudinal cross-sectional view of the LSI during a manufacturing step subsequent to FIG. 26; FIG. 28 is an essential part longitudinal cross-sectional view of the LSI during a manufacturing step subsequent to FIG. 27; FIG. 29 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 28; FIG. 30 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 29; FIG. 21 is a plan view showing a planar pattern of a memory cell unit corresponding to FIG. 20. FIG. 24 is a plan view showing a planar pattern of a memory cell portion corresponding to FIG. 23. FIG. 26 is a plan view showing a planar pattern of a memory cell portion corresponding to FIG. 25. FIG. 30 is a cross-sectional view of a principal part of an LSI representatively illustrating a change in another manufacturing method in a case where a memory cell in which the electrode structure of the memory cell is partially changed is adopted among the manufacturing methods described in FIGS. 15 to 29; is there. It is a fragmentary sectional view of an LSI during a manufacturing process in which both a control gate and a memory gate are processed in a self-aligned manner without depending on processing by lithography. FIG. 36 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 35; FIG. 37 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 36; FIG. 38 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 37; FIG. 39 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 38; FIG. 36 is a longitudinal sectional view showing a structure when a tungsten polycide film is applied to a control gate of a memory cell as a difference from FIG. FIG. 37 is a longitudinal sectional view illustrating a process cross section corresponding to FIG. 36 when the structure in FIG. 40 is employed. FIG. 39 is a longitudinal sectional view illustrating a process cross section corresponding to FIG. 37 when the structure of FIG. 40 is employed. FIG. 37 is a longitudinal sectional view exemplifying a cross section of a process to be added after the process of FIG. 37 when a cobalt silicide film is formed on the memory gate immediately after the process of forming the sided spacer memory gate shown in FIG. is there. FIG. 43 is a longitudinal cross-sectional view illustrating a structure in which a SiO ₂ sidewall is subsequently formed to form a CoSi salicide on the diffusion layer in the case of FIG. FIG. 6 is a plan layout diagram of a multilevel memory cell. FIG. 46 is a plan layout diagram illustrating a control gate of the multilevel memory cell of FIG. 45 and a contact extraction portion to the memory gate. FIG. 46 is a longitudinal sectional view illustrating the multilevel memory cell of FIG. 45. FIG. 46 is a circuit diagram illustrating the memory array in which the multi-valued memory cells of FIG. 45 are arranged in a matrix in an erase operation state. FIG. 46 is a circuit diagram illustrating a memory array in which the multi-valued memory cells of FIG. 45 are arranged in a matrix in a write operation state. FIG. 46 is a circuit diagram illustrating a memory array in which the multilevel memory cells of FIG. FIG. 46 is a circuit diagram illustrating the memory array in which the multi-valued memory cells of FIG. 45 are arranged in a matrix in a backward reading operation state. It is a principal part longitudinal cross-sectional view of LSI in the manufacturing process of a multilevel memory cell. FIG. 53 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process subsequent to FIG. 52; FIG. 54 is a fragmentary longitudinal cross-sectional view of the LSI during a manufacturing step subsequent to FIG. 53; FIG. 55 is an essential part longitudinal cross sectional view of the LSI during a manufacturing step subsequent to FIG. 54; FIG. 56 is an essential part longitudinal cross sectional view of the LSI during a manufacturing step following FIG. 55; FIG. 57 is an essential part longitudinal cross-sectional view of the LSI during the manufacturing process following FIG. 56; It is explanatory drawing of the write-in operation | movement of the non-volatile memory cell based on 1st prior art. It is explanatory drawing of the erase operation of the non-volatile memory cell based on 1st prior art. It is explanatory drawing of the write-in operation | movement of the non-volatile memory cell based on 2nd prior art. It is explanatory drawing of the erase operation of the non-volatile memory cell based on 2nd prior art. It is explanatory drawing of read-out operation | movement of the non-volatile memory cell based on 2nd prior art. It is explanatory drawing of the write-in operation | movement of the non-volatile memory cell based on 3rd prior art. It is explanatory drawing of the erase operation of the non-volatile memory cell which concerns on a 4th prior art. It is explanatory drawing of the write-in operation | movement of the non-volatile memory cell based on a 4th prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 122 Gate oxide film 3, 123 Control gate 4, 124 Oxide film 5 Lower oxide film 6, 125 Silicon nitride film 7, 126 Upper oxide film 8, 127 Memory gate 10 Drain 11 Source 12, 13, 28 Side Spacer 14 Metal salicide film 15 Interlayer insulating film 16, 18, 29 Metal plug 17 Insulating film 19, 30 Bit line 22 Active region

Claims (10)

A method of manufacturing a semiconductor integrated circuit device having a memory cell in a memory cell formation region, a low breakdown voltage transistor operating at a power supply voltage in a peripheral circuit transistor formation region, and a high breakdown voltage transistor operating at a voltage higher than the power supply voltage. There,
(A) forming a first insulating film serving as a gate insulating film of the low breakdown voltage transistor and a first gate insulating film of the memory cell on the semiconductor substrate in the peripheral circuit transistor forming region and the memory cell forming region;
(B) forming a first conductive film on the first insulating film in the peripheral circuit transistor formation region and the memory cell formation region;
(C) patterning the first conductive film in the memory cell formation region to form a first conductive pattern for acting as a control gate electrode of the memory cell;
(D) a second gate insulation of the memory cell including a charge storage layer on the first conductive pattern and the semiconductor substrate in the memory cell formation region and on the first conductive film in the peripheral circuit transistor formation region; Forming a film;
(E) removing the second gate insulating film in the peripheral circuit transistor formation region;
(F) forming a second conductive film on the second gate insulating film in the memory cell formation region and on the first conductive film in the peripheral circuit transistor formation region;
(G) In the memory cell formation region, the second conductive film is etched to form a memory gate electrode of the memory cell on the side wall of the first conductive pattern in a sidewall spacer shape, and in the peripheral circuit transistor formation region Patterning the second conductive film and the first conductive film to form a gate electrode of the peripheral circuit transistor;
(H) forming a source region of the memory cell on the semiconductor substrate in the memory cell formation region;
(I) forming a drain region of the memory cell on the semiconductor substrate in the memory cell formation region;
A method for manufacturing a semiconductor integrated circuit device, comprising: In claim 1,
The method of manufacturing a semiconductor integrated circuit device, wherein the formation of the memory gate electrode and the gate electrode of the peripheral circuit transistor are performed in the same process. In any one of Claim 1 or 2,
The method of manufacturing a semiconductor integrated circuit device, wherein the memory gate electrode is formed in a sidewall spacer shape on the side wall of the first conductive pattern via the second gate insulating film. In any one of Claims 1-3,
In the step (g), an electrode extraction portion for the memory gate electrode is formed. In any one of Claims 1-4,
The method of manufacturing a semiconductor integrated circuit device, further comprising a step of patterning the first conductive pattern after the step (g). In any one of Claims 1-4,
After the step (g),
Forming a side spacer made of an insulating film on a side wall of the memory gate on the first conductive pattern;
And a step of etching the first conductive pattern in a self-aligning manner using the side spacer as a mask. In any one of Claims 1-4,
In the step (g), the memory gate electrode is formed on both the one side wall of the first conductive pattern and the other side wall facing the one side wall via the second gate insulating film,
The memory cell uses the first conductive pattern as a control gate electrode, so that a charge storage layer under the memory gate electrode on the one side wall side and a charge storage layer under the memory gate electrode on the other side wall side A method of manufacturing a semiconductor integrated circuit device, wherein charges can be stored separately in each layer. In any one of Claims 1-7,
The method of manufacturing a semiconductor integrated circuit device, wherein the charge storage layer is a silicon nitride film. In any one of Claims 1-7,
The method of manufacturing a semiconductor integrated circuit device, wherein the charge storage layer is conductive fine particles. In any one of Claims 1-7,
The method of manufacturing a semiconductor integrated circuit device, wherein the charge storage layer is a floating gate electrode made of polysilicon.

Images