JP4438734B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a CCD solid-state imaging device with a built-in drive circuit, a circuit configuration of a drive circuit that enables high-speed drive, low power consumption, high integration, and single power supply drive, timing generation means used in the drive circuit, The present invention relates to a pulse voltage converter and a device structure.

  Currently, an interline CCD solid-state imaging device is mainly used as an imaging device used in a camera-integrated video tape recorder or the like. In order to realize an increase in the saturation signal charge amount, smear suppression, and simultaneous reading of two lines in the interline CCD image sensor, the inventor of the present application disclosed a drive circuit shown in FIG. We proposed a CCD solid-state image sensor with a built-in. In FIG. 14, 125 is a two-dimensionally arranged photodiode for photoelectric conversion, 129 is a vertical charge transfer means having a buried channel structure for transferring a signal charge provided between columns of photodiodes 125 in the vertical direction. It is. 127 is a row selection means for supplying a transfer pulse for transferring the signal charges of the photodiode 125 to the vertical charge transfer means 129 one by one in parallel. A shift register for selecting a row and an output pulse from the shift register for one horizontal scanning period. Consists of an interlace circuit that selects a set of two rows to be read simultaneously. Reference numeral 128 denotes a transfer pulse line for transmitting a transfer pulse output from the interlace circuit to the transfer gate 126 in the same row, and 126 denotes a transfer gate that is opened and closed by the transfer pulse. Reference numeral 130 denotes a drive means for sequentially supplying drive pulses for vertical charge transfer, which is composed of a shift register for generating a drive pulse train and a buffer circuit comprising an inversion circuit for inverting the pulse train output from the shift register. Is done. Reference numeral 131 denotes a drive pulse line that transmits a drive pulse output from the buffer circuit to each electrode of the vertical charge transfer means 129. Further, the horizontal scanning means is constituted by 132 to 125, 132 and 133 are respectively a gate gate and a drain for discharging a smear charge to the outside of the device, 134-1 to 134-3 are a first signal charge and a second signal charge, respectively. The first to third horizontal charge transfer elements for reading out the signal charges and smear charges of the first to third horizontal charge transfer elements 135-1 to 135-3 are output circuits of the first to third horizontal charge transfer elements 134-1 to 134-3, respectively. -1 to 136-3 are respectively between the vertical charge transfer means 129 and the first horizontal charge transfer element 134-1; the first horizontal charge transfer element 134-1 and the second horizontal charge transfer element 134-2; This is a gate for partitioning between the horizontal charge transfer elements 134-2 and the third horizontal charge transfer element 128-3. Incidentally, one transfer element partitioned by a horizontal solid line in the figure of the vertical charge transfer means 129 is composed of two layers of polysilicon electrodes 137 and 138 electrically connected to each other, and the potential below the two electrodes has a potential difference. Yes. The shift register that constitutes the row selecting means and the driving means is a two-phase ratioless dynamic shift register described in Patent Document 3, and the interlace circuit that constitutes the row selecting means is a circuit described in Patent Document 4.

  Since the operation of this circuit is described in detail in Patent Document 1 and Patent Document 2, only a brief description will be given here. First, when four scanning start pulses are input to the shift register constituting the driving means 127 at an interval that is an integral multiple of the cycle of the two-phase shift pulse of the shift register, these pulses are shifted in the shift register and output to each row. This output is inverted by a buffer circuit constituting the driving means 127 and applied to each electrode of the vertical charge transfer means 129 via a transfer pulse line 128. As a result, four types of potential wells are formed and moved across the plurality of electrodes separated by the potential barrier in each vertical charge transfer means 129. These four types of potential wells are for transferring smear charges that are released, smear charges that are read simultaneously with signal charges, first signal charges, and second signal charges, respectively. A transfer pulse is applied to the transfer pulse line 131 of the n-th row when the second signal transfer potential well passes the vicinity of the n-th row of the two rows selected by the row selection means, The signal charges in n rows are transferred from the photodiode 125 to the second potential well for signal charge transfer. In the same manner, the signal charges in the (n + 1) th row are transferred to the first potential well for signal charge transfer. The smear charges emitted in the other two types of empty potential wells and the smear charges read out simultaneously with the signal are accumulated as the potential well moves in the vertical charge transfer means. These four kinds of charges are discharged in the horizontal blanking period by the operation of the discharge gate 132, the gates 136-1 to 136-3 and the horizontal charge transfer elements 134-1 to 134-3. The smear charge is transferred to the third horizontal charge transfer element 134-3, the signal charge of the nth row is transferred to the second horizontal charge transfer element 134-2, and the signal of the (n + 1) th row is transferred to the first horizontal charge transfer element 134-2. It is transferred to the charge transfer element 134-1. Next, in the horizontal scanning period, charges are transferred through the first to third horizontal charge transfer elements 134-1 to 134-3 and amplified and output by the output circuits 135-1 to 135-3. By subtracting the smear signal from the n-th row signal and the (n + 1) -th row signal output in this way, a true signal free from smear signal is obtained. In the next field, interlace scanning is performed by simultaneously reading out n-1 rows and n rows. Such switching is performed by a two-phase interlace pulse input to an interlace circuit constituting the row selection means.

  On the other hand, the publication of Patent Document 5 shows that an amplifier is provided for each vertical charge transfer element of a conventional interline CCD and that the output is multiplexed to eliminate the speed limitation by the horizontal CCD. . In addition, the present inventor has shown in Patent Document 7 that in the above method, the circuit proposed in Patent Document 6 is provided with two capacitors for each amplifier to reduce the passband of the amplifier and reduce noise. .

  Further, Patent Document 8 proposes that a signal charge is converted into a voltage by a capacitive feedback amplifier using a CCD type image pickup device.

  Note that Patent Document 9 and Patent Document 10 include both a drive means for sequentially supplying drive pulses similar to the conventional example of FIG. 14 and a row selection means, and the drive means starts out smear charges, so that the charge transfer means. A plurality of potential wells separated and moved therein, and the row selection means transfers and transfers the signal charge to the potential well consisting of one electrode for transferring the signal charge in the plurality of potential wells. A conventional example is shown in which the gate 126 is shared with the electrode of the vertical charge transfer means 129, and the drive pulse line 128 and the transfer pulse line 131 are shared. Further, although Patent Documents 11 and 12 are different in that vertical charge transfer is performed by external pulses having the same multiphase as that of a typical charge transfer element, the same row selection means as in the conventional example of FIG. 14 is provided. In order to transfer a plurality of charges, a plurality of separated potential wells across a plurality of electrodes are formed and moved in the charge transfer means, and the row selection means transfers the signal charges in the plurality of potential wells. A conventional example is shown in which a signal charge is transferred to a well of a predetermined potential, the transfer gate 126 is shared with the electrode of the vertical charge transfer means 129, and the drive pulse line 128 and the transfer pulse line 131 are shared. Further, Patent Document 13 is different in that a plurality of charges are transferred, but has the same characteristics as those of the conventional example described above in other respects, and the photodiode 125 to the vertical charge transfer means 129. A conventional example in which the transfer is performed a plurality of times is shown.

  Patent Documents 14 and 15 each show a pulse width expander that provides a plurality of switches that are opened by one output of a shift register to obtain a pulse having a width equal to or greater than the shift period of the shift register. .

  In Patent Document 16, in a solid-state imaging device having a built-in drive pulse generation circuit for driving a charge transfer element, the gate oxide film thickness of the drive pulse generation circuit is made thinner than the gate oxide film thickness of the charge transfer element. An example is shown.

  Further, in Patent Document 17, other elements such as the driving means 127, the row selecting means 130, and the output circuits 135-1 to 135-2 are provided in the element having the driving means and the row selecting means similar to the conventional example shown in FIG. A conventional example formed in a well having a higher concentration than that of the portion is shown. Patent Document 18 discloses that the well of the driving means 127 is separated from the wells of other parts, and a lower bias voltage is applied than the other parts.

  Furthermore, Patent Document 19 provides a shielding plate isolated from an external noise source or a substrate semiconductor by sandwiching a sensing node between non-sensing nodes.

  On the other hand, the present inventor disclosed in Patent Document 20 a buffer that generates a pulse of a predetermined voltage level by supplying a trigger and two power sources with a pulse having a single power source value from a timing generator in a CCD type imaging device. Built-in booster or step-down circuit that generates a circuit and a specified DC voltage eliminates the driver chip and reduces the number of DC-DC converters, improving the usability of the CCD image sensor and reducing the consumption of the imaging device Proposed to use electric power.

  Patent Documents 21 and 22 describe that a shift register corresponding to the blanking period is provided to form a ring counter, and various signals are obtained from the shift register output during the blanking period.

  Further, the conventional example of FIG. 14 has a problem in that the horizontal scanning means cannot be highly integrated because there are the discharge gate 132 and the discharge drain 133 for extracting smear charges to the outside of the device. In addition, there is a problem that a potential peak in the charge transfer channel is generated at the portion X of the vertical charge transfer means 129 where an unnecessary charge starts and a signal is read and a transfer efficiency is poor. On the other hand, Patent Documents 5 and 7 are intended for high-speed and low-power consumption of a conventional interline CCD horizontal scanning means, and the above two problems of the conventional example of FIG. Not. Therefore, the second object of the present invention is to realize a horizontal scanning means that eliminates the gate gate 132 and the gate drain 133, and is highly integrated and does not cause poor transfer efficiency.

  In a conventional interline CCD image sensor, a photodiode 125 and a vertical charge transfer means 129 arranged two-dimensionally are formed in a p-well on an n-type substrate, and the potential of the p-well is set as a ground potential. By setting the low level of the drive pulse applied to each electrode of the charge transfer means to a negative value, an inversion layer (p well) is formed on the surface of the buried channel made of an impurity layer having a conductivity type opposite to that of the p well when a low level voltage is applied. A technique for inducing a dark current generated in the vertical charge transfer means 129 is known. In order to implement this method in the conventional example of FIG. 14, in order to drive the shift register constituting the driving means 127 that makes the low level a negative value from the driving signal having a positive single power supply value generated in the timing generation chip. It is necessary to provide a driver for generating three pulses of the two-phase shift pulse and the scan start pulse outside or inside the element and drive a relatively large pulse line in the shift register. In particular, since the two-phase shift pulse for driving the shift register is a high-speed pulse, a large amount of power is consumed in the driver, which has been a factor that hinders the reduction in power consumption of the imaging apparatus. Accordingly, a third object of the present invention is to eliminate a driver that generates a two-phase shift pulse that drives a relatively large pulse line in a shift register, and to reduce the power consumption of the imaging apparatus.

On the other hand, in the conventional example shown in FIG. 14, in the same way as a conventional interline CCD image sensor, a transfer gate is used to increase the amount of signal charge accumulated in the photodiode 125 and to prevent the afterimage phenomenon. A transfer pulse having a high voltage amplitude of about 15V is applied to 126. For this reason, in the conventional example of FIG. 14, the shift register constituting the row selection means 127 having the same high voltage amplitude as the transfer pulse is driven from the drive signal having the positive single power supply value generated by the timing generator. A driver for generating a two-phase shift pulse and a scan start pulse for driving, a two-phase interlace pulse for driving an interlace circuit and a transfer pulse supplied to two transfer pulse lines is provided outside the element or inside the element, The row selection means 127 was driven. However, since it is difficult to construct a circuit having such a large voltage amplitude with a fine transistor, the row selection means 127 composed of a shift register and an interlace circuit cannot be highly integrated. Furthermore, the driver provided inside or outside the element has to have a large area, which prevents the miniaturization of the device. Accordingly, the fourth object of the present invention is to increase the integration of the row selection means 127 by reducing the portion having a large voltage amplitude in the row selection means, and to generate a high voltage that generates five pulses excluding the transfer pulse. The purpose is to reduce the size of the device by eliminating the driver having the amplitude.

JP-A-61-184975

JP 62-126383 A Japanese Patent Publication No.62-045638 Japanese Patent Publication No. 61-061586 Published Patent Publication No. 60-500396 JP 62-185471 A Japanese Patent No. 6-97414 JP-A-57-72375 (JP-B-2-52424) JP 57-78167 (JP-B 61-17152) JP-A-60-98774 Japanese Unexamined Patent Publication No. 63-62480 (Japanese Patent Publication No. 4-46504) Japanese Unexamined Patent Publication No. 64-54879 JP 62-38677 (Japanese Patent Publication No. 3-74997) JP-A-61-157188 JP 61-214871 Japanese Patent Laid-Open No. 1-103861 JP-A-61-234670 JP-A-61-145974 JP-A-5-283614 JP-A-5-103272 JP 52-149022 A Japanese Patent Publication No. 5-24711

  In the conventional example of FIG. 14, in order to perform smear sweeping, smear differential, and two-line simultaneous independent reading while realizing a high saturation signal charge amount, a plurality of separated charge transfer means 129 are provided. The potential well for transferring the signal charge in the plurality of potential wells passes the vicinity of the selected row and applies a transfer pulse to transfer the signal charge to the vertical charge transfer means. Yes. For this reason, the application timing of the transfer pulse and the drive pulse of the vertical charge transfer means 129 cannot be clearly separated in terms of time, and the transfer gate 126 and the vertical charge as in the usual interline CCD type image pickup device are used. There is a problem that it is difficult to achieve high integration of the pixel portion by sharing the electrode of the transfer unit 129, the drive pulse line 128, and the transfer pulse line 131, and applying a ternary pulse to the common line. As conventional examples for solving this problem, there are Patent Document 9 and Patent Document 10. However, the method of generating a multi-valued pulse by using a MOS transistor for inputting the shift register output to the gate and the resistor described in Patent Document 9 has a problem that a through current flows when the MOS transistor is turned on. Moreover, since each MOS transistor directly drives a drive pulse line shared with a transfer pulse having a large capacity at high speed, the through current cannot be reduced. As a result, there is a problem that power consumption increases. On the other hand, the first switch that operates simultaneously in series between the driving means and the driving pulse line described in Patent Document 10 and the second switch controlled by the output of the row selecting means are provided between the power source and the driving pulse line. When the first switch is turned off and the second switch is turned on, the transfer pulse is supplied to the drive pulse line. In other periods, the first switch is turned on, the second switch is turned off, and the drive pulse is supplied. According to the method of applying to the drive pulse line, no through current flows. However, the transfer pulse application time needs to be less than or equal to the shift period of the drive pulse so that the voltage value of the drive pulse changes before and after the first switch is turned on and off and no charge is left behind. In Patent Documents 11 and 12, the same transfer pulse application method is used. As a result, there arises a problem that the transfer pulse does not rise sufficiently and an afterimage is generated. Accordingly, the fifth object of the present invention is to increase the power consumption in the conventional example of FIG. 14 and to prevent the generation of afterimages by making the applied transfer pulse longer than the shift period of the drive pulse. In other words, the pixel portion is highly integrated by using the electrodes of the vertical charge transfer means 129 and the drive pulse line 128 and the transfer pulse line 131 in common.

  In order to achieve the above object, in the solid-state imaging device according to the present invention, the driving means generates at least a shift register for generating a timing signal of the driving pulse, and the timing signal is provided for each driving pulse line. A first switch having one end of the driving pulse line that opens and closes and the first power source as the other end; and a second switch having the second power source as the other end and the driving pulse line as one end. The selection means includes a third switch having a drive pulse line that is always turned off in a non-selected row and turned on when both the first and second switches are turned off in the selected row.

  According to the means for achieving the object of the present invention, the first switch and the second switch constituting the driving means are based on the timing signal from the timing generating means, respectively, and the drive pulse rise and fall times, respectively. The drive pulse line is connected only to the first power supply or the second power supply, and is turned off in other periods. On the other hand, the third switch constituting the row selection means is turned off during the entire period of the non-selected row and the period excluding the transfer pulse application time. Therefore, the period during which the transfer pulse is output to the drive pulse line is between the fall and fall periods of the drive pulse, and the period between the rise and fall of the drive pulse is n times the shift period of the drive pulse. The transfer pulse application time can be set to an arbitrary time not more than n times the shift period of the drive pulse without flowing through current. In this way, there is no increase in power consumption, and there is no afterimage by making the applied transfer pulse longer than the drive pulse shift period, the transfer gate 126 and the electrodes of the vertical charge transfer means 129, and the drive pulse. By using the line 128 and the transfer pulse line 131 in common, the pixel portion can be highly integrated.

  According to the present invention, even when the drive pulse line and the transfer pulse line are shared, the application time of the transfer pulse can be set to an arbitrary time n times the shift period of the drive pulse without flowing through current. The pixel portion can be highly integrated without increasing power or generating afterimages. Furthermore, the drive pulse of the row selection means having a low level as a negative value can be only the pre-transfer pulse, and the row selection means 127 can be highly integrated by reducing the portion of the row selection means 127 where the drive voltage amplitude is high. In addition, it is possible to realize a driving unit having high reliability without applying a high voltage to the output unit of the driving unit.

[Example 1]
First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing the overall circuit configuration of the first embodiment, and FIG. 2 is a drive pulse timing diagram of the element of FIG. FIG. 3 (a) is a circuit configuration diagram of the first embodiment of the driving means comprising the timing generating means 3 and the driving pulse generating means 4, and FIG. 3 (b) is a driving pulse timing chart of the circuit of FIG. 3 (a). It is. In the diagram (a), the inside of the broken line shows the circuit portion provided for each row of the drive pulse generating means 4. FIG. 4A is a circuit configuration diagram of the second embodiment of the drive means, and FIG. 4B is a drive pulse timing diagram of the circuit of FIG. In FIG. 4A, the inside of the broken line shows the circuit for one row of the pulse width expander forming part of the timing generating means 3 and the circuit portion provided for each row of the driving pulse generating means 4. FIG. 5 is a circuit configuration diagram of a third embodiment of the driving means. FIG. 5 shows a circuit for one row of the pulse width expander and the drive pulse generating means 4 forming part of the timing generating means 3 within the broken line. FIG. 6 is a circuit configuration diagram of a fourth embodiment of the driving means. In FIG. 6, the inside of the broken line shows a circuit for one row of the pulse width expander and the driving pulse generating means 4 forming part of the timing generating means 3 within the broken line. FIG. 7A is a circuit configuration diagram of the first embodiment of the row selection means comprising the row selection control means 6 and the transfer pulse generation means 7, and FIG. 7B is a drive pulse for the circuit of FIG. It is a timing diagram. In FIG. 2A, the inside of the broken line shows a circuit for one row of an interlace circuit forming a part of the row selection control means 6 and a circuit portion provided for each row of the transfer pulse generating means 7. FIG. 8 (a) is a circuit configuration diagram of a second embodiment of the row selection means comprising the row selection control means 6 and the transfer pulse generation means 7, and FIG. 8 (b) is a drive pulse for the circuit of FIG. 8 (a). It is a timing diagram. In FIG. 8A, an interlace circuit forming part of the row selection control means 6 and a circuit for one row of the transfer pulse generation means 7 are shown within the broken line. FIG. 9 is a cross-sectional structure diagram of the vertical charge transfer means 2 having a thick gate oxide film and formed in the low-concentration first impurity layer. The impurity distribution of this structure consists of a punch-through structure that enables the reduction of smear, the saturation, and the dark current proposed by the present inventor in Japanese Patent Laid-Open No. 03-289173. FIG. 10 shows an nMOS transistor formed in a third impurity layer having the same thick gate oxide thickness as that of the vertical charge transfer means 2 and having a lower surface concentration than other portions. FIG. 11 shows a source / drain n-type diffusion layer formed in a third impurity layer having the same thick gate oxide thickness as that of the vertical charge transfer means 2 formed by applying a field p layer offset and having a lower surface concentration than other portions. This is an nMOS transistor. FIG. 12 is a structural diagram of a MOS transistor having a gate oxide film thinner than the vertical charge transfer means 2 enabling high speed and high integration and formed in a second impurity layer having a high concentration. FIG. 13 shows a capacitor having an electrode composed of an impurity layer including a first conductivity type impurity layer constituting a photoelectric conversion element provided in the second conductivity type impurity layer.

Hereinafter, first, the overall configuration and operation and the horizontal scanning means will be described with reference to FIGS.
(1) Overall Configuration and Horizontal Scanning Means FIG. 1 shows a case where the photoelectric conversion elements are 3 × 3 matrixes for the sake of simplicity. In FIG. 1, reference numeral 1 denotes a photoelectric conversion element composed of photodiodes arranged two-dimensionally, and 2 denotes vertical charge transfer means having a buried channel structure for transferring signal charges provided between columns of photodiodes 1 in the vertical direction. It is. The vertical charge transfer means 2 is composed of a repetitive part composed of an electrode 2-1 and a charge transfer control part composed of 2-2 to 2-4, 2-1 is an electrode constituting the repetitive part, and f is a final electrode of the repetitive part 2-2 is a gate for partitioning the vertical charge transfer means 2 and the charge storage gate 2-3, 2-3 is a charge storage gate, and 2-4 is an output gate for partitioning the charge storage gate 2-3 and the amplifier 11. 3 and 4 constitute the driving means, 3 is a timing generating means having a shift register to which a positive single power supply driving signal is inputted, and 4 has a negative voltage from the timing signal and the negative power supply at a low level. Drive pulse generating means for supplying drive pulses to the drive pulse line 5, 5 is a drive pulse line common to the transfer pulse line, 6 and 7 constitute row selection means, 6 is a positive single power supply drive signal A row selection control means consisting of a shift register and an interlace circuit for specifying the input selected row, transfer having a high second voltage value higher than the positive power supply voltage value to the selected selected row Transfer pulse generating means for outputting a pulse and generating a negative value voltage in a selected row and a non-selected row in a period in which no transfer pulse is applied and applying it to the gate of a transfer pulse switch MOS transistor having a drive pulse line as a source. 8 and 9 are a charge transfer control unit drive line for transmitting a drive pulse applied from the terminal SB and the terminal ST to the gate 2-2 and the charge storage gate 2-3 constituting the charge transfer control unit, respectively. This is a charge transfer controller drive line that transmits a DC voltage applied to the OG to the output gate 2-4. Further, 11 to 19 constitute scanning means. Amplifying means is composed of 11 to 18, and 11 is an inverting amplifier circuit having a high voltage gain provided for each output terminal of the vertical charge transfer means 2 and operating as a positive single power source as a driver. An amplifier, 12 is a reset switch composed of a p-channel MOS transistor also used as a discharge gate provided between an input terminal and an output terminal of the amplifier 11, and 13 is a feedback capacitor. 14 to 18 are output holding means for holding the signal output after reducing the passband of the amplifier proposed by the present inventor in Japanese Patent Laid-Open No. Sho 62-185471, and 14 is an amplifier input terminal. A first output holding capacitor for holding the first output of the amplifier at the time of reset, 17-1 is the first second output of the amplifier at the time of the first signal input to the amplifier input terminal and the first output of the amplifier at the time of resetting the amplifier input terminal 1st second output holding capacitor for holding a difference value from the first output 20 of 1 and 17-2 is the second output of the amplifier and the amplifier input terminal reset when the second signal is input to the amplifier input terminal A second second output holding capacitor that holds a difference value with the second first output 20 of the amplifier at the time, 15 is a clamp switch that clamps the output terminal side voltage of the first output holding capacitor 14 and performs difference processing, 16-1 and 16-2 are the signal write switches to the first and second output holding capacitors, respectively, and 18-1 and 18-2 are the first A signal readout switch from the second second output storage capacitor. A horizontal scanning circuit 19 selectively opens and closes the reading switches 18-1 and 18-2 to selectively read out the difference values held in the second output holding means. T1, T2, and TIN are single positive power supply value drive signal input terminals for driving the shift register in the timing generating means 4, T1 and T2 are two-phase shift pulse input terminals, TIN is a scan start pulse input terminal, VL Is a negative power supply voltage input terminal equal to the low level voltage of the transfer pulse, VM is a high level voltage input terminal of the transfer pulse, Vcc is a positive power supply voltage value input terminal, GND is a ground terminal, V1, V2 and VIN are row selection control means. 6 is a single positive power supply value drive signal input terminal for driving the shift register, V1 and V2 are two-phase shift pulse input terminals, VIN is a scan start pulse input terminal, and FA and FB are driving an interlace circuit. A two-phase interlace pulse input terminal, V3, V4, which is a single positive power supply value drive signal, is a transfer pulse signal having a second voltage value higher than the positive power supply voltage value at a high level. Terminal, V3L, V4L the location transfer pulse applying terminal before the high level has a positive third voltage value lower than the second voltage value higher than the power supply voltage value vcc to the high level, SB driving pulse of the gate 2-2 Application terminal, ST is a drive pulse application terminal for charge storage gate 2-3, OG is output gate 2
DC voltage application terminal to -4, RG, CP, SH1, SH2 are positive single power source drive signals for driving the amplification means, RG is a reset pulse input terminal to the reset switch 12, and CP is a clamp switch 15 is a clamp pulse application terminal, SH1 and SH2 are sample hold pulse application terminals to read switches 16-1 and 16-2, VC is a DC clamp voltage input terminal, O1 and O2 are signal output terminals, H1 and H2, HIN is a positive single power source driving signal for driving the horizontal scanning circuit 19, H1 and H2 are two-phase shift pulse input terminals of the horizontal scanning circuit 19, and HIN is a scanning start pulse input terminal of the horizontal scanning circuit 19. . The horizontal scanning circuit 19 includes a two-phase ratioless dynamic shift register described in Japanese Patent Publication No. 62-045638. The horizontal solid line in the figure of the vertical charge transfer means 2 indicates the partition of the electrodes constituting the vertical charge transfer means 2, and the vertical charge transfer means is a single-layer electrode structure already proposed by the present applicant in Japanese Patent Laid-Open No. 03-60158. A buried channel structure. In FIG. 2, HBL is the horizontal retrace period, φV1, φV2, φV3, V4 , φV3L, V4L, φTIN, φT1, φT2, φ SB, φ ST, φRG, φCP, φSH1, φSH2, φHIN, φH1, the φH2 1 shows pulse voltages applied to the terminals V1, V2, V3, V4, V3L, V4L, TIN, T1, T2, SB , ST , RG, CP, SH1, SH2, HIN, H1, and H2, respectively. Furthermore, vl and vm are the low level voltage value and the high level voltage value of the drive pulse of the vertical charge transfer means 2, respectively, vh is a second voltage value higher than the positive power supply voltage value vcc, and vhm is higher than the positive power supply voltage value. The third voltage value is lower than the voltage value of 2, and φV1, φV2, φTIN, φT1, φT2, φRG, φCP, φSH1, φSH2, φHIN, φH1, and φH2 are ground voltages, and high levels are positive power supply voltages. The value is vcc. Although not shown in FIG. 2, the voltages applied to the VIN, FA, and FB terminals in FIG. 1 are the same. Further, a DC voltage intermediate between vm and vl is applied to the OG terminal in FIG. 1, and a predetermined DC bias is applied to the O1 and O2 terminals. The DC bias of the VC terminal and the O1 and O2 terminals are the same in order to prevent unnecessary offsets. The DC bias voltage is set to 0 V in order to reduce the voltage applied to the second output holding capacitors 17-1 and 17-2. On the other hand, s, n1, and n2 are respectively applied to a terminal T1 that is input to form a potential well for transferring the first signal charge, the second signal charge, the first unnecessary charge, or the second unnecessary charge. T represents the application time within one horizontal blanking period of the two-phase shift pulse at terminals T1 and T2. As in Japanese Patent Laid-Open No. 62-126383, each time interval has a value that is an integral multiple of the period of the two-phase shift pulse, and satisfies the relationship T = 2s + n1 + n2. Further, the timing at which φV3, V4, φV3L, and V4L become high level is within the horizontal blanking period, although it differs depending on the read row. Ts1 and Ts2 are the first output write time to the first output holding capacitor 14 that holds the first output of the amplifier when the amplifier input terminal is reset, and the second output and amplifier of the amplifier when a signal is input to the amplifier input terminal. The difference value writing time to the second output holding capacitors 17-1 and 17-2 for holding the difference value from the first output of the amplifier at the time of resetting the input terminal, Tn is the sweep time of unnecessary charges. The pulse voltages φCP, φSH1, and φSH2 for operating the amplifying means are synchronized with the pulse voltages φT1 and φT2 for operating the driving means, and the writing time of the first output to the first holding capacitor 14 and the second holding capacitor 14 The influence of the jumping noise on the first and second outputs of φT1 and φT2 at the writing time of the second output to is reduced. Further, the two-phase shift pulse of the timing generating means 3 applied to the terminals T1 and T2 and the two-phase shift pulse of the horizontal scanning circuit 19 applied to the terminals H1 and H2 are synchronized pulses having the same frequency, and generate a drive signal. Simplification.

The overall operation will be described below with reference to FIGS. First, when a two-phase shift pulse is applied to the terminals T1 and T2 and a scan start pulse is input to the terminal TIN at time intervals of s, n1, s, and n2, a driving pulse generating means is generated from the timing signal generated from the timing generating means 3. As a result, a drive pulse having a low level as a negative value is output to the drive pulse line 5, and four types of potential wells are formed and moved across the plurality of electrodes separated by the potential barrier in each vertical charge transfer means 2. The four potential wells transfer the first signal charge, the first unnecessary charge, the second signal charge, and the second unnecessary charge. On the other hand, when a two-phase shift pulse is applied to the terminals V1 and V2 and a scanning start pulse is applied to the terminal TIN, the row selection control means 7 simultaneously selects two adjacent rows, n and n + 1, sequentially in each horizontal scanning period. . The combination of the two rows is switched for each field by an interlace circuit that operates by a two-phase pulse applied to the terminals FA and FB. When the pre-transfer pulse and the transfer pulse are applied to the terminals V3L and V3 when the first signal transfer potential well passes in the vicinity of the nth row of the two rows selected in this way, the transfer pulse is applied. The generation means 7 outputs a transfer pulse far higher than the positive power supply voltage to the driving pulse line 5 in the nth row, and the nth row
The row signal charges are transferred from the photodiode 1 to the first signal charge transfer potential well. Next, a pre-transfer pulse and a transfer pulse are applied to the terminals V4L and V4 to transfer the signal charges in the (n + 1) th row to the second signal charge transfer potential well. Unnecessary charges such as smear charges are accumulated in the other two types of potential wells as the potential wells move in the vertical charge transfer means 2. On the other hand, in parallel with the charge transfer in the vertical charge transfer means 2 by the driving means consisting of 3 and 4 and the signal reading from the photoelectric conversion element 1 of the row selection means 6 and 7 to the vertical charge transfer means 2, The amplifying means consisting of f to 2-4 and 11 to 18 in the vertical charge transfer means 2 extracts unwanted charges and outputs signal charges. At the beginning of the horizontal blanking period, first, the second unnecessary charge in the previous row is discharged from the reset switch 12. That is, after the potential barrier which divides the potential well of the first signal charge transferring second unwanted charges in the previous row has reached just before the gate 2-2, to lower the voltage applied phi SB terminal SB gate 2- 2 is turned off and then, lowering the applied voltage phi ST terminal ST, the input terminal of the second unwanted charge through the output gate 2-4 amplifier 11 lines before stored in the charge storage gates 2-3 The reset switch 12 that is transferred and immediately turned on is discharged from the output terminal of the amplifier 11. (Time t1 in FIG. 2) Thereafter, the signal voltage by the first signal charge is written to the first second output holding capacitor 17-1. That is, the applied voltage phi ST again raised charges in the charge accumulation gate 2-4 of the terminal ST is ready for storage. On the other hand, after time t1, the potential well separating the potential well transferring the first signal charge and the first unnecessary charge moves toward the gate 2-2, and the first signal charge is repeated by the vertical charge transfer means 2. Collected in the final electrode f. This potential barrier is turned high and the gate 2-2 the applied voltage phi SB terminal SB before the arrival to the final electrode f under the channel potential in the final electrode f is lower. Next, when the channel potential of the final electrode f is lowered, the applied voltage φ SB of the terminal SB is lowered and the gate 2-2 is turned off again, the signal charge transferred in the potential well for transferring the first signal charge is transferred. All are transferred and held in the charge storage gate 2-3. Thereafter, the gate 2-2 does not open until the writing of the first signal charge to the first second output holding capacitor is completed, and the first unnecessary charge is not mixed into the first signal. . Note that the final electrode f has a larger charge capacity than the other electrodes, and can store all the first signal charges. When insufficient storage capacity in one electrode, advancing the timing of increasing the phi SB, a plurality electrodes of repetition of the vertical charge transfer section 2 may be accumulated charge. Furthermore, the length of the charge storage gate 2-3 may be made small by increasing the amount of charge that can be held per unit area of the storage gate 2-3 by setting the high level of φST to vcc higher than vm. In addition, the pulse input to the terminal TIN in consideration of the application time T in one horizontal blanking period applied to the terminals T1 and T2 and the number of stages to the final electrode of the timing generating means 3 If the phase in the horizontal blanking is determined, it is easy to set the arrival time of the potential barrier to the final electrode at a predetermined time. (Time t2 in FIG. 2) On the other hand, after the voltage RG of the terminal RG is increased and the reset switch 12 is turned off, the clamp switch 15 is closed when the applied voltage φCP of the terminal CP becomes low after Ts1 time, and the input terminal of the amplifier 11 is reset. The first output of the amplifier 11 at that time is written to the first output holding capacitor 14, and the potential fluctuation at the output terminal of the amplifier 11 after this time is transmitted to the first second output holding capacitor 17-1. . At this time, the pass band of the amplifier 11 is limited to about 1 / Ts 1 by the output resistance of the amplifier 11 and the capacity of the first output holding capacitor 14. (Figure 2 time t3) in this state, lowering the voltage applied phi ST terminal ST, the first signal charge is transferred to the input terminal of the amplifier 11 which has been held in the charge accumulation gate 2-3. (Time t4 in FIG. 2) This signal charge is converted into a signal voltage by the amplifier 11 and the feedback capacitor 13, causing a potential fluctuation at the output terminal of the amplifier 11. This potential fluctuation, that is, the difference value between the second output of the amplifier at the time of signal input to the amplifier input terminal and the first output of the amplifier at the time of resetting the amplifier input terminal is the applied voltage φSH1 of the terminal SH1 after Ts2 time after signal transfer. When the signal writing switch 16-1 is turned off and turned off, the signal is written and held in the first second output holding capacitor 17-1. At this time, the pass band of the amplifier 11 is limited to about 1 / Ts 2 by the output resistance of the amplifier 11 and the series capacitance of the first output holding capacitor 14 and the second output holding capacitor 17-1. As described above, while reducing the pass band of the amplifier 11, it is possible to output the voltage fluctuation due to the signal charge from which the reset noise generated when the reset switch is turned off and the fixed pattern noise due to the DC voltage variation of each amplifier is removed. Yes. (Time t5 in FIG. 2) Next, the second unnecessary charge is ejected from the reset switch 12. That is, the applied voltage phi ST again raised charges in the charge accumulation gate 2-4 of the terminal ST is ready for storage. After time t2, the potential barrier separating the potential well for transferring the first unnecessary charge and the potential well for transferring the second signal charge moves toward the gate 2-2, and the first unnecessary charge is transferred to the vertical charge transfer means. 2 are collected on the final electrode f. This potential barrier is turned to high by gate 8 applied voltage phi SB terminal SB before the lower end electrode f under the channel potential reaches the final vertical electrode f. Then, the channel potential of the final electrode f is lowered, to lower the voltage applied phi SB terminal SB off the gate 2-2 again, lowering the applied voltage phi ST terminal ST first unnecessary charge reset switch 12 To the output terminal of the amplifier 11. Note that the final electrode f has a larger charge capacity than the other electrodes and can store all of the first unnecessary charge, as in the case of reading the first signal. (FIG. 2, time t6) Thereafter, the signal voltage by the second signal charge is written into the second second output holding capacitor 17-2 by the operation from time t2 to t5. (Time t7 in FIG. 2) In the horizontal scanning period, a scanning start pulse is input to the terminal HIN of the horizontal scanning circuit 19, and this pulse is generated in the horizontal scanning circuit by the two-phase driving pulses applied to the terminals H1 and H2. , And sequential signal reading switches 18-1 and 18-2 are turned on and off, so that signals in the nth row are sequentially output from the terminal O1 and signals in the (n + 1) th row from the terminal O2.

According to this embodiment, firstly, the driving means composed of the timing generating means 3 and the driving pulse generating means 4 sequentially outputs driving pulses to a part of the vertical charge transfer means 2, the load capacity is small, and the row selection is performed. The row selection means consisting of the control means 6 and the transfer pulse generation means 7 outputs a transfer pulse to one line, so the load capacity of the row selection means is small, and the signal charge from the vertical charge transfer means 2 is amplified by 11 to 18 Since the second output holding means 17-1 and 17-2 which are the outputs of the amplifying means are selected and output by the horizontal scanning circuit after being amplified by the means, the load capacity of the flat scanning circuit is also small. As a result, drive pulse input terminals T1, T2, TIN of the drive means, drive pulse input terminals V1, V2, VIN, V3L, V4L, V3, V4, FA, FB, drive pulse input terminals SB , ST , The load capacity of RG, CP, SH1, SH2, HIN, H1, and H2 is only one horizontal or vertical pulse line, and there is no speed limitation due to the rise of the drive pulse, and high speed driving is possible.

Secondly, according to the present embodiment, since the reset switch 12 is also used as an extraction gate, an extraction gate and an extraction drain are not required, and it is possible to provide horizontal scanning means with high integration and good transfer efficiency. That is, the signal charge transferred by the first potential well formed in the vertical charge transfer means 2 is transferred to the input terminal of the amplifier 11 within the time Ts2 when the reset switch 12 is off, converted into a voltage and output. It is held in the holding capacitor 17-1 or 17-2. On the other hand, the unnecessary charge transferred by the second potential well formed in the vertical charge transfer means 2 within the time Tn when the reset switch is on is transferred to the outside of the element through the reset switch 12 together with the signal charge that has been output. Swept out. The outputs held in the output holding capacitors 17-1 and 17-2 are selected by the horizontal scanning circuit 19 and outputted from the terminals O1 and O2 to the outside of the element. In this way, the gate gate and the drain are not required, so that high integration is possible, and the signal charge and the unnecessary charge are not separated in the charge transfer path, so that transfer efficiency does not deteriorate. Note that this effect eliminates the charge transfer control unit consisting of 2-2 to 2-4 of the vertical charge transfer means 2, and applies the sub-electrode potential when the high level is applied to the final electrode f of the vertical charge transfer means to the input of the amplifier 11. When the signal is transferred from the vertical charge transfer means 2 at a voltage lower than the terminal potential, the reset switch 12 is turned off and a signal is output and held in the holding capacitor 17-1 or 17-2, which is unnecessary from the vertical charge transfer means 2. When the charge is transferred, the reset switch 12 is turned on and unnecessary charge is released, and the charge can be obtained similarly. Further, at this time, the first output holding capacitor 14 and the clamp switch 15 may be omitted.

Further, when smearing out from the reset switch 12, the vertical charge transfer means 2 is provided with a charge transfer control unit consisting of 2-2 to 2-4 between the input terminals of the amplifier 11, thereby impairing the amplifier noise reduction effect. It is possible to obtain a smear suppression effect by sufficient sweeping without any problems. That is, the charge transfer control unit consisting of 2-2 to 2-4 distributes unnecessary charges distributed in the second potential well across the plurality of electrodes in the vertical charge transfer means 2 to the final electrode of the vertical charge transfer means 2 After collecting them in f, they are transferred all at once to the input terminal of the amplifier 11, and the reset switch 12 is turned off. As a result, the period in which the reset gate 12 needs to be turned on becomes the period Tn necessary to drive out the unnecessary charges collected at the final electrode f, and the reset gate 12 is turned off in all other periods and the signal charge is changed to the voltage. The operation period of the amplifier 11 can be converted into the holding capacitor 17-1 or 17-2. In this way, when performing resetting from the reset switch 12, the write time Ts1 + Ts2 to the storage capacitor is lengthened and the passband of the amplifier 11 is lowered to reduce amplifier noise, and the time n1 in the total shift time T is reduced. By increasing the time of + n2, it is possible to enhance the smear suppression effect due to the extraction. Further, the charge transfer control unit consisting of 2-2 to 2-4 distributes the signal charge distributed and transferred in the first potential well across the plurality of electrodes in the vertical charge transfer means 2 to the final charge transfer means 2 After being collected on the electrode f, it is collectively transferred to the input terminal of the amplifier 11. As a result, the signal charge can be input to the input terminal of the amplifier 11 in a shorter time than the time s required for movement in the first potential well, and a sufficient signal voltage can be obtained even if the pass band of the amplifier 11 is limited. I can do things. The above effect is that the charge transfer control unit is composed of only the gate 2-2, and the high level of the voltage applied to the terminal SB is equal to the applied voltage from vm to the output gate 2-4 in FIG. It can be obtained in the same manner if the value is set to a value, or if the charge transfer control unit is constituted by only the output gate 2-4 and the time when φCP is turned off is before the time t2.

  Furthermore, by configuring the charge transfer control unit with gate 2-2, charge storage gate 2-3, and output gate 2-4, when removing fixed pattern noise due to variations in reset noise and amplifier DC voltage The effect of reducing the passband of the amplifier can be improved. That is, when there is no charge storage gate 2-3 and output gate 2-4 and only gate 2-2 or only output gate 2-4, the first output is used to prevent the mixing of unnecessary charges and unread signal charges. The writing time Ts1 of the storage capacitor 14 must be the same as the time s. On the other hand, for the smear, the time s must be shortened in order to enhance the smear suppression effect by the extraction. As a result, the write time of the amplifier output at the time of resetting the amplifier input terminal to the first holding capacitor 14 is shortened, and the passband of the amplifier at the time of writing must be increased, and the amplifier noise increases. On the other hand, in this embodiment, the charge transfer control unit is configured by the gate 2-2, the charge accumulation gate 2-3, and the output gate 2-4, so that the signal charge transferred by the first potential well can be reduced. After being temporarily held in the charge storage gate 2-3, it is transferred to the amplifier input terminal. As a result, it is not necessary to make the writing time Ts1 of the first output holding capacitor 14 equal to the time s, and Ts1 can be lengthened to reduce amplifier noise.

  In the present embodiment, the first output holding capacitor 14 for holding the first output of the amplifier at the time of resetting the amplifier input terminal is used to remove the fixed pattern noise due to variations in the reset noise and the DC voltage of the amplifier while reducing the amplifier noise. And second output holding capacitors 17-1 and 17-2 for holding a difference value between the first output held in the first output holding capacitor and the second output of the amplifier at the time of signal charge input to the amplifier input terminal, The horizontal scanning circuit 19 that selects and outputs the difference value held in the second output holding capacitor is used. However, the effects described in this embodiment can be implemented regardless of a specific circuit system. That is, another circuit type proposed by the present inventor in Japanese Patent Application Laid-Open No. 6f85471, the amplifier output after the input terminal of the amplifier 11 is reset and the amplifier output when there is signal charge are independent of each other. The same result can be obtained by performing horizontal scanning after holding in the holding capacitor and performing differential processing with a differential provided inside or outside the element. Further, the specific form of the circuit system described above includes various ones such as those described in JP-A 64-39880, JP-A 4-32379, JP-A-5-500891, etc. However, the present invention can be similarly implemented.

  Third, according to the present embodiment, a plurality of separated potential wells carrying a plurality of signal charges are formed in the vertical charge transfer means 2 as in the conventional example of FIG. By providing a plurality of amplifier output holding capacitors 17-1 and 17-2 for each means 2, two rows can be read independently while lowering the passband of the amplifier and reducing amplifier noise.

In the present embodiment, the band limitation described so far is the output resistance of the amplifier 11 and the first output holding capacitor 14 or the output resistance of the amplifier 11 and the first output holding capacitor 14 and the second output holding capacitor 17-1. Although this is done with a series capacitance of 17-2, other methods may be used. That is, by increasing the on-resistance of the clamp switch 15 and the signal write switches 16-1 and 16-2, only the low frequency component of the amplifier output may be passed, or Japanese Patent Laid-Open No. 62-185471. Thus, a charge transfer type low-pass filter proposed by the present inventor may be provided between the amplifier 11 and the first output holding capacitor 14. Furthermore, when fixed pattern noise caused by mixing of charges induced in the channels of the clamp switch 15 and the signal writing switches 16-1 and 16-2 into the signal when each switch is closed becomes a problem, As proposed by the present inventor 224481, a high resistance may be provided in series on the high impedance terminal side of each switch so that channel charge is not mixed into the signal. This high resistance is composed of a MOS transistor or a non-doped polysilicon having a DC voltage applied to the gate. Also, when power consumption becomes a problem because the same number of amplifiers 11 as the number of pixels in the horizontal direction operate in parallel, only the horizontal blanking period is proposed as proposed by the present inventor in Japanese Patent Application Laid-Open No. 1-279681. The amplifier may be operated. At this time, the bias voltage applied to the amplifier 11 is pulsed so that the output during the non-operation period of the amplifier 11 becomes 0 V so that an unnecessary voltage is not applied to the first output holding capacitor. For example, when the amplifier is a known cascode amplifier, the gate voltage of the pMOS cascode MOS on the driver side may be set to vcc. Further, when a large current flows through the ground line or power supply line of the amplifier 11 due to the parallel operation of the amplifier 11 and a pseudo signal such as shading is generated due to a voltage drop, the present inventor disclosed in Japanese Patent Laid-Open No. 1-243462. As proposed, the power line is connected to the substrate for each amplifier, and the ground line is connected to the light shielding film, thereby reducing the resistance of the ground line and the power line. Further, as the driver of the amplifier 11, an element in which the input terminal that does not generate reset noise is depleted, such as the one proposed by the present inventor in Japanese Patent Laid-Open Nos. 63-318874, 2-224480, and 2-224811, is used. Thus, further noise reduction may be achieved.

Fourth, in this embodiment, the power supply voltage of the amplifier can be lowered for the following three reasons, and the power consumption of the amplifier can be reduced. First, a gate 2-2, a charge storage gate 2-3, and an output gate 2-4 connected to the amplifier input terminal are provided, and a transfer electrode immediately before the output gate 2-4 in the vertical charge transfer means 2 is provided. By driving a certain charge storage gate 2-3 with a drive pulse whose low level is negative, the input terminal voltage of the amplifier 11 can be lowered and the power supply voltage of the amplifier 11 can be lowered. That is, the low level of the voltage applied to the charge storage gate 2-3 is a negative voltage voltage that induces a channel layer and an anti-conductive inversion layer under the electrode, so that a low level voltage is applied to the charge storage gate 2-3. The channel voltage at that time can be the lowest voltage that the channel can take. Furthermore, as is well known, by providing the output gate 2-4, (channel voltage when a low level is applied to the transfer electrode immediately before the output gate 2-4) <(channel voltage of the output gate 2-4) Charges can be transferred by satisfying the relationship <(reset voltage value of the input terminal of the amplifier 11). Therefore, the input terminal voltage of the amplifier 11 can be lowered, and the power supply voltage of the amplifier 11 can be lowered. In addition, when the charge transfer control unit described above is configured only by the gate 2-2 whose high level is driven by the same pulse as the output gate 2-4, or in the same manner as the conventional interline CCD, When composed of only the applied output gate 2-4, the drive means consisting of 3 and 4 has a low level drive pulse with a negative voltage that induces the channel layer and the anticonductive inversion layer under the electrode The same effect can be obtained by driving with. Second, since the signal charge is transferred through the potential well formed across the plurality of electrodes of the vertical charge transfer means 2, the channel concentration is lowered and a low level is applied to the transfer electrode immediately before the output gate 2-4. The channel voltage at the time can be lowered, and further voltage reduction is possible. Third, the voltage of the signal charge is further reduced by configuring the conversion of the signal charge into a voltage using a capacitive feedback type charge / voltage converter composed of 11 to 13. That is, the amplifier 11 is composed of a high gain inverting amplifier circuit, and a feedback capacitor 13 is provided between its input and output terminals. Therefore, the input terminal of the amplifier 11 serves as a virtual ground point, and signal charges are input. However, no voltage fluctuation occurs. As a result of the above three points, the power supply voltage of the amplifier 11 can be reduced without adversely affecting the charge transfer, and the power consumption and the voltage of the amplifier can be reduced. Further, the power supply of the amplifier 11 has a positive power supply voltage value, and the number of power supplies is reduced. In addition, since the voltage fluctuation due to the signal charge is at most 1 to 2 V, the amplifier 11 is configured with a source follower circuit as is done with a typical interline CCD image sensor, eliminating the feedback capacitor 13, and the reset switch as a positive power supply Even with an nMOS connected to, the voltage can be lowered by the first and second effects.

  On the other hand, according to the capacitive feedback type amplifier composed of 11 to 13, the charge-voltage conversion coefficient is determined only by the feedback capacitance value regardless of the parasitic capacitance associated with the input terminal of the amplifier 11, and the feedback capacitance can be formed with high accuracy. Thus, fixed pattern noise due to variations in charge-voltage conversion coefficients can be reduced. Further, by configuring the driver and the reset switch whose gates are connected to the amplifier input terminal constituting the amplifier 11 with the PMOS having the opposite polarity to the signal charge, as described in JP-A-63-294182, The dynamic range can be improved.

  In this embodiment, the smear differential described in FIG. 14 is not performed for the sake of simplicity. Of course, another separate potential well for smear differential is formed in the vertical charge transfer means 2, and a third second output means for holding smear charge is provided for each vertical charge transfer means 2. Thus, after the pseudo signal such as smear in the vertical charge transfer means 2 and the signal mixed with the pseudo signal are output independently for each horizontal scanning period, the true signal is detected by differential processing of the two signals, and the smear is detected. Differential operation can be performed to further reduce smear. Further, a differential means such as a clamp circuit already proposed by the present inventor in Japanese Patent Laid-Open No. 62-185471 may be provided for each amplifier 11, and the true signal after differential processing may be horizontally scanned. Furthermore, when an increase in random noise accompanying smear differential becomes a problem, the number of stages ms in which the potential well for transferring smear charges is formed is changed to the number m1 of stages in which the potential well for transferring signal charges is formed, By making it larger than m 2, it is possible to prevent an increase in random noise due to smear differential by increasing the amount of smear charge when taking out only the smear signal from the amount of smear charge mixed in the signal.

In this embodiment, in order to simplify the drive signal generation, the two-phase shift pulse of the timing generating means 3 applied to the terminals T1 and T2 and the two-phase shift of the horizontal scanning circuit 19 applied to the terminals H1 and H2. The pulse was a synchronized pulse of the same frequency. However, the drive means consisting of 3 and 4 drives the electrodes of the vertical charge transfer means parallel to one horizontal line, and has a larger load capacity than the horizontal scanning circuit. As a result, when problems such as deterioration of the charge transfer efficiency of the vertical charge transfer means 2 occur, the two-phase shift pulse of the timing generation means 3 may be set lower than the frequency of the two-phase shift pulse of the horizontal scanning circuit 19. . At this time, if there is no overlap between φT1, φT2 and φH1, φH2 shown in FIG. 2, the pass band of the amplifier 11 is less than the band of the video signal output sequentially output to the terminals O1, O2. There is no problem even if the two-phase shift pulse of the generating means 3 is less than the video signal band.

  The overall configuration of the present invention has been described above in accordance with the embodiment of FIG. 1, but the present invention can be modified as follows.

  Driving means for sequentially supplying a driving pulse for vertical charge transfer to a driving pulse line connecting one horizontal parallel electrode of the vertical charge transferring means; and a signal charge of the photoelectric conversion element for a signal charge of the photoelectric conversion element Row selection means for supplying a transfer pulse for transferring to the vertical charge transfer means one by one to a transfer pulse line provided for each parallel of the photoelectric conversion element, and provided for each output terminal of the vertical charge transfer means. Drive means and row selection means by comprising amplifying means having a reset switch connected to the amplifier and an input terminal of the amplifier, and horizontal scanning means comprising a horizontal scanning circuit for selecting and outputting the output of the amplification means Realizing a high-speed drive element such as an ultra-high-definition image sensor is possible by eliminating the speed limitation caused by the rise of the drive pulse of the horizontal scanning means and enabling high-speed drive of all parts of the element. Stage, row selection means, a horizontal scanning means can be implemented regardless of the specific form The underbarrel above features. For example, the conventional driving means and selection means shown in FIG. 14 may be used. Further, the row selection means and the horizontal scanning means may be constituted by a decoder capable of random access. Further, the amplification means in the horizontal scanning means can be modified as described above, and removal of fixed pattern noise due to variations in the DC voltage of the amplifier described in JP-A-62-122372 which does not use a storage capacitor. A circuit may be used. Further, the vertical charge transfer means may not have the charge control unit.

Also, the horizontal scanning means has an output provided to hold the output of the amplifier and an amplifier provided for each output terminal of the vertical charge transfer means, a reset switch which is also used as an uncharged charge gate connected to the input terminal of the amplifier, and the amplifier. By comprising the amplification means having the capacity and the horizontal scanning circuit for selecting and outputting the output held in the output holding capacity, the gate gate 132 and the source drain 133 are eliminated, resulting in high integration and no poor transfer efficiency. Realization of the horizontal scanning means means that the driving means removes unnecessary charges such as a smear charge flowing into the first potential well and the vertical charge transfer means for transferring the signal charge while holding the signal charge in the vertical charge transfer means. If a second potential well is formed at the same time across a plurality of electrodes of the vertical charge transfer means for holding and transferring, and the amplifying means has at least one holding capacitor, the drive Means, row selection means can be performed regardless of the specific configuration and a driving method of the horizontal scanning means. For example, the driving means and the row selection means are the same as in the present invention, but the signal charge is limited to one electrode and the element and row selection means described in JP-A-57-78167 are parallel to each other as in FIG. Are driven by multi-phase external pulses similar to an interline CCD, Japanese Patent Laid-Open Nos. 60-247382, 62-230270, and 63-62480. The device described in JP-A-64-54879 can be implemented. Further, as in FIG. 1, the driving means sequentially supplies the driving pulses, but the selecting means collectively transfers to the vertical charge transfer elements in the same manner as a conventional interline CCD. The device described in Japanese Patent No. 237871 and Japanese Patent Laid-Open No. 4-286282 can also be implemented. Further, the conventional driving means and selection means shown in FIG. 14 may be used. Further, the row selection means and the horizontal scanning means may be constituted by a decoder capable of random access. The amplification means in the horizontal scanning means can be modified in various ways as described above. Further, the present invention can also be implemented when the vertical charge transfer means does not have a charge transfer control unit.

  The overall configuration of the present invention has been described above. In the following, detailed circuit configurations and operations of four embodiments of the driving unit including the timing generating unit 3 and the driving pulse generating unit 4 will be described with reference to FIGS. In addition, the detailed circuit configuration and operation of two embodiments of the row selection means composed of the row selection control means 6 and the transfer pulse generation means 7 will be described with reference to FIG. 7 and FIG. 13 explains the structure of the device used in the above circuit.

(2) Driving means (a) First embodiment of driving means FIG. 3A is a circuit configuration diagram of a first embodiment of driving means comprising timing generating means 3 and driving pulse generating means 4, FIG. (B) is a drive pulse timing chart of the circuit of FIG. In FIG. 1A, reference numeral 21 denotes a conventional two-phase ratioless dynamic shift register that operates with a single positive power source constituting the timing generating means 3.
A solid line in the shift register 21 indicates a single-stage break, and one level is provided for each row in this embodiment. The drive pulse generating means 4 for supplying a drive pulse having a negative voltage at a low level to the drive pulse line is configured by 20, 22 to 29, and the circuit portion in which the broken line is provided for each row of the drive pulse generating means 4 Indicates. 20, 22, 23, and 27 constitute a pre-drive pulse voltage converter that shifts the low level of the timing signal to a negative value, and 20 is provided outside the array and is a terminal of the row selection control means 6 shown in FIG. A scan start pulse voltage converter 20 that shifts the low level of the scan start pulse of a single positive power supply value applied to VIN to a negative value. The scan start pulse voltage converter 20 is, for example, a voltage converter composed of 41 to 43 shown in FIG. 5 and eliminates the buffer nMOS 41 and connects the terminal VIN to the point c serving as the source of the PMOS 42. 22-1 and 22-2 are first and second coupling capacitors for transmitting a timing signal, 233-1 and 23-2 are bias voltage setting switches, and 27 is a low-level voltage of a drive pulse. Negative power line. In addition, a driver for supplying a negative drive pulse to the drive pulse line from 24 to 27 is configured. A first switch 26 for transmitting to the power supply line 25 is a second switch for transmitting the voltage of the power supply line 25 to the drive pulse line 5. 28 is a high breakdown voltage MOS transistor, 29 is a positive power supply line having the same voltage value as a single positive power supply drive signal for driving the shift register 21, and 5 is a drive pulse line. Further, T1, T2, TIN, VIN, VL, VM, Vcc, and GND are the same as those in FIG. Furthermore, φn and φn + 1 indicate the outputs of the n and n + 1 rows of the shift register 21, respectively. On the other hand, in FIG. 3B, vl, vm, and vcc are the same as those in FIG. fc is the shift frequency of the two-phase shift pulse of the shift register 21, tf is the fall time of the drive pulse line voltage, and tr is the fall time of the drive pulse line voltage. The operation will be described below.

When the scanning start pulse of the row selection control means 6 is input to the terminal VIN during the vertical blanking period, the outputs of all stages are reset to the ground voltage. At the same time, the bias voltage setting switches 23-1, 23-2 are turned on by the output pulse from the scanning start pulse voltage converter 20, and the gate terminal voltages of the first and second switches 24, 26 are applied to the terminal VL. The applied negative voltage value vl is set, the first and second switches 24 and 26 are turned off, and the drive pulse line 5 in each row is in a floating state. Next, the switches 23-1 and 23-2 are turned off, and the gate terminal voltages of the first and second switches 24 and 26 are held at the negative voltage value vl. Thereafter, when the first scan start pulse is applied to TIN in a state where the two-phase shift pulse is applied to the terminals T1 and T2, the pulse is shifted at a time interval of the reciprocal of the frequency fc of the two-phase shift pulse. Shift in 21. When this pulse reaches the n-th row and the n-th row output φn of the shift register 21 changes from the ground voltage to the positive voltage vcc, the gate terminal of the first switch 24 becomes a negative voltage via the first coupling capacitor 22-1. The value vl changes in the positive direction, the switch 26 is turned on, and the voltage of the driving pulse line 5 in the n rows falls from vm to the negative voltage value vl applied to the negative power supply line 27. (Fig. 3 (b)
Time t1) Next, after 1/2 fc time, the output φn of the n-th row becomes the ground voltage, the gate terminal voltage of the first switch 24 becomes vl again, the switch 24 is turned off, and the driving pulse line of the n-th row The voltage of 5 is held at the negative voltage value vl. (FIG. 3 (b) time T2) Further, after 1 / fc time, when the (n + 1) th row output φn + 1 changes from the ground voltage to the positive voltage vcc, the second coupling capacitor 22-2 causes the second The gate terminal voltage of the switch 26 changes in the positive direction from the negative voltage value vl, the switch 26 is turned on, and the voltage of the driving pulse line 5 in the n row rises from vl to vm applied to the power supply line 25. (Fig. 3 (b) time t3) When the n + 1-th row φn + 1 becomes the ground voltage after 3/2 * 1 / fc time, the gate terminal voltage of the second switch 26 becomes vl again, and the switch 26 is turned off. In addition, the voltage of the driving pulse line 5 in n rows is held at vm. (FIG. 3B, time t4) This state is maintained until the next scanning start pulse reaches the nth row. The above operation is performed for each scan start pulse, and a desired potential well is formed in the vertical charge transfer means 2. By applying a transfer pulse generated by the operation of the row selection means described later to the drive pulse line 5, the signal is transferred from the photodiode to the potential well formed in this way. The transfer pulse for the n-th line is the first scan start pulse for forming a potential well for transferring the signal for the n-th line when both the first switch 24 and the second switch 26 are in the OFF state. After t3 in FIG. 3B after reaching the n-th row, the second scanning pulse is applied until the time until it reaches the n-th row. At this time, when the transfer pulse is applied to the drive pulse line 5 in FIG. 3A from the left side of the figure, the voltage at the drive pulse output point A of the first switch 24 and the second switch 26 is also transferred from vm. Rises toward the high level voltage value of. However, since the gate terminal voltage of the high breakdown voltage MOS transistor 28 is fixed at vcc, the voltage at the point A does not rise above vcc-vthd. Here, vthd is a threshold voltage of the depletion type nMOS of FIG. Accordingly, the high level of the transfer pulse and the voltage between vl or vm are divided by the high breakdown voltage MOS transistor 28 and the first switch 24 or the second switch and applied between the source and drain of each transistor.

According to the present embodiment, first, when a single positive power supply value driving signal is applied from the timing generation chip to the terminals T1, T2, and TIN, the shift register 21 receives the timing signal in the nth row and the n + 1th row. Φn and φn + 1 are output. From this timing signal and the negative power supply applied to the negative power supply input terminal VL, the drive pulse generating means composed of 20, 22 to 29 sends a drive pulse having a low voltage value of a low level to a low level as a drive pulse line. Supply to 5. As a result, there is no need for a driver that generates a two-phase shift pulse for driving a relatively large pulse line in the shift register 21, and the power consumption of the imaging apparatus can be reduced. The bias setting switches 23-1 and 23-2 can be provided in one field even if a negative pulse is externally applied to the bias setting switches 23-1 and 23-2 without providing the pre-drive pulse voltage converter 20. Since the operation is performed only once, the effect of reducing the power consumption of the imaging apparatus remains unchanged.

  Further, by setting the high level voltage of the drive pulse applied to the terminal VM to the ground voltage as is done in the conventional interline CCD, the number of power sources for operating the drive means can be reduced, and the terminal The VM and the terminal GND can be shared.

In addition, a p-well in which a fine nMOS operating with a single positive power supply is typically formed has a negative value back to reduce the substrate effect factor, secure the threshold voltage of the field parasitic MOS, and reduce the junction capacitance. A bias vbb is applied. The back bias voltage and the low level voltage of the drive pulse applied to the terminal VL are made equal to reduce the number of power sources for operating the drive means, and the terminal VL is connected to a back bias application terminal (not shown). May be common.

By implementing the two power supply reductions described above in this embodiment, all of the drive means can be divided into a drive signal having a single positive voltage value, a positive power supply having a voltage value equal to the drive signal, and one negative power supply. And can be driven.
Secondly, according to this embodiment, the first switch 24 and the second switch 26 are turned on and off based on the outputs φn and φn + 1 of the shift register 21, and the negative voltage applied to the negative power supply line 27 is turned on. Since the drive pulse is generated in the drive pulse line 5 by switching the high level voltage of the drive pulse applied to the power line 25, the drive pulse line 5 has a drive pulse rising period tf and a falling period tr. Floating state is entered in all periods except for. Therefore, if the application time interval of the scan start pulse is set to n times the shift period of the drive pulse and the application time of the transfer pulse is set to a sufficient time equal to or less than this time interval, an increase in power consumption due to the flow of through current or There is no generation of afterimages, and there is an effect that the drive pulse line and the transfer pulse can be made common and the pixel portion can be highly integrated.

  Thirdly, according to the present embodiment, the high voltage MOS transistor 28 whose gate terminal voltage is set to vcc causes the high level voltage vh and negative voltage vl of the transfer pulse between the drive pulse line 5 and the negative power supply line 27 to be increased. The high level voltage vh and voltage vm of the transfer pulse between the drive pulse line 5 and the power supply line 5 are divided by the high breakdown voltage MOS transistor 28 and the first switch 24 or the second switch. Since the voltage is applied between the source and the drain, there is an effect that the drive pulse generating means can be highly reliable. In addition, since the threshold voltage of the transistor 28 is negative and the positive voltage vcc is applied to its gate, the influence of the drive pulse on the drive line 5 can be reduced.

  In this embodiment, one stage of the shift register 21 is provided for each row. However, each stage of the shift register 21 outputs a pulse that is 180 degrees out of phase in synchronization with both of the two-phase shift pulses. The number of elements constituting the shift register 21 may be halved by using the timing register as one stage of the shift register 21 in two rows.

(B) Second embodiment of driving means In a typical interline CCD, a photodiode 1 and a vertical charge transfer means 2 arranged two-dimensionally are formed in a p-well, and a positive voltage is applied to an n substrate. The excess charge of the photodiode is discharged. However, the substrate voltage to which a voltage for overflow is applied varies from chip to chip due to variations in substrate concentration and the like. As a result, when the pMOS is directly formed on the n substrate, the back bias changes from chip to chip. Therefore, there is a problem that a circuit using the pMOS must have a tolerance considering this change. . Since the two-phase ratioless dynamic shift register used in the first embodiment is composed only of an nMOS formed in a well, there is no problem described above. However, since the output φn of n rows is output in synchronization with one of the two-phase shift pulses, in the configuration of the first embodiment, tf and tr of the drive pulse are ½ of the shift register shift period 1 / fc. The amplitude of the drive pulse decreases when fc is high. On the other hand, the pulse width expanders described in Japanese Patent Application Laid-Open Nos. 61-157188 and 61-214871 have a large number of switches required for expansion and are difficult to achieve high integration. In this embodiment, in order to solve the above problems, the timing generation means is turned on by the output of the first shift register, the first switch that connects the positive power supply line and the output, and the first switch Pulse width comprising a second switch that is turned on by the second output of the shift register that is delayed by N times half the shift period (N is an integer of 2 or more) from the first output and connects the ground line and the output It is composed of an expander. FIG. 4A is a circuit configuration diagram of a second embodiment of the driving means comprising the timing generating means 3 and the driving pulse generating means 4, and FIG. 4B is a driving pulse timing diagram of the circuit of FIG. It is. In FIG. 2A, the inside of the broken line shows the circuit for one row of the pulse width expander constituting a part of the timing generating means 3 and the circuit portion provided for each row of the driving pulse generating means 4. In FIG. 4 (a), the timing generation means 3 is composed of 21 to 33. As in FIG. 3 (a), 21 is a pulse width expander composed of 29 to 33, 30, 31 is a switch, and 32 is a bias setting. The switch 33 is a ground wire. Reference numerals 20, 22 to 29 are the same as in FIG. 3A and constitute drive pulse generating means. 5, T1, T2, TIN, VIN, VL, VM, Vcc, and GND are the same as those in FIG. Furthermore, φn, φn + 1, φn + 2, and φn + 3 indicate outputs of the n-row, n + 1-row, n + 2-row, and n + 3-row of the shift register 21, respectively. On the other hand, in FIG. 4B, vl, vm, vcc, fc, tf, tr are the same as those in FIG. Hereinafter, an operation for setting tf and tr of the drive pulse to a shift register shift period of 1/2 fc or more will be described.

  As in the first embodiment, when the scanning start pulse of the row selection control means 6 is input to the terminal VIN within the vertical blanking period, the outputs of all the stages are reset to the ground voltage, and scanning is performed. By the output pulse from the start pulse voltage converter 20, the bias voltage setting switches 23-1, 23-2 are turned on, and the gate terminal voltages of the first and second switches 24, 26 are applied to the negative power line 27. The negative voltage value vl is reset. At the same time, the bias setting switch 32 is turned on by the scanning start pulse of the row selection control means 6 applied to the terminal VIN, and the other terminals B of the coupling capacitors 22-1 and 22-2 are also applied to the ground line 33. Biased to ground voltage. Thereafter, when the output φn in the nth row changes from the ground voltage to vcc, the switch 30 is turned on, and the voltage at the terminal B rises from the ground voltage (time t1 in FIG. 4 (b)). When the output φn + 1 becomes vcc, the switch 31 is turned on and the voltage at the terminal B becomes the ground voltage. (FIG. 4 (b) time T2) The first timing signal having the 1 / fc width generated at the terminal B in this way turns on the switch 24, and the n-th driving pulse line voltage is 1 / fc. Fall from vm to vl in time. Thereafter, similarly, a second timing signal having a width of 1 / fc is generated by the pulse width expander in the (n + 2) th row from φn + 2 and φn + 3 (FIG. 4B). From time t3 to t4) the second switch 26 is turned on, and the driving pulse line voltage of the n-th row rises from vl to vm within 1 / fc.

  According to this embodiment, first, by providing a pulse width expander composed of a two-phase ratioless dynamic shift register 21 and two switches 30 and 31, without using a pMOS as a timing generation means, Further, the rise / fall time of the drive pulse voltage of the drive pulse line can be reduced to 1 / fc without impairing the degree of integration, and sufficient rise / fall characteristics can be obtained even when the shift register is scanned at high speed. Can do.

  Second, according to the present embodiment, a pulse width expander for generating a timing signal for lowering the driving pulse line voltage of the nth row and a timing signal for raising the driving pulse line voltage of the n + 2th row are generated. By sharing the pulse width expander, there is an effect that the number of transistors constituting the pulse width expander can be reduced.

In this embodiment, an example in which the timing signal is expanded to 1 / fc is shown. However, any pulse width that is N times N times the shift cycle of the shift register (N is an integer of 2 or more) is arbitrary. It is sufficient if the width is. In order to obtain a pulse width that is a non-integer multiple of the shift period of the shift register, not only the output synchronized with one of the two-phase shift pulses of the shift register is used, but also the two-phase shift pulses are synchronized. The output can also be used.

  As described above, the two-phase dynamic shift register used for generating the drive pulse of the charge transfer means 2 of FIG. 1 in this embodiment and the first output of the shift register are turned on to connect the positive power supply line and the output. The timing generation means having a pulse width expander comprising a second switch which is turned on by the first switch and the second output of the shift register and connects the ground line and the output can be obtained from the nMOS only by adding two transistors. The two-phase dynamic shift register shift can be used and can be generated with a pulse width that is N times half the shift period (N is an integer of 2 or more).

(C) Third embodiment of the driving means In the first and second embodiments, the low level voltage of the timing signal is made negative by the coupling capacitors 22-1 and 22-2 in the pre-drive pulse voltage converter. A shifted pre-driving pulse is generated, thereby driving the first and second switches 24 and 26. Such a method for generating a pre-driving pulse for shifting a low level voltage due to capacitive coupling to a negative value has the following three problems. First, since the gate terminals of the first and second switches 24 and 26 that control the voltage of the drive pulse line 5 are in a floating state for most of the period, each switch is turned on by noise and is unnecessary for the drive pulse line voltage. It may cause a voltage change. Second, the voltage amplitude of the gate terminals of the first and second switches 24 and 26 is equal to or less than the voltage amplitude vcc of the pre-driving pulse, and the driving capability of the driving pulse lines of the first and second switches 24 and 26 is high. Low. Third, a low level pulse must be applied to the bias voltage setting switches 23-1, 23-2, and the low level of the scan start pulse of the single positive power supply value drive signal is set to a negative value. A scan start pulse voltage converter 20 for shifting is required. In the present embodiment, a PMOS transistor having a negative threshold voltage value for inputting a positive voltage output pulse of a timing generation means to a source of a pre-driving pulse voltage converter, a drain of the PMOS as a drain, and the negative power supply line as described above. By constructing an nMOS transistor that is always on as a source, the above problems are solved. FIG. 5 is a circuit configuration diagram of a third embodiment of driving means comprising timing generating means 3 and driving pulse generating means 4. In FIG. FIG. 5 shows a circuit for one row of the pulse width expander and the drive pulse generating means 4 forming part of the timing generating means 3 within the broken line. In the figure, numerals 21, 29 to 31, 33 form the timing generating means in the same manner as in FIG. 41 to 43 and 24 to 28 form drive pulse generating means, 41 to 43 form a pre-drive pulse voltage converter, 41 is a buffer nMOS transistor for holding the output of the pulse width expander, and 42 is a PMOS The transistor 43 is an nMOS transistor which has a negative threshold voltage value vthd and is always turned on, and 24 to 28 are the same as those in FIG. 5, T1, T2, TIN, VIN, VL, VM, Vcc, GND, φn, φn + 1, φn + 2, and φn + 3 are the same as those in FIG. Hereinafter, an operation for generating a pre-driving pulse in which the low level voltage is shifted to a negative value in the present embodiment will be described. In this embodiment, since the gate of the PMOS 42 is grounded and the threshold voltage of the PMOS is negative, the PMOS 42 is always turned off when the output of the pulse width expander that generates the timing signal is the ground voltage. That is, when the output of the pulse width expander is at the ground voltage, the buffer nMOS 41 is turned off, and the point C at which the positive voltage becomes the source of the PMOS 42 does not become the positive voltage at which the PMOS is turned on. Therefore, when the output of the pulse width expander is the ground voltage, the negative voltage value of the negative power supply line 27 is applied to the gate terminal of the first switch 24 through the nMOS 43 that is always on with the negative power supply line 27 as the source. Is done. On the other hand, when the output of the pulse width expander becomes a positive voltage, the buffer nMOS 41 is first turned on, and a voltage lower than the output of the pulse width expander by the threshold voltage of the buffer nMOS 41 is applied to the C point voltage. As a result, the PMOS 42 is turned on, and the gate terminal of the first switch 24 becomes a positive voltage. Thereafter, when the output of the pulse width expander becomes the ground voltage again, the buffer nMOS 41 is turned off, and the gate terminal of the first switch 24 becomes the negative voltage value applied to the negative power supply line 27 by the nMOS 43 in the on state. . As described above, the pre-driving pulse in which the low level of the timing signal is shifted to a negative value is generated.

  According to the present embodiment, when the pre-driving pulse voltage converter is composed of the pulse voltage converters 41 to 43, the pre-driving pulse in which the low level of the pulse timing signal is shifted to the negative value is generated. In addition, the gate terminals of the first and second switches 24 and 26 that control the voltage of the drive pulse line 5 are not in a floating state, and an unnecessary voltage change does not occur in the drive pulse line voltage. The voltage amplitude of the gate terminals of the first and second switches 24 and 26 is about vcc-vl-2vth, which can be made equal to or higher than the voltage amplitude vcc of the timing signal. Further, the scan start pulse voltage converter 20 for shifting the low level of the scan start pulse to a negative value is not necessary. When pulse width expansion is not performed, the switches 30 and 31 and the buffer nMOS 41 may be eliminated, and the output φn of the shift register 21 may be directly input to the source of the PMOS 42.

  In this embodiment, the drive pulse line is driven by the first and second switches. However, the above-described effects of the present invention can be obtained regardless of the specific circuit configuration for driving the drive pulse line. For example, the driving pulse line may be driven by an inverting circuit similar to the conventional example.

(D) Fourth Embodiment of Driving Means In the third embodiment, the gate terminal of the first or second switch 24, 26 is discharged by the value of the current flowing through the nMOS 43, and the first or second switch is turned off. . In order to increase the speed of this discharge, it is necessary to increase the value of the current flowing through the nMOS 43. The output of the pulse width expander becomes a positive voltage, and the PMOS 42 is turned on between the positive voltage line 29 and the negative power line 27 Has a problem that the through current cannot be reduced. This embodiment solves this problem by applying a positive voltage to the gate terminal of an nMOS transistor whose source is a negative power supply line at the same time that the output of the pulse width expander becomes the ground voltage and the PMOS is turned off. is there. FIG. 6 is a circuit configuration diagram of a fourth embodiment of driving means comprising timing generating means 3 and driving pulse generating means 4. In FIG. 6, the inside of the broken line shows a circuit for one row of the pulse width expander and the driving pulse generating means 4 forming part of the timing generating means 3 within the broken line. In FIG. 6, 51 is an nMOS transistor to which a positive voltage is applied by the gate terminal simultaneously with turning off the buffer nMOS 41, and the same output pulse of the shift register 21 as that of the switch 31 is applied to the gate. 5, 21, 24 to 31, 33, 41, 42, T1, T2, TIN, VL, VM, Vcc, GND, φn, φn + 1, φn + 2, and φn + 3 are the same as those in FIG. Hereinafter, an operation in which the discharge of the gate terminal of the first switch 24 in the nth row occurs and the first switch 24 is turned off will be described as an example.

  When the shift register 21 outputs the output pulse φn + 1, the switch 31 is turned on, the output of the pulse width expander becomes the ground voltage, the buffer nMOS 41 is turned off, and the PMOS 42 is turned off. At the same time, the gate of the nMOS transistor 51 becomes the positive voltage vcc, and the gate terminal of the first switch 24 is rapidly discharged to the negative voltage value applied to the negative power supply line 27. This large discharge current flows only during a 1/2 fc period in which the output φn + 1 is vcc, and in the other period, the gate terminal of the nMOS 51 is at the ground voltage. Therefore, the through current when the current path between the gate terminal of the first switch 24 and the positive voltage line 29 is turned on can be reduced. When pulse width expansion is not performed, the switches 30 and 31 and the buffer nMOS 41 may be eliminated, and the output φn of the shift register 21 may be directly input to the source of the PMOS 42.

  According to the present embodiment, since the negative power supply line of the pre-drive pulse voltage converter is used as a source, a positive voltage is applied to the gate of the nMOS transistor 51 which is always on at the same time as the PMOS 42 is turned off. When the discharge speed is fast and the PMOS 42 is turned on, the gate voltage of the nMOS 51 is the ground voltage, so that the through current can be reduced between the positive voltage line 29 and the negative power supply line 27.

  As described above in the third and fourth embodiments, the pulse input unit having the low level of the ground voltage and the high level of the positive voltage constituting the pre-driving pulse voltage converter described above is a source, and the ground line is a negative. A pulse voltage converter comprising: a PMOS transistor having a threshold voltage value of: There is no terminal, there is no need for a negative pulse to reset the terminal, and the pulse amplitude after voltage conversion is large, and the low level is the ground voltage and the high level is positive. It can be widely used when converting a low level of a pulse having a voltage into a negative value.

  As described above, the case where the four embodiments of the driving means of the present invention are applied to the element having the overall configuration and the driving system described in FIG. 1 has been described, but the scope of the present invention is limited to the element of FIG. The following modifications are possible.

  Timing generating means having a shift register whose driving means operates with a single positive power source, and a driving pulse having a negative power source for supplying a driving pulse having a negative voltage at a low level to the driving pulse line based on the timing signal By providing the generating means, the driver that generates the two-phase shift pulse that drives the relatively large pulse line in the shift register is eliminated, and the power consumption of the imaging device is reduced. As long as the driving pulses are sequentially supplied to the driving pulse lines connecting the horizontal rows, the driving method of the driving means, the selecting means, and the specific configuration operation of the horizontal scanning means can be implemented. For example, the horizontal scanning means is composed of a charge transfer element as in FIG. 14, and has both a driving means for sequentially supplying driving pulses and a row selection means as in FIG. Examples include those that carry only one signal in one horizontal scanning period described in Japanese Patent No. 58-188156, and those in which signal charges described in Japanese Patent Application Laid-Open No. 57-78167 are limited to one electrode. Further, the device described in Japanese Patent Laid-Open No. 62-237871 in which the row selection means collectively transfers data to the vertical charge transfer device as in the case of a conventional interline CCD can be implemented.

  It is possible to provide a high-reliability driving means without applying a high voltage to the output part of the driving means by providing a high voltage MOS transistor whose gate is connected to a DC voltage between the driving means and the driving pulse line. As long as the driving pulse line 128 and the transfer pulse line 131 are common elements, the driving pulse line 128 and the transfer pulse line 131 can be implemented regardless of the specific configuration of the driving means, row selection means, and horizontal scanning means. For example, the horizontal scanning means is composed of charge transfer elements as in FIG. 14, and the row selection means selects one parallel line as in FIG. 1, but the driving is a multiphase type similar to the interline CCD. The present invention can be applied to the elements described in JP-A-57-207486, JP-A-58-107670, JP-A-63-62480, and JP-A-64-54879 performed by an external pulse. Further, as in FIG. 1, the driving means sequentially supplies the driving pulses, but the selecting means collectively transfers to the vertical charge transfer elements as in the case of a conventional interline CCD. The device described in Japanese Patent No. 237871 and Japanese Patent Laid-Open No. 4-286282 can also be implemented.

(3) Row selection means (a) First embodiment of row selection means FIG. 7A shows a circuit configuration of a first embodiment of row selection means comprising row selection control means 6 and transfer pulse generation means 7. FIG. 4B is a drive pulse timing chart of the circuit of FIG. In FIG. 2A, the inside of the broken line shows a circuit for one row of an interlace circuit forming a part of the row selection control means 6 and a circuit portion provided for each row of the transfer pulse generating means 7. In the figure, 61 to 65 constitute row selection control means 6 that operates with a single positive power source. 61 is a two-phase ratioless dynamic shift register similar to the conventional one. The solid line in the shift register 61 indicates one stage of separation, and one stage is provided for every two rows. Reference numerals 62 to 65 denote switches constituting an interlace circuit similar to the conventional one. In addition, a drive pulse line 5 that shares a transfer pulse having a second voltage value higher than the voltage value of the positive power supply applied to the transfer pulse application line 75 by 60, 66 to 73 with the transfer pulse line. The transfer pulse generating means for outputting to is configured. Among them, the third voltage value vhm higher than the voltage value vcc of the positive power supply applied to the terminal V3L or V4L based on the control signal by 60, 66 to 68 is lower than the second voltage value vh. A fourth voltage value vcc-vthd that is higher than the positive power supply voltage value vcc and lower than the third voltage value vhm is set to a high level from the pre-transfer pulse, and the selected row in the period when the transfer pulse is not applied A pre-transfer pulse voltage converter is configured to generate a low level negative voltage pulse in the selected row. Reference numeral 60 denotes a pre-transfer pulse negative voltage converter for shifting the low level of the pre-transfer pulse applied to the V3L or V4L terminal provided outside the array to a negative value. For example, 41 for one row shown in FIG. The buffer nMOS 41 is eliminated by a voltage converter consisting of the following terminals 43 and the terminal V3L or V4L is connected to the point c serving as the source of the PMOS 42. 66 to 68 are circuit portions provided for each row of the pre-transfer pulse voltage converter, 66 is a bootstrap capacitor of the pre-transfer pulse switch, 67 is a pre-transfer pulse switch MOS, and 68 is a bootstrap MOS. It is. 69 is a transfer pulse switch MOS, 70 is a bootstrap capacity of the transfer pulse switch MOS, 71 to 73 are for improving the withstand voltage of the transfer pulse switch MOS, 71 is a transfer pulse switch MOS high withstand voltage MOS, 72 is a high voltage A bootstrap capacitor 73 of the withstand voltage MOS 71, and a bootstrap MOS 73 of the withstand voltage MOS 71. 74 is a pre-transfer pulse application line, and 75 is a transfer pulse application line. 5 and 29 are the same as in FIG. V1, V2, VIN, FA, FB, V3L, V4L, V3, V4, GND, VL, and Vcc are the same as in FIG. This is the gate terminal of the MOS 71. In FIG. 7B, vm, vl, vcc, vh, and vhm are the same as those in FIG. 11 constituting the MOS 68 for the depletion type, and vthe is the threshold voltage of the enhancement type nMOS shown in FIG. 11 constituting the bootstrap MOS 73. The threshold voltage of the transistors is vthd, and the threshold voltages of the transistors 62 to 65, 67, 73, and 69 are all vthe. In addition, although every other row is connected to two transfer pulse lines 75 and a pre-transfer pulse line 74, only the details of the circuits of n rows are shown here for the sake of simplicity. Example line Take the operation of this embodiment will be described.

As in the prior art, the selected row is specified by an interlace circuit comprising the shift register 61 and the switches 62 to 65, and the gate terminal of the pre-transfer pulse switch MOS 67 in the selected row becomes the voltage of vcc-vthe. Further, since all the outputs of the shift registers 61 in the non-selected rows are at the ground voltage, all the gate terminals of the pre-transfer pulse switch MOS67 are at the ground voltage. Since the low level of the pre-transfer pulse applied to the terminal V3L is shifted to a negative value by the pre-transfer pulse negative voltage converter 60 and applied to the pre-transfer pulse application line 74, all the pre-transfers are transferred. All the pulse switches MOS67 are turned on, and the voltage at the gate terminal A of the transfer pulse switch 69 has the same negative voltage value vl as the low level of the drive pulse. Accordingly, even if a negative low level voltage vl is applied to the drive pulse line 5 from the drive means, not all the transfer pulse switches MOS are turned on. (FIG. 7 (b) time t1) Next, the applied voltage of the pre-transfer pulse applied to the terminal V3L is higher than the positive power supply voltage value vcc from 0 to the third voltage value vhm from the second voltage value vh. Then, the pre-transfer pulse application line 74, which is the output of the pre-transfer pulse negative value voltage converter 60, also becomes vhm. At this time, since the switch 63 of the interlace circuit is off in the selected row, the gate terminal of the pre-transfer pulse switch MOS 67 is boosted to vhm or more by the first bootstrap capacitor 66, and the pre-transfer pulse switch The source terminal of the MOS 67 rises to vhm. The voltage value of vhm is set higher than the potential vcc-vthd (vthd is a negative value) below the bootstrap MOS 68 to which the positive voltage vcc is applied. Becomes the fourth voltage value vcc-vthd, and the transfer pulse switch MOS69 in the selected row is turned on. On the other hand, even in the non-selected row, the source terminal of the pre-transfer pulse switch MOS67 rises. However, since it is connected to the ground voltage of the pre-transfer pulse switch MOS67, the first bootstrap capacitor 66 does not boost the gate terminal of the pre-transfer pulse switch MOS67. As a result, the source terminal of the pre-transfer pulse switch MOS67 only rises to -vthe, and the voltage at the gate terminal A of the transfer pal switch 69 becomes this voltage value. Since the sum 2vthe of the threshold voltage of the transfer pulse switch MOS69 and the threshold voltage of the pretransfer pulse switch MOS67 is set to be larger than the absolute value of the low level voltage value vl of the drive pulse, the drive means supplies the drive pulse line 5. Even in the row to which the low level voltage value vl is applied, the transfer pulse switch MOS is not opened. (FIG. 7 (b), time t2) Further, the voltage applied to the terminals V3 and V4 changes from vm to vh.
At this time, since the transfer pulse switch MOS 69 is turned on and the bootstrap MOS 68 is turned off in the selected row, the voltage of the gate terminal A of the transfer pulse switch MOS 67 reaches a voltage vh ′ higher than vh by the bootstrap capacitor 70. The voltage of the drive pulse line 5 is increased to vh by being boosted. At this time, since the bootstrap MOS 73 of the high breakdown voltage MOS is turned off, the gate terminal B of the high breakdown voltage MOS 71 is also boosted from vcc-vthe to vh ″ by the bootstrap capacitor 72, and the voltage of the drive pulse line 5 is increased. On the other hand, in the non-selected row, since the transfer pulse switch MOS 69 is turned off, the voltage of the drive pulse line 5 does not change even if the voltage of the transfer pulse application line 75 changes from vm to vh. However, the voltage at the terminal C becomes vcc-vthe-vthd, and the high level vh of the transfer pulse applied to the transfer pulse application line 75 and the drive pulse vl or vm applied to the drive pulse line 5 are not affected. The voltage between them is divided by the high breakdown voltage MOS transistor 71 and the transfer pulse switch MOS 24 and applied between the source and drain of each transistor (FIG. 7B). (Time t3) Next, when the applied voltage at the terminal V3 changes from vh to vm, the voltage of the drive pulse line 5 becomes vm in the selected row, and the voltages at the terminals A and B that have risen due to the capacitive coupling are also at the time t2. Finally, when the voltage applied to the terminal V3L becomes 0, the voltage of the pre-driving pulse application line 74 becomes vl, and the voltage of the terminal a of the selected row and the non-selected row is changed to v1. The voltage and the source terminal of the pre-transfer pulse switch MOS67 all become vl, and the gate terminal of the pre-transfer pulse switch MOS67 also returns to the voltage at time t1 (FIG. 7 (b) time t5). This is performed when the first and second switches 24 and 26 of the selection means in the selected row are turned off and the drive pulse line 5 is vm.

  According to the present embodiment, first, when a positive single power source drive signal is applied from the timing generation chip to the terminals V1, V2, VIN, FA, and FB, an interlace circuit composed of shift registers 61 and 62 to 65 is used. The row selection control means configured generates a control signal for specifying the selected row, and the transfer pulse generation means consisting of 66 to 73 is applied to the transfer pulse application line 75 based on this control signal. A transfer pulse having a second voltage value vh higher than the first voltage value vcc at a high level is output to the drive pulse line 5 of the selected row. As a result, the transfer pulse switch MOS 69 directly connected to the transfer pulse application line 75 and the drive pulse line 5 and its high breakdown voltage MOS 71 and its gate terminals A Since only the connected bootstrap MOS 73 and bootstrap MOS 68 can be used, the row selection means can be highly integrated, and the drive pulses for the row selection means excluding the transfer pulses V3, V4, V3L, and V4L can be used. A driver chip for generation is unnecessary, and the device can be miniaturized. The above effect can be obtained regardless of the specific configuration of the row selection control means. For example, when performing random access, a decoder may be used instead of the shift register 61.

  Further, the pre-transfer pulse voltage converter composed of 66 to 68 generates a third voltage value hm which is higher than the positive power supply voltage value vcc applied to the pre-transfer pulse line 74 and lower than the second voltage value vh. A pre-transfer pulse having a high level is output to the selected row, and the voltage at the gate terminal A of the transfer pulse switch MOS 69 is higher than the positive power supply voltage value vcc and lower than the third voltage value vhm. After that, the voltage of the gate terminal A of the transfer pulse switch MOS 69 is boosted by the bootstrap capacitor 70 by applying the transfer pulse. Due to the configuration of this transfer pulse generating means, a transfer pulse having a voltage more than three times the positive power supply voltage vcc, which could not be output by the conventional one-stage bootstrap, is less than the positive power supply voltage value vcc. It is possible to output the selected control signal as a trigger to the selected line. Note that the number of bootstrap stages may be three or more if necessary. Further, in this configuration, since the circuit is configured only by the nMOS, it is possible to output a transfer pulse higher than the substrate voltage to the selected row.

Secondly, according to the present embodiment, when a positive single power source drive signal is applied from the timing generation chip to the terminals V1, V2, VIN, FA, and FB, an interlace circuit composed of shift registers 61 and 62 to 65 is used. The constituted row selection control means generates a control signal for specifying the selected row. Based on this control signal, the pre-transfer pulse voltage converter consisting of 60, 66 to 68 generates a negative voltage in the selected row and the non-selected row during the period when the transfer pulse is not applied, and causes the drive pulse line 5 to This is applied to the gate terminal A of the transfer pulse switch MOS transistor 69 as a source. As a result, even if the drive pulse line 128 and the transfer pulse line 131 are made common, the drive pulse of the row selection means having a negative low level is only the pre-transfer pulse, and the applied voltage can be reduced by setting the low level to a negative value. Only the pre-transfer pulse switch 67 and the transfer pulse switch 69 can increase the amplitude, so that the row selection means can be highly integrated.

  By using the high level voltage vm of the drive pulse as the ground voltage, the low voltage of the transfer pulse applied to the terminal V3 or V4 can be the ground voltage, and the number of power sources for operating the selection means can be reduced.

  Further, the row selection is generally performed by setting the negative back bias back bias voltage vbb applied to the p-well in which the fine nMOS is formed and the low level voltage vl of the drive pulse applied to the terminal VL to the same value. The number of power supplies for operating the means may be reduced, and the terminal VL may be shared with the application terminal (not shown) for the back bias voltage vbb.

  By implementing the two power supply reductions described above in this embodiment, all of the row selection means can be driven by a drive signal having a single positive voltage value, a low level is a ground voltage, and a high level is a single level. It can be driven by a pre-transfer pulse having a positive voltage value higher than the positive voltage value, a transfer pulse, a positive power source having a voltage value equal to the drive signal, and one negative power source.

  Third, since the high breakdown voltage MOS 71 is provided in this embodiment, the high level voltage vh and negative voltage of the transfer pulse between the drive pulse line 5 and the transfer pulse application line 75 generated in the non-selected row when the transfer pulse is applied. The voltage vl or the high level voltage vh and the voltage vm of the transfer pulse is divided by the high voltage MOS transistor 71 and the transfer switch 69, and the source-drain voltage of each transistor can be lowered. Increase reliability. In addition, since the threshold voltage of the high breakdown voltage MOS 71 is negative, the bootstrap capacitor 72 is provided, and the gate terminal B of the high breakdown voltage MOS 71 is boosted by the transfer pulse, the transfer pulse to the driving line 5 The impact can be reduced. Further, by providing the bootstrap capacitor 72 and the bootstrap MOS 73, the voltage between the gate terminal B of the high breakdown voltage MOS 71 and the transfer pulse applying line 75 at the time of applying the transfer pulse in the non-selected row is set to vh− (vcc−vthe). Therefore, the breakdown or deterioration phenomenon of the gate oxide film of the high breakdown voltage MOS 71 can be prevented, and high reliability can be achieved.

(B) Second embodiment of row selection means In the first embodiment, the voltage of the gate terminal A of the transfer pulse switch 69 rises above the vl voltage when the pre-transfer pulse is applied even in the non-selected row. In order to prevent the transfer pulse switch MOS69 from opening in the row where the low level voltage value vl is applied from the drive means to the drive pulse line, the threshold voltage of the transfer pulse switch MOS69 and the threshold of the pretransfer pulse switch MOS67 It was necessary to set the sum of voltages larger than the absolute value of the low level voltage value vl of the drive pulse. Further, at this time, since the pre-transfer pulse switch MOS operates in saturation, a charge pumping phenomenon occurs due to the bootstrap capacitor 70, and when the drive pulse changes from vl to vm, the terminal a shifts in the positive direction and the transfer pulse switch The problem of opening the MOS also occurred. In addition, there is also a problem that the pre-transfer pulse negative value voltage converter 60 is required in order to eliminate a driver chip that supplies a drive pulse whose negative value is low level to the row selection means. In the second embodiment, in order to solve these problems, a positive threshold voltage having a pre-transfer pulse voltage converter with the output pulse input section of the row selection means as the gate and the drain as the pre-transfer pulse input section. NMOS transistor for pulse input having a value, a PMOS transistor having a negative threshold voltage value using the ground line as a gate and the source of the pulse input nMOS as a source, and the above-described negative value using a drain of a PMOS serving as an output as a drain The pulse voltage converter is composed of an nMOS transistor that is always on with a power supply as a source. FIG. 8 (a) is a circuit configuration diagram of a second embodiment of the row selection means comprising the row selection control means 6 and the transfer pulse generation means 7, and FIG. 8 (b) is a drive pulse for the circuit of FIG. 8 (a). It is a timing diagram. In FIG. 8A, an interlace circuit forming part of the row selection control means 6 and a circuit for one row of the transfer pulse generation means 7 are shown within the broken line. In FIG. 2A, the broken line indicates a part of the transfer pulse generation means 7 and the row selection control means 6 for one row. The positive power supply voltage from the pre-transfer pulse having a third voltage value vhm higher than the positive power supply voltage value vcc and lower than the second voltage value vh at 66, 76 to 78 in FIG. A fourth voltage value vcc-vthd that is higher than the value vcc and lower than the third voltage value vhm is at a high level, and before a negative voltage is generated in a selected row and a non-selected row in a period in which no transfer pulse is applied. A pre-transfer pulse voltage converter for generating a pre-transfer pulse in a selected row is constructed, 76 is a pulse input nMOS transistor having a positive threshold voltage vthe, 77 is a PMOS transistor, and 78 is a negative threshold voltage value vthd. Is an nMOS transistor. 61 to 66, 69 to 75, 5, 29, V1, V2, VIN, FA, FB, V3L, V4L, V3, V4, Vcc, VL, GND, A, B are the same as in FIG. 7A. 27 is the same as FIG. 3 (a). In FIG. 8B, vh, vm, vcc, vhm, vh ′, vh ″, vthd, and vthe are the same as those in FIG. 7B. The solid line in the shift register 61 is delimited by one stage. In addition, one row is provided for every two rows, and the wiring of the switches constituting the interlace circuit is different between the n-th row and the n + 1-th row, and there are two transfer pulse lines 75 and a pre-transfer pulse. Although every other row is connected to the line 74, only the details of the n-row circuit are shown here for the sake of simplicity, and the operation of this embodiment will be described below taking n rows as an example.

In this embodiment, in the non-selected rows, all the gate terminals of the pre-transfer pulse switch MOS76 are at the ground voltage, and the voltage at the terminal V3L is a positive voltage, so the pulse input MOS76 and the PMOS77 are off. Therefore, in all periods, the negative voltage value vl is applied to the voltage at the gate terminal A of the transfer pulse switch MOS 69 of the non-selected row via the nMOS 78 that is always on with the negative power supply line 27 as the source. As a result, even when a negative low level voltage vl is applied to the drive pulse line 5 from the drive means, the transfer pulse switch MOS in the non-selected row is not turned on. On the other hand, in the selected row, first, the gate terminal of the pre-transfer pulse switch MOS76 becomes a voltage of vcc-vthe, and the nMOS 76 is turned on. However, since the voltage at the terminal V3L is 0v, the PMOS 77 is not turned on and the nMOS 78 is open, so the voltage at the gate terminal A of the transfer pulse switch MOS 69 remains at the vl voltage. (FIG. 8 (b) time t1) Next, the voltage applied to the terminal V3L changes from the ground voltage to the third voltage value vhm which is higher than the positive power supply voltage value vcc and lower than the second voltage value vh. Since the nMOS 76 is turned on, the PMOS 77 is also turned on, and the drain terminal of the nMOS 78 rises from the vl voltage to the positive voltage. At this time, since the switch 63 of the interlace circuit is turned off in the selected row, the gate terminal of the pre-transfer pulse switch MOS 67 is boosted to vhm or more by the first bootstrap capacitor 66, and the drain terminal of the nMOS 83 is A positive voltage value determined by the resistance between the drain terminal and the pre-transfer pulse application line 74 and between the negative power supply line 27 is obtained. Since this voltage value is set higher than the potential vcc-vthd under the bootstrap MOS 68 to which the positive voltage vcc is applied, the bootstrap MOS 68 is turned off and the voltage at the gate terminal A of the transfer pulse switch 69 becomes vcc-vthd. Thus, the transfer pulse switch MOS69 is turned on. (FIG. 8 (b) time t2) Further, when the applied voltage at the terminal V3 changes from vm to vh, the voltage of the drive pulse line 5 rises to vh as in FIG. (FIG. 7 (b) time t3) Next, when the applied voltage at the terminals V3 and V4 changes from vh to vm, the drive pulse line voltage becomes vm, and the voltages at the terminals a and b that have risen due to capacitive coupling are also: The voltage returns to the voltage at time t2. (FIG. 8 (b) time t4) Finally, when the applied voltage at the terminal V3L becomes 0v, the PMOS 77 is turned off, and the voltage at the gate terminal A of the transfer pulse switch MOS69 is always on with the negative power supply line 27 as the source. It becomes the negative voltage value vl of the negative power supply line 27 via the nMOS 78. (Fig. 8 (b) time t5)
According to this embodiment, the pulse input nMOS transistor having a positive threshold voltage value having the output pulse input portion of the row selection means as the gate and the drain as the input portion of the pre-transfer pulse, and the ground line as the gate, A pulse composed of a PMOS transistor having a negative threshold voltage value with the source of the pulse input nMOS as a source, and an nMOS transistor which is always on with the drain of the PMOS serving as the drain as the drain and the negative power supply as the source. The voltage converter outputs a negative voltage with the same value as the low level of the drive pulse to the gate terminal A of the transfer pulse switch MOS69 in the period when the transfer pulse is not applied in the selected row and in all the periods in the non-selected row To do. As a result, even if the sum of the threshold voltage of the transfer pulse switch MOS 69 and the threshold voltage of the pre-transfer pulse switch MOS 76 is not set larger than the absolute value of the low level voltage value vl of the drive pulse, the low level is set to a negative value. When the drive pulse to be applied is applied to the drive pulse line 5, the transfer pulse switch MOS 69 constituting the output of the row selection means is not turned on. In addition, the pre-transfer pulse negative voltage converter 60 is not necessary.

  In this embodiment, the PMOS 77 is used as the pre-pulse generating means. However, the source / drain diffusion layer of the PMOS 77 has a high level vhm of the pre-transfer pulse applied to V3L and V4L by the action of the bootstrap MOS. The transfer pulse having a voltage value higher than the substrate voltage can be applied to the drive pulse line 5 by setting vhm to the substrate voltage or less.

  The first pulse input section having a low level is the ground voltage and the high level is a positive voltage described in this embodiment, and the second pulse input section having the low level is the ground voltage and the high level is a positive voltage. The output is a pulse input nMOS transistor having a positive threshold voltage value with a drain as the drain, a PMOS transistor having a negative threshold voltage value with the ground line as the gate and the source of the pulse input nMOS as the source, and an output. A pulse voltage converter consisting of an nMOS transistor that is always on with the drain of the PMOS as the drain and the negative power supply as the source, calculates the logical product of the first input pulse having the positive voltage value and the second input pulse. In addition, it has the effect that the low level of the output pulse can be set to a negative value, and can be widely applied.

  As described above, the two examples of the row selection means of the present invention are applied to the element having the overall configuration and the driving method described in FIG. 1, but the scope of the present invention is limited to the element of FIG. The modifications described below are possible.

A row selection control unit that operates with a single positive power source that generates a control signal for specifying a selected row by the selection unit, and a voltage of the positive power source applied to the transfer pulse application line based on the control signal A transfer pulse generating means for outputting a transfer pulse having a second voltage value higher than the value at a high level to the transfer pulse line of the selected row, so that a large voltage in the row selecting means is applied to the transfer pulse. It is possible to achieve high integration of the row selection means 127 by using only the transfer pulse supply path in the generation means, and to reduce the size of the apparatus by eliminating a driver having a high voltage amplitude that generates five pulses excluding the transfer pulse. The row selection means supplies a transfer pulse for transferring the signal charges of the photoelectric conversion elements to the vertical charge transfer means one by one in parallel to the transfer pulse line provided for each horizontal parallel of the photoelectric conversion elements. If you drive It can be carried out regardless of the specific configuration operations of the horizontal scanning means. For example, the horizontal scanning means is composed of a charge transfer element as in FIG. 14, and has both a driving means and a row selection means for sequentially supplying drive pulses as in FIG. Examples include those that carry only one signal in one horizontal scanning period described in Japanese Patent No. 58-188156, and those in which signal charges described in Japanese Patent Application Laid-Open No. 57-78167 are limited to one electrode. Further, the driving is performed by multi-phase external pulses similar to the interline CCD, Japanese Patent Laid-Open Nos. 54-75927, 57-207486, 58-107670, 62-230270. The present invention can be applied to the elements described in JP-A-60-247382, JP-A-63-62480, and JP-A-64-54879. A row selection control means in which the row selection means operates with a ground voltage at a low level, and a pre-transfer pulse voltage conversion having a negative power source for generating a negative value voltage in a selected row and a non-selected row during a period when no transfer pulse is applied. And a transfer pulse generating means having a transfer pulse generating means having a transfer pulse switch MOS transistor having the output part of the pre-transfer pulse voltage converter as a gate and the drive pulse line as a source. Even if the transfer pulse line 131 is shared, only the pre-transfer pulse has a low level as a negative value, and the row selection unit 127 is highly integrated by reducing the high drive voltage amplitude portion. This is an element in which the drive pulse line 128 and the transfer pulse line 131 are used in common, and the row selection means transfers the signal charge of the photoelectric conversion element to the vertical charge transfer means one by one in parallel. As long as it supplies feed pulses to the transfer pulse line provided for each one horizontal row of the photoelectric conversion element, the driving means can be performed regardless of the specific configuration operations of the horizontal scanning means. For example, the horizontal scanning means is composed of a charge transfer element as in FIG. 14, and has both a driving means and a row selection means for sequentially supplying drive pulses as in FIG. Examples include those that carry only one signal in one horizontal scanning period described in Japanese Patent No. 58-188156, and those in which signal charges described in Japanese Patent Application Laid-Open No. 57-78167 are limited to one electrode. Further, driving is performed by external pulses having the same multiphase as in the interline CCD, Japanese Patent Laid-Open Nos. 57-207486, 58-107670, 63-62480, and 64. -54879 can also be applied to the device.

(4) Device structure (a) Transistor In the present invention, as described above, the horizontal scanning means is composed of 11 to 19, and the vertical charge transfer means is driven with a negative value, and the amplifier is a capacitive feedback consisting of 11 to 13 By providing the type amplifier circuit and providing the drive pulse voltage converter 4 and the transfer pulse voltage converter 7, most of the elements operate with a single positive power source. However, as long as the charge transfer means is used for the vertical transfer, it is impossible to eliminate the application portion of the high voltage transfer pulse. In contrast, the high breakdown voltage MOS 28 shown in FIGS. 3 to 5 and the high breakdown voltage MOS 71 shown in FIGS. 7 and 8 divide the applied voltage to reduce the voltage applied between the source and drain, and when the transistor is off. Improve the breakdown voltage between the source and drain. The circuit configuration shown in FIGS. 7 and 8 can output the transfer pulse applied to the V3 and V4 terminals and the pre-transfer pulse applied to the V3L and V4L terminals to the drive pulse line 5 without using a high DC voltage. Lower the high voltage application duty, and substantially lower the voltage applied between the source and drain of the high breakdown voltage MOS 71, transfer pulse switch 69, and high breakdown voltage MOS 28 in the transfer pulse application path, and the transistor is turned on. Circuit measures such as preventing deterioration of transistor characteristics due to hot carriers at the time were made. However, in spite of the above-mentioned circuit design, the following two issues remain.

  First, by making the gate oxide film thickness of the drive pulse generator circuit as described in JP-A-1-103861 thinner than the gate oxide film thickness of the charge transfer element, the drive pulse generator can be made faster. It is difficult to achieve integration. That is, in order to apply a high transfer pulse to the vertical charge transfer means 2 and to realize no afterimage reading, the transfer pulse generation means 7 and the drive pulse generation means 4 apply a transfer pulse having a high voltage value and a pre-transfer pulse application. A portion where the voltage between the gate and source of the transistor or the voltage between the gate and drain is high remains in the path. As a result, if the transfer means consisting of 3 and 4 and the row selection means consisting of 6 and 7 shown in FIG. Arise. Therefore, the gate oxide film cannot be thinned. Therefore, in the present invention, the transfer switch MOS 69, the bootstrap MOS 73, the high-resistance MOS 71, the bootstrap MOS 68, and the boot strap MOS 68 shown in FIGS. 7 and 8 constituting the transfer pulse generating means 7 having a high gate-source voltage or gate-drain voltage. 7, the forward transfer pulse switch 67 of FIG. 7 or the pulse input nMOS 76 of FIG. 8, the nMOS 78 of FIG. 8, and the high-resistance MOS 28 of FIGS. 3 to 6 constituting the drive pulse generating means 4, the first and second The gate oxide film thickness of the switches 24 and 26 and the nMOS 51 of FIG. 6 is made equal to the gate oxide film thickness of the vertical charge transfer means 2, and the gate oxide film thicknesses of the other MOS transistors are reduced.

  Secondly, as described in JP-A-61-234670, the driving means and the row selection means have a second concentration higher than that of the first impurity layer in which the photoelectric conversion element 1 and the vertical charge transfer means 2 are formed. The following problems occur when forming the impurity layer. That is, in order to highly integrate the driving means and the row selection means, it is necessary to increase the surface concentration of the second impurity layer so that punch-through does not occur even if the length of the gate electrode is shortened. As a result, firstly, the substrate bias effect of the transfer pulse switch 69 and the high breakdown voltage MOS 71 of FIGS. 7 and 7 becomes large, and in order to pass the transfer pulse, the gate terminals A to B are set to the high level voltage vh of the transfer pulse. The voltage must be boosted to vh ′ and vh ″ that are much higher, and further measures for improving the breakdown voltage are required. Second, the transfer switch MOS 69 in FIG. 7 and FIG. 8 constituting the transfer pulse generating means 7, the MOS transistor 71 for high resistance, the bootstrap MOS 68, the pre-transfer pulse switch 67 in FIG. 7, or the nMOS 76 for pulse input in FIG. 8 and the high-resistance MOS 28 of FIGS. 3 to 6 constituting the drive pulse generating means 4 are short in duty, but a high source / drain voltage is applied when the transistor is turned on, and the characteristics deteriorate due to hot carriers. Occurs. In order to solve this problem, the MOS transistors at the above-described locations are provided in the third impurity layer whose surface concentration is lower than that of other portions of the driving means and the row selection means, thereby reducing the substrate effect and improving the hot carrier breakdown voltage. I planned. Note that the first impurity layer in which the photoelectric conversion element 1 and the vertical charge transfer means 2 are formed has a very low concentration for performing an overflow operation. Although the carrier breakdown voltage can be improved, it is necessary to make the gate electrode length very long in order to prevent the punch-through phenomenon. In order to prevent this, the third impurity layer has a surface concentration higher than that of the first impurity layer, and the gate electrode length can be shortened while realizing a desired substrate effect and withstand voltage. Further, as already proposed by the inventor in Japanese Patent Application No. 5-19531, the third impurity layer is formed shallower in the first impurity layer than in the first impurity layer, and a high voltage is applied to the gate electrode. As a result, the entire region up to the substrate is depleted, and the threshold voltage increase due to the substrate bias effect is further reduced.

  Hereinafter, the structure of the transistor of the present invention will be described with reference to FIGS. 9 is a cross-sectional view taken along the line AA 'of the vertical charge transfer means 2 having the thick gate oxide film and the first p-well with a low concentration in FIG. 1, and FIG. 10 is a transfer pulse generation means 7 and drive pulse in FIG. Cross section of a MOS transistor formed in a third p-well having a thick gate oxide film thickness equal to the gate oxide film thickness of the vertical charge transfer means 2 used for a part of the generating means 4 and having a lower surface concentration than other parts FIG. 11 shows a structure having a thick gate oxide film thickness equal to that of the vertical charge transfer means 2 used for the transfer pulse generation means 7 and the drive pulse generation means 4 in FIG. FIG. 12 is a cross-sectional view of a MOS transistor formed in a third p-well having a lower surface concentration than the portion, and FIG. 12 shows the row selection control means 6, the timing generation means 3, the transfer pulse generation means 7 and the drive pulse generation means 4 of FIG. Used for the rest of the FIG. 5 is a cross-sectional structure diagram of a MOS transistor having a gate oxide film thickness and formed in a high-concentration second impurity layer.

  FIG. 9 is a cross-sectional view of the A-A ′ portion of the vertical charge transfer means 2 shown in FIG. 1 having a thick gate oxide film. The impurity distribution of this structure consists of a punch-through structure that enables the reduction of smear, the saturation, and the dark current proposed by the present inventor in Japanese Patent Laid-Open No. 03-289173. Each electrode has a single-layer electrode structure that the applicant of the present application has already proposed in Japanese Patent Laid-Open No. 03-60158. In FIG. 9, a positive voltage vsub is applied to the grounded first P-well 81 for performing a vertical overflow drain operation on an n-type substrate. 82 is a first P well having a very low concentration to which a ground voltage of 0 v is applied, 83 is a first photodiode n well for reducing the overflow voltage, 84 is a second photodiode n well for element isolation, 85 is an n layer constituting the photodiode, 86 is a photodiode surface p layer for reducing dark current, 87 is a double well p layer for suppressing smear, 88 is an n-type channel layer of the vertical charge transfer means 2, 89 is a gate electrode, 90 is a thick gate oxide film, and vsub is an n-substrate applied voltage. In the interline CCD in which this structure is shown as an example, a high voltage is applied to the gate electrode 89 in order to read the signal from the photodiode n layer 85 to the n-type channel layer 88 of the vertical charge / charge transfer means 2 without image lag. It is necessary to apply. At this time, the gate oxide film 90 cannot be made thin because the voltage between the electrode and the photodiode p layer 90 having the ground potential does not cause destruction of the gate oxide film 90 or deterioration due to carrier injection. In addition, the gate 2-2, the charge storage gate 2-3, and the output gate 2-4 constituting the charge transfer control unit in FIG. 1 have a device structure in which the n layer 85 constituting the photodiode and the photodiode surface p layer 86 are not provided. Have.

  FIG. 12 is a structural diagram of a MOS transistor having a gate oxide film thinner than the vertical charge transfer means 2 that enables high-speed and high-integration, and is formed in a high-concentration second p-well and n-well. In FIG. 12, 111 is a high-concentration second P well in which nMOS is formed, 112 is an nMOS transistor field p layer, 113 is an nMOS transistor source / drain n-type diffusion layer, 114 is an n well in which pMOS is formed, and 115 is The pMOS transistor field n layer, 116 is a pMOS transistor source / drain p-type diffusion layer, 117 is a LOCOS oxide film, and 118 is a thin gate oxide film. 81, 89, and vsub are the same as those in FIG. Further, vbb is a negative back bias applied to the second P well. 12 is driven by a single positive power source, a part of the MOS constituting the amplifier 11 constituting the horizontal scanning means shown in FIG. 1, a clamp switch 15, signal write switches 16-1, 16-2 The signal reading switches 18-1 and 18-2, the horizontal scanning circuit 19, the shift register 21 shown in FIGS. 3 to 6 constituting the timing generating means 3 in FIG. 1, and the pulse expander shown in FIGS. The switches 30 to 32, and the shift register 61 shown in FIGS. 7 and 8 constituting the row selection control means 6 of FIG. The same applies to the buffer nMOS 41 shown in FIG. 5 and FIG. 6 that constitutes the drive pulse voltage converter 3 that is not driven by a single positive power source but the source voltage does not drop below about 0V. 12, the driver of the amplifier 11 constituting the horizontal scanning means shown in FIG. 1, the reset switch 12, the PMOS 42 shown in FIG. 5 and FIG. 6 constituting the drive pulse voltage converter 4 in FIG. 1, and the transfer pulse voltage A PMOS 77 shown in FIG. 8 constituting the converter 3 is configured. In the PMOS 42, the power supply amplitude is vcc-vl (vl; negative), but the source terminal voltage does not rise above vcc-2vth and the gate is grounded. Only a voltage is applied, and a thin gate oxide film is used. In the PMOS 77, when the pre-driving pulse is applied in the selected row, the gate-source voltage becomes vhm and exceeds the positive voltage value vcc, but since the applied duty is 10-4 or less, a thin gate oxide film is used. As already proposed in Japanese Patent Laid-Open No. 5-103272 by the present inventor, the p-type transistor source / drain p-type diffusion layer 116 and the photodiode for reducing dark current are used as the n-well 114 and the second photodiode n-well 84. If the surface p layer 86 is also used, the process steps can be simplified.

  FIG. 10 shows an nMOS transistor formed in a third well having the same thick gate oxide film thickness as that of the vertical charge transfer means 2 and having a lower surface concentration than other portions. In the figure, 81, 82, 88, 89, 90 and vsub are the same as in FIG. 9, and 112, 113 and 117 are the same as in FIG. Reference numeral 91 denotes a third p well layer having a surface concentration higher than that of the second P well 111 but lower than that of the first p well 82 and shallower than that of the first p well 82. Vl is the same as that in FIG. A back bias having a negative value vl that is a low level voltage of the transfer pulse is applied to the first P well 82 so that the source / drain diffusion layer 113 is not biased forward with respect to the third P well 82. In this embodiment, the above-described structure is formed in the second impurity layer having a thick gate oxide film thickness and having a surface concentration lower than that of other portions only by adding the step of forming the second double well p layer. NMOS transistors can be formed. The enhancement-type nMOS in FIG. 10 can guarantee the reliability of the gate oxide film with a thin maximum gate-drain voltage even when the transfer pulse application duty constituting the drive pulse voltage converter 4 in FIG. 1 is considered. The first and second switches 24 and 26 shown in FIGS. 3 to 6 having the above-described vcc-vthd-vl, and the nMOS 51 shown in FIG. The pre-transfer pulse switch 67 shown in FIG. 7 or the pulse shown in FIG. 8 is connected directly to the drain of the pre-transfer pulse application line constituting the pulse voltage converter 7 and the maximum voltage between the gate and drain is as low as vhm but the application duty is high. An input nMOS 76 is configured. In addition, the depletion type transistor of FIG. 10 enables the gate oxide film thickness reliability to be low even when the application voltage of the pre-transfer pulse constituting the transfer pulse voltage converter 7 of FIG. 1 is taken into consideration. The nMOS 78 of FIG. 8 is configured to have a vhm-vl higher than the voltage that can guarantee the above.

  In the nMOS 78 shown in FIG. 8, when the vm-vl voltage is applied between the source and drain when the pre-transfer pulse is applied, the transistor characteristics are deteriorated due to hot carriers. A transistor having an n-type channel layer provided only on a part of the terminal side may be used, and its gate terminal may be a ground voltage. With this configuration, although the gate length becomes long, it is possible to relax the strong electric field on the drain side.

Further, in the portion where the voltage higher than the transfer pulse is applied, there is a problem that even if the transistor having the thick gate oxide film shown in FIG. 10 is used, the applied voltage exceeds the junction breakdown voltage and the voltage cannot be applied. . That is, in the MOS structure with a thin oxide film described in FIG. 12, the nMOS transistor field p layer 112 is formed so that the punch-through phenomenon does not occur even if the length of the isolation region where the LOCOS oxide film 117 is formed is reduced. High concentration. As a result, the junction breakdown voltage with the nMOS transistor source / drain n-type diffusion layer 113 is low. In order to simplify the manufacturing process, the structure of FIG. 10 having the same field p layer 112 as in FIG. 12 having a thin oxide film cannot similarly obtain a high junction breakdown voltage, making it impossible to apply a transfer pulse. Become. In FIG. 11, in order to solve this problem without increasing the number of manufacturing steps, the source / drain n-type diffusion layer 113 is formed with an offset of Lof from the field p layer 112. In the figure, 81, 82, 88 to 91, 112, 113, 117, vsub, vl are the same as in FIG. Lof indicates an offset distance between the source / drain n-type diffusion layer 113 and the field p layer 112. By this offset, the source / drain n-type diffusion layer 113 does not contact the high-concentration field p layer 112, and the junction breakdown voltage can be improved. Similar to FIG. 10, a back bias having a negative value vl, which is a low level voltage of the transfer pulse, is applied to the first P well 82. The enhancement-type nMOS in FIG. 11 makes the maximum voltage between the gate and drain constituting the transfer pulse voltage converter 7 in FIG. 1 vcc-vthe-vthd-vl (vthd, vl; negative), and the maximum voltage between the drain wells becomes vh−. The transfer switch MOS 69 of FIG. 7 and FIG. 8 that becomes vl, and the bootstrap MOS 73 of FIG. 7 and FIG. 8 in which the maximum voltage between the gate and drain becomes vh ″ −vcc and the maximum voltage between the drain wells becomes vh ″ −vl. Is done. Further, with the depletion type transistor of FIG. 10, the maximum gate-drain voltage constituting the drive pulse voltage converter 4 of FIG. 1 becomes vh-vcc and the maximum drain-well voltage becomes vh-vl. The high breakdown voltage MOS 28 shown in FIG. 1 and the gate-drain voltage constituting the transfer pulse voltage converter 3 of FIG. 1 is vh− (vcc−vthe) and the drain well voltage is vh−vl. The bootstrap MOS 68 shown in FIG. 7 and FIG. 8 is constructed in which the gate-drain voltage is vh′-vcc and the drain-well voltage is vh′-vl. It should be noted that the junction breakdown voltage only needs to be improved for terminals to which a high voltage is applied. Therefore, in the high breakdown voltage MOS 28 and bootstrap MOS 68 and 73, if an offset is applied only to terminals to which a high voltage is applied (for example, terminals A and B). Good.

  Note that if a high threshold voltage is not required for the MOS formed parasitically in the LOCOS oxide film 117 portion, which is an isolation region between transistors, or if there is no parasitic MOS, the LOCOS oxide film 117 having the structure of FIG. By adopting a structure in which the nMOS transistor field p layer is not provided below, the junction breakdown voltage can be improved without increasing the number of manufacturing steps, and the degree of integration can be improved as compared with the case of applying the offset of FIG. Although the number of processes increases, the concentration of the nMOS transistor field p layer under the LOCOS oxide film 117 may be lowered.

  Further, in this embodiment, all transistors having a thick gate oxide film have a surface concentration in the first P well 82 higher than that of the first P well 82 and lower than that of the second P well 111 and shallower than that of the first P well. A transistor that is formed in the third p-well 91 but does not cause an increase in threshold voltage or hot carrier breakdown voltage due to the substrate effect is formed in the second P-well 111 to achieve higher integration. Needless to say, you can.

  According to this embodiment, first, a portion where the gate-source voltage or the gate-drain voltage of the drive pulse generating means 4 and transfer pulse generating means 7 is high is equal to the gate oxide film thickness of the vertical charge transfer means 2. By forming the MOS transistor having a gate oxide film thickness, the breakdown voltage of the gate oxide film can be improved without increasing the number of manufacturing steps as compared with the prior art described in Japanese Patent Laid-Open No. 1-103861, and it is thin. By forming the timing generation means 3, the row selection control means 6, 11 to 18 amplification means, and the horizontal scanning circuit 19 with MOS transistors having a gate oxide film thickness, the integration degree of other portions can be increased as in the prior art. Therefore, a high-speed, high-integration and high-reliability drive circuit can be realized.

  Second, according to the present embodiment, the source / drain n-type diffusion layer 113 is separated from the field p layer 112 at a location where a voltage higher than the transfer pulse voltage of the transfer pulse generating means 7 and the drive pulse generating means 4 is applied. By using the MOS transistor, the junction breakdown voltage can be improved and transfer pulses having a high voltage can be applied without increasing the number of manufacturing steps even if the degree of integration of other parts is impaired.

  Thirdly, according to the present embodiment, the transfer pulse generation path of the transfer pulse generation means 7 and the drive pulse generation means 4 and the portion where the source drain voltage is high at the ON time are lower in the surface concentration than the second P well 111. 3 consisting of MOS transistors formed in the p-well 91, preventing a threshold voltage rise due to the substrate effect and deterioration of breakdown voltage due to hot carriers, timing generation means 3, row selection control means 6, amplifying means of 11 to 18; By forming the horizontal scanning circuit 19 in the second P well 111 having a high concentration, a highly integrated driving circuit with high integration and high reliability can be realized. Further, by making the surface concentration of the third p-well 91 higher than that of the first P-well 82, the gate electrode length can be shortened while realizing the desired substrate effect and withstand voltage, and the third p-well 91 can be shortened. It is possible to achieve both high breakdown voltage and high integration of the MOS transistor formed therein. Further, the depth of the third p-well 91 is made shallower than that of the first P-well 82, and when a high voltage is applied to the gate electrode 89, the entire region up to the substrate 81 is depleted, thereby causing a substrate effect. The increase in threshold voltage can be further reduced and the reliability can be further improved.

  As described above, the case where the transistor structure of the present invention is applied to the element having the overall configuration and the driving method described in FIG. 1 has been described, but the scope of the present invention is not limited to the element of FIG. The modifications described in (1) are possible.

  By configuring the drive circuit of the charge transfer means with a first MOS transistor whose gate oxide film thickness is equal to the gate oxide film thickness of the charge transfer means and a second MOS transistor whose gate oxide film thickness is smaller than the first MOS transistor, Even in the high voltage application section in the drive circuit, the gate oxide film will not be destroyed or the reliability will be lowered, and the low voltage part will be highly integrated, and a highly reliable and highly integrated charge transfer device will be realized. The realization can be widely used for highly reliable and highly integrated charge transfer devices having charge transfer means and drive circuits on the same semiconductor substrate. For example, the horizontal scanning means is composed of charge transfer elements as in FIG. 14, and the driving circuit is composed of driving means for sequentially supplying driving pulses and row selection means as in FIG. Devices described in Japanese Patent Laid-Open Nos. 58-188156 and 57-78167. Further, the row selection means is different from that shown in FIG. 1 and the transfer to the vertical charge transfer element is performed at the same time as in the usual interline CCD, as described in JP-A-62-237871 and JP-A-4-286282. element. The driving is different from that shown in FIG. 1 and is performed by external pulses of the same multiphase as in the interline CCD, Japanese Patent Laid-Open Nos. 54-75927, 57-207486, 58-107670, and Sho-sho. It can be implemented with the elements described in JP-A-62-230270, JP-A-60-247382, JP-A-63-62480, and JP-A-64-54879. Not only these two-dimensional image pickup devices but also one-dimensional solid-state image pickup devices and charge transfer types described in, for example, Television Society Technical Report CE'91-12 (Feb. 1991) that incorporates a drive circuit that requires a high drive voltage. It can also be implemented in a delay line or the like. Further, it goes without saying that the present invention can also be implemented in an element in which the horizontal scanning means of FIG.

  The drive circuit for the charge transfer means is formed in the first MOS transistor formed in the first impurity layer having a high surface concentration and in the second impurity layer having a lower surface concentration than the first impurity layer. By configuring with the second MOS transistor, it is difficult for the high voltage application part in the drive circuit to deteriorate characteristics due to hot carriers and the threshold voltage increase due to the substrate effect, and the low voltage part is highly integrated. In order to realize a highly reliable and highly integrated charge transfer device, similar to the first invention, a highly reliable and highly integrated charge transfer device having charge transfer means and a drive circuit on the same semiconductor substrate. Can be used widely.

(B) Capacitance In the present invention, as shown in FIG. 1, the first output holding capacitor 14 and the second output holding capacitors 17-1 and 17-2 for holding the analog output voltage of the amplifier 11 are required. In a charge transfer device including a charge transfer means, a circuit that processes the output of the charge transfer means by using a capacity formed between a gate electrode and a channel layer constituting the charge transfer means as a holding capacitor for an analog voltage. This is a well-known technique. (For example, J.T.Cabis et al .; I E E E Journal of Solid Circuit, Vol. 14, pp. 65-73, February 1979 JTCAVIES et al .; IEEE J. Solid-State Circuits,
VOL. SC-14, pp. 65-73 Feb. 1979) This technology has the advantage that capacitance can be formed without adding process steps. However, if the concentration of the channel n layer is lowered in order to operate the charge transfer means at a low voltage, the capacitance value has a strong voltage dependency. As a result, in the embodiment shown in FIG. 1, the removal accuracy of the fixed pattern noise due to the reset noise and the variation of the DC voltage of the amplifier is reduced, and the signal charge read from the second output holding means 17-1 and 17-2 is nonlinear. Increases sex. Therefore, in the present invention, an n layer 85 constituting a photodiode is added to the n-type channel layer 88 of the vertical charge / charge transfer means 2 to increase the concentration without increasing the number of process steps. Furthermore, the first output holding capacitor 14 and the second output holding capacitors 17-1 and 17-2 need to have a large capacitance value in order to increase the signal charge amount read from the reading switches 16-1 and 16-2. There is. Therefore, in the present invention, an insulating film thinner than the gate insulating film of the vertical charge transfer means 2 is used as the insulating film between the gate electrode and the channel n layer. Hereinafter, the structure of the capacitor of the present invention will be described with reference to FIG.

  FIG. 13 is a cross-sectional structural view taken along the line B-B′-B ″ of the first output holding capacitor 14 of FIG. 1. In the figure, 85, 88, 89, and vsub are the same as those in FIGS. 9 and 12, and 111 to 113, 117, 118, and vl are the same as those in FIG. 121 is a capacitor forming electrode, 122 is an insulating film having a larger unit area than the thin gate oxide film 118, 123 is an n layer 85 constituting a photodiode and the n-type channel layer 88 of the vertical charge / charge transfer means 2 and the photodiode. Wiring connecting the n-type diffusion layer connected to. The n-type diffusion layer 113 forming one end of the capacitor is connected to the output of the amplifier 11, and the gate electrode 89 forming the other end is connected to the input terminals of the write switches 16-1 and 16-2 having high impedance. The second output holding capacitors 17-1 and 17-2 have the same structure, the n-type diffusion layer 113 forming one end of the capacitor is grounded, and the gate electrode 89 forming the other end is a high impedance read switch 17 -1, connected to 17-2 input terminals.

  According to the present embodiment, first, since one end of the capacitor is constituted by the n-type diffusion layer connected to the n-type channel layer 88 of the vertical charge transfer means 2 and the n-layer 85 constituting the photodiode, the process is performed. Since the voltage dependency of the capacitance can be reduced without increasing the number of steps, it improves the removal accuracy of fixed pattern noise due to variations in reset noise and amplifier DC voltage, and is read from the second output holding means 17-1 and 17-2. The non-linearity of signal charge can be reduced. When the n layer 85 constituting the photodiode is sufficiently larger than the n-type channel layer 88 of the vertical charge transfer means 2, the n-type channel layer 88 of the vertical charge transfer means 2 may not be formed.

  Second, according to this embodiment, the insulating film between the gate electrode 89, the n-type channel layer 88, and the n layer 85 constituting the photodiode is formed by the thick gate oxide film 88 of the vertical charge transfer means 2 as in the prior art. By using a thin gate oxide film 118, the capacitance value per unit area can be increased and high integration can be achieved.

  Third, according to the present embodiment, the gate electrode 89 and the n-type channel layer 88, which is electrically isolated from the p-well 111 and electrically separated, and the electrode comprising the n-layer 85 constituting the photodiode and the capacitor forming Capacitance is formed by the electrode 121, the gate electrode 122 is connected to the high impedance node, and the electrode composed of the n-type channel layer 88 and the n layer 85 constituting the photodiode and the capacitance forming electrode 121 are connected to the low impedance node. Therefore, as described in JP-A-5-283614, the output is not affected by noise from the n-type substrate 81 or the well 111 or an external noise source. In the case where the capacitance value per unit area of the insulating film 122 does not need to be larger than the capacitance value of the thin gate oxide film 118, for example, the capacitance forming electrode is shared with the aluminum wiring layer, and the insulating film 122 is gated. A process step may be simplified as an interlayer insulating film between the electrode and the aluminum wiring layer.

  Note that the first well 111 may be the third p well 82, or the second double well 91 and the third well 82. Further, as in the case of the second holding means 17-1 and 17-2, the potential of the n-type diffusion layer in which the electrode forming one end of the capacitance is connected to the n-type channel layer 88 and the n-layer 85 constituting the photodiode is In the case where each column is the same, the LOCOS oxide film 117 and the field p layer for lateral separation are not formed in the region B ″, but the n-type channel layer 88 and the n layer 85 constituting the photodiode are formed. It can be formed on the entire surface to increase the degree of integration.

  In the first bootstrap capacitor 66, the bootstrap capacitor 70, and the bootstrap capacitor 72 of the high breakdown voltage MOS 71 constituting the transfer pulse generating means 7 constituting the row selection means, a voltage applied between both terminals of the capacitors. Therefore, the structure is the same as that of the depletion type nMOS shown in FIG. That is, the insulating film between the gate electrode 89 and the n-channel layer 88 uses the same thick gate oxide film 90 as that of the vertical charge transfer means 2 to prevent a breakdown voltage failure of the insulating film. Further, the lower electrode is composed of only the n-channel 88, thereby preventing the punch-through breakdown voltage from decreasing between the n-type diffusion layer 113 and the substrate 81 due to the addition of the n-layer 85 constituting the deep photodiode. Note that the gate terminal side of the bootstrap capacitors 66, 70, 72 (for example, terminals a, b in FIG. 7) is connected to the gate electrode 89, and the gate electrode is always positive with respect to the n channel layer at the time of bootstrap. The inversion layer is not lost.

  As described above, the case where the capacitance structure of the present invention is applied to the element having the overall configuration and the driving method described in FIG. 1 is described, but the scope of the present invention is not limited to the element of FIG. The following modifications are possible.

An impurity layer comprising a first conductivity type impurity layer constituting one end of the output holding capacitor by a gate electrode constituting charge transfer means and the other end constituting a photoelectric conversion element provided in the second conductivity type impurity layer With this configuration, the voltage dependence of the capacitance value of the output holding capacitor can be relaxed widely regardless of the specific form of the charge transfer means and the amplification means. For example, it can be implemented by an element in which the horizontal scanning unit shown in FIG. That is, in the same way as in FIG. 1, the driving circuit is composed of driving means for sequentially supplying driving pulses and row selecting means, but different driving methods are disclosed in JP-A-58-188156 and JP-A-57-78167. The described element. Further, the row selection means is different from that shown in FIG. 1 and the transfer to the vertical charge transfer device is performed in the same manner as in the conventional interline CCD. JP-A-62-237871 and JP-A-4-286282 element. The driving is different from that shown in FIG. 1 and is carried out by multi-phase external pulses similar to the interline type CCD. JP-A-54-75927, JP-A-57-207486, JP-A-58-107670, JP It can be applied to the elements described in JP-A-62-230270, JP-A-60-247382, JP-A-63-62480, and JP-A-64-54879. Further, the above two-dimensional element, the usual interline CCD, and the output terminal of the one-dimensional solid-state imaging element described in Television Society Technical Report CE'91-12 (Feb. 1991) are described in JP-A-1-277066. Even when a correlated double sampling circuit as described above is applied, it can be implemented.
[Example 2]

Second Embodiment The present inventor disclosed in Japanese Patent Application Laid-Open No. 5-103272, a built-in voltage generator for generating a multi-value voltage level pulse necessary for driving a CCD type image pickup device and eliminating a driver chip. It has been proposed to reduce the number of DC-DC converters, improve the usability of the CCD type image pickup device, and reduce the power consumption of the image pickup apparatus. The solid-state imaging device according to the first object of the present invention has a smaller pulse load capacity for driving the driving means, the row selection / selection means, and the horizontal scanning means than the conventional interline CCD type imaging device, so that the current By incorporating a voltage converter with a small driving capacity and a small occupation area, an element capable of driving only a positive single power source driving signal and a positive power source can be realized. In the first embodiment, by providing the drive pulse generation means 4, the drive means is equal to a drive signal having a single positive voltage value, a positive power supply having a voltage value equal to the drive signal, and a low level voltage of the drive pulse. It was driven by a negative power source with a voltage value. In addition, by providing the transfer pulse generation means 7, the row selection means has a drive signal having a single positive voltage value, and the low level is a ground voltage and the high level has a positive voltage value higher than the single positive voltage value. It was driven by a pre-transfer pulse, a transfer pulse, a positive power source having a voltage value equal to the drive signal, and a negative power source having a voltage value equal to the low level voltage of the drive pulse. Furthermore, by providing an output gate 2-4 and driving the vertical charge transfer means 2 with a negative drive pulse and converting the signal charge into a voltage by a capacitive feedback type charge-voltage converter consisting of 11 to 13, The power supply of the amplifier 11 in the horizontal scanning means is a positive power supply voltage value. As a result, since the signal voltage in the horizontal scanning means does not exceed the positive power supply voltage value, the horizontal scanning means can be easily replaced with a drive signal having a single positive voltage value and a positive power supply having a voltage value equal to the drive signal. Can drive. Therefore, in the second embodiment, the row selection means includes a transfer pulse booster that boosts the positive single power supply drive signal and generates a transfer pulse having a second voltage value at a high level on the transfer pulse application line. The positive single power supply drive signal is boosted to supply a pretransfer pulse having a high third voltage value higher than the positive power supply voltage value and lower than the second voltage value to the pretransfer pulse application line. A pre-transfer pulse booster is added to the charge transfer control drive line connecting the parallel electrodes of the charge transfer control unit of the vertical charge transfer means 2 from the positive single power supply drive signal and the negative power supply to the negative value A charge transfer control unit drive pulse generator that generates a drive pulse having a low voltage level is provided so that the element can be driven by only a positive single power source drive signal without providing a driver chip. Furthermore, a substrate voltage generator that generates a second positive power supply voltage by boosting from the positive power supply and a negative voltage generator that generates a negative power supply voltage having a voltage value equal to the low level of the drive pulse are provided, and the DC voltage is also positive. A DC-DC converter is not required because only a power source is required. As a result, the solid-state imaging device of this embodiment does not require a driver chip or a DC-DC converter, and can be driven only by a positive single power source drive signal and a positive power source. Hereinafter, description will be made with reference to FIGS. FIG. 15 is a diagram showing the overall circuit configuration of the second embodiment, FIG. 16 (a) is a circuit configuration diagram of the pre-transfer pulse booster 141 of FIG. 15, and FIG. 15 (b) is the same diagram (a). It is a drive pulse timing diagram of the circuit of.

15, 1 to 10 and 19 are the same as in FIG. 1, 140 is an amplifying means consisting of 11 to 18 in FIG. 1, 74 and 75 are the same as in FIGS. 7 (a) and 8 (a), and 141 is a front end. Transfer pulse booster, 142 is a transfer pulse booster, 143-1 and 143-2 are two-phase shift pulse lines connected to terminals H1 and H2 of the horizontal scanning circuit 19, 144 is a DC clamp voltage application line, and 145 and 146 Are a gate 2-2 constituting the charge control unit, a charge transfer control unit drive pulse generator for generating a drive pulse to the charge accumulation gate 2-3, and 147 is a charge storage ground voltage at the output gate constituting the charge control unit. An output gate DC bias generator that applies a DC voltage in the middle of the low-level negative voltage vl of the transfer pulse, 148 is a substrate voltage generator that generates a second positive power supply voltage vsub by boosting from the positive power supply, and 149 is a fine Back-by generating back bias voltage vbb applied to the well of the nMOS transistor Scan voltage generator, 150 is a negative power supply voltage generator having the same voltage value vl and low level of the drive pulse. T1, T2, TIN, V1, V2, VIN, FA, FB, RG, CP, SH1, SH2, H1, H2, HIN, O1, O2, Vcc, GND are the same as in FIG. 1, V3T, V4T are positive power supplies The positive single power source drive signal application terminal V3LT, V4LT for generating a transfer pulse having a second voltage value vh higher than the first voltage value at a high level is higher than the positive power source voltage value vcc at the second level. A positive single power source drive signal application terminal for generating a pre-transfer pulse having a third voltage value vhm lower than the voltage value of SBT, SBT is a positive single power source for generating a drive pulse for gate 2-2 A drive signal application terminal STT is a positive single power supply drive signal application terminal for generating a drive pulse for the charge storage gate 9. In this embodiment, the DC clamp voltage applied to the terminal VC in FIG. 1 and the high level voltage value vm of the drive pulse of the vertical charge transfer means 2 are the ground voltage. In FIG. 2, the timing of the pulses applied to each terminal is such that the pulses φH1 and φH2 applied to the terminals H1 and H2 are continuous, and the terminals V3T, V4T, V3LT, and V4LT are connected to φV3, φV4, φV3L, and φV4L. At the same timing, a pulse of low level is ground voltage, high level is positive power supply voltage value vcc, φ SB and φ ST are inverted to terminals SBT and STT, low level is ground voltage, and high level is positive power supply voltage value vcc These pulses are applied. Hereinafter, the configurations and operations of the pulse voltage converters 141, 142, 145, and 146 and the voltage generators 147 to 150 will be described.

  The pre-transfer pulse booster 141 boosts the positive single power supply drive signal in a short time to shorten the application time of the transfer pulse to the drive pulse line and has the third voltage value vhm at a high level. It is necessary to supply the pre-transfer pulse to the pre-transfer pulse application line. A charge pump capacitor having a relatively large capacitance value is necessary to obtain the current driving capability for realizing this, and the booster area cannot be reduced. Furthermore, when reading two rows of signals in one horizontal scanning period as described in FIG. 1, transfer pulses must be applied to the two rows of drive pulse lines simultaneously selected by the row selection control means 6 at different times. First, it is necessary to generate two pre-transfer pulses. As a result, two boosters are required. Therefore, when two rows are read independently and two pre-transfer pulses are generated, the number of charge pump capacitors is halved by sharing the booster to reduce the area of the booster. In addition, the voltage amplitude of the boost pulse applied to the charge pump capacitor is set to a voltage amplitude obtained by adding the negative power supply voltage value and the positive power supply voltage value, thereby realizing a necessary capacity value reduction.

  Hereinafter, the configuration and operation of the pre-transfer pulse booster 141 will be described with reference to FIG. 16A is a circuit configuration diagram of the pre-transfer pulse booster 141 in FIG. 15, and FIG. 16B is a drive pulse timing diagram of the circuit in FIG. In FIG. 16A, B1 is an OR circuit that inputs two positive single power source drive signals that determine the application time to the pre-transfer pulse application line applied to the terminals V3LT and V4LT and outputs the logical sum thereof. is there. mn1, mn2, and mn3 are nMOSs that constitute the OR circuit B1, and mp1, mp2, and mp3 are pMOSs that constitute the OR circuit B1. B2 is an AND circuit that outputs a logical product of the shift pulse applied to the terminal H1 and the positive single power source drive signal applied to the terminal V3LT or V4LT. mn4, mn5, mn6 and mn7 are nMOSs constituting the AND circuit B2, and mp4, mp5, mp6 and mp7 are pMOSs constituting the AND circuit B2. B3 is a voltage converter for setting the voltage amplitude of the output pulse of the AND circuit of the terminal Y2 to a voltage amplitude obtained by adding the negative power supply voltage value vl and the positive power supply voltage value vcc. 155 is a PMOS whose gate is grounded, 156 is an AND The inverted output value terminal Y5 of the circuit is an nMOS connected to the gate. The configuration of the voltage converter is the same as that described in FIG. B4 is a booster that boosts the output of the OR circuit at the terminal Y1. 151-1 and 151-2 are applied with a positive power supply vcc at the gate, and an initial voltage setting nMOS for initially setting terminals Y6 and Y4 in the booster by the output of the OR circuit B1, 152 is a charge pump nMOS, 153 is a charge pump capacity , 154 are voltage limiters that prevent unnecessary high voltages from being formed by a plurality of diode-connected transistors. B5 is a selection switch for outputting the booster output of the terminal Y4 to the pre-transfer pulse applying line 74-1 or 74-2 based on the positive single power source driving signal applied to the terminal V4LT or V3LT. . 157-1 and 157-2 are switch nMOS, 158-1 and 158-2 are drive signal input switches for controlling on / off of the switches 157-1 and 157-2, and 159-1 and 159-2 are bootstraps. Capacitors 160-1 and 160-2 are reset switches whose gates are connected to the inverted value output terminal Y7 of the OR circuit. Terminals Vcc, GND, VL, V3LT, V4LT, and H1 are the same as in FIG. 15, and terminals V3L and V4L are the same as in FIG. The mn1 to mn7, mp1 to mp7, and the PMOS 155 constituting the logic circuit are constituted by the transistors of FIG. Further, since the high level of the terminal Y6 is limited to 2 vcc or less, the initial voltage setting nMOSs 151-1 and 151-2, the charge pump nMOS 152, and the voltage limiter 154 are also constituted by the transistors of FIG. Further, since the nMOS 156, the switching nMOSs 157-1 and 157-2, the drive signal input switches 158-1 and 158-2, and the reset switches 160-1 and 160-2 require a high breakdown voltage, the enhancement shown in FIG. A type nMOS is used. Since the voltage across the charge pump capacitor 153 exceeds vcc, the structure is the same as the depletion type nMOS of FIG. 11 having the same thick oxide film as the bootstrap capacitor 66 and the like. Since the terminal Y3 is always lower in voltage than the terminal Y6, the terminal Y6 is connected to the gate electrode 89. In addition, a ground voltage is applied to the booster B4 (excluding the charge pump capacitor 153) and the p-well of the selection switch B5, thereby increasing the threshold voltage due to the substrate effect and reducing the voltage between the diffusion layer wells. Terminals Y1 and Y7 are the outputs of the OR circuit B and their inverted output terminals, terminals Y2 and Y5 are the outputs of the AND circuit B2 and their inverted output terminals, terminal Y3 is the output terminal of the boost pulse voltage converter B3, and terminal Y4 is the booster. The output terminal of the device B4, the terminal Y6 is a terminal in the booster, and the terminal P1 is a gate terminal of the switch 157-1 or 157-2. In FIG. 16B, φV3LT and φH1 indicate pulse voltages applied to the terminals V3LT and H1 in FIG. 1, respectively. Furthermore, vl and vcc are a negative power supply voltage value and a positive power supply voltage value, respectively. vh1 is a value when the Y4 terminal of the gate terminal P1 is initialized, vh2 is a maximum voltage value of the gate terminal P2, and vth is a threshold voltage of the charge pump nMOS 152. vhm indicates a third voltage value that is higher than the positive power supply voltage value and lower than the second voltage value. Hereinafter, an operation when a pre-transfer pulse is generated at the terminal V3L will be described as an example with reference to FIG. First, when the voltage applied to the terminal V3LT becomes vcc, the OR circuit output terminal Y1 also becomes vcc, and the voltages at the terminal Y6 and the output terminal Y4 in the booster become vcc via the initial voltage setting nMOSs 15-1 and 15-2. -vth. At the same time, the gate terminal P1 of the switch 157-1 is first set to vcc-vthe via the drive signal input switch 158-1, and the switch 157-1 is turned on. As a result, the voltage at the terminal V3L rises to vcc-vth, and the bootstrap capacitor 159-1 causes the voltage at the terminal P1 to become a voltage vh1 greater than or equal to vcc-vthe. On the other hand, since the voltage applied to the terminal V4LT is the ground voltage at this time, the switch 157-2 is not turned on. At this time, the reset switches 160-1 and 160-2 whose gates are connected to the inverting output terminal Y7 of the OR circuit are turned off. (Time t1) Next, in synchronization with the pulse at the terminal H1, the voltage at the AND circuit output terminal Y2 becomes vcc, and the voltage at the boost pulse voltage converter output terminal Y3 changes from vl to vcc. As a result, the terminal Y6 in the booster circuit becomes 2vcc-vth-vl (vl: negative value) via the charge pump capacitor 153, the charge pump nMOS is turned on, and the voltage at the booster output terminal Y4 rises. Accordingly, the V3L terminal voltage and the voltage at the gate terminal P1 also increase. At this time, if cp ((2vcc-vth-vl)-(vhm + vth)) is set equal to cl (vhm- (vcc-vth)), the voltage at the terminals Y4 and V3L can be set to Vhm. Here, cl is a parasitic capacitance associated with the pre-transfer pulse line 74-1, and cp is a capacitance value of the charge pump capacitor 153. (Time t2) Then, when the voltage at the terminal H1 becomes 0v, the voltage at the AND circuit output terminal Y2 also becomes 0v, and the boosted pulse voltage converter output voltage Y3 is connected to the inverting output terminal Y5 of the AND circuit with the nMOS 156. The voltage becomes vl. As a result, the voltage at the terminal Y6 in the booster circuit becomes the same vcc-vth as at time t1. (Time t3) Thereafter, when the voltage at the terminal H1 becomes vcc again, the voltage at the booster pulse converter output terminal Y3 changes from vl to vcc, and the voltage at the booster output terminal Y4 tends to rise to vhm or higher. However, the voltage limit circuit 154 is turned on when the voltage at the output terminal Y4 of the booster circuit B4 becomes equal to or higher than vhm, and the voltage does not increase. A similar operation occurs after (time t4), and a reactive current of cl (vhm− (vcc−vth)) * 1 / fc (fc: shift pulse frequency applied to the terminal H1) is reduced. Operates in a short time during which the voltage at the terminal V3LT is vcc, so that the power consumption is small. Next, when the voltage applied to the terminal V3LT becomes 0v, the voltage of the OR circuit output terminal Y1 also becomes 0v, and the voltages of the terminals Y6 and Y4 in the booster via the initial voltage setting nMOSs 15-1 and 15-2. Becomes 0v. At the same time, the gate terminal P1 of the switch 157-1 becomes 0v via the drive signal input switch 158-1, and the switch 157-1 is turned off. On the other hand, the reset switches 160-1 and 160-2 whose gates are connected to the OR circuit inverted output terminal Y7 are turned on, and the pre-transfer pulse application line voltage 74-1 becomes 0V. On the other hand, the voltage of the AND circuit output terminal Y2 remains 0v, and the voltage of the boost pulse voltage converter output terminal voltage Y3 remains vl. At (time t5), the pre-transfer pulse output to the terminal V3L is completed. Subsequently, the output of the pre-transfer pulse to the terminal V4L is similarly performed by the drive signal applied to the terminal V4LT.

  The transfer pulse booster 142 adds another stage 151-1, 152, 153 in the booster B4 in FIG. 16A, and an AND circuit B2 that receives the shift pulse applied to the terminal H2 and the boost pulse. A voltage converter B3 is added, and its output is connected to the charge pump capacitor 153 at the stage where the booster B4 is added. 3 is provided between the reset switches 160-1 and 160-2 and the transfer pulse application line 75, and the switches 157-1 and 157-2 have a terminal Y4. A high withstand voltage circuit from 71 to 73 in Fig. 7 was added on the side to achieve high withstand voltage. Since the high level of the terminal Y6 is not limited to 2 vcc or less, the nMOS shown in FIG. 10 or FIG. 11 is used as the transistor in the booster B4. The offset structure shown in FIG. 11 is used for the bootstrap node of the terminal P1, the terminal Y4, the transfer pulse applying lines 75 and 71 to 73, and the diffusion layer of the next booster node in the booster B4. In addition, a ground voltage is applied to the p-well of the booster B4 (except for the charge pump capacitor 153) and the selection switch B5, thereby increasing the threshold voltage due to the substrate effect and reducing the voltage between the diffusion layer wells. The voltage of the terminal V3T or V4T is increased by applying the voltage of the terminal Y1 to the p-well of the booster B4 (excluding the charge pump capacitor 153 and the voltage limit circuit 154) through the same transistor as the initial voltage setting nMOS 15-1. At the level, the p-well voltage may be vcc-vthe to further reduce the threshold voltage increase due to the substrate effect and increase the boosting efficiency. Furthermore, when higher speed boosting is required, another booster B4 for performing the final stage charge pump with different shift pulses may be provided.

  The charge transfer controller drive pulse generator 145 or 146 connects the terminal SBT or STT to the gate of the buffer nMOS 41 of the voltage converter 41 to 43 shown in FIG. 5, and the voltage converter output is connected to the ground line and the negative power line. Are connected to the input of a CMOS inversion circuit provided between them and the output of the inversion circuit is connected to the charge transfer control line 8 or 9. 41 and 42 and the CMOS inversion circuit are constituted by transistors shown in FIG. A positive single power source drive signal applied to the terminal SBT or STT is converted into a pulse having a negative value at a low level by a voltage converter composed of 41 to 43 and then inverted, and each charge transfer control drive line 8 or 9 is inverted. To be applied.

  An output gate bias generator 147 includes a widely used diode-connected nMOS transistor described in Japanese Patent Application Laid-Open No. 5-103272 between a ground line and a negative value source line. And a DC voltage intermediate between the ground voltage and the low level negative voltage vl of the transfer pulse is applied to the charge transfer control drive line 10. Since the voltage between the terminals of each transistor is less than vcc, the nMOS of FIG. 12 is used. As is well known, a DC bias voltage for operating the amplifier 11 is also generated by a circuit having the same configuration provided between the ground line and the positive power supply line.

  The substrate voltage generator 148 is a means for generating a DC voltage applied to the substrate from the voltage boosted from the same positive power supply as previously proposed in FIG. Is added to make the substrate voltage non-adjustable. At this time, boosting is performed by continuous shift pulses applied to the terminal H1. In the embodiment shown in FIGS. 1 and 15, the sensitivity is adjusted by the method described in Japanese Examined Patent Publication No. 4-46504. Therefore, a circuit for adding a pulse for varying the sensitivity to the substrate is not provided. Further, since the depletion transistor shown in FIG. 10 used in the present invention has a small absolute value of the threshold voltage, the power supply of the bias voltage generating circuit uses the output from the booster circuit. The booster circuit and the two bias voltage generation circuits are constituted by the nMOS shown in FIG. 12, the voltage drop n-channel depletion MOS transistor, and the load transistor are constituted by the transistors shown in FIG. Since a voltage higher than vcc is not applied to the charge pump capacitor in the booster circuit, the capacitor shown in FIG. 13 that does not include the capacitor forming electrode 121 is used. Needless to say, if the boost of one stage is insufficient, the number of booster stages may be increased.

The back bias voltage generator 149 and the negative power supply voltage generator 150 are circuits that generate a negative voltage composed of a charge pump capacitor and a diode-connected nMOS widely used in dynamic memories, static memories and the like. (For example, see Japanese Patent Publication No. 5-70941, FIG. 1) The charge pump is operated by a continuous shift pulse applied to the terminal H1. Since the voltage in each generator is less than or equal to vcc, the transistor shown in FIG. 12 is used, and the capacitor shown in FIG. 13 that does not include the capacitor forming electrode 121 is used. In the embodiment of FIGS. 1 and 15, the drive pulse generator 4, the transfer pulse generator 7, the charge transfer controller drive pulse generator 145 or 146, the output gate bias generator 147, the pre-transfer pulse booster 141, the transfer A through current flows through the negative power supply line 27 in the pulse booster 142, and the negative power supply voltage value is not stable. In particular, fluctuations in the back bias voltage applied to the n-well P-well of the amplifying means 11 to 18 that handle analog voltages have become noise in the output signal, which necessitates stabilization. Therefore, in the embodiment of FIG. 15, two negative power supply generation circuits are provided, the negative power supply line through which the through current flows is connected to the output of the negative power supply voltage generator 150, and the power supply lines of other parts are back biased. Connected to voltage generator 149. With this configuration, it is possible to prevent the through current flowing through the above portion from affecting the p-well back bias voltage at the portion where the through current does not flow. A continuous shift pulse applied to the terminal H1 is applied to the two negative voltage generators to generate a negative voltage. When two negative power generators are provided inside the element as described above, the back bias voltage vbb and the voltage value vl equal to the low level of the drive pulse need not be equal. Further, the charge pump capacitor of the negative power supply voltage generator 150 that requires a large current driving capability may be provided outside.

  According to this embodiment, first, when positive single power source drive signals φT1, φT2, and φT3 are inputted, the drive means consisting of 3 and 4 generates a drive pulse having a negative low level for vertical charge transfer. When the positive single power supply drive signals φSBT and φSTT are inputted to the drive pulse line 5 in sequence, the charge transfer control unit drive pulse generators 145 and 146 are connected to 2-2 and 2-4 in the charge transfer control unit A drive pulse having a negative voltage at a low level is generated on the charge transfer control drive line, and the output gate bias generator 147 transfers a DC voltage intermediate between the ground voltage and the low level negative voltage vl of the transfer pulse. When a positive single power source drive signal φV1, φV2, φVIN, φFA, φFB, φV3LT, φV4LT, φV3T, φV4T is input to the control drive line 10, the row selection means consisting of 6, 7, 141, 142 is photoelectrically converted. Vertical signal transfer of device signal charge A transfer pulse having a high second voltage value higher than the positive power supply voltage value for transfer to the means is supplied to the drive pulse line, and positive single power supply drive signals φCP, φRG, φSH1, φSH2, φH1, When .phi.H2 and .phi.HIN are applied, the horizontal scanning means composed of an amplifying means 11 to 18 having an amplifier 11 and a reset switch 12 provided for each output terminal of the vertical charge transferring means and a horizontal scanning circuit 19 transfers vertical charges The signal charge transferred from the means 2 is amplified and output. As a result, the voltage converter is applied to the semiconductor substrate and the negative power supply having a voltage value equal to the positive power supply signal, the positive power supply, and the low level of the drive pulse without increasing the area. It can be operated with 2 positive power supplies, eliminating the need for a driver chip. In this embodiment, the case where the vertical charge transfer means has a charge transfer control unit consisting of 2-2 to 2-4 is described, but the charge transfer control unit is configured only by the output gate 2-4, and When the drive voltage is the ground voltage, the charge transfer control unit drive pulse generators 145 and 146 and the output gate bias generator 147 need not be provided.

  Secondly, according to the present embodiment, the substrate voltage generator 148 generates the second positive power supply voltage vsub from the positive power supply voltage vcc by the continuous positive single power supply driving signal applied to the terminal H1. A DC-DC converter that generates a substrate voltage outside the device can be eliminated.

Thirdly, since the negative voltage generator 150 generates a negative power supply voltage having a voltage value equal to the low level of the drive pulse by a continuous positive single power supply drive signal applied to the terminal H1, A DC-DC converter that generates a voltage value equal to the low level of the drive pulse can be eliminated. Further, the negative power supply voltage generator 150 reduces the substrate effect coefficient applied to the p-well in which a fine nMOS operating with a single positive power supply is formed, secures the threshold voltage of the field parasitic MOS, and increases the junction capacitance. Apart from the back bias voltage generator 149 that generates a negative back bias vbb for reduction, the back bias voltage of the p-well formed by the fine nMOS is unstable due to the through current flowing in the negative power supply voltage generator 150. Can be prevented.

  In the present embodiment, by performing the above three simultaneously, neither a driver chip nor a DC-DC converter is required, and only a positive single power source drive signal and a positive power source can be driven.

  Fourth, according to the present embodiment, when a positive single power source drive signal φV1, φV2, φVIN, φFA, φFB, φ is input, the row selection control means 6 generates a control signal for specifying the selected row Then, the transfer pulse booster 142 boosts the positive single power supply drive signals φV3T and φV4T to generate a transfer pulse having a second voltage value higher than the positive power supply voltage value at the transfer pulse application line 75 at a high level. Then, since the transfer pulse generating means 7 outputs the transfer pulse applied to the transfer pulse applying line to the drive pulse line 5 of the selected row based on the control signal, the row selecting means can be highly integrated and transfer There is no need for an external driver to generate pulses.

  Furthermore, when positive single power supply drive signals φV3T and φV4T are input, the OR circuit B1 outputs a logical sum, and the booster B4 generates a transfer pulse having a second voltage value at a high level from the logical sum. Since the selection switch B5 outputs the booster output to each of the two transfer pulse application lines based on φV3T and φV4T, the number of charge pump capacitors 153 is set to 1 when two rows are read independently. Therefore, the area of the transfer pulse generator 142 can be reduced. In addition, the voltage value of the boost pulse applied to the charge pump capacitor by the boost pulse voltage converter B3 is set to a voltage amplitude obtained by adding the negative power supply voltage value and the positive power supply voltage value, thereby realizing a necessary capacity value reduction.

  Fifth, according to the present embodiment, the pre-transfer pulse booster 141 boosts the positive single power supply drive signals φV3LT and φV4LT and causes the pre-transfer pulse application line 74 to be higher than the voltage value of the positive power supply. When a pre-transfer pulse having a high third voltage value lower than the voltage value of 2 is generated, the pre-transfer pulse voltage converter consisting of 66 to 68 or 66, 76 to 78, 68 is Is applied to the selected row and the voltage of the gate terminal A of the transfer pulse switch MOS69 is set to the fourth voltage value vcc-vthd higher than the positive power supply voltage value vcc and lower than the third voltage value vhm, and then the transfer pulse is applied. As a result, the bootstrap capacitor 70 boosts the voltage at the gate terminal A of the transfer pulse switch MOS69. As a result, a transfer pulse having a voltage more than three times the positive power supply voltage vcc is triggered by a control signal having a positive power supply voltage value vcc or less without providing an external driver for generating a pretransfer pulse. It is possible to output to the selected line. Further, the pre-transfer pulse booster 141 has the same configuration as the transfer pulse booster, and when performing two rows simultaneous independent reading, the number of charge pump capacitors 153 is halved and the pre-transfer pulse generator 141 is used. Can be reduced. In addition, the voltage value of the boost pulse applied to the charge pump capacitor by the boost pulse voltage converter B3 is set to a voltage amplitude obtained by adding the negative power supply voltage value and the positive power supply voltage value, thereby realizing a necessary capacity value reduction.

As described above, the case where the present invention is applied to the element having the overall configuration and the driving method described in FIG. 15 has been described. However, the scope of the present invention is not limited to the element of FIG. Is possible. Driving means for sequentially supplying a low level negative driving pulse for vertical charge transfer to a driving pulse line connecting one parallel electrode of the vertical charge transferring means by inputting a positive single power source driving signal; By inputting a positive single power supply drive signal, a second voltage value higher than the positive power supply voltage value for transferring the signal charge of the photoelectric conversion element to the vertical charge transfer means one by one in parallel is set to a high level. A row selecting means for supplying the drive pulse line to the drive pulse line; an amplifier provided for each output terminal of the vertical charge transfer means; an amplifying means having a reset switch connected to the input terminal of the amplifier; and the amplifying means By providing a horizontal scanning means composed of a horizontal scanning circuit that operates with a positive single power supply driving signal for selecting and outputting the output, the current driving capability required for the voltage converter provided in the element is reduced. Occupation An element that can be driven with a positive single power source drive signal with a reduced area can be implemented regardless of the specific form of the voltage converter of the drive means and row selection means. For example, a voltage converter similar to the charge transfer control unit drive pulse generators 145 and 146 may be provided immediately after each input terminal of the conventional drive unit 136 of FIG. Further, a booster similar to the transfer pulse booster 142 may be provided at each input terminal of the conventional driving means 137 of FIG. Furthermore, the specific forms of the charge transfer control unit in the vertical charge transfer means are various as described above, and according to the form, the charge transfer control unit drive pulse generators 145 and 146 and the output gate bias generator 147 are provided. Change it. Further, various embodiments of the amplifying means can be implemented as described above, and the amplifier 11 is constituted by a source follower circuit as in the case of a typical interline CCD image pickup device, and a feedback capacitor 13 The reset switch may be an nMOS connected to a positive power source.
[Example 3]

Third Embodiment The second embodiment can be driven from the outside by a positive single power source drive signal and a positive power source. However, it requires a timing generator that generates a number of positive single power supply drive signals. In particular, the present invention has a problem that the number of pins increases because it requires a large number of timing signals as compared with a conventional interline CCD for driving the element, which makes mounting difficult. Therefore, in the third embodiment, a timing generator is built in and a video signal output is obtained by applying a single basic clock, a ground power source, and a positive power source from the outside. In the first embodiment shown in FIG. 1, although it is a CCD type image pickup device, vertical and horizontal scanning is performed by a row selection control means 6 having a shift register and a horizontal scanning circuit 19 comprising a shift register. In addition, since each operates with a positive single power supply drive signal, a shift register corresponding to the blanking period described in JP-A-52-149022 and JP-B-5-24711 is provided with a ring counter. By configuring and obtaining various signals from the shift register output during the blanking period, the timing generator can be configured easily. In the third embodiment, the timing generator configured as described above is realized by the solid-state imaging device of the second embodiment shown in FIG. Further, in this embodiment, the external power supply voltage vdd applied to the terminal VDD is stepped down to supply the internal power supply voltage vcc to the timing generator to reduce the power consumption and the degree of integration. Improved. The external power supply voltage value vdd requires a high voltage and is the same value as the power supply voltage of the amplifier 11 through which a large current flows. Hereinafter, description will be made with reference to FIG. FIG. 17 is a diagram showing an overall circuit configuration of the third embodiment. In order to simplify the description, the ground line and the two negative power supply lines shown in FIG. 15 are omitted.

In FIG. 17, 1 to 10 and 19 are the same as FIG. 1, and 74, 75, 143 to 147 and 150 are the same as FIG. 161 is a flip-flop for supplying two-phase shift clocks φH1 and φH2 from the basic clock, 162 is a horizontal delay shift register having the number of stages corresponding to the horizontal blanking period added to the horizontal scanning circuit 19, and 163 is when power is turned on An OR circuit that takes the logical sum of the trigger pulse that is input only once to the terminal STH and the final stage output of the horizontal scanning circuit 19, and 164 is the output of each stage of the horizontal delay shift register 162, φRG, φCP, φSH1, φSH2 Timing signal and φSBT, φSTT, φTIN
, And a gate circuit for determining the shift time T of the shift pulse of the timing generating means 3, φV1, φV2, a logic circuit including a plurality of RS flip-flops for generating a horizontal blanking pulse output from the terminal HBK, 165 is φH1, AND circuit 166 for obtaining the logical product of the gate signals generated at φH2 and 164 and generating φT1 and φT2, 166 for vertical delay having the number of stages corresponding to the vertical blanking period added to the shift register in the row selection control means 6 The shift register, 167 is an OR circuit that takes the logical sum of the trigger pulse input to the terminal STV only once at power-on and the final stage output of the vertical delay shift register 166, and 168 is the first stage of the vertical delay shift register 166. RS flip-flop for generating a vertical blanking pulse output from terminal VBK from the final stage output, 169 is a vertical blanking ½ frequency divider that divides the pulse by 1/2 to produce φFA and φFB, 170 is reset by φVIN, counter CV that counts φV1 and φV2, and counter CT that counts φT1 and φT2 is reset by φHIN A logic circuit that generates φV3LT, φV3, φV4LT, and φV4 based on the coincidence of the counter output, 171 is a reset pulse that resets the shift register in the timing generating means 3 at a predetermined time within the vertical blanking period. A wiring 172 for transmission is a power supply voltage dropr for stepping down the external power supply voltage vdd applied to the terminal VDD to reduce the power consumption and improving the integration to the internal positive power supply voltage vcc. The external power supply voltage value vdd needs to be a high voltage and is the same value as the power supply voltage of the amplifier 11 through which a large current flows. 173 is a pulse voltage converter for setting the high level of the timing signal having the same high level as the internal power supply vcc output from the logic circuit 164 constituting the horizontal scanning means to the external power supply voltage vdd, and 174 constitutes the horizontal scanning means. Pulse voltage converter for setting the high level of the selection signal having the same high level as the internal power supply vcc output from the scanning circuit 19 to the external power supply voltage vdd, 175 is a pre-transfer pulse booster, and 176 is a transfer pulse booster 177 is a pulse voltage converter for setting the high level of the basic clock to the external power supply voltage vdd, 178 is a substrate voltage generator that generates a second positive power supply voltage vsub by boosting from the external power supply voltage vdd, and 179 is a fine A back bias voltage generator for generating a back bias voltage vbb applied to the well of an nMOS transistor, 180 is a voltage value equal to the low level of the drive pulse Negative supply voltage generator for generating a l, 181 is an amplification means consisting of 11 to 18 of Figure 1. φT1, φT2, φTIN, φV1, φV2, φVIN, φFA, φFB, φH1, φH2, and φHIN are the same as those in FIG. , SBT, and STT indicate pulse voltages, and φRGH, φCPH, φSH1H, and φSH2H indicate pulses in which the high-level voltage is changed to the external power supply voltage vdd in FIG. 2 to clarify the connection relationship of each circuit block. It was described in. O1, O2, and GND are the same as those in FIG. Further, CLK is a basic clock input terminal having a high level of vcc, VDD is an external positive power supply input terminal, and STH and STV are trigger pulse input terminals having a high level of vcc that are input only once when power is turned on. VBK and HBK are output terminals for a vertical blanking pulse and a horizontal blanking pulse having a high level of vcc for forming a video signal, respectively.

When the power is turned on, the flip-flop 161 supplies the two-phase shift clocks φH1 and φH2 from the basic clock applied to the terminal CLK. Further, the trigger pulse input to the terminal STH is input from the OR circuit 163 to a ring counter composed of the horizontal scanning circuit 19 and the horizontal delay shift register 162 having the number of stages corresponding to the horizontal blanking period, and starts circulation. The output of the horizontal scanning circuit is converted into a pulse having a high level voltage as the external power supply voltage vdd by the voltage converter 174 and supplied to the amplifying means 140. A logic circuit 164 including a plurality of RS flip-flops outputs a timing signal from the output of each stage of the horizontal delay shift register 162 to the voltage converter 173. The voltage converter 173 outputs the high level voltage shown in FIG. Pulses φRG, φCP, φSH1, and φSH2 with voltage vdd are output to amplifying means 140. Further, the logic circuit 164 inverts φSB and φST shown in FIG. 2 and outputs a pulse having a low level as a ground voltage and a high level as a positive power supply voltage value vcc to the charge transfer control unit drive pulse generator 145 or 146, as shown in FIG. ΦTIN shown is supplied to the timing generation means 3 and φV1 and φV2 are supplied to the row selection control means 6. The AND circuit 165 takes the logical product of φH1, φH2 and the gate signal that determines the shift time T of the shift pulse generated at 164, generates φT1, φT2 shown in FIG. On the other hand, φV1 generated in the logic circuit 164 is output as a horizontal blanking pulse for forming a video signal from the terminal HBK.

  Also, the trigger pulse input to the terminal STV is input to a ring counter configured by a shift register in the row selection control means 6 and a vertical delay shift register 166 having the number of stages corresponding to the vertical blanking period via the OR circuit 167. Then, the cycle starts with φV1 and φV2 generated in the logic circuit 164. The RS flip-flop 168 generates a vertical blanking pulse from the first stage output and the last stage output of the vertical delay shift register 166, and outputs it from the terminal VBK to form a video signal. A 1/2 divider 169 divides the vertical blanking pulse by 1/2 to produce φFA and φFB, and supplies them to an interlace circuit in the row selection control means. On the other hand, 171 forms a predetermined potential barrier in the vertical charge transfer means 2 before the vertical scanning by the row selection control means starts, so that the output of the stage several stages before the final stage of the vertical delay shift register 166 is timed. The reset pulse for resetting the shift register in the generating means 3 is transmitted from the wiring 171 to the timing generating means 3.

  On the other hand, φV3T, φV4T, φV3LT, and φV4LT, which are delayed in phase by 2 bits of the moving speed of the potential barrier in the vertical charge transfer means 2 every horizontal scanning period, are generated by the logic circuit 170, and the pre-transfer pulse booster 175, This is supplied to the transfer pulse booster 176. That is, the counter CV that resets by φVIN and counts φV1 and φV2 outputs 1 when φVIN is input, and the count number increases by 1 for each horizontal scanning period. On the other hand, the counter CT which is reset by φHIN and counts φT1 and φT2 counts the time within one horizontal blanking period in units of shift periods 1 / fc of φT1 and φT2. Therefore, the time when the outputs of both counters coincide is 1 / fc for each horizontal scanning period, when the count value of CV is 1, with the start time of the shift time T of the shift pulses φT1, φT2 in the horizontal blanking. It will be late. In the present embodiment, each stage of the shift register 21 outputs a pulse that is 180 degrees out of phase in synchronization with both of the two-phase shift pulses, and both are used as timing signals, so that the vertical charge transfer means 2 The moving speed of the inner potential barrier is 1 / 2fc. Eventually, the phase at which the outputs of both counters coincide is delayed by 2 bits for the moving speed of the potential barrier for each horizontal scanning period. Therefore, using the coincidence signals of the outputs of both counters as a trigger, pulses having the same timing as φV3, φV4, φV3L, and φV4L in FIG. 2 are generated by the logic circuit, and the pre-transfer pulse booster 141 and the transfer pulse booster 142 To be supplied. The maximum count number of the counters CV and CT is T * fc. When the counter CV reaches this value, it is reset and starts counting from 1 again.

In order to generate the above timings 19, 6, 161 to 170, the internal power supply voltage vdd applied to the terminal VDD is stepped down by the power supply voltage drop unit 172 to reduce the power consumption and the degree of integration. A power source having a positive power source voltage vcc is supplied. Further, the positive power supply vcc is also supplied to the timing generating means 3 and the charge transfer control unit drive pulse generators 145 and 146 that do not require a high voltage. On the other hand, the external power supply voltage value vdd requires a high voltage to handle an analog voltage, and is the same value as the power supply of the amplifier 11 through which a large current flows. Similarly, the amplifying means 181 for outputting an analog voltage includes φRG, φCP, φSH1, and φSH2 having the external power supply voltage value vdd from the voltage converter 173 at a high level, and a high level voltage from the voltage converter 174. An output pulse of the horizontal scanning circuit having the external power supply voltage vdd is supplied to the amplifying unit 181. Further, a high voltage MOS 28 shown in FIGS. 3 to 6 in the drive pulse generating means 4 requiring a high voltage, and a DC applied to the bootstrap MOSs 68 and 73 in the transfer pulse generating means 7 shown in FIGS. An external power supply voltage value vdd is supplied as the voltage. The stepped-down positive power supply vcc is supplied to the OR circuit B1 and AND circuit B2 which perform the logical operation shown in FIG. 16A in the pre-transfer pulse booster 175. However, in order to perform high-speed boosting, an external power supply that does not step down is supplied to the booster B4 and the selection switch B5 shown in FIG. In order to connect the circuit blocks operating with these two power sources, the high level voltage of the pulse is set to vdd between the terminal Y1, terminal Y3, terminals V3LT, V4LT and the drive signal input switch in FIG. A voltage converter is provided. The configuration of the transfer pulse booster 176 is also the same as that of the transfer pulse booster 142. The substrate voltage generator 148 is also supplied with an external power supply because it requires a high voltage. In order to reduce the number of stages of charge pumping, the substrate voltage generator 178, the negative power supply voltage generator 180 having a voltage value vl equal to the low level of the driving pulse, and the back bias voltage generator 179 generating the back bias voltage vbb The charge pump is performed by a pulse with a high level applied to the terminal CLK by the voltage converter 177 and a basic clock with the high level set to the external power supply voltage vdd. Since the transistor of FIG. 12 having a thin oxide film has a withstand voltage of vcc, the amplifying means 140, the pulse voltage converters 173 and 174, and the pre-transfer pulse booster 175 supplied with pulses having the amplitude of the external power supply and the external power supply voltage The booster B4 and pulse voltage converter to be configured, the pulse voltage converter to configure the transfer pulse booster 176, the booster in the substrate voltage generator 178, the negative power supply voltage generator 179, and the back bias voltage generator 179 are configured. The enhancement type transistor of FIG. 10 is used for the nMOS, and the pMOS of FIG. 12 with the gate oxide film having the same thick gate oxide film 90 as the vertical charge transfer means 2 is used for the pMOS. It goes without saying that an additional process for producing such a pMOS is not necessary. Further, since the output of the pre-transfer pulse booster 175 becomes 2 vcc or more, the switches 62 to 65 constituting the interlace circuit connected to the bootstrap node shown in FIGS. Consists of 10 enhancement type transistors. Also, the PMOS 77 shown in FIG. 9 is the same as the PMOS shown in FIG. 12 except that the gate oxide film is the same thick gate oxide film 90 as the vertical charge transfer means 2. Further, the capacitors constituting the booster, the negative power supply voltage generator 180, and the back bias voltage generator 179 in the substrate voltage generator 178 are the same as the depletion type nMOS of FIG. 10 having the same thick oxide film as the bootstrap capacitor 66 and the like. The structure is as follows. When vcc is lower than vl, the charge transfer control unit drive pulse generators 145 and 146 are also formed of transistors having a thick oxide film.

  The clamp switch 15 and the signal write switches 16-1 and 16-2 shown in FIG. 1 in the amplification unit 140 are CMOS switches, and a complementary pulse having a high level voltage value of vcc is output from the logic circuit 164 to the amplification unit 140. The circuit for outputting φCP, φSH1, and φSH2 in the pulse voltage converter 173 may be eliminated. Further, the signal reading switches 18-1 and 18-2 shown in FIG. 1 are CMOS switches, and an inverting circuit is provided between the horizontal scanning circuit and the amplifying means instead of the pulse voltage converter to have a high level voltage value of vcc. The readout switches 18-1 and 18-2 may be driven with complementary pulses. Further, an A / D converter as described in JP-A-62-154981 may be provided to scan a digital value.

  According to the present embodiment, the timing generator consisting of 19, 6, 161 to 170 from the single basic clock applied to the terminal CLK and the trigger pulse applied to the terminals STH and STV is the driving means consisting of 3 and 4 Horizontal scanning means comprising 19, 173, 174, 181; row selecting means comprising 6, 7, 175, 176; and a plurality of positive units inputted from 145, 146 to the charge transfer controller drive pulse generator. Since one power source drive signal is generated, an easy-to-use solid-state imaging device that does not require a large number of timing signals, reduces the number of pins, and can be easily mounted can be realized. In order to obtain this effect, the timing generator may be composed of a known frequency divider.

  Further, the horizontal delay shift register 162 and the vertical delay shift register 166 are added to the row selection control means 6 having a shift register that operates in the vertical and horizontal scanning with a positive single power source drive signal, and the horizontal scanning circuit 19 comprising the shift register. Since the timing generator is configured by providing 161, 163 to 165, and 168 to 170 based on the added ring counter, the timing generator can be easily realized with a small additional circuit.

Further, the power supply voltage value vdd applied to the terminal VDD is equal to the power supply voltage value of the amplifier, and the timing generator composed of 19, 6, 161 to 170 is supplied from the power supply voltage dropr 172 that steps down the positive power supply. Operated by a high-voltage power supply vcc, drive means consisting of 3, 4; horizontal scanning means consisting of 19, 173, 174, 181; row selection means consisting of 6, 7, 175, 176; charge transfer control units from 145, 146 Since a plurality of positive single power source driving signals having a voltage of vcc are supplied to the driving pulse generator, there is no need to generate a power source voltage of the amplifier 11 through which a large current flows, and 19, 6, 161 Therefore, it is possible to reduce the power consumption and improve the integration of the timing generator consisting of 170 to 170.

    According to the present invention, the gate gate and the drain are not required, so that high integration is possible, and the signal charge and the unnecessary charge are not separated in the charge transfer path, so that transfer efficiency does not deteriorate. Further, even when unnecessary charges are extracted from the reset switch, it is possible to obtain a smear suppressing effect by sufficient sweeping without impairing the amplifier noise reduction effect. Further, when removing the fixed pattern noise due to reset noise and variations in the DC voltage of the amplifier, the effect of reducing the passband of the amplifier can be improved. Further, the input terminal voltage of the amplifier can be lowered, the power supply voltage of the amplifier can be lowered, and the power consumption and the voltage of the amplifying means can be reduced. Furthermore, a driver chip for driving the charge transfer control unit in the vertical charge transfer means is not required.

  Furthermore, according to the present invention, a driver for generating a high-speed two-phase shift pulse for driving a pulse line having a relatively large capacity in a shift register in the driving means is not required, and the power consumption of the imaging apparatus can be reduced.

  Further, since a large voltage in the row selection means can be applied only to the transfer pulse line in the transfer pulse generation means and the portion connected to the transfer pulse application line, the high integration of the row selection means can be achieved. it can. Furthermore, an external driver for generating a transfer pulse is not necessary. In addition, when performing two rows simultaneous independent reading, the area of the transfer pulse generator constituting the row selection means can be reduced by halving the number of charge pump capacitors. On the other hand, it is possible to output a transfer pulse having a voltage three or more times as high as the positive power supply voltage vcc to the selected row using a control signal equal to or lower than the positive power supply voltage value vcc as a trigger. Further, an external driver for generating the pre-transfer pulse transfer pulse is not required. In addition, when performing two-row simultaneous independent reading, the number of charge pump capacitors can be halved to reduce the area of the transfer pulse generator.

It is a whole block diagram of one Example of this invention. It is a drive pulse timing diagram of one Example of this invention. FIG. 2 is a circuit configuration diagram and a drive pulse timing diagram of the first embodiment of the drive means comprising the timing generation means 3 and the drive pulse generation means 4 of FIG. FIG. 4 is a circuit configuration diagram of a second embodiment of the driving means comprising the timing generating means 3 and the driving pulse generating means 4 of FIG. 1 and its driving pulse timing diagram. FIG. 4 is a circuit configuration diagram of a third embodiment of driving means comprising timing generating means 3 and driving pulse generating means 4 of FIG. FIG. 6 is a circuit configuration diagram of a fourth embodiment of drive means comprising timing generation means 3 and drive pulse generation means 4 of FIG. FIG. 2 is a circuit configuration diagram of a first embodiment of a row selection unit comprising a row selection control unit 6 and a transfer pulse generation unit 7 of FIG. 1 and a drive pulse timing diagram thereof. FIG. 4 is a circuit configuration diagram of a second embodiment of a row selection means comprising the row selection control means 6 and transfer pulse generation means 7 of FIG. 1 and its drive pulse timing diagram. FIG. 2 is a cross-sectional view taken along the line A-A ′ of the vertical charge transfer means 2 formed in the first impurity layer having a thick oxide film thickness and a low concentration shown in FIG. 1. Cross-sectional structure of a MOS transistor formed in a third impurity layer having a thick oxide film thickness used for a part of the transfer pulse generation means 7 and the drive pulse generation means 4 in FIG. 1 and having a lower surface concentration than other parts FIG. The MOS transistor formed in the third impurity layer having a thick oxide film thickness used for the transfer pulse generating means 7 and other part of the drive pulse generating means 4 in FIG. 1 and having a lower surface concentration than the other parts. FIG. 5 is a cross-sectional structure diagram of a second embodiment. Thin oxide film thickness and high concentration used for scanning circuit 9 and amplification means 11 to 18 in FIG. 1, transfer pulse generation means 7 and the remaining part of drive pulse generation means 4, row selection control means 6 and timing generation means 3 FIG. 5 is a cross-sectional structure diagram of a MOS transistor having a second impurity layer. FIG. 2 is a cross-sectional structure diagram of B-B′-B ″ of the first output holding capacitor 14 of FIG. 1. It is a whole block diagram of the CCD type solid-state image sensor incorporating the conventional drive circuit. FIG. 6 is a diagram showing an overall circuit configuration of a second embodiment. FIG. 16 is a circuit configuration diagram of the pre-transfer pulse booster 141 in FIG. 15 and its drive pulse timing diagram. FIG. 6 is a diagram showing an overall circuit configuration of a third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Two-dimensionally arranged photoelectric conversion element, 2 ... Vertical charge transfer means, f ... Repeating part last electrode of vertical charge transfer means, 2-1 ... Repeating part electrode of vertical charge transfer means, 2-2 ... Amplification means 2. Gates constituting the charge transfer control unit, 2-3 ... Charge storage gates constituting the charge transfer control unit of the vertical charge transfer means 2, 2-4 ... Outputs constituting the charge transfer control unit of the vertical charge transfer means 2 Gate, 3... Timing generating means having a shift register that operates with a single positive power source constituting the driving means, 4... Supplying a driving pulse having a low negative voltage constituting the driving means to the driving pulse line 5 Drive pulse generating means, 5 ... drive pulse line common to transfer pulse line, 6 ... row selection control means operating with a single power source constituting the row selection means, 7 ... positive power supply constituting the row selection means Transfer pulse with high second voltage value higher than voltage value Transfer pulse generating means for output, 8, 9, 10 ... charge transfer control unit drive line, 11 ... amplifier constituting the amplifying means, 12 ... reset switch for undesired charge constituting the amplifying means, 13 ... amplifying means The feedback capacitor to be configured, 14 ... the first output holding capacitor that constitutes the amplifying means, 15 ... the clamp switch that performs differential processing that constitutes the amplifying means, 16-1, 16-2 ... the first and second that constitute the amplifying means A signal write switch to the second output holding capacitor, 17-1... A first second output holding capacitor constituting the amplifying means, 17-2. A second second output holding capacitor constituting the amplifying means, 18 -1, 18-2: Signal reading switches from the first and second second output holding capacitors constituting the amplifying means, 19 ... horizontal scanning circuit, 20 ... scanning start pulse voltage converter, 21 ... timing generating means Shift registers, 22-1, 22-2 ... Shift the low level of the timing signal to a negative value First and second coupling capacitors constituting the pre-pulse generator, 23-1, 23-2 ... bias setting switch constituting the pre-drive pulse voltage converter, 24 ... first constituting the drive means
1 switch, 25... Power supply line for supplying high level of drive pulse, 26... Second switch constituting drive means, 27... Negative power supply line for supplying low level voltage of drive pulse, 28. High voltage MOS transistor, 29 ... Positive power supply line, 30, 31 ... Switch constituting pulse width expander, 32 ... Bias setting switch constituting pulse width expander, 33 ... Ground line, 41 ... Pre-drive Buffer nMOS transistor constituting a pulse voltage converter, 42... PMOS transistor constituting a pre-drive pulse voltage converter, 43... NMOS transistor having a negative threshold voltage value constituting a pre-drive pulse voltage converter, 51 ... nMOS transistor constituting pre-drive pulse voltage converter, 60 ... pre-transfer pulse negative voltage converter, 61 ... shift register constituting row selection control means, 62, 63, 64, 65 ... row selection Switch of interlace circuit constituting control means, 66 ... Bootstrap capacity of pre-transfer pulse switch MOS constituting pre-transfer pulse voltage converter, 67 ... Pre-transfer pulse constituting pre-transfer pulse voltage converter Switch MOS, 68... Bootstrap MOS constituting pre-transfer pulse voltage converter, 69... Transfer pulse switch MOS constituting transfer pulse generating means, 70... Bootstrap of transfer pulse switch MOS constituting transfer pulse generating means. Capacitance 71... Transfer pulse switch MOS high breakdown voltage MOS constituting transfer pulse generating means 72 72 Bootstrap capacitance of high breakdown voltage MOS 71 73 Bootstrap MOS of high breakdown voltage MOS 71 74 Pre-transfer pulse Application line, 75... NMOS transistor for pulse input constituting a pre-transfer pulse voltage converter, 77. PMOS transistor that constitutes a pre-driving pulse voltage converter, 78... NMOS transistor having a negative threshold voltage value that constitutes a pre-driving pulse voltage converter, 81... N-type substrate, 82. P ... 83, first photodiode n-well, 84 ... second photodiode n-well, 85 ... n layer constituting photodiode 1, 86 ... photodiode surface p layer, 87 ... double well p layer, 88 ... vertical N-type channel layer of charge-charge transfer means 2, 89 ... gate electrode, 90 ... thick gate oxide film, 91 ... surface concentration is higher than the first P well, lower than the second p well, and shallower than the first p well 3rd p-well, 111... High concentration second P-well, 112... NMOS transistor field p-layer, 113... NMOS transistor source / drain n-type diffusion layer, 114. 116 ... pMOS transistor source / drain p-type diffusion layer, 117 ... locus oxide film, 118 ... thin gate oxide film, 121 ... capacitor forming electrode, 122 ... insulating film per unit area larger than the thin gate oxide film 118,123 ... Wiring, 125 ... photodiode, 126 ... transfer gate, 127 ... row selection means, 128 ... transfer pulse line, 129 ... vertical charge transfer means, 130 ... drive means, 131 ... drive pulse line, 132 ... leading gate, 133 ... leading drain , 134-1 to 134-3, first to third horizontal charge transfer elements, 135-1 to 135-3, output circuits of the first to third horizontal charge transfer elements 134-1 to 134-3, 136 -1 to 136-3: Gate, 140, 181 ... Amplifying means, 141, 175 ... Pre-transfer pulse booster, 142, 176 ... Transfer pulse booster, 143-1, 143-2 ... Terminal of horizontal scanning circuit 19 Two-phase shift pulse lines connected to H1 and H2, 144... DC clamp voltage application line, 145 and 146... 2-2, a charge transfer control unit drive pulse generator for generating a drive pulse to the charge storage gate 2-3, 147 ... a charge storage ground voltage and a low level of the transfer pulse at the output gate 2-4 constituting the charge control unit Output gate DC bias generator for applying an intermediate DC voltage of negative voltage vl, 148, 178 ... Substrate voltage generator for generating a second positive power supply voltage vsub by boosting from a positive power supply, 149, 179 ... Fine nMOS Back bias voltage generator for generating back bias voltage vbb applied to the well of the transistor, 150, 180... Negative power supply voltage generator having a voltage value vl equal to the low level of the drive pulse, B1... Applied to terminals V3LT and V4LT OR circuit which inputs a positive single power supply driving signal inputted thereto and outputs a logical sum thereof, B2... Shift pulse applied to terminal H1, and positive single applied to terminal V3LT or V4LT. AND circuit that outputs a logical product with the power supply drive signal, B3... Voltage converter for setting the voltage amplitude of the output pulse of the AND circuit to a voltage amplitude obtained by adding the negative power supply voltage value vl and the positive power supply voltage value vcc, B4. Booster, B5... Selection for outputting the booster output of the terminal Y4 to the pre-transfer pulse applying line 74-1 or 74-2 based on the positive single power source driving signal applied to the terminal V4LT or V3LT. Switches, mn1, mn2, mn3... NMOS constituting the OR circuit B1, mp1, mp2, mp3... PMOS constituting the OR circuit B1, mn4, mn5, mn6, mn7... NMOS constituting the AND circuit B2, mp4, mp5, mp6, mp7... pMOS constituting AND circuit B2, 151-1, 151-2... Initial voltage setting nMOS for initializing terminals Y6 and Y4 in the booster by the output of OR circuit B1, 152. NMOS, 153... Charge pump capacitance, 154... Voltage limiter, 155... PMOS grounded on the gate, 156... NMOS having the inverted output value terminal Y5 of the AND circuit connected to the gate, 157-1, 157-2. nMOS, 158-1, 158-2 ... drive signal input switch, 159-1, 159-2 ... bootstrap capacitance, 160-1, 160-2 ... gate connected to inverted output terminal Y7 of the OR circuit Reset switch, 161... Flip-flop, 162... Horizontal delay shift register having the number of stages corresponding to the horizontal blanking period, 163... OR circuit, 164... Logic circuit including a plurality of RS flip-flops, 165. ... vertical delay shift register having the number of stages corresponding to the vertical blanking period, 167 ... OR circuit, 168 ... RS flip-flop, 169 ... 1/2 frequency divider, 170 ... φ with counter CV and counter CT 3LT, φV3, φV4LT, φV4 logic circuit, 171... Wiring for transmitting a reset pulse for resetting the shift register in the timing generating means 3, 172... Power supply voltage droprs... 173 and 174. A pulse voltage converter in which a high level of a pulse having the same high level as the internal power supply vcc constituting the external power supply voltage vdd is provided;
7 ... Pulse voltage converter for setting the high level of the basic clock to the external power supply voltage vdd, T1, T2 ... Two-phase shift pulse having a single positive power supply value for driving the shift register 21 constituting the timing generating means Input terminal, TIN: Scan start pulse input terminal which is a single positive power supply value drive signal for driving the shift register 21 constituting the timing generating means, VL: Negative power supply voltage input terminal, VM: High level voltage of drive pulse Input terminal, Vcc... Single positive power supply voltage input terminal, GND... Ground terminal, V1, V2... Two-phase shift pulse input having a single positive power supply value for driving shift register 61 constituting row selection control means Terminal, VIN... Scan start pulse input terminal which is a single positive power supply value drive signal for driving the shift register 61 constituting the row selection control means, FA, FB. Two-phase interlace pulse input terminal, which is a single positive power supply value drive signal for driving the interlace circuit constituting the control means, V3, V4... High second voltage value higher than the positive power supply voltage value Transfer pulse application terminals, V3L, V4L, a pre-transfer pulse application terminal having a third voltage value higher than the positive power supply voltage value and lower than the second voltage value at a high level, SB : drive pulse application of the gate 8 ST : drive pulse application terminal of charge storage gate 9, OG : DC voltage application terminal to output gate 10, RG: reset pulse input terminal having positive single power supply value of reset switch 12, VC: DC clamp voltage Input terminal, CP: Clamp pulse application terminal with positive single power supply value of clamp switch 15, SH1, SH2: Sample hole with positive single power supply value of read switches 16-1, 16-2 Pulse application terminal, O1, O2... Signal output terminal, H1, H2, HIN... Two-phase shift pulse and scan start pulse input terminal of horizontal scanning circuit 19 having a single positive power supply value,... Gate of transfer pulse switch MOS69 Terminal, b: gate terminal of transfer pulse switch MOS high voltage MOS 71, V3T, V4T: positive single for generating a transfer pulse having a second voltage value vh higher than the voltage value of the positive power supply at a high level Power supply drive signal application terminal, V3LT, V4LT ... Positive single power supply drive signal application terminal for generating a pre-transfer pulse having a voltage value vhm whose high level is higher than the positive power supply voltage value vcc and lower than the second voltage value , SBT... Positive single power source driving signal application terminal for generating a driving pulse for the gate 2-2, STT... Positive single power source driving for generating a driving pulse for the charge storage gate 9. Signal application terminal, Y1, Y7 ... Output of OR circuit B and its inverted output terminal, Y2, Y5 ... Output of AND circuit B2 and its inverted output terminal, Y3 ... Output terminal of boost pulse voltage converter B3, Y4 ... Booster B4 output terminal, Y6: booster internal terminal, P1: gate terminal of switch 157-1 or 157-2, CLK: basic clock input terminal with high level of vcc, VDD: external positive power supply input terminal, STH, STV ... A high level vcc trigger pulse input terminal that is input only once when the power is turned on, VBK, HBK ... high level vcc vertical blanking pulse and horizontal blanking pulse output terminals for video signal formation, HBL ... horizontal feedback Line period, vl ... Low level voltage value of negative drive pulse, vm ... High level voltage value of drive pulse, vcc ... Single positive power supply voltage value, vh ... Positive power supply voltage A second voltage value higher than the value, vhm ... a third voltage value higher than the positive power supply voltage value and lower than the second voltage value, s ... a potential well for transferring the first signal charge or the second signal charge. The time interval of the scan start pulse input to the terminal T1 to create, n1, n2,... Of the scan start pulse input to the terminal T1 to create the potential well for transferring the first unnecessary charge and the second unnecessary charge. Time interval, T ... application time of two-phase shift pulse, Ts1 ... first output writing time to the first output holding capacitor, Ts2 ... difference value writing time to the second first output holding capacitor, Tn ... unnecessary charge Sweep time, φn, φn + 1, φn + 2, φn + 3, n row, n + 1, n + 2, n + 3 row output of shift register 21, fc, 2-phase pulse of shift register 21 Frequency, tf ... Driving time of drive pulse line voltage, tr ... Falling time of drive pulse line voltage , 0: ground voltage value, vh ′: maximum voltage value at gate terminal A, vh ″: maximum voltage value at gate terminal b, vthd: threshold voltage of depletion type nMOS of FIG. 10 or FIG. Or, the threshold voltage of the enhancement type nMOS in FIG. 11, vsub... Substrate voltage, vbb... Back bias voltage, vth... Threshold voltage of nMOS in FIG. 12, .phi.V3LT. When the Y4 terminal is initialized, vhp2... The maximum voltage value of the gate terminal P2, .phi.V3T, .phi.V4T, .phi.V3LT, .phi.V4LT, .phi.SBT, .phi.STT. Pulse voltage, φRGH, φCPH, φSH1H, φSH2H: High level voltage is external power supply voltage v
Pulse that became dd.

Claims (9)

Two-dimensionally arranged photoelectric conversion elements on the same semiconductor substrate, vertical charge transfer means having a plurality of electrodes for transferring signal charges provided between the photoelectric conversion elements in the vertical direction, and the vertical charges A driving means for sequentially supplying a driving pulse for vertical charge transfer to a driving pulse line connecting one horizontal parallel electrode of the transferring means, and a signal charge of the photoelectric conversion element is transferred to the vertical charge transferring means one by one in parallel; Row selection means for supplying a transfer pulse to the drive pulse line, and horizontal scanning means for transferring a signal from the vertical charge transfer means in the horizontal direction, the drive means including a plurality of at least one signal charge In order to transfer individual charges, a plurality of separated potential wells are formed across the plurality of electrodes in the charge transfer means, and the row selection means transfers signal charges in the plurality of potential wells. Well for potential In the solid-state imaging device that transfers signal charges to the driving device, the driving unit includes a timing generation unit including a shift register for generating a timing signal of a driving pulse by inputting a logic signal, and the timing signal for each driving pulse line. Based on
Drive and a second switch to the other end of the second power supply and one end of the first switch and the drive pulse line shall be the other end of the first power supply and one end of the drive pulse line to open and close-out Dzu consists of a pulse generating means, said row selection means comprises a row selection control means for generating a control signal for specifying the selected row by inputting a logic signal, said first-out basis Dzu to the control signal, the second A solid-state imaging device comprising: a transfer pulse generating means comprising: a third switch having one end of the drive pulse line that is turned on when both of the switches are off and the other end of the transfer pulse application line .   The timing generation means includes a first switch that is turned on by the first output of the shift register and connects the positive power supply line and the output, and N times half the shift period from the first output (N is 2 or more) 2. A solid-state device according to claim 1, further comprising a pulse width expander comprising a second switch which is turned on by the second output of the shift register delayed by an integer) and connects the ground line and the output. Image sensor.   2. The solid-state image pickup device according to claim 1, wherein the drive pulse generating means includes a high voltage MOS transistor whose gate is connected to a DC voltage between the drive pulse line and the drive pulse line.   The second power supply is a negative power supply, and the drive pulse generating means generates a drive pulse having a negative voltage from the timing signal and the negative power supply at a low level on the drive pulse line. The solid-state imaging device according to claim 1.   5. The solid-state image pickup device according to claim 4, further comprising a negative voltage generator for generating the negative power source on the same semiconductor.   The transfer pulse generating means has an output portion connected to the gate of the MOS transistor constituting the third switch, and a selected row and a non-selected row in a period in which no transfer pulse is applied from the control signal and the negative power source. 5. The solid-state image pickup device according to claim 4, further comprising a generation pre-transfer pulse voltage converter for generating a negative voltage.   The transfer pulse generating means outputs a transfer pulse having a high second voltage value higher than the voltage value of the logic signal applied to the transfer pulse application line to the transfer pulse line of the selected row. The solid-state imaging device according to claim 1.   The driving means and the row selecting means are composed of a first MOS transistor having a gate oxide film thickness equal to that of the vertical charge transfer means and a second MOS transistor having a gate oxide film thickness smaller than that of the first MOS transistor. 8. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is used. The driving means and the row selection means are a first MOS transistor formed in a first impurity layer, and a second impurity layer formed in a second impurity layer having a lower surface concentration than the first impurity layer. the solid-state imaging device of claims paragraph 1 or et paragraph 7, wherein it is composed of MOS transistors.

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