JP4415588B2 - Recycled wafer reclaim processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, a semiconductor wafer into which ions have been implanted is superposed on a support wafer to form a laminated body, and the laminated body is heat-treated to regenerate a thick release wafer separated from the thin film of the semiconductor wafer in the ion-implanted region. about the how to. More particularly, for manufacturing a wafer such as SOI (Silicon On Insulator) wafer, in a so-called ion implantation delamination method, but about the reproduction process how the layer transferred wafer to be replicated.
[0002]
[Prior art]
Conventionally, as a method for manufacturing an SOI wafer, ions are implanted into a main surface of a semiconductor wafer to form an ion implantation region inside the semiconductor wafer, and the main surface of the semiconductor wafer is overlaid on the main surface of a support wafer and stacked. There is known a method of manufacturing an SOI wafer by forming a body, further heat-treating the laminated body at a predetermined temperature, and peeling the ion-implanted wafer after bonding. Both the semiconductor wafer and the support wafer used in this method have the same diameter and the same thickness, and the semiconductor wafer is peeled into a thin film using the ion implantation region implanted into the main surface of the semiconductor wafer as a cleavage plane. In this technique, the support wafer is heat-treated together with the thin film to strengthen the bond to form an SOI wafer. In this method, an SOI wafer having a good mirror surface and a high uniformity in the thickness of the SOI layer can be obtained relatively easily.
On the other hand, when a bonded wafer such as an SOI wafer is manufactured by such an ion implantation separation method, one separation wafer is inevitably produced as a by-product. In this ion implantation separation method, by regenerating the by-product separation wafer, a plurality of SOI wafers can be obtained using substantially one semiconductor wafer, so that the cost can be greatly reduced. I can do it.
[0003]
However, the wafer is generally chamfered, and even if the wafers with the same outer diameter are stacked, the entire periphery does not come into contact with each other. There was a problem that the periphery remained without being peeled, and a step was generated around the peeled wafer produced as a by-product. Further, a damage layer due to ion implantation exists on the separation surface of the separation wafer, and the surface roughness is large, and the separation wafer cannot be used as it is. Therefore, in order to regenerate this exfoliated wafer, it is necessary to remove those steps and damaged layers, improve the surface roughness and regenerate, and the generation of particles due to the ion implantation layer remaining on the steps is reduced. It was also necessary to prevent.
Conventionally, as a method for reclaiming a peeled wafer of this type, a peeled wafer that polishes the main surface of the peeled wafer after removing the ion implantation layer remaining on the step around the separation surface of the peeled wafer by chamfering or etching. A reproduction processing method is known (see, for example, Patent Document 1). In this regeneration processing method, since the ion implantation layer is removed by chamfering or the like, the surface roughened by the chamfering or the like is then subjected to so-called mirror polishing (mirror chamfering). In this separation wafer reclaim processing method, by removing the ion implantation layer, the generation of particles due to the presence of the ion implantation layer is prevented, and the damage layer on the surface of the separation wafer is removed. Roughness can be improved.
[0004]
[Patent Document 1]
JP 2001-155978 A (Claim 1, paragraph number 0032, paragraph number 0052)
[0005]
[Problems to be solved by the invention]
However, in the conventional method for reclaiming a peeled wafer shown in Patent Document 1, mirror polishing is performed after the ion-implanted layer is removed by chamfering or etching, so that the surface roughness of the peeled wafer can be reduced. As a result, the time required to regenerate the peeled wafer is increased, and the machining allowance for grinding is relatively increased, resulting in a decrease in the number of times the reprocessing can be performed.
An object of the present invention, as well as to reduce the shorter to play cost processing time required to regenerate the layer transferred wafer, providing a reproduction process how a layer transferred wafer capable of increasing the number of plays by decreasing the allowance at the time of reproduction There is to do.
[0006]
[Means for Solving the Problems]
In the invention according to claim 1, as shown in FIG. 1, the main surface of the semiconductor wafer 13 has a main flat portion 13d and a chamfered portion 13c formed around the main flat portion 13d. Ions are implanted only into the portion 13d to form an ion implantation region 13b inside the semiconductor wafer 13, and the laminated body 16 is formed by superimposing the main flat portion 13d of the semiconductor wafer 13 on the main surface of the support wafer 14. This is a method of reprocessing the thick release wafer 12 obtained by heat-treating the body 16 at a predetermined temperature and separating the semiconductor wafer 13 from the thin film 17 at the ion implantation region 13b.
The characteristic point is that the semiconductor wafer 13 is sandwiched between the upper and lower chucks 21 and 22 and rotated horizontally, and the polishing liquid 23 is dropped, and a polishing roller 24 made of a drum-shaped grindstone having a concave groove 24b formed around it. Is rotated and brought into contact with the periphery of the semiconductor wafer 13 so that the main flat portion 13d of the semiconductor wafer 13 protrudes from the chamfered portion 13c and has a ring-shaped step 13e, and ions are formed so as not to generate a step around the periphery. The separation wafer 12 is obtained by separating the semiconductor wafer 13 from the thin film 17 over the entire surface of the implantation region 13b.
[0007]
In the separation wafer regeneration processing method according to the first aspect, since the semiconductor wafer 13 is separated from the thin film 17 over the entire surface of the ion implantation region 13b, no step is generated around the separation surface 12a of the separation wafer 12. . For this reason, the chamfering process or etching conventionally performed in order to remove the ion implantation layer remaining in the step can be omitted. Therefore, in the invention according to the first aspect, the processing time for regenerating the peeled wafer is shortened compared to the conventional method, and the regenerating cost can be reduced, and the machining allowance 12c at the time of regenerating can be decreased to increase the number of times of regenerating. it can.
Further, since the main flat portion 13d from the chamfered portion 13c is formed a semiconductor wafer 13 so as to have a ring-shaped stepped 13e projects, the main outer diameter D ₁ of the flat portion 13d is smaller than the outer diameter D ₂ of the support wafer 14 Thus, since all of the main flat portion 13d is in contact with the support wafer 14, the semiconductor wafer 13 can be relatively easily separated from the thin film 17 over the entire surface of the ion implantation region 13b.
[0008]
The invention according to claim 2 is the invention according to claim 1, wherein the semiconductor wafer 13 further includes a ring-shaped flat portion 13f between the main flat portion 13d and the chamfered portion 13c, as shown in FIG. The width w of the ring-shaped flat portion 13f is 0.1 to 2 mm.
This peel wafer reproduction processing method according to claim 2, makes it easy to form the main flat portion 13d of smaller diameter than the outer diameter D ₂ of the support wafer 14 by forming a ring-shaped flat portion 13f, By setting the width w of the ring-shaped flat portion 13 f to 0.1 to 2 mm, the entire overlapping surface of the semiconductor wafer 13 can be brought into contact with the support wafer 14. Here, when the width w of the ring-shaped flat portion 13f is less than 0.1 mm, there is a problem that a step is generated around the peeled wafer 12, and when the width w exceeds 2 mm, the SOI device creation area is narrowed. is there.
[0009]
The invention according to claim 3 is the invention according to claim 2, and as shown in the enlarged view of FIG. 2, the end face connecting the double-sided chamfers 13 c and 13 g respectively formed on both main surfaces of the semiconductor wafer 13. A deviation amount s in which the center p deviates from the center c in the thickness direction of the semiconductor wafer 13 is 50 μm or less.
In the method for reclaiming a peeled wafer according to the third aspect, the main flat portion 13d is further easily formed by biasing the center p with respect to the center c. Here, when the deviation amount s exceeds 50 μm, it becomes difficult to handle the peeled wafer 12 in subsequent polishing or the like.
[0010]
The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the ring-shaped step 13e is 5 to 100 μm.
According to the fourth aspect of the present invention, it is possible to form the ion implantation region 13b by implanting ions only into the main flat portion 13d by setting the ring-shaped step 13e to 5 to 100 μm. To. Here, if the ring-shaped step 13e is less than 5 μm, there arises a problem that the number of reuses is reduced. Further, when the ring-shaped step 13e exceeds 100 μm, the step 13e starts to be drooped, and it becomes difficult to superimpose all the main flat portions 13d on the main surface of the support wafer 14. The ring-shaped step 13e is more preferably 10 to 50 μm.
[0011]
The invention according to claim 5 is the invention according to any one of claims 1 to 4, further comprising the step of polishing the separation surface 12 a of the release wafer 12 to obtain a reclaimed wafer, as shown in FIG. 3. In addition, the machining allowance 12c on the separation surface 12a of the release wafer 12 during polishing is 0.2 μm or more and 1 μm or less.
In the method for reclaiming a peeled wafer described in claim 5, the processing time for reclaiming the peeled wafer 12 is shortened by setting the machining allowance 12c at the time of polishing shown in FIG. 3C to 1 μm or less. It is possible to reduce the reproduction cost and sufficiently increase the number of reproductions. Here, when the machining allowance 12c exceeds 1 μm, there is a problem that the flatness of the polished surface is deteriorated, and when the machining allowance 12c is less than 0.2 μm, there is a problem that the damaged region on the separation surface cannot be removed.
[0012]
The invention according to claim 6 is the invention according to claim 5, wherein the reclaimed wafer obtained by polishing the separation surface 12 a of the release wafer 12 is heat-treated at 900 ° C. to 1100 ° C. in an oxidizing atmosphere. And
In the method for reclaiming a peeled wafer according to the sixth aspect of the present invention, damage to the chamfered portion 13c caused at the time of ion implantation can be reduced by heat treating the reclaimed wafer 32.
[0013]
The invention according to claim 7 is the invention according to any one of claims 1 to 6, wherein the recycled wafer 32 is used for the semiconductor wafer 13.
In the method for reclaiming a peeled wafer according to the seventh aspect, by making the first semiconductor wafer 13 relatively thick, the reclaimed wafer 32 can be reused twice or more. Ru can be further reduced manufacturing cost.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, when the SOI wafer 11 is manufactured, a separation wafer 12 is generated as a secondary. To manufacture the SOI wafer 11, a semiconductor wafer 13 as a bond wafer and a support wafer 14 as a base wafer are prepared as shown in FIG. In this embodiment, these wafers 13 and 14 are respectively manufactured by the Czochralski method, have the same diameter and the same thickness, and chamfered portions 13c, 13g, 14a, and 14b around both main surfaces. Are formed respectively. These wafers 13 and 14 are RCA cleaned wafers after being polished on both sides.
[0015]
However, a main flat portion 13d is formed on one main surface of the semiconductor wafer 13, and the main flat portion 13d is formed so as to protrude from a chamfered portion 13c formed in the periphery and to have a ring-shaped step 13e in the periphery. . In order to manufacture the semiconductor wafer 13 in which the main flat portion 13d protrudes from the chamfered portion 13c, the ring-shaped step 13e is simultaneously formed when chamfering the periphery of the wafer sliced from the ingot to form the chamfered portions 13c and 13g. . Here, FIG. 2 shows a chamfering device 20 for forming a chamfered portion 13c around the wafer.
[0016]
The chamfering apparatus shown in FIG. 2 sandwiches a wafer 10 sliced from an ingot from above and below, and rotates the wafer 10 horizontally and upper and lower chucks 21 and 22, a pipe 23a for supplying an abrasive 23, and grinding around the wafer. Thus, the polishing roller 24 is formed with the chamfered portions 13c and 13g. The upper and lower chucks 21 and 22 are provided with support shafts 21a and 22a, respectively, and are connected to a rotation motor (not shown). The upper and lower chucks 21 and 22 are configured to have a diameter smaller than the wafer diameter, and have a size such that the periphery of the wafer 10 is exposed by sandwiching the wafer 10 from above and below. The polishing roller 24 is made of a grindstone and has a drum shape. The polishing roller 24 is provided with a support shaft 24a, and is rotated by a rotation motor (not shown) so that the surface of the polishing roller 24 faces the periphery of the wafer 13. The polishing roller 24 is formed with a groove 24b around the wafer 13 so as to form chamfered portions 13c, 13g and a ring-shaped step 13e. The pipe 23a is provided at a position where the abrasive 23 is supplied to the wafer chamfered surface.
[0017]
In order to form the chamfered portion 13c and the ring-shaped step 13e around the wafer 10 by the chamfering device 20, the wafer 10 is sandwiched between the upper and lower chucks 21 and 22 and horizontally rotated by a rotation motor (not shown). Then, the polishing roller 24 is rotated while dropping the polishing liquid 23 from the pipe 23a to contact the periphery of the wafer 10, and the periphery is ground by the polishing roller 24 to form the chamfered portion 13c and the ring-shaped step 13e. Thereafter, the wafer 10 is subjected to mechanical polishing (lapping), etching, PCR, mirror polishing (polishing) and cleaning steps, and a semiconductor wafer 13 having a ring-shaped step 13e with the main flat portion 13d protruding from the chamfered portion 13c is obtained. Manufactured.
[0018]
Here, in this embodiment, as shown in the enlarged view of FIG. 2, the semiconductor wafer 13 shows an example in which a ring-shaped flat portion 13f is formed between the main flat portion 13d and the chamfered portion 13c. The width w of the flat portion 13f is in the range of 0.1 to 2 mm. Further, the deviation amount s in which the center p of the end face connecting the double-sided chamfers 13c and 13g formed on both main surfaces of the semiconductor wafer 13 from the center c in the thickness direction of the semiconductor wafer 13 is 50 μm or less. A double-sided part 13c is formed. The ring-shaped step 13e, that is, the thickness t of the main flat portion 13d is formed to be in the range of 5 to 100 μm.
[0019]
Referring back to FIG. 1A, the semiconductor wafer 13 manufactured in this way is first thermally oxidized, whereby an oxide film 13a (SiO ₂ film) that is an insulating film is formed on the main flat portion 13d that is the overlapping surface of the wafer 13. ) Is formed, hydrogen ions (H +) as hydrogen gas ions of 3.0 × 10 ¹⁶ / cm ² or more or hydrogen molecular ions (H ²⁺ ) of 1.5 or more are formed on the main flat portion 13d of the wafer 13. Ion implantation is performed with a dose amount of × 10 ¹⁶ / cm ² or more (FIG. 1A). Here, reference numeral 13b in FIG. 1 (a) denotes an ion implantation region formed in the main flat portion 13d by implantation of hydrogen gas ions or hydrogen molecular ions, and this ion implantation region 13b is parallel to the oxide film 13a. That is, it is formed parallel to the surface of the semiconductor wafer 13. Further, in the case of hydrogen gas ions (H ⁺ ), an injection amount that is about twice that of hydrogen molecular ions (H ²⁺ ) is required. Instead of hydrogen gas ions and hydrogen molecular ions, helium ions (He +) may be implanted together with hydrogen gas ions or hydrogen molecular ions. In this case, the dose of helium ions is preferably 0.5 × 10 ¹⁶ / cm ² or more.
[0020]
Next, the main surface of the support wafer 14 shown in FIG. 1B is overlapped with the main flat portion 13d of the semiconductor wafer 13 through the oxide film 13a at room temperature to form a laminate 16 (FIG. 1C). . The laminated body 16 is heated to a temperature of 500 to 800 ° C. in a nitrogen (N ₂ ) atmosphere, and kept in this temperature range for 5 to 30 minutes to perform a thin film separation heat treatment. As a result, the semiconductor wafer 13 is broken at the ion implantation region 13b and separated into an upper thick release wafer 12 and a lower thin film 17 (FIG. 1D). Here, the characteristic point of the present invention is that the separation wafer 12 is obtained by separating the semiconductor wafer 13 from the thin film 17 over the entire surface of the ion implantation region 13b so as not to cause a step in the periphery.
[0021]
Next, the temperature of the laminated body 16 in which the semiconductor wafer 13 is broken in the ion implantation region 13b is lowered, and the separation wafer 12 is separated from the support wafer 14 (hereinafter simply referred to as the support wafer 14) on which the thin film 17 is laminated via the oxide film 13a. Remove. The support wafer 14 is heated to 900 to 1200 ° C. in an oxygen (O ₂ ) or nitrogen (N ₂ ) atmosphere, and heat treatment is performed for 30 to 120 minutes in this temperature range (FIG. 1E). This heat treatment is a heat treatment for strengthening the bonding of the thin film 17 to the support wafer 14. Further, the separation surface of the support wafer 14 is annealed or polished (touch polishing) to be smoothed (FIG. 1 (g)). As a result, the support wafer 14 becomes the SOI wafer 11.
[0022]
On the other hand, since the semiconductor wafer 13 is separated from the thin film 17 over the entire surface of the ion implantation region 13b, no step is generated around the separation wafer 12. Then, the separation wafer 12 is regenerated by polishing the separation surface 12a. As shown in FIG. 3A, when the oxide film 12d formed by heat treatment or the like remains on the second main surface opposite to the separation surface 12a of the separation wafer 12, the separation wafer 12 is polished. Before the step, it is preferable to remove the oxide film 12d as shown in FIG. 3B by immersing the peeled wafer 12 in hydrofluoric acid.
[0023]
Next, the release wafer 12 is polished. This polishing is performed in a general polishing apparatus (not shown). Specifically, the peeling wafer 12 is mounted and fixed on a holding table of a polishing apparatus (not shown), the polishing liquid is supplied from the polishing liquid supply means, and the polishing cloth is impregnated with the polishing cloth. In this state, the holding table is rotated together with the peeling wafer 12 and the polishing cloth holder is rotated together with the polishing cloth. Then, the polishing cloth is pressed against the separation surface 12a of the peeling wafer 12 by pressure contact / rotation means to polish the peeling wafer 12. To do. At this time, since grinding using a grindstone that is performed when a level difference is generated is not performed, there is no damage due to grinding, and a removal allowance 12c at the time of polishing on the separation surface 12a of the separation wafer 12 shown in FIG. It can be as follows. Further, the surface of the release wafer 12 is finish-polished and then subjected to finish cleaning. For finish polishing, use a suede type finish polishing cloth in which urethane resin is foamed on a non-woven fabric base fabric, and a finishing abrasive with an organic polymer added as a haze inhibitor in addition to abrasive grains. Is done. In this way, the layer transferred wafer 12 is reproduction processing reproduction wafer 32 shown in Fig. 3 (d) is obtained.
[0024]
As described above, in the separation wafer reclaim processing method of the present invention, ions are implanted only into the main flat portion 13d protruding from the chamfered portion 13c to form the ion implantation region 13b inside the semiconductor wafer 13, and the ion implantation region 13b is formed. In order to separate the semiconductor wafer 13 from the thin film 17 over the entire surface to obtain a peeled wafer 12 that does not generate a step around the surface, it has been conventionally performed to remove the ion implantation layer remaining on the step formed around the separation surface of the peeled wafer 12. Therefore, chamfering or etching can be omitted. Accordingly, the reclaimed wafer 32 can be obtained by a relatively simple operation of only polishing the separation surface 12a of the release wafer 12, and the obtained reclaimed wafer 32 is not damaged and has a very small polishing allowance 12d during polishing. The number of times that the semiconductor wafer 13 or the support wafer 14 can be reused increases, and the manufacturing cost of the SOI wafer 11 can be reduced.
[0025]
【The invention's effect】
As described above, according to the present invention, a polishing roller composed of a drum-shaped grindstone having a concave groove formed in the periphery thereof while a semiconductor wafer is sandwiched between upper and lower chucks and horizontally rotated and the polishing liquid is dropped. By rotating and contacting the periphery of the semiconductor wafer, ions are implanted only into the main flat portion protruding from the chamfered portion to form an ion implantation region inside the semiconductor wafer, and the semiconductor wafer is thinned over the entire surface of the ion implantation region. Therefore, a chamfering process or etching that has been conventionally performed to remove the ion-implanted layer remaining on the step around the separation surface of the separation wafer can be omitted. Therefore, the processing time for reclaiming the peeled wafer by reclaiming the separated wafer immediately by polishing the separation surface of the peeled wafer is remarkably shortened compared to the conventional method, the reclaiming cost is reduced, and the allowance for reclaiming is reduced To increase the number of playbacks.
[0026]
Further, when a ring-shaped flat portion is formed between the main flat portion and the chamfered portion, the main flat portion can be easily formed if the width of the ring-shaped flat portion is 0.1 to 2 mm. If the amount of deviation in which the center of the end face connecting the double-sided portions formed on both main surfaces of the semiconductor wafer is deviated from the center in the thickness direction of the semiconductor wafer is 50 μm or less, the formation of the main flat portion becomes easier. On the other hand, if the ring-shaped step is 5 to 100 [mu] m, it becomes easy to form an ion implantation region by implanting ions only into the main flat portion.
[0027]
In addition, if the removal allowance at the time of polishing on the separation surface of the peeled wafer is 1 μm or less, the processing time for reclaiming the peeled wafer will be further shortened to reduce the regeneration cost and increase the number of times of regeneration sufficiently. Can do. Then, by using this playback wafer support wafer or semiconductor wafer, it is possible to re-use more than 2 times the playback wafer, Ru can further reduce the manufacturing cost of the SOI wafer.
[Brief description of the drawings]
FIG. 1 is a view showing a manufacturing method of an SOI wafer including a separation wafer according to an embodiment of the present invention in the order of steps.
FIG. 2 is a cross-sectional configuration diagram showing an apparatus for grinding the periphery of a wafer.
FIGS. 3A and 3B are diagrams sequentially illustrating a process of obtaining a reclaimed wafer by polishing the separation surface of the peeled wafer. FIGS.
[Explanation of symbols]
12 Separation wafer 12a Separation surface 12c Cutting allowance 13 Semiconductor wafer 13b Ion implantation region 13c, 13g Chamfered portion 13d Main flat portion 13e Ring-shaped step 13f Ring-shaped flat portion 14 Support wafer 16 Laminate 17 Thin film 32 Recycled wafer w Ring-shaped flat portion Width p Center of end face connecting double-sided chamfer c Center of semiconductor wafer thickness s Deviation

Claims (7)

The main surface of the semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed around the main flat portion (13d), and ions are formed on the main surface of the semiconductor wafer (13). To form an ion implantation region (13b) inside the semiconductor wafer (13), and the main flat portion (13d) of the semiconductor wafer (13) is stacked on the main surface of the support wafer (14). A thickness obtained by forming the body (16) and further heat-treating the laminate (16) at a predetermined temperature to separate the semiconductor wafer (13) from the thin film (17) in the ion implantation region (13b). A method for reclaiming a meat release wafer (12),
The semiconductor wafer (13) is sandwiched between upper and lower chucks (21, 22), horizontally rotated, and comprises a drum-shaped grindstone in which concave grooves (24b) are formed while dropping a polishing liquid (23). By rotating the polishing roller (24) and bringing it into contact with the periphery of the semiconductor wafer (13), the main flat portion (13d) of the semiconductor wafer (13) protrudes from the chamfered portion (13c) to form a ring-shaped step ( 13e)
Separating the semiconductor wafer (13) from the thin film (17) over the entire surface of the ion implantation region (13b) so as not to cause a step in the periphery, thereby obtaining a separated wafer (12). Method.   The semiconductor wafer (13) further has a ring-shaped flat portion (13f) between the main flat portion (13d) and the chamfered portion (13c), and the width (w) of the ring-shaped flat portion (13f) is 0. The method for reclaiming a peeled wafer according to claim 1, which is 1 to 2 mm.   A deviation in which the center (p) of the end face connecting the double-sided chamfers (13c, 13g) formed on both main surfaces of the semiconductor wafer (13) is deviated from the thickness direction center (c) of the semiconductor wafer (13). The method for reclaiming a peeled wafer according to claim 2, wherein the amount (s) is 50 µm or less.   The method for reclaiming a peeled wafer according to any one of claims 1 to 3, wherein the ring-shaped step (13e) is 5 to 100 µm.   The method further includes a step of polishing the separation surface (12a) of the separation wafer (12) to obtain a reclaimed wafer, and a removal allowance (12c) on the separation surface (12a) of the separation wafer (12) during polishing is 0.2 μm or more 1 The method for reclaiming a peeled wafer according to any one of claims 1 to 4, wherein the thickness is 0.0 µm or less.   The method for reclaiming a peeled wafer according to claim 5, wherein the reclaimed wafer obtained by polishing the separation surface (12a) of the peeled wafer (12) is heat-treated at 900 ° C to 1100 ° C in an oxidizing atmosphere.   The method for reclaiming a peeled wafer according to any one of claims 1 to 6, wherein the reclaimed wafer (32) is used as a semiconductor wafer (13).

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