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JP4403407B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4403407B2
JP4403407B2 JP2005027799A JP2005027799A JP4403407B2 JP 4403407 B2 JP4403407 B2 JP 4403407B2 JP 2005027799 A JP2005027799 A JP 2005027799A JP 2005027799 A JP2005027799 A JP 2005027799A JP 4403407 B2 JP4403407 B2 JP 4403407B2
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semiconductor chip
semiconductor device
noise shielding
layer
semiconductor
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修 山形
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of SiP formation in which noise acting between chips is suppressed when two or more semiconductor chips are stacked integrally. <P>SOLUTION: In the semiconductor device packaged while including a semiconductor, a noise shielding layer SDa or a noise shielding layer consisting of a meshed conductive layer is formed in a predetermined region of the upper layer of a first semiconductor chip 12 including an active element to cover the entire surface of that region, and a second semiconductor chip 16 including an active element is stacked on the upper layer of the noise shielding layer SDa. Alternatively, a noise shielding layer may be provided between a substrate 10 and the first semiconductor chip 12. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は半導体装置およびその製造方法に関し、特に能動素子や受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰ（システムインパッケージ）形態の半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a SiP (system in package) type semiconductor device incorporating an active element and a passive element and incorporating a matching circuit and a filter, and a manufacturing method thereof.

デジタルビデオカメラ、デジタル携帯電話、あるいはノートパソコンなど、携帯用電子機器の小型化、薄型化、軽量化に対する要求は強くなる一方であり、これに応えるために近年のＶＬＳＩなどの半導体装置においては３年で７割の縮小化を実現してきた一方で、このような半導体装置をプリント配線基板上に実装した電子回路装置としても、実装基板（プリント配線基板）上の部品実装密度をいかに向上させるかが重要な課題として研究および開発がなされてきた。   The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While an electronic circuit device in which such a semiconductor device is mounted on a printed wiring board has been realized by 70% reduction year by year, how can the component mounting density on the mounting substrate (printed wiring substrate) be improved? Has been researched and developed as an important issue.

例えば、半導体装置のパッケージ形態としては、ＤＩＰ（Dual Inline Package ）などのリード挿入型から表面実装型へと移行し、さらには半導体チップのパッド電極にはんだや金などからなるバンプ（突起電極）を設け、フェースダウンでバンプを介して配線基板に接続するフリップチップ実装法が開発された。   For example, as a package form of a semiconductor device, a transition from a lead insertion type such as DIP (Dual Inline Package) to a surface mounting type is performed, and furthermore, bumps (projection electrodes) made of solder, gold, or the like are provided on a pad electrode of a semiconductor chip. A flip-chip mounting method has been developed in which a face-down connection is made to the wiring board via bumps.

さらに、インダクタンスやキャパシタなどの受動素子を内蔵し、整合回路やフィルタなどを取り込んだＳｉＰと呼ばれる複雑な形態のパッケージへと開発が進んでおり、例えば、特許文献１に上記のＳｉＰ形態の半導体装置の構成が開示されている。   Further, development has progressed to a package having a complicated form called SiP that incorporates a passive element such as an inductance or a capacitor and incorporates a matching circuit or a filter. For example, Patent Document 1 discloses the above-described SiP-type semiconductor device. The configuration is disclosed.

上記のようなＳｉＰ形態の半導体装置において、デジタルチップとデジタルチップ、デジタルチップとアナログチップ、アナログチップとアナログチップなど、能動素子を含むチップを２個以上含んで一体化した半導体装置が知られている。   Among the semiconductor devices of the SiP type as described above, a semiconductor device in which two or more chips including active elements such as a digital chip and a digital chip, a digital chip and an analog chip, and an analog chip and an analog chip are integrated is known. Yes.

例えばアナログチップとデジタルチップをスタック型にした半導体装置では、特にデジタルチップからアナログチップへのデジタルノイズの影響が存在するため、デジタルチップとアナログチップの間隔を十分距離を離す必要がある。このため、特許文献１に記載のように、同一平面上に平置きした構造が取られることが多い。   For example, in a semiconductor device in which an analog chip and a digital chip are stacked, there is an influence of digital noise particularly from the digital chip to the analog chip. Therefore, the distance between the digital chip and the analog chip needs to be sufficiently long. For this reason, as described in Patent Document 1, a structure that is laid flat on the same plane is often used.

しかしながら、上記のような２つ以上の半導体チップを平置きにする構造では、半導体装置全体のサイズが大きくなってしまい、小型化の要求を満足しない。
また、２つ以上の半導体チップを縦置きしたスタック構造としたときにノイズ遮蔽シートを介在させることが考えられるが、ノイズ遮蔽シートは厚さが１００μｍ以下のものは存在しないため、スタック構造に採用することは事実上できない。
このため、有機基板の両側にアナログおよびデジタルチップをそれぞれ実装することが行われているが、基板のスルーホールと片側に外部電極の形成が必要であり、全体の厚さが厚くなってしまうので薄型化は困難となっている。 However, the structure in which two or more semiconductor chips as described above are laid flat increases the size of the entire semiconductor device, and does not satisfy the demand for miniaturization.
In addition, it is conceivable that a noise shielding sheet is interposed when a stack structure in which two or more semiconductor chips are vertically arranged. However, there is no noise shielding sheet having a thickness of 100 μm or less. It is virtually impossible to do.
For this reason, analog and digital chips are mounted on both sides of the organic substrate, respectively, but it is necessary to form external electrodes on one side and through-holes on the substrate, which increases the overall thickness. Thinning has become difficult.

上記では特にアナログチップとデジタルチップを有する半導体装置について説明したが、デジタルチップとデジタルチップ、あるいは、アナログチップとアナログチップの組み合わせにおいてもチップ間のノイズの影響を低減することが望まれており、スタック型に一体化する場合の課題となっている。
特開平５−１１４６９３号公報 In the above, a semiconductor device having an analog chip and a digital chip has been particularly described. However, it is desired to reduce the influence of noise between chips even in a combination of a digital chip and a digital chip, or an analog chip and an analog chip. This is a problem when integrating into a stack type.
Japanese Patent Laid-Open No. 5-114693

解決しようとする問題点は、ＳｉＰ形態の半導体装置において２個以上の半導体チップをスタック型に一体化する場合のチップ間に作用するノイズを抑制することが困難である点である。   The problem to be solved is that it is difficult to suppress noise acting between chips when two or more semiconductor chips are integrated into a stack type in a semiconductor device of SiP type.

本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、能動素子を含む第１半導体チップと、前記第１半導体チップの上層の所定の領域に形成されたノイズ遮蔽層と、前記ノイズ遮蔽層の上層に積層された能動素子を含む第２半導体チップとを有する。   A semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, and includes a first semiconductor chip including an active element, and a noise shielding layer formed in a predetermined region above the first semiconductor chip. And a second semiconductor chip including an active element stacked on an upper layer of the noise shielding layer.

上記の本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、能動素子を含む第１半導体チップの上層の所定の領域にノイズ遮蔽層が形成されており、このノイズ遮蔽層の上層に、能動素子を含む第２半導体チップが積層されている構成である。   The above-described semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, and a noise shielding layer is formed in a predetermined region above the first semiconductor chip including the active element. The second semiconductor chip including the active element is stacked on the upper layer.

本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、能動素子を含む半導体基板と、前記半導体基板の上層の所定の領域に形成されたノイズ遮蔽層と、前記ノイズ遮蔽層の上層に積層された能動素子を含む半導体チップとを有する。   The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, and includes a semiconductor substrate including an active element, a noise shielding layer formed in a predetermined region above the semiconductor substrate, and the noise shielding. And a semiconductor chip including an active element stacked on the upper layer.

本発明の半導体装置は、半導体を含んでパッケージ化された半導体装置であって、能動素子を含む半導体基板の上層の所定の領域にノイズ遮蔽層が形成されており、このノイズ遮蔽層の上層に、能動素子を含む半導体チップが積層されている構成である。   The semiconductor device of the present invention is a semiconductor device packaged including a semiconductor, and a noise shielding layer is formed in a predetermined region on an upper layer of a semiconductor substrate including an active element. In this configuration, semiconductor chips including active elements are stacked.

本発明の半導体装置の製造方法は、半導体を含んでパッケージ化された半導体装置の製造方法であって、能動素子を含む第１半導体チップの上層の所定の領域に、ノイズ遮蔽層を形成する工程と、前記ノイズ遮蔽層の上層に、能動素子を含む第２半導体チップを積層する工程とを有する。   The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor, and a step of forming a noise shielding layer in a predetermined region on an upper layer of a first semiconductor chip including an active element. And a step of laminating a second semiconductor chip including an active element on the noise shielding layer.

上記の本発明の半導体装置の製造方法は、半導体を含んでパッケージ化された半導体装置の製造方法であって、能動素子を含む第１半導体チップの上層の所定の領域に、ノイズ遮蔽層を形成し、ノイズ遮蔽層の上層に、能動素子を含む第２半導体チップを積層する。   The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor, wherein a noise shielding layer is formed in a predetermined region above the first semiconductor chip including an active element. Then, a second semiconductor chip including an active element is stacked on the noise shielding layer.

本発明の半導体装置の製造方法は、半導体を含んでパッケージ化された半導体装置の製造方法であって、能動素子を含む半導体基板の上層の所定の領域に、ノイズ遮蔽層を形成する工程と、前記ノイズ遮蔽層の上層に、能動素子を含む半導体チップを積層する工程とを有する。   A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device packaged including a semiconductor, and a step of forming a noise shielding layer in a predetermined region on an upper layer of a semiconductor substrate including an active element; Laminating a semiconductor chip including an active element on the noise shielding layer.

上記の本発明の半導体装置の製造方法は、半導体を含んでパッケージ化された半導体装置の製造方法であって、能動素子を含む半導体基板の上層の所定の領域に、ノイズ遮蔽層を形成し、ノイズ遮蔽層の上層に、能動素子を含む半導体チップを積層する。   The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device packaged including a semiconductor, in which a noise shielding layer is formed in a predetermined region on an upper layer of a semiconductor substrate including an active element, A semiconductor chip including an active element is stacked on the noise shielding layer.

本発明の半導体装置は、ＳｉＰ形態の半導体装置において、積層された第１半導体チップと第２半導体チップの間に、ノイズ遮蔽層が形成された構成であり、スタック型として一体化してもチップ間に作用するノイズを抑制することができる。   The semiconductor device of the present invention has a configuration in which a noise shielding layer is formed between the stacked first semiconductor chip and the second semiconductor chip in the SiP-type semiconductor device. The noise which acts on can be suppressed.

本発明の半導体装置の製造方法は、積層された第１半導体チップと第２半導体チップの間に、ノイズ遮蔽層が形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   In the method of manufacturing a semiconductor device according to the present invention, since a noise shielding layer is formed between the stacked first semiconductor chip and the second semiconductor chip, noise acting between the chips can be suppressed even when integrated as a stack type. A simple semiconductor device can be manufactured.

以下に、本発明に係る半導体装置およびその製造方法の実施の形態について、図面を参照して説明する。   Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

第１実施形態
図１は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
例えば、シリコン基板１０上に酸化シリコンからなる下地絶縁膜１１が形成され、その上層に、能動素子が設けられた第１半導体チップ１２がダイアタッチフィルム１３により接着されている。第１半導体チップ１２は、半導体本体部分１２ａにパッド１２ｂが形成され、パッド１２ｂを除く領域は酸化シリコンの保護層１２ｃで覆われた構成であり、フェースアップで、即ち、パッド１２ｂ形成面の反対側の面側からマウントされている。 First Embodiment FIG. 1 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
For example, a base insulating film 11 made of silicon oxide is formed on a silicon substrate 10, and a first semiconductor chip 12 provided with active elements is bonded to the upper layer by a die attach film 13. The first semiconductor chip 12 has a configuration in which a pad 12b is formed on a semiconductor body portion 12a, and a region excluding the pad 12b is covered with a silicon oxide protective layer 12c, and is face-up, that is, opposite to the pad 12b formation surface. It is mounted from the side of the side.

第１半導体チップ１２を被覆して、ポリイミド樹脂、エポキシ樹脂あるいはアクリル樹脂などからなる第１絶縁層１４が形成されている。
第１絶縁層１４には、半導体チップ１２のパッド１２ｂに達する開口部が形成されている。
上記の開口部内に埋め込まれてパッド１２ｂに接続するプラグ部分と一体になって、第１絶縁層１４上にバリアメタル層１５ａおよび銅層１５ｂからなる第１配線１５が形成されている。 A first insulating layer 14 made of polyimide resin, epoxy resin, acrylic resin, or the like is formed so as to cover the first semiconductor chip 12.
In the first insulating layer 14, an opening reaching the pad 12b of the semiconductor chip 12 is formed.
A first wiring 15 including a barrier metal layer 15a and a copper layer 15b is formed on the first insulating layer 14 so as to be integrated with the plug portion embedded in the opening and connected to the pad 12b.

また、第１半導体チップ１２の上層における第１絶縁層１４上の所定の領域であって、第１配線１５が形成されていない領域において、ノイズ遮蔽層ＳＤａが形成されている。ノイズ遮蔽層ＳＤａは、例えばグラウンドなどの一定の電位に保持される。
上記のノイズ遮蔽層ＳＤａは、上記の所定の領域を全面に被覆する導電層から構成されており、例えば第１配線１５と同様にバリアメタル層と銅層の積層体などから構成されていてもよい。 Further, the noise shielding layer SDa is formed in a predetermined region on the first insulating layer 14 in the upper layer of the first semiconductor chip 12 and in which the first wiring 15 is not formed. The noise shielding layer SDa is held at a constant potential such as ground.
The noise shielding layer SDa is composed of a conductive layer that covers the entire surface of the predetermined region. For example, similar to the first wiring 15, the noise shielding layer SDa may be composed of a laminate of a barrier metal layer and a copper layer. Good.

上記のノイズ遮蔽層ＳＤａの上層に、能動素子が設けられた第２半導体チップ１６がダイアタッチフィルム１７により、フェースアップで接着されている。第２半導体チップ１６は、半導体本体部分１６ａにパッド１６ｂが形成され、パッド１６ｂを除く領域は酸化シリコンの保護層１６ｃで覆われた構成である。
ここで、上記のノイズ遮蔽層ＳＤａが形成されている所定の領域は、例えば第２半導体チップ１６の領域全体を被覆するような領域とする。あるいは、第２半導体チップ１６の領域の一部を被覆する構成でもよい。 On the noise shielding layer SDa, the second semiconductor chip 16 provided with active elements is bonded face up with a die attach film 17. The second semiconductor chip 16 has a configuration in which a pad 16b is formed on a semiconductor body portion 16a, and a region excluding the pad 16b is covered with a protective layer 16c made of silicon oxide.
Here, the predetermined region where the noise shielding layer SDa is formed is a region that covers the entire region of the second semiconductor chip 16, for example. Or the structure which coat | covers a part of area | region of the 2nd semiconductor chip 16 may be sufficient.

第１配線１５および第２半導体チップ１６を被覆して第１絶縁層１４と同様のポリイミド樹脂などからなる第２絶縁層１８が形成されている。
第２絶縁層１８には、第２半導体チップ１６のパッド１６ｂおよび第１配線１５の表面に達する開口部が形成されている。
上記の開口部内に埋め込まれてパッド１６ｂおよび第１配線１５に接続するプラグ部分と一体になって、第２絶縁層１８上にバリアメタル層１９ａおよび銅層１９ｂからなる第２配線１９が形成されている。 A second insulating layer 18 made of the same polyimide resin as the first insulating layer 14 is formed so as to cover the first wiring 15 and the second semiconductor chip 16.
In the second insulating layer 18, an opening reaching the pad 16 b of the second semiconductor chip 16 and the surface of the first wiring 15 is formed.
A second wiring 19 composed of a barrier metal layer 19a and a copper layer 19b is formed on the second insulating layer 18 so as to be integrated with the plug portion embedded in the opening and connected to the pad 16b and the first wiring 15. ing.

また、第２配線１９に接続して、銅などからなる導電性ポスト２０が形成されている。
導電性ポスト２０の間隙における第２絶縁層１８の上層に、ポリアミドイミド樹脂、ポリイミド樹脂、エポキシ樹脂、フェノール樹脂あるいはポリパラフェニレンベンゾビスオキサゾール樹脂などからなる絶縁性のバッファ層２１が形成されている。
さらに、バッファ層２１の表面において導電性ポスト２０に接続するようにバンプ（突起電極）２２が形成されている。 In addition, a conductive post 20 made of copper or the like is formed in connection with the second wiring 19.
An insulating buffer layer 21 made of polyamideimide resin, polyimide resin, epoxy resin, phenol resin, polyparaphenylene benzobisoxazole resin, or the like is formed on the second insulating layer 18 in the gap between the conductive posts 20. .
Further, bumps (projection electrodes) 22 are formed on the surface of the buffer layer 21 so as to be connected to the conductive posts 20.

上記の本実施形態の半導体装置において、第１半導体チップ１２は、例えばデジタルチップであり、一方、第２半導体チップ１６は、例えばアナログチップである。
基板１０に樹脂層が積層して絶縁層（１４，１８）が形成されており、上記の第１半導体チップ１２および第２半導体チップ１６が絶縁層中に埋め込まれている。 In the semiconductor device according to the present embodiment, the first semiconductor chip 12 is, for example, a digital chip, while the second semiconductor chip 16 is, for example, an analog chip.
A resin layer is laminated on the substrate 10 to form an insulating layer (14, 18), and the first semiconductor chip 12 and the second semiconductor chip 16 are embedded in the insulating layer.

上記の本実施形態の半導体装置は、ＳｉＰ形態の半導体装置において、基板上に２個の半導体チップが積層して一体化したスタック型であるが、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。   The semiconductor device of the present embodiment is a stack type in which two semiconductor chips are stacked and integrated on a substrate in the SiP type semiconductor device. The stacked first semiconductor chip and second semiconductor chip are the same. In this configuration, a noise shielding layer is formed between them, and noise acting between chips such as digital noise can be suppressed.

第１半導体チップ１２および第２半導体チップ１６が、上記と逆の組み合わせ、あるいは、両者共にデジタルチップあるいはアナログチップであっても、上記と同様にチップ間のノイズを抑制することができる。   Even if the first semiconductor chip 12 and the second semiconductor chip 16 are a combination opposite to the above, or both are digital chips or analog chips, noise between chips can be suppressed in the same manner as described above.

次に、上記の本実施形態の半導体装置の製造方法について図２〜８を参照して説明する。本実施形態においては、例えば図２〜８に示す全ての工程についてウェハレベルで行うことができる。
まず、図２（ａ）に示すように、例えば、７２５μｍの厚さのシリコン基板１０に、ＣＶＤ（化学気相成長）法、熱拡散法あるいはスパッタリング法により、３００ｎｍの膜厚の酸化シリコンを堆積し、下地絶縁膜１１を形成する。
さらに、必要に応じて、所定のパターンのレジスト膜を成膜し、ウェットあるいはドライエッチングを施すことにより、下地絶縁膜１１に、次工程で第１半導体チップをマウントするときのアライメントマークを形成する。 Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. In the present embodiment, for example, all steps shown in FIGS. 2 to 8 can be performed at the wafer level.
First, as shown in FIG. 2A, for example, silicon oxide having a thickness of 300 nm is deposited on a silicon substrate 10 having a thickness of 725 μm by a CVD (chemical vapor deposition) method, a thermal diffusion method, or a sputtering method. Then, the base insulating film 11 is formed.
Further, if necessary, a resist film having a predetermined pattern is formed, and wet or dry etching is performed, thereby forming an alignment mark for mounting the first semiconductor chip in the next step on the base insulating film 11. .

次に、図２（ｂ）に示すように、例えば、下地絶縁膜１１の上層に、別工程において予め薄型個片化工程までしておいた能動素子を有する第１半導体チップ１２をマウントする。
第１半導体チップ１２は、半導体本体部分１２ａにパッド１２ｂが形成され、パッド１２ｂを除く領域は酸化シリコンの保護層１２ｃで覆われた構成であり、例えば半導体本体部分１２ａに能動素子が形成されたチップであり、上記のマウント前に予め薄型／個片化を行っておく。即ち、シリコンの場合は２５μｍ、ＧａＡｓの場合は５０μｍの厚さまで研削を行い、これに接着層をラミネートし、ダイシングを行うことで、薄型個片の半導体チップとする。
高精度ダイボンダを用いて、上記のアライメントマークと第１半導体チップ１２のパッド１２ｂを１台のカメラで同時に認識して、上記の構成の第１半導体チップ１２をフェースアップで、即ちパッド１２ｂ形成面の反対側の面側から、ダイアタッチフィルム１３を介して高精度に積層させ、１６０℃の温度で１．６Ｎの荷重を２秒間かけて接着し、さらに１７０℃で１時間以上の硬化を行う。搭載精度は、例えば±１μｍ程度である。 Next, as shown in FIG. 2B, for example, a first semiconductor chip 12 having an active element that has been processed in a separate process in advance into a thin singulation process is mounted on the base insulating film 11.
The first semiconductor chip 12 has a configuration in which a pad 12b is formed on a semiconductor body portion 12a, and a region excluding the pad 12b is covered with a silicon oxide protective layer 12c. For example, an active element is formed on the semiconductor body portion 12a. The chip is thinned / divided in advance before mounting. That is, grinding is performed to a thickness of 25 μm in the case of silicon and 50 μm in the case of GaAs, an adhesive layer is laminated thereon, and dicing is performed to obtain a thin semiconductor chip.
Using a high-precision die bonder, the alignment mark and the pad 12b of the first semiconductor chip 12 are simultaneously recognized by one camera, and the first semiconductor chip 12 having the above configuration is face-up, that is, the pad 12b forming surface. Laminate with high accuracy from the opposite surface side through the die attach film 13, adhere 1.6 N load at 160 ° C. over 2 seconds, and further cure at 170 ° C. for 1 hour or more. . The mounting accuracy is, for example, about ± 1 μm.

次に、図２（ｃ）に示すように、例えば、スピンコート法などにより、ポリイミド樹脂、エポキシ樹脂、ポリオレフィン系樹脂、シリコーン樹脂、フェノール樹脂あるいはアクリル樹脂などの感光性絶縁材料を供給し、第１絶縁層１４を形成する。
例えば硬化後に例えば５０μｍの膜厚となるように形成するが、これは第１半導体チップ１２を被覆するような厚さとすればよい。
感光性ポリイミド樹脂の場合、例えば以下の条件で成膜する。
スピンコート：７０００ｒｐｍ（２５秒）＋１０００ｒｐｍ（１２５秒）＋１０００ｒｐｍ（１０秒）＋１５００ｒｐｍ（１０秒）
プリベーク：６０℃（２４０秒）＋９０℃（２４０秒）＋１１０℃（１２０秒）
上記の処理によって７８μｍの膜厚とする。 Next, as shown in FIG. 2C, for example, a photosensitive insulating material such as polyimide resin, epoxy resin, polyolefin resin, silicone resin, phenol resin, or acrylic resin is supplied by spin coating or the like. 1 Insulating layer 14 is formed.
For example, the film is formed so as to have a film thickness of, for example, 50 μm after curing, but this may be a thickness that covers the first semiconductor chip 12.
In the case of a photosensitive polyimide resin, for example, the film is formed under the following conditions.
Spin coating: 7000 rpm (25 seconds) + 1000 rpm (125 seconds) + 1000 rpm (10 seconds) + 1500 rpm (10 seconds)
Pre-bake: 60 ° C (240 seconds) + 90 ° C (240 seconds) + 110 ° C (120 seconds)
A film thickness of 78 μm is obtained by the above treatment.

次に、露光量３００ｍＪ／ｃｍ2でパターン露光および現像し、第１半導体チップ１２のパッド１２ｂに達する開口部を第１絶縁層１４に形成する。
現像後、１５０℃（３０分）＋２５０℃（１２０分）のポストキュア処理を行って第１絶縁層１４を５０μｍの膜厚とする。 Next, pattern exposure and development are performed at an exposure amount of 300 mJ / cm 2 , and an opening reaching the pad 12 b of the first semiconductor chip 12 is formed in the first insulating layer 14.
After the development, post-curing treatment at 150 ° C. (30 minutes) + 250 ° C. (120 minutes) is performed to make the first insulating layer 14 have a thickness of 50 μm.

図３（ａ）に示すように、例えば、シードスパッタリングにより１６０ｎｍのＴｉ層／６００ｎｍのＣｕ層の積層体あるいはＣｒＣｕを成膜し、第１絶縁層１４に形成した開口部の内壁を被覆して、全面にバリアメタル層１５ａを形成し、Ｏ2アッシャー（３００Ｗ）で５分処理する。 As shown in FIG. 3A, for example, a 160 nm Ti layer / 600 nm Cu layer stack or CrCu is formed by seed sputtering, and the inner wall of the opening formed in the first insulating layer 14 is covered. Then, a barrier metal layer 15a is formed on the entire surface and treated with O 2 asher (300 W) for 5 minutes.

次に、図３（ｂ）に示すように、例えば、第１絶縁層１４に形成した開口部と第１配線の形成領域以外にメッキされるのを防止するために、レジスト塗布および現像処理を行い、第１絶縁層１４に形成した開口部と第１配線の形成領域を開口するパターンのレジスト膜Ｒ１を成膜する。   Next, as shown in FIG. 3B, for example, in order to prevent plating other than the opening formed in the first insulating layer 14 and the formation region of the first wiring, resist coating and development processing are performed. Then, a resist film R1 having a pattern opening the opening formed in the first insulating layer 14 and the formation region of the first wiring is formed.

次に、図３（ｃ）に示すように、例えば、レジスト膜Ｒ１をマスクとし、バリアメタル層１５ａをシードとする１．５Ａ、９０分の電解メッキにより、第１絶縁層１４上での膜厚が５μｍ程度となるように銅をメッキして、第１絶縁層１４に形成した開口部と第１配線の形成領域に銅層１５ｂを形成する。   Next, as shown in FIG. 3C, for example, the film on the first insulating layer 14 is electroplated by 1.5A for 90 minutes using the resist film R1 as a mask and the barrier metal layer 15a as a seed. Copper is plated so as to have a thickness of about 5 μm, and a copper layer 15b is formed in the opening formed in the first insulating layer 14 and the formation region of the first wiring.

次に、図４（ａ）に示すように、例えば、アッシング処理などによりレジスト膜Ｒ１を除去し、さらに図４（ｂ）に示すように、銅層１５ｂをマスクとしてバリアメタル層１５ａをエッチング加工する。このシードエッチングにおいてアンダーカットがないようにするため、第１絶縁層１４に形成した開口部とレジスト膜Ｒ１のパターンのオーバーラップ部分は、少なくとも５μｍとする。
以上で、パッド１２ｂに接続するプラグ部分と一体にして、第１絶縁層１４上にバリアメタル層１５ａおよび銅層１５ｂからなる第１配線１５を形成する。 Next, as shown in FIG. 4A, the resist film R1 is removed by, for example, ashing, and the barrier metal layer 15a is etched using the copper layer 15b as a mask as shown in FIG. 4B. To do. In order to prevent undercut in this seed etching, the overlap portion between the opening formed in the first insulating layer 14 and the pattern of the resist film R1 is at least 5 μm.
Thus, the first wiring 15 including the barrier metal layer 15a and the copper layer 15b is formed on the first insulating layer 14 integrally with the plug portion connected to the pad 12b.

次に、図４（ｃ）に示すように、例えばＣＶＤ法あるいはスパッタリング法により、導電性材料を全面に堆積させ、第１半導体チップ１２の上層における所定の領域を残すようにパターンエッチング加工を行って、所定の領域に全面にノイズ遮蔽層ＳＤａを形成する。
ノイズ遮蔽層ＳＤａは、第１配線１５と同様にシード層と銅層の積層体で構成してもよく、この場合には第１配線と同時にパターン形成することができる。 Next, as shown in FIG. 4C, a conductive material is deposited on the entire surface by, eg, CVD or sputtering, and pattern etching is performed so as to leave a predetermined region in the upper layer of the first semiconductor chip 12. Thus, the noise shielding layer SDa is formed on the entire surface in a predetermined region.
The noise shielding layer SDa may be formed of a stacked body of a seed layer and a copper layer similarly to the first wiring 15, and in this case, a pattern can be formed simultaneously with the first wiring.

次に、図５（ａ）に示すように、例えば、ノイズ遮蔽層ＳＤａの上層に、別工程において予め薄型個片化工程までしておいた能動素子を有する第２半導体チップ１６をマウントする。
第２半導体チップ１６は、半導体本体部分１６ａにパッド１６ｂが形成され、パッド１６ｂを除く領域は酸化シリコンの保護層１６ｃで覆われた構成であり、例えば半導体本体部分１６ａには能動素子が形成されたチップであり、上記のマウント前に予め薄型／個片化を行っておく。即ち、シリコンの場合は２５μｍ、ＧａＡｓの場合は５０μｍの厚さまで研削を行い、これに接着層をラミネートし、ダイシングを行うことで、薄型個片の半導体チップとする。
例えば、高精度ダイボンダを用いて、第１半導体チップのパッドに接続する第１配線と第２半導体チップ１６のパッド１６ｂを１台のカメラで同時に認識して、第１半導体チップ１２のマウントと同様にして、ダイアタッチフィルム１７により、例えば±１μｍ程度の高い精度でマウントする。 Next, as shown in FIG. 5A, for example, the second semiconductor chip 16 having an active element that has been processed in a separate process in advance into a thin singulation process is mounted on the noise shielding layer SDa.
The second semiconductor chip 16 has a configuration in which a pad 16b is formed in a semiconductor body portion 16a, and a region excluding the pad 16b is covered with a silicon oxide protective layer 16c. For example, an active element is formed in the semiconductor body portion 16a. The chip is thinned / divided in advance before mounting. That is, grinding is performed to a thickness of 25 μm in the case of silicon and 50 μm in the case of GaAs, an adhesive layer is laminated thereon, and dicing is performed to obtain a thin semiconductor chip.
For example, the first wiring connected to the pad of the first semiconductor chip and the pad 16b of the second semiconductor chip 16 are simultaneously recognized by one camera using a high-precision die bonder, and the same as the mounting of the first semiconductor chip 12 Then, the die attach film 17 is mounted with high accuracy of, for example, about ± 1 μm.

次に、図５（ｂ）に示すように、例えば、上記の第１絶縁層１４の形成と同様にして、第２半導体チップ１６を被覆して、第２絶縁層１８を形成する。成膜条件は、第１絶縁膜１４と同様とし、例えば露光量３００ｍＪ／ｃｍ2でパターン露光および現像し、第２半導体チップ１６のパッド１６ｂおよび第１配線１５の表面に達する開口部を第２絶縁層１８に形成し、１５０℃（３０分）＋２５０℃（１２０分）のポストキュア処理を行って第２絶縁層１８を５０μｍの膜厚とする。 Next, as shown in FIG. 5B, for example, the second insulating layer 18 is formed by covering the second semiconductor chip 16 in the same manner as the formation of the first insulating layer 14 described above. The film forming conditions are the same as those for the first insulating film 14. For example, pattern exposure and development are performed at an exposure amount of 300 mJ / cm 2 , and the openings reaching the pads 16 b of the second semiconductor chip 16 and the surface of the first wiring 15 are formed in the second state. It forms in the insulating layer 18, and 150 degreeC (30 minutes) +250 degreeC (120 minutes) post-cure process is performed, and the 2nd insulating layer 18 is made into a film thickness of 50 micrometers.

次に、図５（ｃ）に示すように、例えば、シードスパッタリングにより１６０ｎｍの膜厚のＴｉ層／６００ｎｍの膜厚のＣｕ層の積層体、あるいはＣｒＣｕを成膜し、第２半導体チップ１６のパッド１６ｂに達する開口部および第１配線１５に達する開口部の内壁を被覆して、全面にバリアメタル層１９ａを形成し、Ｏ2アッシャー（３００Ｗ）で５分処理する。
次に、レジスト塗布および現像処理を行い、第２半導体チップ１６のパッド１６ｂに達する開口部および第１配線１５に達する開口部と第２配線の形成領域を開口するパターンのレジスト膜（不図示）を成膜し、これをマスクとし、バリアメタル層１９ａをシードとする４００ｍＡ、５０分の電解メッキにより銅をメッキして、第２半導体チップ１６のパッド１６ｂに達する開口部および第１配線１５に達する開口部と第２配線の形成領域に銅層１９ｂを形成する。この後、上記のレジスト膜を除去する。 Next, as shown in FIG. 5C, for example, a 160 nm-thickness Ti layer / 600 nm-thickness Cu layer stack or CrCu is formed by seed sputtering to form the second semiconductor chip 16. The barrier metal layer 19a is formed over the entire surface covering the inner wall of the opening reaching the pad 16b and the opening reaching the first wiring 15, and is treated with O 2 asher (300 W) for 5 minutes.
Next, resist coating and development are performed, and a resist film (not shown) having a pattern that opens the opening reaching the pad 16b of the second semiconductor chip 16, the opening reaching the first wiring 15, and the formation area of the second wiring. Is used as a mask, copper is plated by electrolytic plating of 400 mA, 50 minutes using the barrier metal layer 19a as a seed, and the openings reaching the pads 16b of the second semiconductor chip 16 and the first wiring 15 The copper layer 19b is formed in the reaching opening and the formation region of the second wiring. Thereafter, the resist film is removed.

次に、図６（ａ）に示すように、例えば感光性ドライフィルムを貼り合わせ、あるいはレジスト膜Ｒ２を成膜し、パターン露光および現像して導電性ポスト用の開口部を形成する。   Next, as shown in FIG. 6A, for example, a photosensitive dry film is bonded or a resist film R2 is formed, and pattern exposure and development are performed to form openings for conductive posts.

次に、図６（ｂ）に示すように、バリアメタル膜１９ａを用いた銅の電解メッキにより、導電性ポスト用の開口部内に、高さ８０〜１８０μｍ、径１８０〜３００μｍの導電性ポスト２０を形成する。   Next, as shown in FIG. 6B, conductive posts 20 having a height of 80 to 180 μm and a diameter of 180 to 300 μm are formed in the openings for the conductive posts by electrolytic plating of copper using the barrier metal film 19a. Form.

次に、図７（ａ）に示すように、ドライフィルムあるいはレジスト膜Ｒ２を除去し、図７（ｂ）に示すように、に導電性ポスト２０および銅層１９ｂをマスクとしてバリアメタル層１９ａをエッチング加工する。これにより、バリアメタル層１９ａおよび銅層１９ｂからなる第２配線１９が形成される。   Next, as shown in FIG. 7A, the dry film or resist film R2 is removed, and as shown in FIG. 7B, the barrier metal layer 19a is formed using the conductive posts 20 and the copper layer 19b as a mask. Etching process. Thereby, the second wiring 19 composed of the barrier metal layer 19a and the copper layer 19b is formed.

次に、図８（ａ）に示すように、例えばエポキシ系樹脂、ポリイミド系樹脂、シリコーン系樹脂、ポリアミドイミド樹脂、ポリイミド樹脂、フェノール樹脂あるいはポリパラフェニレンベンゾビスオキサゾール樹脂などの樹脂を、スピンコート、印刷またはモールドなどにより成膜し、導電性ポスト２０を完全に覆うような膜厚で絶縁性のバッファ層２１を形成する。
例えばポリイミド系樹脂を用いる場合、印刷法によりＮＶ値２７．５のペーストを使用し、スキージにより印刷を行うことで形成する。硬化は、例えば１００℃（１０分）＋１５０℃（１０分）＋２００℃（１０分）＋２５０℃（６０分）で行う。 Next, as shown in FIG. 8A, for example, an epoxy resin, a polyimide resin, a silicone resin, a polyamideimide resin, a polyimide resin, a phenol resin, or a polyparaphenylene benzobisoxazole resin is spin-coated. Then, the insulating buffer layer 21 is formed with a film thickness so as to completely cover the conductive post 20 by forming a film by printing or molding.
For example, when using a polyimide resin, the paste is formed by using a paste having an NV value of 27.5 by a printing method and printing with a squeegee. Curing is performed at, for example, 100 ° C. (10 minutes) + 150 ° C. (10 minutes) + 200 ° C. (10 minutes) + 250 ° C. (60 minutes).

次に、図８（ｂ）に示すように、バッファ層２１の樹脂硬化後に、研削により導電性ポスト２０の頭出しを行う。このときの条件は、例えば＃６００のホイールを用い、３５００ｒｐｍ、０．５ｍｍ／秒とする。   Next, as shown in FIG. 8B, after the buffer layer 21 is cured with the resin, the conductive post 20 is cued by grinding. The conditions at this time are set to 3500 rpm and 0.5 mm / second using, for example, a # 600 wheel.

次に、導電性ポスト２０に接続するように、例えばハンダボールの搭載、ＬＧＡ、あるいはハンダバンプの印刷などにより、バンプ（突起電極）２２を形成する。
ハンダバンプの印刷の場合には、例えば無鉛ハンダを０．２ｍｍの径で印刷し、２６０℃以下の温度でリフローしてバンプに成形する。
この後、例えばシリコン基板１０をハーフカットし、薄型化を行うことでダイシングすることで、二次接続信頼性を有し、応力緩和可能なバッファ層を有するためにアンダーフィル不要でリペア可能な、図１に示す構成のウェハレベルのＳｉＰ形態の半導体装置とすることができる。 Next, bumps (projection electrodes) 22 are formed so as to be connected to the conductive posts 20 by, for example, mounting solder balls, printing LGA, or solder bumps.
In the case of printing solder bumps, for example, lead-free solder is printed with a diameter of 0.2 mm and reflowed at a temperature of 260 ° C. or lower to form bumps.
After that, for example, the silicon substrate 10 is half-cut and diced by thinning, thereby having secondary connection reliability and having a buffer layer that can relieve stress, and therefore can be repaired without an underfill. A wafer-level SiP semiconductor device having the configuration shown in FIG. 1 can be obtained.

上記の本実施形態に係る半導体装置の製造方法によれば、ＳｉＰ形態の半導体装置を製造する際に、積層された第１半導体チップと第２半導体チップの間に、ノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method of manufacturing a semiconductor device according to the above-described embodiment, when a SiP-type semiconductor device is manufactured, a noise shielding layer is formed between the stacked first semiconductor chip and second semiconductor chip. Even when integrated as a stack type, a semiconductor device capable of suppressing noise acting between chips can be manufactured.

第２実施形態
図９は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
本実施形態の半導体装置は、第１実施形態の半導体装置と同様の構成であって、さらに、基板１０が能動素子を有する半導体基板であり、基板１０と第１半導体チップ１２の間の所定の領域においてノイズ遮蔽層ＳＤｂが形成されている。また、第１実施形態の半導体装置と同様に、第１半導体チップ１２と第２半導体チップ１６との間の所定の領域において、第２半導体チップの領域を被覆するようにノイズ遮蔽層ＳＤｃが形成されている。ノイズ遮蔽層（ＳＤｂ，ＳＤｃ）は、例えばグラウンドなどの一定の電位に保持される。
上記のノイズ遮蔽層（ＳＤｂ，ＳＤｃ）は、例えば第１実施形態と同様に、上記の各所定の領域を全面に被覆する導電層から構成されている。
上記の所定の領域は、ノイズ遮蔽層ＳＤｂについては第１半導体チップ１２の領域全体または一部を被覆する領域であり、ノイズ遮蔽層ＳＤｃについては第２半導体チップ１６の領域全体または一部を被覆する領域である。 Second Embodiment FIG. 9 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment, and the substrate 10 is a semiconductor substrate having an active element. A noise shielding layer SDb is formed in the region. Similarly to the semiconductor device of the first embodiment, a noise shielding layer SDc is formed in a predetermined region between the first semiconductor chip 12 and the second semiconductor chip 16 so as to cover the region of the second semiconductor chip. Has been. The noise shielding layers (SDb, SDc) are held at a constant potential such as ground.
The noise shielding layer (SDb, SDc) is composed of a conductive layer that covers the predetermined regions on the entire surface, for example, as in the first embodiment.
The predetermined region is a region covering the whole or part of the first semiconductor chip 12 with respect to the noise shielding layer SDb, and covering the whole or part of the second semiconductor chip 16 with respect to the noise shielding layer SDc. It is an area to do.

上記の本実施形態に係る半導体装置は、第１実施形態と同様に、ＳｉＰ形態の半導体装置において、基板と２個の半導体チップが積層して一体化したスタック型であるが、積層された基板と第１半導体チップの間および第１半導体チップと第２半導体チップの間にそれぞれノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。 As in the first embodiment, the semiconductor device according to the present embodiment is a stack type in which a substrate and two semiconductor chips are stacked and integrated in the SiP type semiconductor device. Noise shielding layers are formed between the first semiconductor chip and the first semiconductor chip and between the first semiconductor chip and the second semiconductor chip, so that noise acting between the chips such as digital noise can be suppressed.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip.

上記の本実施形態に係る半導体装置は、基板１０として能動素子を有する半導体基板を用い、基板１０と第１半導体チップ１２の間にノイズ遮蔽層ＳＤｂを形成する、即ち、第１半導体チップ１２のマウント工程前に第１半導体チップ１２の領域にノイズ遮蔽層ＳＤｂを形成し、他の工程は第１実施形態と同様にして形成することができる。   The semiconductor device according to the present embodiment uses a semiconductor substrate having an active element as the substrate 10 and forms the noise shielding layer SDb between the substrate 10 and the first semiconductor chip 12. The noise shielding layer SDb is formed in the region of the first semiconductor chip 12 before the mounting step, and the other steps can be formed in the same manner as in the first embodiment.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された基板と第１半導体チップの間および第１半導体チップと第２半導体チップの間にそれぞれノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device according to the present embodiment, when manufacturing a SiP-type semiconductor device, as in the first embodiment, between the stacked substrate and the first semiconductor chip and the first semiconductor. Since the noise shielding layer is formed between the chip and the second semiconductor chip, a semiconductor device capable of suppressing noise acting between the chips even when integrated as a stack type can be manufactured.

第３実施形態
図１０は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
本実施形態の半導体装置は、第１実施形態の半導体装置と同様の構成であって、さらに、基板１０が能動素子を有する半導体基板であり、基板１０と第１半導体チップ１２の間の所定の領域においてノイズ遮蔽層ＳＤｄが形成されている。一方で、第１実施形態と異なり、第１半導体チップ１２と第２半導体チップ１６との間にはノイズ遮蔽層は形成されていない。ノイズ遮蔽層ＳＤｄは、例えばグラウンドなどの一定の電位に保持される。
上記のノイズ遮蔽層ＳＤｄは、例えば第１実施形態と同様に、上記の所定の領域を全面に被覆する導電層から構成されており、ノイズ遮蔽層ＳＤｄが形成されている所定の領域は、第１半導体チップ１２の領域全体または一部を被覆する領域である。 Third Embodiment FIG. 10 is a sectional view of a SiP type semiconductor device according to this embodiment.
The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment, and the substrate 10 is a semiconductor substrate having an active element. A noise shielding layer SDd is formed in the region. On the other hand, unlike the first embodiment, no noise shielding layer is formed between the first semiconductor chip 12 and the second semiconductor chip 16. The noise shielding layer SDd is held at a constant potential such as ground.
The noise shielding layer SDd is composed of a conductive layer that covers the predetermined area over the entire surface, for example, as in the first embodiment. The predetermined area where the noise shielding layer SDd is formed is 1 This is a region that covers the whole or a part of the semiconductor chip 12.

上記の本実施形態に係る半導体装置は、第１実施形態と同様に、ＳｉＰ形態の半導体装置において、基板と２個の半導体チップが積層して一体化したスタック型であるが、積層された基板と第１半導体チップの間にノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。また、本実施形態において、第２半導体チップはなくてもよい。 As in the first embodiment, the semiconductor device according to the present embodiment is a stack type in which a substrate and two semiconductor chips are stacked and integrated in the SiP type semiconductor device. In this configuration, a noise shielding layer is formed between the first semiconductor chip and the noise acting between the chips, such as digital noise.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip. In the present embodiment, the second semiconductor chip may not be provided.

上記の本実施形態に係る半導体装置は、基板１０として能動素子を有する半導体基板を用い、基板１０と第１半導体チップ１２の間にノイズ遮蔽層ＳＤｄを形成する、即ち、第１半導体チップ１２のマウント工程前に第１半導体チップ１２の領域にノイズ遮蔽層ＳＤｄを形成し、一方で第１半導体チップ１２と第２半導体チップ１６との間にはノイズ遮蔽層を形成しないことにより、他の工程は第１実施形態と同様にして形成することができる。   The semiconductor device according to the present embodiment uses a semiconductor substrate having an active element as the substrate 10 and forms the noise shielding layer SDd between the substrate 10 and the first semiconductor chip 12. The noise shielding layer SDd is formed in the region of the first semiconductor chip 12 before the mounting process, while the noise shielding layer is not formed between the first semiconductor chip 12 and the second semiconductor chip 16, thereby allowing other processes. Can be formed in the same manner as in the first embodiment.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された基板と第１半導体チップの間にノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method of manufacturing a semiconductor device according to the above-described embodiment, as in the first embodiment, when manufacturing a SiP-type semiconductor device, a noise shielding layer is provided between the stacked substrate and the first semiconductor chip. Therefore, it is possible to manufacture a semiconductor device capable of suppressing noise acting between the chips even when integrated as a stack type.

第４実施形態
図１１は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。また、図１２は本実施形態に係るＳｉＰ形態の半導体装置のノイズ遮蔽層のレイアウト図である。
本実施形態の半導体装置は、第１実施形態の半導体装置と同様の構成であって、第１半導体チップ１２と第２半導体チップ１６との間の所定の領域において、第２半導体チップの領域を被覆するように、所定の領域に全面に形成された導電層に対して、所定の大きさの開口部が多数並んで形成されたメッシュ状導電層であるノイズ遮蔽層ＳＤｅが形成されている。ノイズ遮蔽層ＳＤｅは、例えばグラウンドなどの一定の電位に保持される。
また、本実施形態におけるノイズ遮蔽層ＳＤｅは、第１配線１５として延伸領域Ｅが形成されており、一部のパッドにおいて第１半導体チップ１２に接続してグラウンド電位などを与えており、さらに基板１０に接続され、第１半導体チップ１２または第２半導体チップ１６で発生した熱を基板１０に輸送する熱放散路として機能する構成となっている。
一方、第１半導体チップ１２の他のパッドにはパッド接続用の第１配線Ｐ（１５）が形成されている。 Fourth Embodiment FIG. 11 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment. FIG. 12 is a layout diagram of the noise shielding layer of the SiP type semiconductor device according to this embodiment.
The semiconductor device of this embodiment has the same configuration as that of the semiconductor device of the first embodiment, and the region of the second semiconductor chip is defined in a predetermined region between the first semiconductor chip 12 and the second semiconductor chip 16. A noise shielding layer SDe, which is a mesh-like conductive layer in which a large number of openings having a predetermined size are arranged side by side with respect to the conductive layer formed on the entire surface in a predetermined region, is formed so as to cover. The noise shielding layer SDe is held at a constant potential such as ground.
In addition, the noise shielding layer SDe in the present embodiment has the extended region E formed as the first wiring 15 and is connected to the first semiconductor chip 12 at some pads to give a ground potential or the like. 10 is configured to function as a heat dissipation path for transporting heat generated in the first semiconductor chip 12 or the second semiconductor chip 16 to the substrate 10.
On the other hand, first pads P (15) for pad connection are formed on the other pads of the first semiconductor chip 12.

上記のノイズ遮蔽層ＳＤｅが形成されている所定の領域は第２半導体チップ１６の領域全体または一部を被覆する領域である。
また、ノイズ遮蔽層ＳＤｅに形成された多数の開口部は、例えば１辺が３０μｍ程度の正方形であり、開口部間の導電層の幅も３０μｍ程度となっている。開口部の形状および大きさと開口部間の導電層の幅は、第１半導体チップ１２と第２半導体チップ１６の間で遮蔽しようとするノイズの周波数に応じて適宜変更可能である。 The predetermined region where the noise shielding layer SDe is formed is a region covering the entire region or a part of the second semiconductor chip 16.
In addition, the large number of openings formed in the noise shielding layer SDe are, for example, squares each having a side of about 30 μm, and the width of the conductive layer between the openings is also about 30 μm. The shape and size of the opening and the width of the conductive layer between the openings can be appropriately changed according to the frequency of noise to be shielded between the first semiconductor chip 12 and the second semiconductor chip 16.

上記の本実施形態に係る半導体装置は、第１実施形態と同様に、ＳｉＰ形態の半導体装置において、基板上に２個の半導体チップが積層して一体化したスタック型であるが、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。 As in the first embodiment, the semiconductor device according to the present embodiment is a stack type in which two semiconductor chips are stacked and integrated on a substrate in a SiP-type semiconductor device. In this configuration, a noise shielding layer is formed between the first semiconductor chip and the second semiconductor chip, and noise acting between the chips such as digital noise can be suppressed.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip.

上記の本実施形態に係る半導体装置は、第１実施形態における半導体装置の製造方法において、ノイズ遮蔽層を上記のようにメッシュ状導電層にパターン加工することで、他の工程は第１実施形態と同様にして形成することができる。また、本実施形態のノイズ遮蔽層は、第１配線を利用してパターン形成することも可能である。   In the semiconductor device manufacturing method according to the first embodiment, the noise shielding layer is patterned into a mesh-like conductive layer as described above in the semiconductor device manufacturing method according to the first embodiment, and other processes are performed in the first embodiment. It can be formed in the same manner. Moreover, the noise shielding layer of this embodiment can also be patterned using the first wiring.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device according to the above-described embodiment, as in the first embodiment, when a SiP-type semiconductor device is manufactured, between the stacked first and second semiconductor chips. Since the noise shielding layer is formed, it is possible to manufacture a semiconductor device that can suppress noise acting between chips even when integrated as a stack type.

第５実施形態
図１３は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。また、図１４（ａ）は本実施形態に係るＳｉＰ形態の半導体装置の基板と第１半導体チップ間のノイズ遮蔽層のレイアウト図であり、図１４（ｂ）は第１半導体チップと第２半導体チップ間のノイズ遮蔽層のレイアウト図である。
本実施形態の半導体装置は、第２実施形態の半導体装置と同様の構成であって、基板１０と第１半導体チップ１２との間の所定の領域において、第１半導体チップの領域を被覆するように、所定の領域に全面に形成された導電層に対して、所定の大きさの開口部が多数並んで形成されたメッシュ状導電層であるノイズ遮蔽層ＳＤｆが形成されている。一方、第１半導体チップ１２と第２半導体チップ１６との間の所定の領域において、第２半導体チップの領域を被覆するように、所定の領域に全面に形成された導電層に対して、所定の大きさの開口部が多数並んで形成されたメッシュ状導電層であるノイズ遮蔽層ＳＤｇが形成されている。ノイズ遮蔽層（ＳＤｆ，ＳＤｇ）は、例えばグラウンドなどの一定の電位に保持される。本実施形態においては、ノイズ遮蔽層ＳＤｆもノイズ遮蔽層ＳＤｇと同様の延伸領域Ｅが形成され、基板に接して熱放散路として機能する構成である。
本実施形態においては、第３実施形態と同様に、ノイズ遮蔽層ＳＤｇが形成されていない構成としてもよい。
メッシュ状導電層の開口部の形状および大きさと開口部間の幅は、第４実施形態のメッシュ状導電層の説明と同様である。 Fifth Embodiment FIG. 13 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment. FIG. 14A is a layout diagram of a noise shielding layer between the substrate of the SiP-type semiconductor device and the first semiconductor chip according to the present embodiment, and FIG. 14B is a diagram illustrating the first semiconductor chip and the second semiconductor. It is a layout figure of the noise shielding layer between chips.
The semiconductor device of this embodiment has the same configuration as that of the semiconductor device of the second embodiment, and covers a region of the first semiconductor chip in a predetermined region between the substrate 10 and the first semiconductor chip 12. In addition, a noise shielding layer SDf, which is a mesh-like conductive layer in which a large number of openings having a predetermined size are arranged side by side with respect to the conductive layer formed on the entire surface in a predetermined region, is formed. On the other hand, in a predetermined region between the first semiconductor chip 12 and the second semiconductor chip 16, the conductive layer formed on the entire surface in the predetermined region so as to cover the region of the second semiconductor chip is predetermined. A noise shielding layer SDg, which is a mesh-like conductive layer formed with a large number of openings having a size of, is formed. The noise shielding layers (SDf, SDg) are held at a constant potential such as ground. In the present embodiment, the noise shielding layer SDf also has a configuration in which an extension region E similar to the noise shielding layer SDg is formed and functions as a heat dissipation path in contact with the substrate.
In the present embodiment, as in the third embodiment, the noise shielding layer SDg may not be formed.
The shape and size of the openings of the mesh-like conductive layer and the width between the openings are the same as those described for the mesh-like conductive layer of the fourth embodiment.

上記の本実施形態に係る半導体装置は、第１実施形態と同様に、ＳｉＰ形態の半導体装置において、基板と２個の半導体チップが積層して一体化したスタック型であるが、積層された基板と第１半導体チップの間および第１半導体チップと第２半導体チップの間にそれぞれノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。 As in the first embodiment, the semiconductor device according to the present embodiment is a stack type in which a substrate and two semiconductor chips are stacked and integrated in the SiP type semiconductor device. Noise shielding layers are formed between the first semiconductor chip and the first semiconductor chip and between the first semiconductor chip and the second semiconductor chip, so that noise acting between the chips such as digital noise can be suppressed.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip.

上記の本実施形態に係る半導体装置は、第２実施形態における半導体装置の製造方法において、各ノイズ遮蔽層（ＳＤｆ，ＳＤｇ）を上記のようにメッシュ状導電層にパターン加工することで、他の工程は第１実施形態と同様にして形成することができる。   In the semiconductor device manufacturing method according to the second embodiment, each of the noise shielding layers (SDf, SDg) is patterned into a mesh-like conductive layer as described above in the semiconductor device manufacturing method according to the second embodiment. The process can be formed in the same manner as in the first embodiment.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された基板と第１半導体チップの間および第１半導体チップと第２半導体チップの間にそれぞれノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device according to the present embodiment, when manufacturing a SiP-type semiconductor device, as in the first embodiment, between the stacked substrate and the first semiconductor chip and the first semiconductor. Since the noise shielding layer is formed between the chip and the second semiconductor chip, a semiconductor device capable of suppressing noise acting between the chips even when integrated as a stack type can be manufactured.

第６実施形態
図１５（ａ）は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。また、図１５（ｂ）および（ｃ）は本実施形態に係るＳｉＰ形態の半導体装置のノイズ遮蔽層の構成を示す模式的斜視図である。
本実施形態の半導体装置は、第１実施形態の半導体装置と同様の構成であって、第１半導体チップ１２と第２半導体チップ１６との間の所定の領域において、第２半導体チップの領域を被覆するように、ノイズ遮蔽層ＳＤｈが形成されている。ここで、ノイズ遮蔽層ＳＤｈは、所定の領域において、略直方体の導電部Ｃｃと絶縁部Ｃｉが交互に敷き詰められて形成されたメッシュ状導電層である。各導電部Ｃｃは、角において隣接する導電部に接しており、所定の領域全体で面内方向に導電性を有する構造となっている。
例えば、図１５（ｂ）に示すように、略直方体の導電部Ｃｃと絶縁部Ｃｉが交互に敷き詰められて形成された第１メッシュ状導電層Ｍ１と、略直方体の導電部Ｃｃと絶縁部Ｃｉが交互に敷き詰められて形成された第２メッシュ状導電層Ｍ２の複数のメッシュ状導電層が、積層方向にも導電部Ｃｃと絶縁部Ｃｉが交互に配置されるように積層して形成されている構成である。第１メッシュ状導電層Ｍ１の１層構成であってもよい。また、ノイズ遮蔽層ＳＤｈは、例えばグラウンドなどの一定の電位に保持される。 Sixth Embodiment FIG. 15A is a sectional view of a SiP-type semiconductor device according to this embodiment. FIGS. 15B and 15C are schematic perspective views showing the configuration of the noise shielding layer of the SiP-type semiconductor device according to this embodiment.
The semiconductor device of this embodiment has the same configuration as that of the semiconductor device of the first embodiment, and the region of the second semiconductor chip is defined in a predetermined region between the first semiconductor chip 12 and the second semiconductor chip 16. A noise shielding layer SDh is formed so as to cover it. Here, the noise shielding layer SDh is a mesh-like conductive layer formed by alternately laying substantially rectangular parallelepiped conductive portions Cc and insulating portions Ci in a predetermined region. Each conductive part Cc is in contact with an adjacent conductive part at a corner, and has a structure having conductivity in the in-plane direction over the entire predetermined region.
For example, as shown in FIG. 15 (b), a first mesh conductive layer M1 formed by alternately laying a substantially rectangular parallelepiped conductive portion Cc and an insulating portion Ci, a substantially rectangular parallelepiped conductive portion Cc and an insulating portion Ci. A plurality of mesh-like conductive layers of the second mesh-like conductive layer M2 formed by alternately laying layers are formed so that the conductive portions Cc and the insulating portions Ci are alternately arranged also in the stacking direction. It is the composition which is. A one-layer configuration of the first mesh-like conductive layer M1 may be used. The noise shielding layer SDh is held at a constant potential such as ground.

上記のノイズ遮蔽層ＳＤｈが形成されている所定の領域は第２半導体チップ１６の領域全体または一部を被覆する領域である。
また、ノイズ遮蔽層ＳＤｈを構成する導電部Ｃｃは、例えば１辺が３０μｍ程度の立方体であり、絶縁部の１辺も３０μｍ程度となっている。導電部Ｃｃの１辺の長さは、第１半導体チップ１２と第２半導体チップ１６の間で遮蔽しようとするノイズの周波数に応じて適宜変更可能である。 The predetermined region where the noise shielding layer SDh is formed is a region covering the entire region or a part of the second semiconductor chip 16.
Further, the conductive portion Cc constituting the noise shielding layer SDh is, for example, a cube having one side of about 30 μm, and one side of the insulating portion is also about 30 μm. The length of one side of the conductive portion Cc can be appropriately changed according to the frequency of noise to be shielded between the first semiconductor chip 12 and the second semiconductor chip 16.

上記の本実施形態に係る半導体装置は、第１実施形態と同様に、ＳｉＰ形態の半導体装置において、基板上に２個の半導体チップが積層して一体化したスタック型であるが、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。
本実施形態においては、第２実施形態と同様に、上記の構成のノイズ遮蔽層が基板と第１半導体チップ間にも形成されていてもよい。あるいは、第３実施形態と同様に、上記の構成のノイズ遮蔽層が基板と第１半導体チップ間のみに形成されている構成でもよい。 As in the first embodiment, the semiconductor device according to the present embodiment is a stack type in which two semiconductor chips are stacked and integrated on a substrate in a SiP-type semiconductor device. In this configuration, a noise shielding layer is formed between the first semiconductor chip and the second semiconductor chip, and noise acting between the chips such as digital noise can be suppressed.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip.
In the present embodiment, as in the second embodiment, the noise shielding layer having the above configuration may be formed between the substrate and the first semiconductor chip. Or similarly to 3rd Embodiment, the structure by which the noise shielding layer of said structure was formed only between the board | substrate and the 1st semiconductor chip may be sufficient.

上記の本実施形態に係る半導体装置は、第１実施形態における半導体装置の製造方法において、ノイズ遮蔽層を上記のようにメッシュ状にパターン形成することで、他の工程は第１実施形態と同様にして形成することができる。   In the semiconductor device manufacturing method according to the first embodiment, the semiconductor device according to the present embodiment described above is similar to the first embodiment except that the noise shielding layer is formed in a mesh pattern as described above. Can be formed.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device according to the above-described embodiment, as in the first embodiment, when a SiP-type semiconductor device is manufactured, between the stacked first and second semiconductor chips. Since the noise shielding layer is formed, it is possible to manufacture a semiconductor device that can suppress noise acting between chips even when integrated as a stack type.

第７実施形態
図１６は本実施形態に係るＳｉＰ形態の半導体装置の断面図である。
本実施形態の半導体装置は、第１実施形態の半導体装置と同様の構成であって、第１半導体チップ１２と第２半導体チップ１６との間の所定の領域において、第２半導体チップの領域を被覆するように、ノイズ遮蔽層が形成されているものであり、本実施形態におけるノイズ遮蔽層は、導電性ポスト１５ｃとそれに接続する導電層１５ｄおよび、それらの間隙を埋め込む絶縁層１４ａからなる構成となっている。
また、本実施形態では、第２絶縁層１８内においても導電性ポスト１５ｅが形成されている。
上記のように、ノイズ遮蔽層として導電性ポスト１５ｃとこれに接続する導電層１５ｄが形成されているので、第１半導体チップと第２半導体チップの間の距離を遠ざける効果を有し、これによってノイズを抑制することができる。即ち、ＳｉＰ形態の半導体装置において、基板上に２個の半導体チップが積層して一体化したスタック型であるが、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層が形成された構成であり、デジタルノイズなどのチップ間に作用するノイズを抑制することができる。
基板、第１半導体チップ、第２半導体チップは、それぞれ、デジタルチップとアナログチップのいずれでもよい。 Seventh Embodiment FIG. 16 is a cross-sectional view of a SiP-type semiconductor device according to this embodiment.
The semiconductor device of this embodiment has the same configuration as that of the semiconductor device of the first embodiment, and the region of the second semiconductor chip is defined in a predetermined region between the first semiconductor chip 12 and the second semiconductor chip 16. A noise shielding layer is formed so as to cover, and the noise shielding layer in the present embodiment is composed of a conductive post 15c, a conductive layer 15d connected to the conductive post 15c, and an insulating layer 14a filling the gap therebetween. It has become.
In the present embodiment, the conductive posts 15 e are also formed in the second insulating layer 18.
As described above, since the conductive post 15c and the conductive layer 15d connected to the conductive post 15c are formed as the noise shielding layer, it has the effect of increasing the distance between the first semiconductor chip and the second semiconductor chip. Noise can be suppressed. In other words, the SiP type semiconductor device is a stack type in which two semiconductor chips are stacked and integrated on a substrate, but a noise shielding layer is formed between the stacked first and second semiconductor chips. Thus, noise acting between chips such as digital noise can be suppressed.
Each of the substrate, the first semiconductor chip, and the second semiconductor chip may be a digital chip or an analog chip.

上記の本実施形態に係る半導体装置は、第１実施形態における半導体装置の製造方法において、ノイズ遮蔽層として、導電性ポストを他数個隣接して形成することで、他の工程は第１実施形態と同様にして形成することができる。   In the semiconductor device manufacturing method according to the first embodiment, in the semiconductor device manufacturing method according to the first embodiment, several other conductive posts are formed adjacent to each other as the noise shielding layer. It can be formed in the same manner as the form.

上記の本実施形態に係る半導体装置の製造方法によれば、第１実施形態と同様に、ＳｉＰ形態の半導体装置を製造する際に、積層された第１半導体チップと第２半導体チップの間にノイズ遮蔽層を形成するので、スタック型として一体化してもチップ間に作用するノイズを抑制可能な半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device according to the above-described embodiment, as in the first embodiment, when a SiP-type semiconductor device is manufactured, between the stacked first and second semiconductor chips. Since the noise shielding layer is formed, it is possible to manufacture a semiconductor device that can suppress noise acting between chips even when integrated as a stack type.

本発明は上記の説明に限定されない。
例えば、第４および第５実施形態における延伸領域の構成は、他の実施形態において採用されてもよい。
また、第１および第２配線などに、インダクタンスやキャパシタなどの受動素子が形成されていてもよい。
実施形態においては、絶縁層中の配線として２層の配線（第１配線および第２配線）が形成されているが、これに限らない。樹脂の絶縁層の層数も上記のような２層などに限定されない。
バッファ層や第１〜第４絶縁層に用いる樹脂は上記に限らず、その他の樹脂を用いることもできる。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。 The present invention is not limited to the above description.
For example, the structure of the extending | stretching area | region in 4th and 5th embodiment may be employ | adopted in other embodiment.
Also, passive elements such as inductances and capacitors may be formed on the first and second wirings.
In the embodiment, two layers of wiring (first wiring and second wiring) are formed as the wiring in the insulating layer, but the present invention is not limited to this. The number of resin insulation layers is not limited to the two layers as described above.
The resin used for the buffer layer and the first to fourth insulating layers is not limited to the above, and other resins can also be used.
In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置は、システムインパッケージ形態の半導体装置に適用できる。   The semiconductor device of the present invention can be applied to a semiconductor device in a system in package form.

本発明の半導体装置の製造方法は、システムインパッケージ形態の半導体装置の製造方法に適用できる。   The semiconductor device manufacturing method of the present invention can be applied to a system-in-package semiconductor device manufacturing method.

図１は本発明の第１実施形態に係る半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. 図２（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。2A to 2C are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図３（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。3A to 3C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図４（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。4A to 4C are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図５（ａ）〜（ｃ）は本発明の第１実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。5A to 5C are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図６（ａ）および図６（ｂ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 6A and FIG. 6B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図７（ａ）および図７（ｂ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 7A and FIG. 7B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the embodiment of the present invention. 図８（ａ）および図８（ｂ）は本発明の実施形態に係る半導体装置の製造方法の製造工程を示す断面図である。FIG. 8A and FIG. 8B are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention. 図９は本発明の第２実施形態に係る半導体装置の断面図である。FIG. 9 is a sectional view of a semiconductor device according to the second embodiment of the present invention. 図１０は本発明の第３実施形態に係る半導体装置の断面図である。FIG. 10 is a sectional view of a semiconductor device according to the third embodiment of the present invention. 図１１は本発明の第４実施形態に係る半導体装置の断面図である。FIG. 11 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. 図１２は本発明の第４実施形態に係る半導体装置のノイズ遮蔽層のレイアウト図である。FIG. 12 is a layout diagram of the noise shielding layer of the semiconductor device according to the fourth embodiment of the present invention. 図１３は本発明の第５実施形態に係る半導体装置の断面図である。FIG. 13 is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. 図１４（ａ）は本発明の第５実施形態に係るＳｉＰ形態の半導体装置の基板と第１半導体チップ間のノイズ遮蔽層のレイアウト図であり、図１４（ｂ）は第１半導体チップと第２半導体チップ間のノイズ遮蔽層のレイアウト図である。FIG. 14A is a layout diagram of the noise shielding layer between the substrate of the SiP-type semiconductor device and the first semiconductor chip according to the fifth embodiment of the present invention, and FIG. 14B is the first semiconductor chip and the first semiconductor chip. It is a layout figure of the noise shielding layer between two semiconductor chips. 図１５（ａ）は本発明の第６実施形態に係る半導体装置の断面図であり、図１５（ｂ）および（ｃ）はノイズ遮蔽層の構成を示す模式的斜視図である。FIG. 15A is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention, and FIGS. 15B and 15C are schematic perspective views showing the configuration of a noise shielding layer. 図１６は本発明の第７実施形態に係るＳｉＰ形態の半導体装置の断面図である。FIG. 16 is a cross-sectional view of a SiP-type semiconductor device according to the seventh embodiment of the present invention.

符号の説明Explanation of symbols

１０…シリコン基板、１１…下地絶縁膜、１２…第１半導体チップ、１２ａ…半導体本体部分、１２ｂ…パッド、１２ｃ…保護層、１３…ダイアタッチフィルム、１４…第１絶縁層、１５…第１配線、１５ａ，１９ａ…バリアメタル層、１５ｂ，１９ｂ…銅層、１５ｃ，１５ｅ…導電性ポスト、１５ｄ…導電層、１６…第２半導体チップ、１６ａ…半導体本体部分、１６ｂ…パッド、１６ｃ…保護層、１７…ダイアタッチフィルム、１８第２絶縁層、１９…第２配線、２０…導電性ポスト、２１…バッファ層、２２…バンプ、ＳＤａ〜ＳＤｈ…ノイズ遮蔽層、Ｅ…延伸領域、Ｐ…パッド接続用の第１配線、Ｃｃ…導電部、Ｃｉ…絶縁部、Ｍ１…第１メッシュ状導電層、Ｍ２…第２メッシュ状導電層、Ｒ１，Ｒ２…レジスト膜
DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Base insulating film, 12 ... 1st semiconductor chip, 12a ... Semiconductor main-body part, 12b ... Pad, 12c ... Protection layer, 13 ... Die attach film, 14 ... 1st insulating layer, 15 ... 1st Wiring, 15a, 19a ... barrier metal layer, 15b, 19b ... copper layer, 15c, 15e ... conductive post, 15d ... conductive layer, 16 ... second semiconductor chip, 16a ... semiconductor body portion, 16b ... pad, 16c ... protection Layer, 17 ... die attach film, 18 second insulating layer, 19 ... second wiring, 20 ... conductive post, 21 ... buffer layer, 22 ... bump, SDa to SDh ... noise shielding layer, E ... stretched region, P ... First wiring for pad connection, Cc ... conductive portion, Ci ... insulating portion, M1 ... first mesh conductive layer, M2 ... second mesh conductive layer, R1, R2 ... resist film

Claims (4)

半導体を含んでパッケージ化されており、
能動素子を含む第１半導体チップと、
前記第１半導体チップの上層の所定の領域に形成されたノイズ遮蔽層と、
前記ノイズ遮蔽層の上層に積層された能動素子を含む第２半導体チップと
を有し、
前記ノイズ遮蔽層は、前記所定の領域において、略直方体の導電部と絶縁部が交互に敷き詰められて形成されたメッシュ状導電層である
半導体装置。 Packaged with semiconductors,
A first semiconductor chip including active elements;
A noise shielding layer formed in a predetermined region of the upper layer of the first semiconductor chip;
A second semiconductor chip including an active element stacked on an upper layer of the noise shielding layer,
The noise shielding layer is a mesh-like conductive layer formed by alternately laying a substantially rectangular parallelepiped conductive portion and an insulating portion in the predetermined region . 前記ノイズ遮蔽層として、積層方向にも前記導電部と前記絶縁部が交互に配置されるように、前記メッシュ状導電層が複数積層して形成されている
請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein the noise shielding layer is formed by laminating a plurality of the mesh-like conductive layers so that the conductive portions and the insulating portions are alternately arranged in the stacking direction. 半導体を含んでパッケージ化された半導体装置を製造するために、
能動素子を含む第１半導体チップの上層の所定の領域に、ノイズ遮蔽層を形成する工程と、
前記ノイズ遮蔽層の上層に、能動素子を含む第２半導体チップを積層する工程と
を有し、
前記ノイズ遮蔽層を形成する工程においては、前記所定の領域において、略直方体の導電部と絶縁部を交互に敷き詰めて、前記ノイズ遮蔽層としてメッシュ状導電層を形成する
半導体装置の製造方法。 In order to manufacture a semiconductor device packaged including a semiconductor,
Forming a noise shielding layer in a predetermined region of the upper layer of the first semiconductor chip including the active element;
Laminating a second semiconductor chip including an active element on the noise shielding layer, and
In the step of forming the noise shielding layer, a method for manufacturing a semiconductor device includes forming a mesh-like conductive layer as the noise shielding layer by alternately laying substantially rectangular conductive parts and insulating parts in the predetermined region . 前記ノイズ遮蔽層を形成する工程において、積層方向にも前記導電部と前記絶縁部が交互に配置されるように、前記ノイズ遮蔽層として前記メッシュ状導電層を複数積層して形成する
請求項３に記載の半導体装置の製造方法。 In the step of forming said noise shielding layer, so that the insulating portion and the conductive portion are alternately arranged in the stacking direction, claim 3 formed by stacking a plurality of the mesh-shaped conductive layer as the noise shielding layer The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
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US8736065B2 (en) * 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
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