JP4498500B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device that supplies power to a plurality of functional blocks.
[0002]
[Prior art]
In a semiconductor device, as the degree of integration increases due to progress in miniaturization, a plurality of circuits having different functions are mounted on one chip for the purpose of simplifying the configuration of the electronic device on which the semiconductor device is mounted or improving performance. ing. Power is supplied to the plurality of mounted functional blocks by power wiring for each block.
[0003]
In addition, a semiconductor device is required to increase speed in order to perform more advanced processing, and power consumption increases due to such speed increase. Such an increase in power consumption causes problems such as an increase in the amount of heat generated by the semiconductor device and an obstacle to stable operation, or an increase in power consumption shortens the usable time of a portable device. For this reason, reduction in power consumption of the semiconductor device is required. For example, a method is adopted in which the circuit is brought into a non-operating state by stopping the clock of the non-operating block to reduce the power consumption. Japanese Patent Laid-Open No. 6-85666 discloses a technique for reducing power consumption by changing the clock frequency.
[0004]
Further, the transistor withstand voltage is lowered due to the miniaturization of the transistor, and the operating voltage of the transistor is inevitably lowered. However, when the operating voltage of the transistor is lowered, the current driving capability is lowered, so that the speed is degraded. In order to operate at a low voltage without impairing the operation speed, a technique for improving the current driving capability and reducing the delay time by reducing the threshold voltage Vth of the transistor is adopted as a technique for speeding up the MIS transistor. Has been.
[0005]
[Problems to be solved by the invention]
However, by reducing the threshold voltage Vth, the subthreshold current becomes a problem. Since the leakage current increases and the leakage current flows even when the clock operation is stopped, the through current flows even in the complementary CMIS circuit regardless of the leakage current, and cannot be ignored.
[0006]
That is, the power supply leakage current increases by lowering the threshold voltage, and the power consumption during non-operation cannot be ignored. This power supply leakage current cannot be dealt with by stopping the circuit operation when the clock is stopped, and the power consumption due to the power supply leakage current when the clock is not operated cannot be reduced.
[0007]
An object of the present invention is to provide a technique capable of reducing power consumption due to a leakage current during non-operation of a circuit built in a semiconductor device and achieving both low power and high speed.
[0008]
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for solving problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0010]
In a semiconductor device having a plurality of circuit blocks and power is supplied to each block by power supply wiring, the power supplied by the inter-block power supply wiring is supplied to the power in the block via a power control circuit provided in each block. For example, the power control circuit provided in each block is supplied by wiring, and the power control circuit provided in each block is supplied by the control signal transmitted from the central control circuit according to the operation / non-operation of each block when the block is not in operation. Reduce the power supply voltage in the block.
[0011]
The drain current in the subthreshold region is almost independent of Vds and changes with an exponential function of the difference between the gate voltage Vgs and the threshold value.
[0012]
As for the subthreshold characteristics of the transistor, if the drain-source voltage Vds, the gate-source voltage Vgs, the temperature T, the constant k, and the charge q, the flowing current I is
I∝ (1-exp (−qVds / kT)) × exp (qVgs / kT)
Corresponding to the fact that Vds decreases when the power supply voltage is lowered, the current is substantially constant at the low power supply voltage of 1v to 3v that is usually used at present, and the power consumption due to the leakage current is the power supply voltage. Is proportional to Therefore, by reducing the power supply voltage when the circuit is not operating, leakage current is reduced and power consumption can be reduced.
[0013]
Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a schematic plan view illustrating the arrangement of circuit blocks having various functions constituting a semiconductor device according to an embodiment of the invention. In addition, each circuit block shown in FIG. 1 is a circuit in which active elements such as FETs and passive elements such as resistors are connected by wiring in the same manner as usual. A plurality of circuit blocks 1 and one central control circuit 2 are provided in the same chip, and a power control circuit 3 that receives a control signal from the central control circuit 2 is provided in each circuit block 1.
[0015]
FIG. 2 is a schematic plan view illustrating the inter-block power supply wiring 4. The inter-block power supply wiring 4 extends in the vertical direction and the horizontal direction over the entire chip area and is connected to the power control circuit 3 of each block 1 (illustrated by broken lines). ing.
[0016]
FIG. 3 is a schematic diagram illustrating the intra-block power supply wiring. The intra-block power supply wiring 5 extends in the vertical direction and the horizontal direction over the entire block and is separated for each block 1. Separated and supplied with a potential controlled from the power control circuit 3 of each block 1.
[0017]
That is, as shown in FIG. 4, the power supplied by the inter-block power supply wiring 4 is supplied to the intra-block gate circuit or the like by the intra-block power supply wiring 5 via the power control circuit 3 provided in each block 1. The power control circuit 3 provided in each block 1 is controlled by a control signal transmitted from the central control circuit 2 according to the operation / non-operation of each block. For example, the power supply voltage is lowered to a standby potential of about ½ of the operating potential by a step-down circuit. The standby potential may be different depending on the function of each circuit. For example, when it is necessary to maintain a circuit state such as a flip-flop even when not operating, the standby potential is a potential necessary to maintain the state. In a circuit that does not function at all during non-operation, the potential may be the ground potential.
[0018]
However, when the power supply potential is simply lowered, as shown in FIG. 5, the signal D1 from the logic circuit of the transmission block on the left side in the drawing causes the transmission signal D2 from the output unit to be high and the reception block on the right side in the drawing. Is sent to the input section of
When the transmission block is deactivated and the power supply potential VDDS is lowered, the transmission signal D2 from the output unit of the transmission side block is also lowered, and an intermediate level potential is applied to the inverter of the input unit of the reception block on the right side in the figure. As a result, both the p-type FET and the n-type FET of the inverter are turned on, and the leakage current due to the power supply leakage in the block flows from the power supply potential VDDK to the ground.
[0019]
For this reason, in this embodiment, as shown in FIG. 6, a level shift circuit is provided at the input section of the reception block. In the level shift circuit, the p-type FET functions as a pull-up resistor, and when the transmission block becomes non-operational and the transmission signal D2 falls, the input of the reception block in the operation state is in the operation block. Boosting to the power supply potential, preventing a power supply leak in the block due to an intermediate level potential being applied to the input section, and enabling signal transfer between different potential power supply blocks.
[0020]
Further, when the level shift is performed as shown in FIG. 6, in a state where the transmission block becomes non-operating and the block power supply potential VDDS is lowered, the reception block having a high power supply potential VDDK in the operating state is changed from Power leakage occurs between block power supplies. In order to prevent this leakage, as shown in FIG. 7, in this embodiment, a leakage current interruption circuit is provided at the output section of the transmission block. In the leakage current cutoff circuit, a NAND circuit is connected in series to the p-type FET of the output unit, and an inverter circuit is connected in series to the n-type FET of the output unit. This leakage current cut-off circuit operates with the truth value displayed in FIG. 8 according to the control signal EN and the level of each signal, and in a non-operating state, the p-type FET of the output unit is set to a high impedance state to cut off the current between blocks To do.
[0021]
Note that the n-type FET added to the input unit of the reception block in FIG. 7 is the power supply potential in the block of the reception block when a high level signal is input in a state where the reception block is inactive and the power supply potential is lowered. Is provided with a function of lowering the signal level.
[0022]
In the semiconductor device of the present embodiment having the above-described configuration, the input / output characteristics of the transmission signal from the transmission block, that is, the input signal D2 to the reception block and the signal D3 in the reception block are shown in FIGS. When the power supply potential VDDS of the transmission block shown in FIG. 9 is higher than the power supply potential VDDK of the reception block, even if the input signal D2 increases, the in-block signal D3 is suppressed to the power supply potential VDDK when the reception block is not operating. When the power supply potential VDDS of the transmission block shown in FIG. 10 is lower than the power supply potential VDDK of the reception block, the in-block signal D3 is raised to the power supply potential VDDK during operation of the reception block even if the input signal D2 is low. Signal transfer between different potential power supply blocks can be performed without problems.
[0023]
In the embodiment described above, the power control circuit is provided in all the blocks. However, for example, the present invention can be implemented by selectively providing the power control circuit in a block having a large leakage current. It is also possible to control a plurality of behaving blocks with one power control circuit.
[0024]
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0025]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0026]
(1) According to the present invention, the power control circuit can reduce the power supply potential of the block when not in operation.
[0027]
(2) According to the present invention, there is an effect that the leakage current can be reduced by the effect (1).
[0028]
(3) According to the present invention, by providing a level shift circuit at the input portion of the block, there is an effect that signal transfer between different potential power supply blocks can be performed without any problem.
[0029]
(4) According to the present invention, by providing a leakage current cutoff circuit at the output part of the block, there is an effect that signal transfer between different potential power supply blocks can be performed without any problem.
[Brief description of the drawings]
FIG. 1 is a schematic plan view illustrating the arrangement of circuit blocks constituting a semiconductor device according to an embodiment of the invention;
FIG. 2 is a schematic plan view illustrating power supply wiring between blocks of a semiconductor device according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating power supply wiring in a block of the semiconductor device according to the embodiment of the invention.
FIG. 4 is a diagram illustrating power supply of a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating an operating state of a conventional semiconductor device.
FIG. 6 is a diagram illustrating an operating state of a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating an operating state of a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a diagram displaying a truth value of a leakage current cutoff circuit of a semiconductor device according to an embodiment of the present invention.
FIG. 9 is a graph showing input / output characteristics of a semiconductor device according to an embodiment of the present invention;
FIG. 10 is a graph showing input / output characteristics of a semiconductor device according to an embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Circuit block, 2 ... Central control circuit, 3 ... Power control circuit, 4 ... Power supply wiring between blocks, 5 ... Power supply wiring in a block.

Claims (3)

In a semiconductor device having a plurality of circuit blocks and power is supplied to each block by power supply wiring,
The power supplied by the inter-block power supply wiring is supplied into the block by the power supply wiring in the block via the power control circuit provided in each block, and the power control circuit provided in each block is supplied to each block. By the control signal transmitted from the central control circuit according to the operation / non-operation, the power supply voltage in the block to be supplied is lowered when the block is not operating,
Semiconductor device said blanking Lock level shift circuit in the input section of the click, characterized in that the leakage current cut-off circuit is provided at the output portion of the block.   The semiconductor device according to claim 1, wherein the block includes a logic circuit.   The semiconductor device according to claim 1, wherein the circuit constituting the block has a complementary circuit configuration.

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