JP4470555B2 - converter - Google Patents

Description

  The present invention relates to a converter mounted on various devices as a part of a power supply circuit.

A converter that uses resonance to reduce power loss is disclosed in Patent Document 1. Further, there is a converter disclosed in Patent Document 2 that can improve the power factor.
JP 07-255169 A JP 2001-136739 A

FIG. 14 is a circuit diagram showing an example of a conventional capacitor input type converter.
Similar to the converter of Patent Document 1, this converter is a converter that uses resonance to reduce power loss, and includes a filter 4 connected to an AC power source 1 via a filter 2 and a rectifier circuit 3. A smoothing capacitor 5 is connected between the output terminal 4a of the filter 4 and the ground terminal 4b. One electrode of a capacitor 6 for current resonance is connected to the output terminal 4 a of the filter 4, and the other electrode of the capacitor 6 is connected to one end of the primary winding 8 a of the transformer 8 via the leakage inductor 7. ing.

An N-channel MOS transistor (hereinafter referred to as NMOS) 9 serving as a switching element is connected between the other end of the primary winding 8a and one electrode of the capacitor 6. Between the other end of the primary winding 8a and the ground terminal 4b of the filter 4, a capacitor 10 for voltage pseudo resonance and an NMOS 11 serving as a switching element are connected in parallel.
Next, the operation of this converter will be described with reference to FIG.
FIG. 15 is a waveform diagram for explaining the operation of the converter of FIG.
The AC voltage generated by the AC power source 1 is filtered by the filter 2 and input to the rectifier circuit 3. The rectifier circuit 3 performs full-wave rectification of the AC voltage and outputs a pulsating voltage. The filter 4 filters the output voltage of the rectifier circuit 3, and the capacitor 5 charges and discharges the output voltage of the rectifier circuit 3 to generate a smoothed DC voltage.

  The capacitor 13 is charged based on the output voltage of the capacitor 5. When the charging voltage of the capacitor 13 exceeds a predetermined value, the control unit 14 is driven. The driven control unit 14 generates a control signal for turning on and off the NMOSs 9 and 11 and drives the gates of the NMOSs 9 and 11 by voltage. As a result, the NMOSs 9 and 11 are alternately turned on and off with a dead time in which both of them are not turned on.

  When the gate voltage of the NMOS 11 becomes a high level (hereinafter referred to as “H”) and the NMOS 11 is turned on, the positive electrode of the capacitor 5 is switched from the positive electrode of the capacitor 5 to the negative electrode of the capacitor 5 via the capacitor 6, the leakage inductor 7, the primary winding 8a, A current i1 flows. The current i1 is a current obtained by synthesizing a resonance current having a resonance frequency determined by the characteristics of the capacitor 6 and the leakage inductor 7 and an excitation current generated by exciting the primary winding 8a, and has a waveform shown in FIG. It becomes.

  A current corresponding to the resonance current of the current i1 flows through the secondary winding 8b of the transformer 8 and is applied to the load and the capacitor 22 via the diode 20, and the capacitor 22 is charged. The voltage applied to the primary winding 8 a of the transformer 8 generates a voltage corresponding to the winding ratio in the auxiliary winding 8 c, and this voltage is applied to the capacitor 13 via the diode 18. Thereby, the capacitor 13 is charged and the control unit 14 is continuously driven.

  When the NMOS 11 is turned off while the current i1 is flowing, the voltage V11 across the NMOS 11 and the voltage V9 across the NMOS 9 are voltage pseudo values determined by the capacitance of the capacitor 10 and the inductance of the leakage inductor 7 and the primary winding 8a. The voltage V11 across the NMOS 11 increases and the voltage V9 across the NMOS 9 decreases while changing with the resonance waveform.

  When the voltage V11 rises and reaches the power supply voltage E, the current i1 is commutated to the parasitic diode of the NMOS 9. Thereafter, when the control unit 14 turns on the NMOS 9, the current commutated to the parasitic diode of the NMOS 9 is reduced, the polarity (its direction) is changed, and the current flows to the NMOS 9. When the NMOS 9 is turned on, a current i 9 flows from the capacitor 6 to the NMOS 9, the primary winding 8 a, the leakage inductor 7, and the capacitor 6. The current i9 is a current obtained by synthesizing a resonance current having a resonance frequency determined by the capacitance of the capacitor 6 and the inductance of the leakage inductor 7 and an excitation current generated by exciting the primary winding 8a. It becomes the waveform shown in. A current corresponding to the resonance current of the current i9 flows through the secondary winding 8b and is given to the load and the capacitor 22 via the diode 21. The above operation is repeated, and a DC voltage is supplied to the load.

  By controlling the switching frequency of the NMOSs 9 and 11 at a frequency higher than the resonance frequency, the output power can be controlled and zero voltage switching in the NMOSs 9 and 11 can be realized.

  However, the converter of FIG. 14 is a capacitor input type converter, and the rectified current flows to the capacitor 5 only at the peak portion of the sine wave where the AC voltage generated by the AC power supply 1 is higher than the charging voltage of the capacitor 5. For this reason, the AC voltage, which is the input voltage, and the waveform of the input current are different from each other, the power factor is poor, and many harmonic currents are generated.

In recent years, a standard (for example, IEC61000-3-2) that regulates harmonic current flowing in a commercial AC power supply line has been established. Due to these standards, the converter of FIG. 14 cannot be used as it is.
In order to reduce the harmonic current, it is important to make the input current waveform close to a sine wave, and this is generally done by improving the power factor.

  As the simplest example, as shown in FIG. 16, a choke coil 30 is connected between the AC power source 1 and the rectifier circuit 3 to reduce the input peak voltage and lengthen the period in which the input current flows. Conceivable. However, when the choke coil 30 is adapted to the commercial frequency (50/60 Hz), there is a drawback that the choke coil 30 is large and heavy.

In order to reduce the harmonic current, an active filter 40 based on a boost chopper circuit may be provided in front of the converter as shown in FIG.
FIG. 17 is a circuit diagram showing another conventional converter.

  This converter is a converter provided with an active filter 40 as in the converter disclosed in the technical document 2. The active filter 40 boosts the low voltage portion of the AC voltage so that the input current can flow continuously, improving the power factor.

The conventional converter shown in FIG. 14 has a low power factor, and generates many harmonic currents.
On the other hand, in the converter of FIG. 16, when the choke coil 30 is made to correspond to the commercial frequency (50/60 Hz), the choke coil 30 is large and heavy.
In the converter of FIG. 17, the switching frequency in the active filter 40 is as high as several tens of KHz, and the active filter 40 includes a choke coil 41, a coil 42 that is electromagnetically coupled to the choke coil 41, a switching element 43, and a voltage detection device. Resistors 44 to 48, comparators 49 and 51, an operational amplifier 50, a multiplier circuit 52, a flip-flop 53, and the like are required. The choke coil 41 may be smaller than the choke coil 30 shown in FIG. 16, but the number of components constituting the others increases, and there is an increase in switching loss and an increase in switching noise.

  An object of the present invention is to provide a converter that has a small number of parts, is inexpensive, and can reduce harmonic current.

To achieve the above object, the converter according to the present onset Ming is connected between a rectifier circuit for rectifying an AC voltage, a first capacitor, and one electrode of the said rectifier circuit first capacitor a series circuit of the first coil and the first rectifying element, a series circuit of the second coil and second rectifying element connected between the other electrode of the said rectifier circuit first capacitor a transformer having a primary winding and a secondary winding, a first switching element connected between one end of one of the electrode and the primary winding of said first capacitor, said first capacitor A second switching element connected between the other electrode of the first winding and one end of the primary winding, one electrode connected to the other end of the primary winding, and the other electrode serving as the first coil and said first second connected to the connection point of the rectifying element And capacitor, one electrode connected to the other end of the primary winding, and a third capacitor and the other electrode connected to the connection point of the second coil and the second rectifying element, said first A switching control unit for turning on and off the switching element and the second switching element to flow current to the primary winding, output means for supplying energy corresponding to the current from the secondary winding to the load, and the first Means for outputting energy from the second capacitor to the first capacitor via the first coil; and means for outputting energy from the third capacitor to the first capacitor via the second coil; , characterized in that it comprises a.

  According to the present invention, it is possible to realize a converter that has a small number of parts, is inexpensive, and has a low harmonic current.

[First Embodiment]
FIG. 1 is a block diagram showing a converter according to the first embodiment of the present invention. Elements common to those in FIG. 14 are denoted by common reference numerals. FIG. 2 is a configuration diagram showing a main part of the control unit 14 in FIG.

In this converter, a coil 60, a diode 61 and a capacitor 62 are newly provided to the capacitor input type converter.
A filter 2 is connected to the AC power source 1, and a filter 4 is connected to the filter 2 via a rectifier circuit 3.

  One end of the coil 60 is connected to the negative output terminal 4 b of the filter 4, and the cathode of the diode 61 is connected to the other end of the coil 60. The anode of the smoothing capacitor 5 is connected to the anode of the diode 61. The positive electrode of the capacitor 5 is connected to the positive output terminal 4 a of the filter 4.

  One electrode of the capacitor 6 for current resonance is connected to the negative electrode of the capacitor 5, and the other electrode of the capacitor 6 is connected to one end of the primary winding 8 a of the transformer 8 via the leakage inductor 7. A capacitor 62 is connected between the other electrode of the capacitor 6 and the cathode of the diode 61.

  Between the other end of the primary winding 8a and one electrode of the capacitor 6, an N-channel MOS transistor (hereinafter referred to as NMOS) 9 as a switching element and a capacitor 10 for voltage quasi-resonance are connected in parallel. . An NMOS 11 serving as a switching element is connected between the other end of the primary winding 8a and the positive electrode of the capacitor 5.

  A resistor 12 and a capacitor 13 are further connected in series between the positive electrode and the negative electrode of the capacitor 5. The resistor 12 and the capacitor 13 are for driving the control unit 14. The control unit 14 controls on / off of the NMOSs 9 and 11. The ground terminal GND of the control unit 14 is connected to the negative electrode of the capacitor 5.

  As shown in FIG. 2, the control unit 14 includes a power supply terminal VCC, a feedback terminal FB, a drive power supply terminal VB, a reference voltage terminal VS, a ground terminal GND, and two gate drive terminals HD and LD. It has been. The gate drive terminals HD and LD are connected to the gates of the NMOSs 9 and 11, respectively.

  The control unit 14 includes an oscillator (OSC) 14a. An oscillator 14a is connected to the feedback terminal FB, and a delay flip-flop (D-FF) 14b is connected to the oscillator 14a. Timing setting circuits (DT) 14c and 14d for setting a dead time are connected to the output side of the delay flip-flop 14b. A level shifter 14e is connected to the timing setting circuit 14c. A buffer 14f is connected to the level shifter 14e. A buffer 14g is connected to the timing setting circuit 14d.

  The output terminal of the buffer 14f is connected to the gate drive terminal HD, and the output terminal of the buffer 14g is connected to the gate drive terminal LD. The buffer 14f drives the gate drive terminal HD using the voltage supplied from the drive power supply terminal VB based on the data given from the level shifter 14e. The buffer 14g drives the gate drive terminal LD.

  A power supply terminal VCC of the control unit 14 is connected to a connection point between the resistor 12 and the capacitor 13. Further, the anode of the diode 15 and the cathode of the diode 18 are connected to the connection point between the resistor 12 and the capacitor 13.

  One electrode of a capacitor 16 is connected to the cathode of the diode 15. The other electrode of the capacitor 16 is connected to the source of the NMOS 11 and the reference voltage terminal VS of the control unit 14. The diode 15 and the capacitor 16 constitute a charge pump for driving the gate voltage of the NMOS 11 to a high level.

  An auxiliary winding 8c is coupled to the primary winding 8a of the transformer 8 via a core. The anode of the diode 18 is connected to one end of the auxiliary winding 8 c, and the other end of the auxiliary winding 8 c is connected to the ground terminal GND of the control unit 14. The auxiliary winding 8c charges the capacitor 13.

  One end of the secondary winding 8b of the transformer 8 is connected to the anode of the diode 20, and the cathode of the diode 20 is connected to the output terminal OUTa. The secondary winding 8b of the transformer 8 is provided with an intermediate tap, and the intermediate tap is connected to the output terminal OUTb.

  The other end of the secondary winding 8b is connected to the anode of the diode 21, and the cathode of the diode 21 is connected to the output terminal OUTa. The output terminal OUTa and the output terminal OUTb are terminals for supplying a DC voltage to the load, and a smoothing capacitor 22 is connected between the output terminals OUTa and OUTb.

The converter further includes a voltage detection circuit 23 that detects a voltage supplied to the load, a light emitting diode 24a, and a phototransistor 24b.
The light emitting diode 24a emits light according to the voltage detected by the voltage detection circuit 23, and the phototransistor 24b receives the light and feeds back a corresponding signal to the feedback terminal FB of the control unit 14.

Hereinafter, the operation of the converter will be described with reference to FIGS.
FIG. 3 is a waveform diagram for explaining the operation of the converter of FIG.
FIG. 4 is an explanatory diagram showing the relationship between the switching frequency and the output power.
FIG. 5 is an explanatory diagram showing an input current waveform.

  The AC voltage generated by the AC power source 1 is filtered by the filter 2 and input to the rectifier circuit 3. The rectifier circuit 3 performs full-wave rectification of the AC voltage and outputs a pulsating rectified voltage. The filter 4 filters the rectified voltage, and the capacitor 5 charges and discharges the output voltage of the rectifier circuit 3 to generate a smoothed DC voltage.

  The capacitor 13 is charged based on the output voltage of the capacitor 5. When the charging voltage of the capacitor 13 exceeds a predetermined value, the control unit 14 is driven. The driven control unit 14 generates a control signal for turning on and off the NMOSs 9 and 11 and voltage-drives the gates of the NMOSs 9 and 11. As a result, the NMOSs 9 and 11 are alternately turned on and off with a dead time in which both of them are not turned on.

  When the gate voltage of the NMOS 11 becomes high (FIG. 3A) and the NMOS 11 is turned on, a current flows from the positive electrode of the capacitor 5 to the cathode of the capacitor 5 through the NMOS 11, the primary winding 8a, the leakage inductor 7, and the capacitor 6. i11 flows. The current i11 is a combined current of a resonance current having a resonance frequency determined by the capacitance of the capacitor 6 and the inductance of the leakage inductor 7 and an excitation current generated by exciting the primary winding 8a. Further, if the charging voltage of the capacitor 62 is lower than the instantaneous value of the AC voltage generated by the AC power source 1, the NMOS 11 and the primary winding 8a are passed through the AC power source 1, the filter 2, the rectifier circuit 3, and the filter 4. The current flows through the path of the leakage inductance 7, the capacitor 62, and the coil 60. At this time, the boosted energy is stored in the coil 60 and at the same time, a current for charging the capacitor 62 flows. This current is added to the combined current.

  Therefore, the current i11 has a waveform indicated by a solid line in FIG. This current i11 corresponds to the current i1 of the conventional converter of FIG. 15, but since the current i1 does not include a current for charging the capacitor 62, it has a waveform indicated by a broken line in FIG. That is, the current value of the current i11 is larger than that of the current i1.

  A current corresponding to the resonance current of the current i11 flows through the secondary winding 8b of the transformer 8 and is given to the load and the capacitor 22 via the diode 21, so that the capacitor 22 is charged. The voltage applied to the primary winding 8 a of the transformer 8 generates a voltage corresponding to the winding ratio in the auxiliary winding 8 c, and this voltage is applied to the capacitor 13 via the diode 18. Thereby, the capacitor 13 is charged and the control unit 14 is continuously driven.

  When the NMOS 11 is turned off while the current i11 is flowing, the voltage V11 across the NMOS 11 and the voltage V9 across the NMOS 9 are voltage pseudo values determined by the capacitance of the capacitor 10, the inductance of the leakage inductor 7 and the primary winding 8a, and the like. It changes with the resonance waveform. The voltage V11 across the NMOS 11 increases and the voltage V9 across the NMOS 9 decreases.

  When the voltage V11 rises and reaches the power supply voltage E, the current i11 is commutated to the parasitic diode of the NMOS 9. After that, when the control unit 14 sets the gate voltage data of the NMOS 9 to a high level and turns on the NMOS 9 (FIG. 3B), the current commutated to the parasitic diode of the NMOS 9 decreases and its polarity changes. Flows between the drain and source.

  When the NMOS 9 is turned on, a current i 9 flows from the capacitor 6 to the leakage inductor 7, the primary winding 8 a, the NMOS 9, and the capacitor 6. The current i9 is a current obtained by combining a resonance current having a resonance frequency determined by the capacitance of the capacitor 6 and the inductance of the leakage inductor 7 and the like and an excitation current generated by exciting the primary winding 8a.

  Here, before the NMOS 9 is turned on, energy is stored in the capacitor 62. If the output voltage of the filter 4 is higher than the charging voltage of the capacitor 62, the energy stored in the capacitor 62 is transferred from the capacitor 62 to the reage inductor. 7. Discharge by flowing through the path of the primary winding 8a, NMOS 9, diode 61 and capacitor 62. At the same time, the energy stored in the coil 60 is discharged to the capacitor 5 via the AC power source 1, the filter 2, the rectifier circuit 3, the filter 4, and the diode 61. That is, the capacitor 5 is charged.

  A current corresponding to the resonance current of the current i9 flows through the secondary winding 8b of the transformer 8 and is applied to the load and the capacitor 22 via the diode 20, and the capacitor 22 is charged. Electric power is supplied to the load via the capacitor 22. The control unit 14 controls the power supplied to the load with the switching frequency of the NMOSs 9 and 11. The control unit 14 controls the output power P0 by changing the switching frequency of the NMOSs 9 and 11 at a frequency higher than the frequency f0 of the resonance current (see FIG. 4).

  As described above, the converter according to the present embodiment is provided with the coil 60, the diode 61, and the capacitor 62 in the capacitor input type converter. These coil 60, diode 61, and capacitor 62 serve as a boost chopper for the capacitor 5.

  Capacitor 62 can be considered to shunt energy flowing through resonant capacitor 6 that sets the resonant current. Here, since the output voltage is controlled by the switching frequency of the NMOSs 9 and 11 according to input / output fluctuations such as load weight or input voltage, the voltage of the capacitor 6 is also controlled simultaneously. Therefore, the charging voltage of the capacitor 62 is also controlled according to the input / output fluctuation of the converter. Thereby, it is possible to prevent the capacitor 5 from being boosted more than necessary.

  Therefore, the period during which the input current flows increases, and the input current becomes close to the waveform of the AC voltage as shown in FIG. Therefore, the power factor is improved and the generation of harmonics can be suppressed.

  Moreover, since the power factor can be improved by adding a small number of components such as the coil 60, the diode 61, and the capacitor 62 provided in the capacitor input type converter, an increase in cost can be suppressed.

[Second Embodiment]
FIG. 6 is a block diagram showing a converter according to the second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This converter differs from the converter according to the first embodiment in that the coil 60 and the diode 61 are not provided, and a coil 70 and a diode 71 instead of the coil 60 and the diode 61 are provided. In this converter, the capacitor 10 for voltage quasi-resonance is connected not between the drain and source of the NMOS 9 but between the drain and source of the NMOS 11.

  One end of the coil 70 is connected to the positive electrode output terminal 4 a of the filter 4, and the other end of the coil 70 is connected to the anode of the diode 71. The cathode of the diode 71 is connected to the positive electrode of the smoothing capacitor 5. The anode of the diode 71 and the other end of the coil 70 are connected to the other electrode of the capacitor 62. Other configurations are the same as those of the converter of the first embodiment.

  Also in this converter, the coil 70, the diode 71, and the capacitor 62 function in the same manner as the coil 60, the diode 61, and the capacitor 62, and provide the same operational effects as in the first embodiment. The voltage quasi-resonant capacitor 10 may be connected between the drain and source of the NMOS 9 or may be connected between the drain and source of the NMOS 11, and furthermore, the drain and source of both transistors of the NMOS 9 and 11. Each may be connected between the sources.

[Third Embodiment]
FIG. 7 is a block diagram showing a converter according to the third embodiment of the present invention. Elements common to those in FIG. 6 are denoted by common reference numerals.

  This converter includes a coil 70, a diode 71, and a capacitor 62 that are connected in the same manner as in the second embodiment. In the second embodiment, the current resonance capacitor 6 connected between the leakage inductor 7 and the negative electrode of the capacitor 5 is connected between the leakage inductor 7 and the positive electrode of the capacitor 5. A capacitor 6 for voltage quasi-resonance is connected between the drain and source of the NMOS 9. Other configurations are the same as those of the second embodiment.

  Also in this converter, the coil 70, the diode 71, and the capacitor 62 function similarly to the coil 60, the diode 61, and the capacitor 62, and the current resonance capacitor 6 functions similarly to the capacitor 6 of the first embodiment. That is, the capacitor 6 having one end connected to the leakage inductor 7 can pass a resonance current regardless of which electrode of the capacitor 5 is connected to the other end. Therefore, the converter of this embodiment also has the same operational effects as the converter of the first embodiment. Note that the other end of the capacitor 6 may be connected to the negative electrode of the capacitor 5.

[Fourth Embodiment]
FIG. 8 is a block diagram showing a converter according to the fourth embodiment of the present invention. Elements common to those in FIGS. 1 and 6 are denoted by common reference numerals.
This converter differs from the converter of the first embodiment in that a coil 70, a diode 71, and a capacitor 72 are provided, and the other configuration is the same as that of the converter of the first embodiment.

  One end of the coil 70 is connected to the positive electrode output terminal 4 a of the filter 4, and the other end of the coil 70 is connected to the anode of the diode 71. The cathode of the diode 71 is connected to the positive electrode of the smoothing capacitor 5. A capacitor 72 is connected between the other end of the coil 70 and the anode of the diode 71 and the leakage inductor 7.

  Since this converter includes the coil 60, the diode 61 and the capacitor 62, and the coil 70, the diode 71 and the capacitor 72, the boosting operation on both sides is performed on the negative electrode side and the positive electrode side of the capacitor 5. Therefore, in the first embodiment, there is an unbalance between the current i11 and the current i9, but in the converter of this embodiment, the unbalance between the current i11 and the current i9 is eliminated.

[Fifth Embodiment]
FIG. 9 is a block diagram showing a converter according to the fifth embodiment of the present invention.
This converter does not have the coil 60, the diode 61, and the capacitor 62 of the first embodiment, but includes a coil 70 and a diode 71 instead of the coil 60 and the diode 61. One end of the coil 70 is connected to the positive electrode output terminal 4 a of the filter 4, and the other end of the coil 70 is connected to the anode of the diode 71. The cathode of the diode 71 is connected to the positive electrode of the smoothing capacitor 5. In the first embodiment, the capacitor 6 connected between the leakage inductor 7 and the negative electrode of the capacitor 5 is connected between the leakage inductor 7 and the anode of the diode 71. Other configurations are the same as those of the first embodiment.

  The capacitor 62 of the first embodiment and the second embodiment shunts a part of the current flowing through the capacitor 6 and used it for boosting, but in this embodiment, the current flowing through the capacitor 6 is all of the capacitor 6. Is used for boosting. By adopting such a configuration, it becomes difficult to adjust the boosted energy, but the power factor can be improved as in the first embodiment.

[Sixth Embodiment]
FIG. 10 is a block diagram showing a converter according to the sixth embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  In the converter of the first embodiment, the intermediate winding is provided in the secondary winding 8b of the transformer 8, and the diodes 20 and 21 are attached to both ends of the secondary winding 8b to configure a double-wave rectifier circuit. Then, the full-wave rectifier circuit 25 is connected to both ends of the secondary winding 8b without using the diodes 20 and 21. A smoothing capacitor 22 is connected between the output terminals of the full-wave rectifier circuit 25. Other configurations are the same as those of the first embodiment.

  Even if such a configuration is adopted, the same effects as those of the first embodiment can be obtained except that the energy supplied to the load from the secondary winding 8a is different.

[Seventh Embodiment]
FIG. 11 is a block diagram showing a converter according to the seventh embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  In this converter, the capacitor 6 that is connected between the leakage inductor 7 and the negative electrode of the capacitor 5 in the first embodiment is connected between the leakage inductor 7 and the positive electrode of the capacitor 5. On the other hand, on the secondary winding 8b side of the transformer 8, one end of the secondary winding 8b is connected to the anode of the diode 20, and the cathode of the diode 20 is connected to the positive electrode of the smoothing capacitor 22 and the output terminal OUTa. The other end of the secondary winding 8b is connected to the negative electrode of the capacitor 22 and the output terminal OUTb. That is, a half-wave rectifier circuit is formed on the secondary winding 8 b side of the transformer 8, and the output of the half-wave rectifier circuit is smoothed by the capacitor 22. Other configurations are the same as those of the converter of the first embodiment.

  The basic operation on the primary winding 8a side of the transformer 8 of the converter is the same as that of the first embodiment. However, the switching control of the NMOSs 9 and 11 performed by the control unit 14 is different.

  The switching frequency of the NMOSs 9 and 11 is fixed or slightly changed. The control unit 14 basically performs switching of the NMOSs 9 and 11 by PWM control (pulse width control) with a dead time interposed therebetween.

In the PWM control, the duty ratio for turning on the NMOSs 9 and 11 is controlled (see FIGS. 12 and 13).
12 (a) to 12 (e) are diagrams showing waveforms at various parts in FIG. FIG. 13 is a characteristic diagram showing the relationship between the on-duty ratio of the NMOS 9 and the output voltage.

  When the duty ratio of the NMOS 9 is changed, the output voltage Vo increases with the duty ratio from 0 to about 0.35, and when the duty ratio exceeds 0.35, the output voltage Vo monotonously decreases. The control unit 14 of the present embodiment controls the output voltage Vo by changing the duty ratio greater than 0.35 to turn on and off the NMOS 9.

  With the PWM control, the voltage waveform of the NMOS 9 is FIG. 12A, the current waveform of the NMOS 9 is FIG. 12B, the current flowing through the primary winding 8a is FIG. 12C, and the voltage waveform of the diode 20 is FIG. ) And the output voltage waveform of the diode 12 are as shown in FIG.

In addition, this invention is not limited to the said form, Furthermore, various deformation | transformation can be considered.
For example, the voltage pseudo-resonance capacitor 10 may be connected between the drain and source of the NMOS 9, may be connected to the drain and source of the NMOS 11, or may be connected to the drain and source of both NMOS 9 and 11. Each may be connected between the sources. Furthermore, it can be omitted by using the parasitic capacitance of the NMOSs 9 and 11.

  On the other hand, the leakage inductor 7 may be attached as a component, or the leakage inductor inside the transformer 8 may be used as it is.

It is a lineblock diagram showing the converter concerning a 1st embodiment of the present invention. It is a block diagram which shows the principal part of the control part in FIG. It is a wave form diagram for demonstrating operation | movement of the converter of FIG. It is explanatory drawing which shows the relationship between a switching frequency and output electric power. It is explanatory drawing which shows an input current waveform. It is a block diagram which shows the converter which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the converter which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the converter which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the converter which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the converter which concerns on the 6th Embodiment of this invention. It is a block diagram which shows the converter which concerns on the 7th Embodiment of this invention. It is a figure which shows the waveform of each part of FIG. It is a characteristic view which shows the relationship between on-duty ratio and an output voltage. It is a circuit diagram which shows an example of the conventional capacitor | condenser input type converter. FIG. 15 is a waveform diagram for explaining the operation of the converter of FIG. 14. It is a block diagram which shows the converter using a choke coil. It is a block diagram which shows the other example of a converter.

Explanation of symbols

1 AC Power Supply 3 Rectifier Circuit 5 Smoothing Capacitor 6 Current Resonance Capacitor 7 Leakage Inductor 8 Transformer 9, 11 NMOS
10 Capacitor for Voltage Pseudo Resonance 14 Control Unit 60 Coil 61 Diode as Rectifier 62, 72 Capacitor

Claims (1)

A rectifier circuit for rectifying an alternating voltage;
A first capacitor;
A series circuit of a first coil and a first rectifier element connected between the rectifier circuit and one electrode of the first capacitor;
A series circuit of a second coil and a second rectifier element connected between the rectifier circuit and the other electrode of the first capacitor;
A transformer having a primary winding and a secondary winding;
A first switching element connected between one electrode of the first capacitor and one end of the primary winding;
A second switching element connected between the other electrode of the first capacitor and one end of the primary winding;
A second capacitor having one electrode connected to the other end of the primary winding and the other electrode connected to a connection point of the first coil and the first rectifying element;
A third capacitor in which one electrode is connected to the other end of the primary winding and the other electrode is connected to a connection point of the second coil and the second rectifying element;
A switching control unit for turning on and off the first switching element and the second switching element to flow a current through the primary winding;
Output means for supplying energy corresponding to the current from the secondary winding to the load;
Means for outputting energy from the second capacitor to the first capacitor via a first coil;
Means for outputting energy from the third capacitor to the first capacitor via the second coil;
A converter comprising:

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