JP4461268B2 - Semiconductor device component, manufacturing method thereof, and semiconductor device using the same - Google Patents

Description

  The present invention relates to a semiconductor device component such as a heat sink, a manufacturing method thereof, and a semiconductor device such as a power semiconductor module to which the semiconductor device component is bonded.

2. Description of the Related Art In recent years, heat sinks are widely used in semiconductor devices to efficiently dissipate heat generated from semiconductor elements and to disperse heat temporarily. For example, in a power semiconductor module, heat generated from a semiconductor element is transferred to a heat sink through a circuit board made of a pattern such as copper or aluminum, a ceramic such as Al ₂ O ₃ or AlN, and a conductor layer. In order to lower the temperature of the entire structure, the heat sink is required to have high thermal conductivity.

Power semiconductor modules have a semiconductor element and circuit board, and the circuit board and heat sink are soldered together. The semiconductor element and circuit board have a small solder joint area, so there is often no problem, but the circuit board and heat sink are soldered. Since the area is large, if the difference in thermal expansion coefficient between the two is large, a large stress is applied to the solder joints. It may not be obtained.
In recent years, there has been an increasing demand for solder containing no lead, that is, Pb-free solder, due to environmental problems. For bonding between a circuit board and a heat sink, Sn—Cu-based (having Sn and Cu as main components), Sn— When using Pb-free solder such as Ag-based (Sn and Ag as main components) and Sn-Ag-Cu-based (Sn, Ag and Cu as main components), the heat sink plate warps when soldering. It gets bigger. Since the heat radiating plate is fixed to the heat radiating fin, if the warp is large, the contact area is reduced, and the heat radiating property to the fin side is greatly deteriorated.
The reason why the warpage becomes large is that the solder is solidified, and at the same time, stress due to the difference in thermal expansion coefficient between the circuit board and the heat sink is applied, and the heat sink is deformed according to the load stress. In a Sn—Pb-based solder (having Sn and Pb as main components), deformation due to creep occurs with respect to the load stress after deformation, and the amount of warpage of the heat sink is reduced. However, Pb-free solder has little deformation due to creep at room temperature, and the heat sink remains largely warped.

As one of the countermeasures, there is a method of forming a large warp in the opposite direction to the warp generated by soldering on the heat sink before soldering. Generally, the heat sink is warped by a press. As the value increases, the accuracy decreases. Further, even during assembly, it is difficult to position the circuit board and the semiconductor element by soldering accurately with respect to the curved heat sink.
In addition, there is a method using a material having high thermal conductivity and not easily softened during heating, that is, a material such as a precipitation-strengthened copper-based alloy with little deterioration in yield strength during heating (for example, see Patent Document 1), but Pb. It does not lead to deformation of free solder.
In order to solve this problem essentially, a heat sink having a low thermal expansion coefficient is required. Cu and Al, which have high thermal conductivity, are widely used as the metal used for the heat sink material. However, in the power semiconductor module, since a particularly high thermal conductivity is required, a Cu-based material is used. Cu has a thermal conductivity of 390 W / m · K, but its thermal expansion coefficient is as high as 17 × 10 ⁻⁶ / K, and the amount of warpage after soldering becomes large. In order to reduce the thermal expansion coefficient of the material, a material in which a low thermal expansion coefficient element such as Mo, W, or Cr, or a nonmetallic compound such as Cu ₂ O or SiC is dispersed as a second phase has been proposed. However, there are problems such as a decrease in thermal conductivity and an increase in cost due to restrictions on the manufacturing method.
JP 2003-68949 A

  The present invention is not intended to reduce the thermal expansion coefficient by dispersing the second phase for reducing the thermal expansion coefficient, which is often harmful in the conventional materials for semiconductor device components such as the heat sink, inside the metal. An object of the present invention is to provide a semiconductor device component such as a heat sink that solves the above problems by forming a treatment film on a metal surface, a manufacturing method thereof, and a semiconductor device such as a power semiconductor module to which the semiconductor device component is bonded.

  The present invention reduces the stress at the joint caused by the difference in thermal expansion coefficient when joining a circuit board and a heat sink with different thermal expansion coefficients in a semiconductor device, has excellent thermal conductivity, and is inexpensive. A semiconductor device component such as a heat sink, a manufacturing method thereof, and a semiconductor device such as a power semiconductor module to which the semiconductor device component is bonded, and a low thermal expansion coefficient and a high heat conduction required for the semiconductor device component such as a heat sink In order to achieve the rate, a copper or copper-based alloy plate-like body is used as a base material, and an intermetallic compound such as a Cu—Sn-based material having a low thermal expansion coefficient is formed on the surface and coated, Even when joined with free solder, warpage can be reduced and a good semiconductor device can be obtained.

That is, the present invention provides, firstly, a semiconductor device component for bonding to a semiconductor device, in which layers of an intermetallic compound are formed on both front and back surfaces of a plate-like body made of copper or a copper-based alloy; The semiconductor device component according to the first aspect, wherein the semiconductor device component is a radiator plate having a thermal conductivity of 200 W / m · K or more and a thermal expansion coefficient of 16 × 10 ⁻⁶ / K or less; 1. The semiconductor device component according to 1 or 2, wherein the compound layer is a layer of a Cu—Sn intermetallic compound (intermetallic compound containing Cu and Sn as main components); fourth, the Cu—Sn metal The semiconductor device component according to the _{third aspect} , wherein the intermetallic compound layer is a Cu ₃ Sn layer or a stack of a Cu ₃ Sn layer and a Cu ₆ Sn ₅ layer; fifth, the thickness of the Cu ₃ Sn layer but 1 to 15 m, the thickness of the layer of Cu ₆ Sn ₅ is 15μm or less, the semiconductor device of the fourth aspect Goods; Sixth, the sum of half the thickness of the layer of the layer thickness of the Cu ₃ Sn and the Cu ₆ Sn ₅ is 2μm or more, the semiconductor device parts according to the fourth or fifth, first 7. The semiconductor device component according to any one of 1 to 6, wherein the bonding is bonding using Sn—Cu-based, Sn—Ag-based, or Sn—Ag—Cu-based Pb-free solder; The semiconductor device component according to any one of 1 to 7, wherein the semiconductor device is a power semiconductor module; ninth, an intermetallic compound layer is formed on both front and back surfaces of a plate-like body made of copper or a copper-based alloy. The intermetallic compound layer is a Cu ₃ Sn layer or a stack of a Cu ₃ Sn layer and a Cu ₆ Sn ₅ layer, and the Cu ₃ Sn layer has a thickness of 1 to 15 μm, the Cu ₆ the thickness of the layer of Sn ₅ is at 15μm or less, and the thickness of the said layer of the Cu ₃ Sn Cu ₆ Sn ₅ A plate-like body on which an intermetallic compound layer is formed, the sum of which is ½ of the thickness of the layer being 2 μm or more; 10th, 1 on both sides of the plate-like body made of copper or a copper-based alloy; A method for producing the semiconductor device component according to any one of 1 to 8, wherein Sn plating having a thickness of ˜15 μm is performed, and then heat treatment is performed at 180 to 240 ° C. for 2 hours or longer; 11th, following the heat treatment A manufacturing method according to the tenth aspect, wherein the secondary heat treatment is performed at a temperature exceeding 240 ° C .; twelfth, a semiconductor device formed by bonding the semiconductor device components according to any one of the first to eighth aspects.

  The semiconductor device component according to the present invention has a low thermal expansion coefficient close to that of a circuit board made of an insulating substrate or the like of a semiconductor device to be bonded, and further has a high thermal conductivity, and is manufactured at low cost with high productivity. Thus, in the bonding to the semiconductor device, there is an effect that a warp can be reduced and a semiconductor device with good heat dissipation can be provided at low cost.

  The contents of the present invention will be described more specifically below. Copper or copper-based alloy is excellent in thermal conductivity, but is larger than a circuit board including an insulating substrate to which a thermal expansion coefficient is bonded. Therefore, the present inventors have found that a method of lowering the thermal expansion coefficient while maintaining thermal conductivity by covering both front and back surfaces of a plate-like body made of copper or a copper-based alloy with an intermetallic compound has been achieved. The Cu—Sn intermetallic compound is formed by heat treatment by plating Sn with electrolysis or electroless using a plate-like body made of copper or a copper-based alloy as a base material. The Sn plating thickness is desirably 1 to 15 μm. If it is less than 1 μm, the target Cu—Sn intermetallic compound is not formed after heat treatment, and if it exceeds 15 μm, it is very difficult to form the required Cu—Sn intermetallic compound. This is because it takes a long time and is disadvantageous in terms of cost and productivity. On the other hand, when the thickness exceeds 15 μm, Sn plated before the Cu—Sn intermetallic compound is formed easily melts due to the heat treatment temperature, and a smooth flat surface cannot be obtained on the droplets. is there. Further preferable Sn plating thickness is 1 to 10 μm.

The thickness of the copper or copper-based alloy plate used in the present invention is preferably 1 to 5 mm, and is often thicker than copper or copper-based alloys used for other electronic materials such as connectors. The thermal expansion of such a relatively thick plate can be controlled by a relatively thin intermetallic compound coating of several μm to 30 μm, and further, the decrease in thermal conductivity is small, and both characteristics are sufficient as a heat sink. This is the greatest feature and advantage of the present invention. In particular, the present inventors have found that by coating such a relatively thin intermetallic compound layer, the thermal expansion of a relatively thick copper or copper-based alloy plate-like body can be controlled, and the present invention has been achieved.
Therefore, the thickness of the copper or copper-based alloy plate is preferably 1 to 5 mm, more preferably 2 to 5 mm.

After Sn plating, Cu is diffused into Sn by heat treatment at 180 ° C. to 240 ° C. for 2 hours or more, preferably 2 to 200 hours, and the target Cu—Sn based intermetallic compound layer is formed. Can be formed. The heat treatment temperature is more preferably 200 ° C to 240 ° C. In the case of less than 180 ° C. or less than 2 hours, Cu does not sufficiently diffuse, so that the target Cu—Sn intermetallic compound is not formed. Further, at a temperature exceeding 240 ° C., Sn is melted before the Cu—Sn intermetallic compound is formed. In addition, when the time exceeds 200 hours, the diffusion effect is saturated, which is disadvantageous in terms of productivity and cost.
A target Cu—Sn intermetallic compound is obtained by performing a heat treatment after Sn plating. The intermetallic compounds are Cu ₆ Sn ₅ and Cu ₃ Sn, each having a thickness of 0 to 15 μm and 1 to 15 μm, and the sum of 1/2 of the thickness of Cu ₆ Sn _{5 and} the thickness of Cu ₃ Sn. Is preferably 2 μm or more. This is because when the sum is less than 2 μm, the required low thermal expansion coefficient cannot be obtained, and when the thickness of each layer of the intermetallic compound exceeds 15 μm, the required thermal conductivity cannot be obtained.

The heat treatment necessary for forming the Cu—Sn-based intermetallic compound is more preferably performed in two stages of 180 ° C. to 240 ° C. and a temperature exceeding 240 ° C. The first stage is performed at 180 ° C. or higher and 240 ° C. or lower in the vicinity of the Sn melting point, thereby diffusing Cu into Sn. After that, by performing a secondary heat treatment at a temperature exceeding 240 ° C. in the second stage, it takes a short time to obtain the necessary Cu ₆ Sn ₅ , Cu ₃ Sn thickness, which is excellent in productivity and cost. Because.
As described above, a semiconductor device component such as a heat sink coated with a Cu-Sn intermetallic compound formed on both front and back surfaces of a plate made of copper or a copper-based alloy has a thermal conductivity of 200 W / m · K. As described above, the thermal expansion coefficient is 16 × 10 ⁻⁶ / K or less. When the thermal conductivity is less than 200 W / m · K, the heat dissipation required by the semiconductor device cannot be obtained, and when the thermal expansion coefficient is greater than 16 × 10 ⁻⁶ / K, the reliability of the junction of the semiconductor device is increased. This is because it cannot be obtained. More preferably, the thermal conductivity is 350 W / m · K or more and the thermal expansion coefficient is 15 × 10 ⁻⁶ / K or less.

In addition, as a plate-like body having the above-described structural requirements, an intermetallic compound layer is formed on both front and back surfaces of a plate-like body made of copper or a copper-based alloy, and the intermetallic compound layer is made of Cu ₃ Sn. A layer or a stack of a Cu ₃ Sn layer and a Cu ₆ Sn ₅ layer, the Cu ₃ Sn layer having a thickness of 1 to 15 μm, and the Cu ₆ Sn ₅ layer having a thickness of 15 μm or less, In addition, the plate-like body on which the sum of the thickness of the Cu ₃ Sn layer and 1/2 of the thickness of the Cu ₆ Sn ₅ layer is 2 μm or more is formed with an intermetallic compound layer. It has the above characteristics with a rate of 200 W / m · K or more and a thermal expansion coefficient of 16 × 10 ⁻⁶ / K or less, and has a wide range of uses such as not only semiconductor device parts but also machine parts. .

  Examples of the present invention will be described below, but it goes without saying that the technical scope of the present invention is not limited to these descriptions.

[Example A] Copper was melted using a high-frequency induction melting furnace, and an ingot was cast with a thickness of 180 mm. Then, the homogenization process was performed at 900 degreeC and it hot-rolled to the thickness of 10 mm. Thereafter, cold rolling, annealing, and cold rolling were repeated to produce a specimen of a plate having a thickness of 3.0 mm.
As shown in FIG. 1 for the plan view and side view of the heat sink, the specimen is pressed into a shape of 90 mm × 50 mm, pretreated such as dipping, electrolytic degreasing, and pure water washing, and then applied to the entire outer peripheral surface. Electric Sn plating with a thickness of 3, 5, 10 μm was applied. The plating thickness is shown in Table 1. The warp amount of the base (specimen) at that time was a warp of 70 μm in the longitudinal direction and 0 μm in the short direction in the direction opposite to the warp direction generated after joining. Thereafter, heat treatment was performed at a predetermined temperature in the range of 150 ° C. to 350 ° C., the cross section was cut, and the thickness of the Cu—Sn based metal compound was measured. Specifically, after cutting the cross section, the cross section was polished, and the thicknesses of layers having different colors were measured with a laser microscope. The layers having different colors were identified and confirmed by an X-ray diffractometer and EPMA, respectively, such as Sn, Cu ₃ Sn, Cu ₆ Sn _{5 and} other metals and intermetallic compounds. The thickness of each layer was measured at 10 points with a laser microscope, and the average was taken as the representative value. The results are shown in Table 1.

Thereafter, a plan view and a side view profile shown in FIG. 2 is made of Al ₂ O ₃ of 60 mm × 35 mm for the insulating substrate 5 and the copper pattern 4 (the thickness of the circuit board to the heat dissipating plate 1 obtained as described above 0 .3 mm) and a circuit board 3 composed of a copper plate conductor layer 6 (thickness 0.3 mm) were joined by soldering. Solder joining was Pb-free solder 2 of Sn-3.0Ag-0.5Cu (that is, Sn 96.5% by mass, Ag 3.0% by mass, Cu 0.5% by mass), and joined by heating at 300 ° C. for 1 minute. When a copper plate-like body is used as the power semiconductor module heat dissipation plate, Ni plating is usually applied in order to maintain solder wettability reduction and solder joint soundness due to copper oxidation. Therefore, the electric Ni plating was applied to the specimen to a thickness of 3 μm as a reference, and the warpage amount after joining with the Pb-free solder 2 was measured. The amount of warpage before joining of the specimen after Ni plating was 70 μm in the longitudinal direction and 0 μm in the short direction in the opposite direction to the warping direction generated after joining, as compared with the warping amount after solder joining in this case, The amount of warpage was measured for Examples 1 to 23 and Comparative Examples 1 to 4 and 6 to 8, and Ni plating was performed as shown in FIG. The amount of warpage reduction of each example and comparative example with respect to the amount of warpage of the applied heat sink 1 was measured and evaluated. The results are shown in Table 1 above.
In addition, the part shown with the broken line about the heat sink 1 of FIG. 3 is the heat sink (the shape and position) before joining, and the part shown with the solid line is the heat sink (the shape and position) where the warp after joining occurred. Thus, the difference between the above-described warpage amounts (warpage reduction amount dx) was obtained and used as the warpage reduction amount.

From the results of Table 1, in each of Examples 1 to 23 according to the present invention, the thickness of the Cu ₃ Sn layer is in the range of 1 to 15 μm, the thickness of the Cu ₃ Sn layer and the thickness of Cu ₆ Sn ₅ Since the sum of 1/2 of the layer thickness is 2 μm or more, the amount of warpage reduction is excellent at 20 μm or more. In order for the sum of Cu ₃ Sn thickness and Cu ₆ Sn ₅ thickness to be 2 μm or more, Sn plating thickness before heat treatment is 1 to 15 μm, heat treatment temperature is 180 ° C. to 240 ° C., and heat treatment is performed. The time needs to be 2 hours or more.
In Comparative Examples 1, 2, 6, and 7, the heat treatment temperature is low, and since the diffusion of Cu into Sn is insufficient, the target Cu—Sn intermetallic compound layer thickness cannot be obtained. The amount of warpage reduction is small and the effect cannot be obtained. In Comparative Examples 3, 4, and 8, the heat treatment time is as short as 1 hour, and the diffusion of Cu into Sn is insufficient, so that the target Cu—Sn intermetallic compound layer thickness cannot be obtained. The amount of warpage reduction is small and the effect cannot be obtained. In Comparative Examples 5 and 9, since the heat treatment temperature is high, Sn melts before Cu diffuses into Sn, and Sn droplets are generated on the surface of the heat radiating plate 1 to form irregularities. Becomes as high as several tens of μm, and the soundness of the solder joint with the circuit board 3 cannot be obtained.

  [Example B] Examples 13 and 15 which are the products of the present invention shown in Table 1 above, Comparative Example 10 with only a Cu plate not subjected to plating heat treatment, and electric Ni plating on the aforementioned Cu plate The thermal expansion coefficient and the thermal conductivity of the comparative example 11 (the above-described reference heat radiating plate) subjected to the above were measured. The thermal expansion coefficient was measured at 20 to 300 ° C., and the elongation at 300 ° C. was measured with respect to the length in the longitudinal direction of the heat sink of 20 ° C., respectively. The thermal conductivity was measured at 20 ° C. by the laser flash method. The results are shown in Table 2.

From the results of Table 2, Examples 13 and 15 according to the present invention are excellent in that the thermal expansion coefficient is as low as 16 × 10 ⁻⁶ / K or less, and further as low as 14 × 10 ⁻⁶ / K or less. The thermal conductivity is 200 W / m · K or more, further 350 W / m · K or more, indicating a high value, and Cu—Cr or Cu—Cu ₂ O having a similar thermal expansion coefficient with a copper-based alloy. In comparison, it has a high thermal conductivity of 100 W / m · K or more and is excellent. Since Comparative Examples 10 and 11 have a high thermal expansion coefficient of 17 × 10 ⁻⁶ / K or more, the warpage amount after soldering with the circuit board 3 including the insulating substrate is large.

FIG. 4 is a conceptual diagram showing a cross section of a power semiconductor module according to the present invention. In a circuit board 3 composed of an insulating substrate 5 made of Al ₂ O ₃ , a copper pattern 4 and a conductor layer 6 such as a copper plate, A Si chip 7 is joined to the copper pattern 4 with solder 2 and this is wired with Al lead wires 8 to form a circuit, and the heat sink 1 is joined to the conductor layer 6 with solder 2.

  Further, FIG. 5 is a perspective view showing the inside of the power semiconductor module according to the present invention, with a part thereof broken, showing an epoxy case 9, a silicone gel filler 10, a terminal 11, a semiconductor chip 12, and an adhesive. Composed of the agent 13, the heat radiating plate 14, the circuit board 15, and the Al lead wire 16, and fixed to the heat radiating fins (not shown) through the screw holes formed in the heat radiating plate 14. It is.

  It is suitable for semiconductor device parts such as a heat sink that has a low coefficient of thermal expansion and high thermal conductivity and reduces warping after bonding even when Pb-free solder is used.

It is the top view and side view of a heat sink. It is the top view and side view of a circuit board. It is sectional drawing at the time of joining of a heat sink and a circuit board, the figure on the left is a figure which shows joining of each Example and Comparative Examples 1-10, and the figure on the right uses the heat sink which gave electric Ni plating It is a figure which shows the case of the comparative example 11 for the references | standards joined. It is a conceptual diagram which shows the cross section of a power semiconductor module. It is the perspective view which fractured | ruptured one part and showed the inside in the example of a power semiconductor module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Heat sink 2 Pb free solder 3 Circuit board 4 Copper pattern 5 Insulation board 6 Conductor layer dx Warpage reduction 7 Si chip 8 Al lead wire 9 Epoxy case 10 Silicone gel filler 11 Terminal 12 Semiconductor chip 13 Adhesive 14 Heat sink 15 Circuit board 16 Al lead wire

Claims (13)

Sn is plated on both front and back surfaces of a plate-like body made of copper or a copper-based alloy, and then heat-treated to form an intermetallic compound layer. The intermetallic compound layer is a Cu ₃ Sn layer or a Cu ₃ Sn layer. a lamination of the layers of the layer and Cu ₆ Sn _5, the thickness of the layer of the Cu ₃ Sn is 1 to 15 m, the thickness of the layer of the Cu ₆ Sn ₅ is 15μm or less, for bonding to the semiconductor device Semiconductor device parts. Sn is plated on both front and back surfaces of a plate-like body made of copper or a copper-based alloy, and then heat-treated to form an intermetallic compound layer. The intermetallic compound layer is a Cu ₃ Sn layer or a Cu ₃ Sn layer. And a layer of Cu ₆ Sn _5, the thickness of the Cu ₃ Sn layer is 1 to 15 μm, the thickness of the Cu ₆ Sn ₅ layer is 15 μm or less, and the Cu ₃ Sn A semiconductor device component for bonding to a semiconductor device, wherein the sum of the thickness of the layer and 1/2 of the thickness of the Cu ₆ Sn ₅ layer is 2 μm or more. The semiconductor device component according to claim 1 , wherein the step of plating and then heat-treating Sn is a step of performing Sn plating with a thickness of 1 to 15 μm and then heat-treating at 180 to 240 ° C. for 2 hours or more. The semiconductor device component according to claim 3, wherein a secondary heat treatment is performed at a temperature exceeding 240 ° C. following the heat treatment at 180 to 240 ° C. for 2 hours or more. The semiconductor device component, the thermal conductivity of 200 W / m · K or more, the thermal expansion coefficient of less of the heat sink 16 × 10 ^-6 / K, a semiconductor device component according to any of claims 1 to 4. The semiconductor device component according to claim 1 , wherein the bonding is a Sn—Cu based, Sn—Ag based, or Sn—Ag—Cu based Pb-free solder. The semiconductor device component according to claim 1 , wherein the semiconductor device is a power semiconductor module. Sn is plated on both front and back surfaces of a plate-like body made of copper or a copper-based alloy, and then heat-treated to form an intermetallic compound layer. The intermetallic compound layer is a Cu ₃ Sn layer or a Cu ₃ Sn layer. And a layer of Cu ₆ Sn _5, the thickness of the Cu ₃ Sn layer is 1 to 15 μm, the thickness of the Cu ₆ Sn ₅ layer is 15 μm or less, and the Cu ₃ Sn A plate-like body on which an intermetallic compound layer is formed, in which the sum of the thickness of the layer and 1/2 of the thickness of the Cu ₆ Sn ₅ layer is 2 μm or more. The plate-like body according to claim 8, wherein the step of plating and then heat-treating Sn is a step of performing Sn plating with a thickness of 1 to 15 μm and then heat-treating at 180 to 240 ° C. for 2 hours or more. The plate-like body according to claim 9 , which is subjected to a secondary heat treatment at a temperature exceeding 240 ° C. following the heat treatment at 180 to 240 ° C. for 2 hours or more. Plated with Sn with a thickness of 1~15μm on both sides of the plate of the copper or copper-base alloy, then heat-treated for 2 hours or more at 180 to 240 ° C., according to claim 1 A method of manufacturing the semiconductor device component. The manufacturing method of Claim 11 which performs secondary heat processing at the temperature over 240 degreeC following the said heat processing. A semiconductor device formed by bonding the semiconductor device component according to claim 1 .

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