JP4455208B2 - リードフレーム及び半導体装置の製造方法 - Google Patents
リードフレーム及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4455208B2 JP4455208B2 JP2004224456A JP2004224456A JP4455208B2 JP 4455208 B2 JP4455208 B2 JP 4455208B2 JP 2004224456 A JP2004224456 A JP 2004224456A JP 2004224456 A JP2004224456 A JP 2004224456A JP 4455208 B2 JP4455208 B2 JP 4455208B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- coining
- lead frame
- die pad
- suspension
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 69
- 238000000034 method Methods 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000000725 suspension Substances 0.000 claims description 57
- 230000008569 process Effects 0.000 claims description 40
- 239000011347 resin Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 10
- 238000005520 cutting process Methods 0.000 description 8
- 238000000465 moulding Methods 0.000 description 7
- 239000011295 pitch Substances 0.000 description 7
- 238000004080 punching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
100 パターン
110 ダイパッド
110a 隅部
112 薄肉部
120 インナーリード
122 薄肉部
130 セクションバー
140 吊りリード
142 第1のリード
144 第2のリード
150 空間部
100A パターン
140A 吊りリード
142A 第1のリード
144A 第2のリード
150A 空間部
100B パターン
140B 吊りリード
142B 第1のリード
144B 第2のリード
150B 空間部
100C パターン
140C 吊りリード
142C 第1のリード
144C 第2のリード
150C 空間部
Claims (4)
- 圧印加工により薄肉部を形成した後で樹脂封止される半導体装置を形成する形成領域を複数有するリードフレームであって、
前記形成領域は、前記圧印加工前の状態において、
半導体チップを載置するダイパッドと、
前記ダイパッドの隅部から延出し、前記ダイパッドを支持する第1のリードと第2のリードを有するとともに、該第1のリードと第2のリードとの間に空間部を有し、全体が圧印加工される一対の吊りリードとを有し、
前記第1のリードと第2のリードは、中央部分が互いに向き合う方向に近接する形状を有するとともに、前記ダイパッドの隅部から延出する方向において幅が細くなった後に再度太くなる形状を有することを特徴とするリードフレーム。 - 請求項1に記載のリードフレームを用いた半導体装置の製造方法であって、
前記空間部が形成されたリードフレームの露出面側において、前記吊りリードのダイパッド側の領域を圧印加工する第1の圧印加工ステップと、
前記第1の圧印加工ステップ後に、前記露出面側において前記吊りリードの前記ダイパッドとは反対側の領域を圧印加工する第2の圧印加工ステップと、
前記圧印加工されたリードフレームを樹脂封止するステップとを有し、
前記第1の圧印加工ステップと前記第2の圧印加工ステップとにより前記吊りリードの全体を圧印加工することを特徴とする半導体装置の製造方法。 - 前記第1の圧印加工ステップは、前記ダイパッド及び前記吊りリードに対して圧印加工を行うことを特徴とする請求項2記載の半導体装置の製造方法。
- 請求項1に記載のリードフレームを製造するリードフレームの製造方法であって、
複数回に分けて前記リードフレームを圧印加工した際に各々の圧印加工による前記リードフレームの変形を吸収しあうように、前記ダイパッドを支持する前記吊りリードに前記空間部を形成するステップを有することを特徴とするリードフレームの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004224456A JP4455208B2 (ja) | 2004-07-30 | 2004-07-30 | リードフレーム及び半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004224456A JP4455208B2 (ja) | 2004-07-30 | 2004-07-30 | リードフレーム及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006049372A JP2006049372A (ja) | 2006-02-16 |
JP4455208B2 true JP4455208B2 (ja) | 2010-04-21 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004224456A Expired - Lifetime JP4455208B2 (ja) | 2004-07-30 | 2004-07-30 | リードフレーム及び半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4455208B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5248232B2 (ja) * | 2008-07-31 | 2013-07-31 | 株式会社三井ハイテック | リードフレーム及びその製造方法 |
JP2018041956A (ja) * | 2016-09-06 | 2018-03-15 | エイブリック株式会社 | 半導体装置の製造方法 |
CN107799498A (zh) * | 2016-09-06 | 2018-03-13 | 精工半导体有限公司 | 半导体装置的制造方法 |
US10867894B2 (en) | 2018-10-11 | 2020-12-15 | Asahi Kasei Microdevices Corporation | Semiconductor element including encapsulated lead frames |
JP7397783B2 (ja) * | 2019-11-21 | 2023-12-13 | 順▲徳▼工業股▲分▼有限公司 | リードフレームストリップ |
TWM598526U (zh) * | 2019-11-21 | 2020-07-11 | 順德工業股份有限公司 | 導線架料片 |
-
2004
- 2004-07-30 JP JP2004224456A patent/JP4455208B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JP2006049372A (ja) | 2006-02-16 |
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