JP4454013B2 - Differential output circuit - Google Patents

Description

  The present invention relates to a differential output circuit designed to reduce noise.

  A general output circuit employs a technique of reducing the slew rate by dulling the rising and falling waveforms of the output signal in order to reduce noise. FIG. 5A is a diagram showing an output circuit employing such a slew rate control method. By dulling the falling waveform of the output node PG11 on the source side of the pre-driver 21 and dulling the rising waveform of the output node NG11 on the sink side, the PMOS transistor P11 and the NMOS transistor N11 are changed as shown in FIG. The rising and falling waveforms of the output signal at the output node OUT of the final output stage are blunted.

  In addition, as shown in FIG. 6, the final output stage PMOS transistor is divided into transistors P21 and P22, and the final output stage NMOS transistor is divided into N21 and N22. After the transistor P21 is turned on by the output node PG21, the transistor P22 is turned on by the output node PG22. In the case of sink side driving, the transistor N21 is turned on by the output node NG22 and then the transistor N22 is turned on by the output node NG21. As shown in FIG. 6B, the rising and falling waveforms of the output signal at the output node OUT are blunted so as to be conducted.

  Further, in the case of a differential output circuit of a high-speed interface system (for example, LVDS: Low Voltage Differential Signaling) as shown in FIG. 7, the output of a driver (differential output circuit) 31 uses a transmission line 32 whose impedance is controlled. When transmitting to the receiver 33, a termination resistor R11 is connected to the input side of the receiver 33 in order to prevent reflection. In this case, if only the termination resistor R11 on the receiver 33 side is insufficient, the termination resistor R12 is additionally arranged on the driver 31 side.

  However, in the conventional example described with reference to FIGS. 5 and 6, when the speed is further increased, the waveforms of the output nodes PG11 and NG11 of the pre-driver 21 are blunted or the output transistors P21, P22, N21, and N22. The time allowed for the circuit operation of shifting the conduction timing is small, and there is a possibility that a sufficient effect cannot be obtained as a measure for reducing noise.

  Further, in the conventional example described in FIG. 7, when the termination resistor R12 is additionally arranged on the driver 31 side, the amplitude of the output signal is reduced by half, so the output current needs to be doubled. There is a problem that current consumption increases.

  In view of the above points, an object of the present invention is to provide a differential output circuit that solves the above-described problem by reducing the impedance between differential output terminals only when an output signal transitions.

The differential output circuit of the invention according to claim 1 includes a differential output circuit body for outputting a differential output signal to the differential output terminal on the basis of the input signal, a switch connected with the impedance between the differential output terminals The differential output signal is changed from low level to high level or from high level to low level by changing the input signal from low level to high level, or from high level to low level. in, wherein the switch of the switch with the impedance element is temporarily conductive connecting said impedance element between the differential output terminals.

According to a second aspect of the present invention, in the differential output circuit according to the first aspect, the differential output circuit body includes a pre-driver that generates a complementary signal based on the input signal, and a complementary generated by the pre-driver. A differential output stage that is driven by a signal and outputs a differential signal; a first inversion delay circuit that inputs and inverts one of the complementary signals; and inputs the other signal of the complementary signal A second inversion delay circuit that performs inversion delay, and the impedance element with switch includes an impedance element, a transistor driven by an input signal of the first inversion delay circuit, and a transistor driven by an output signal . a first switch configured are connected in series, driven by transistors and the output signal driven by the input signal of the second inverting delay circuit And transistor is provided with a second switch configured are connected in series, characterized in that.

  According to a third aspect of the present invention, in the differential output circuit according to the second aspect, the impedance element with a switch uses a conduction resistance of the first switch and a conduction resistance of the second switch as the impedance element. It is characterized by doing.

  According to the present invention, since the impedance element is connected between the differential output terminals only when the output signal transitions, the slew rate of the output signal is reduced, and the antireflection function is also provided to effectively prevent noise. And power consumption is not increased.

  In the present invention, as shown in FIG. 1, in a differential output circuit body 1 that outputs a differential output signal to differential output terminals OUT + and OUT− based on an input signal input from an input terminal IN, the differential output terminal The impedance element 2 with a switch is connected between OUT + and OUT−, and the switch of the impedance element 2 with the switch is turned on only at the transition of the output signal by a control signal created inside the differential output circuit body 1. Thereby, since the impedance element 2 with a switch is connected between the differential output terminals OUT + and OUT− at the time of transition of the output signal, noise can be reduced. Further, since the switch of the impedance element 2 is in an open state in a steady state, the current consumption does not increase.

  FIG. 2 is a circuit diagram showing a configuration of a differential output circuit of an embodiment in which the present invention is applied to an LVDS driver circuit. The differential output circuit body 1 includes a pre-driver 11, a differential output stage 12, and inverting delay circuits 13 and 14. The pre-driver 11 includes inverters INV1 to INV4 and a transfer gate TG as a delay element, and outputs a complementary signal accurately in reverse phase to the output nodes PG and NG based on the input signal IN. The differential output stage 12 includes a PMOS transistor P1, an NMOS transistor N1 as a bias circuit, and NMOS transistors N2 to N5 as output drive elements. Further, the inverting delay circuit 13 outputs a signal A ′ obtained by inverting the output signal A of the node PG by the time T, and the inverting delay circuit 14 also delays the output signal B of the node NG by the inverting time T. Is output.

  The impedance element 2 with a switch includes resistors R1 and R2 as impedance elements, NMOS transistors N6 and N7 that constitute a switch that operates when the output signal OUT + rises and the output signal OUT− falls, and the output signal OUT + falls , And NMOS transistors N8 and N9 that constitute a switch that operates when the output signal OUT− rises. The transistor N6 is the input signal A of the inverting delay circuit 13, the transistor N7 is the output signal A 'of the inverting delay circuit 13, the transistor N8 is the input signal B of the inverting delay circuit 14, and the transistor N9 is the output signal of the inverting delay circuit 14. Driven by B ′. The resistors R1 and R2 can use polysilicon resistors, diffusion resistors, and transistor conduction resistances. In particular, when the transistor conduction resistance is used, the resistors and transistors can be realized by a single PMOS or NMOS transistor. For example, the total conduction resistance value of the transistors N6 and N7 and the total conduction resistance value of the transistors N8 and N9 may be set to the total resistance value of the resistors R1 and R2, respectively.

  When the voltage at the input terminal IN changes from “L” (low voltage level) to “H” (high voltage level), the node PG changes from “L” to “H”, and the node NG changes from “H” to “H”. Transition to “L”. As a result, the transistors N2 and N5 change from cutoff to conduction, and the transistors N3 and N4 change from conduction to cutoff, so that the output terminal OUT + changes from “L” to “H” and OUT− changes from “H” to “L”. , Each starts a transition.

  At this time, in the impedance element with switch 2, the transistor N6 is turned on, but the transistor N7 is turned on before that, and the transistor N7 is cut off when the time T set by the inversion delay time 13 has elapsed. The transistor N8 is cut off. As a result, the output terminals OUT + and OUT− are connected by the transistors N6 and N7 and the resistors R1 and R2 for the time T set by the inversion delay time 13. Therefore, by appropriately setting the resistance values of the resistors R1 and R2 and the time T, noise when the output terminal OUT + changes from “H” to “L” and OUT− changes from “L” to “H”. Can be reduced.

  On the other hand, when the voltage at the input terminal IN changes from “H” to “L”, the node PG changes from “H” to “L”, and the node NG changes from “L” to “H”. As a result, the transistors N2 and N5 change from conduction to interruption, and the transistors N3 and N4 change from interruption to conduction, so that the output terminal OUT + changes from “H” to “L” and OUT− changes from “L” to “H”. , Each starts a transition.

  At this time, in the impedance element with switch 2, the transistor N8 is turned on, but the transistor N9 is turned on before that, and the transistor N9 is cut off when the time T set by the inversion delay time 14 has elapsed. Further, the transistor N6 is cut off. As a result, the output terminals OUT + and OUT− are connected by the transistors N8 and N9 and the resistors R1 and R2 for the time T set by the inversion delay time 14. Therefore, by appropriately setting the resistance values of the resistors R1 and R2 and the time T, noise when the output terminal OUT + changes from “L” to “H” and OUT− changes from “H” to “L”. Can be reduced.

  FIG. 3 is a simulation waveform diagram of the operation at a data transfer rate of 655 Mbps (maximum rate in the LVDS standard ANSI / TIA / EIA-644). (a) is the voltage waveform of the input signal at the input terminal IN, (b) is the voltage waveform of the control signals A and A ′, (c) is the voltage waveform of the control signals B and B ′, and (d) is the differential output terminal. It is a waveform of a differential output potential difference between OUT + and OUT−. The switches of the impedance element 2 with the switch are turned on during the time portion of “current path ON” shown in (b) and (c) and the resistors R1. R2 is connected between the output terminals OUT + and OUT−.

  FIG. 4 is an eye diagram of the differential output potential difference of the simulation at the data transfer rate of 655 Mbps. FIG. 4A shows the case where the impedance element with switch 2 is not connected and FIG. . In (b), it is obvious that ringing during transition can be prevented.

  In the present embodiment described above, the function equivalent to the function of controlling the slew rate of the output signal waveform and the termination resistor connection for preventing reflection can be realized with a simple circuit configuration. Further, by adjusting the delay time T of the inverting delay circuits 13 and 14 and the resistance values of the resistors R1 and R2 of the impedance element 2 with switch, various board / cable conditions, data transfer rates, interface standards, and the like can be obtained. It can be easily handled. Furthermore, it is possible to adjust the actual application by programming these two elements (slew rate and termination resistance). Since the impedance element 2 with a switch according to the present embodiment functions with the switch conducting only at the time of transition, it is not necessary to increase the output current, so that an increase in current consumption is not caused.

It is a block diagram of a differential output circuit for explaining the principle of the present invention. It is a circuit diagram of the differential output circuit of the Example of this invention. FIG. 3 is a simulation waveform diagram of the operation of the differential output circuit of FIG. 2, where (a) is a voltage waveform diagram of an input signal, (b) is a voltage waveform diagram of control signals A and A ′, and (c) is control signals B and B. (D) is a waveform diagram of a differential output potential difference. (a) is an eye diagram of the differential output potential difference of the simulation of the operation of the differential output circuit in which the impedance element with the switch is deleted from the differential output circuit of FIG. 2, and (b) is the operation of the differential output circuit of FIG. It is an eye diagram of the differential output potential difference of simulation. (a) is a circuit diagram of a conventional output circuit, and (b) is an operation waveform diagram thereof. (a) is a circuit diagram of another conventional output circuit, and (b) is an operation waveform diagram thereof. It is the transmission circuit diagram which used the conventional differential output circuit as a driver.

Explanation of symbols

1: differential output circuit body, 2: impedance element with switch, 11, 21, 22: pre-driver, 12: differential output stage, 13, 14: inverting delay circuit, 31: driver, 32: transmission line, 33: Receiver INV1 to INV4: Inverter, TG: Transfer gate, N1 to N9, N11, N21, N22: NMOS transistors, P1, P11, P21, P22: PMOS transistors, R1, R2, R11, R12: Resistors

Claims (3)

A differential output circuit body that outputs a differential output signal to a differential output terminal based on an input signal, and an impedance element with a switch connected between the differential output terminals,
When the differential output signal is changed from low level to high level or from high level to low level by changing the input signal from low level to high level, or from high level to low level, the impedance with switch differential output circuit, characterized in that the element switch is temporarily conductive connecting said impedance element between the differential output terminals. The differential output circuit according to claim 1,
The differential output circuit body includes a pre-driver that generates a complementary signal based on the input signal, a differential output stage that is driven by the complementary signal generated by the pre-driver and outputs a differential signal, and the complementary signal A first inverting delay circuit that inputs and inverts one of the signals, and a second inverting delay circuit that inputs and inverts the other of the complementary signals,
The impedance element with a switch includes a first switch configured by connecting an impedance element, a transistor driven by an input signal of the first inverting delay circuit, and a transistor driven by an output signal in series ; A second switch configured by connecting a transistor driven by an input signal of the second inverting delay circuit and a transistor driven by an output signal in series ;
A differential output circuit characterized by that. The differential output circuit according to claim 2,
The differential impedance circuit, wherein the impedance element with a switch uses a conduction resistance of the first switch and a conduction resistance of the second switch as the impedance element.

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