JP4448076B2 - Timing adjustment circuit for data transmission / reception circuit, LSI and data transmission / reception system - Google Patents

Description

  The present invention relates to a data transmission / reception circuit that performs data transmission / reception between a plurality of elements and circuit blocks in an LSI, data transmission / reception between LSIs, data transmission / reception between boards and housings, for example, between a data transmission unit and a data reception unit In particular, it converts the input parallel data into serial data, for example, converts the input parallel data with a data bit width of 16 bits and a speed of 2.5 Gbps from 8 bits 5 Gbps to 4 bits 10 Gbps. → In a data transmission circuit that performs stepwise conversion using a clock obtained by dividing the internally generated clock, such as 2bit 20Gbps → 1bit 40Gbps, data transmission / reception between multiplexers that sequentially perform stepwise data bit width conversion can be performed reliably. As described above, the present invention relates to a timing adjustment circuit for adjusting the phase relationship between data and a clock.

  In recent years, the amount of information to be processed has increased in the computer and communication fields. In order to cope with this increasing amount of information, the data transmission / reception speed between LSIs is increasing. Although at the research level, CMOS 10Gbps transceivers were announced in 2002. Since then, research has focused on CMOS 40Gbps transceivers. In particular, state-of-the-art technology is applied in an area where these high data transfer rates are required. For example, CMOS 40Gbps transceivers are being researched assuming technology of 0.1um or less. However, in a data transmission / reception system that requires a high data transfer rate, it is necessary to further increase the LSI internal clock frequency. Contrary to the improvement in transistor performance due to the miniaturization of semiconductor processes, the process variation is very large. Conventionally, a timing margin for data reception has been secured by making the blocks for data transmission and reception as close as possible to each other by means of layout. However, due to the improvement of the data transfer rate and the influence of process variations, such a method is reaching its limit.

  A configuration example of a data transmission circuit which is an example of the high-speed transceiver is shown in FIG. The data transmission circuit shown in FIG. 10 divides the internally generated clock generated by the PLL (100) after temporarily storing parallel data of 16-bit width and 2.5 Gbps in the first-in first-out (FIFO) data buffer 110. The input parallel data is converted into serial data step by step using the clocks sequentially divided by the devices (210, 220, 230). That is, input 16bit 2.5Gbps data is converted to 8bit 5Gbps data by 16: 8 multiplexer (120), then converted to 4bit 10Gbps data by 8: 4 multiplexer (130), and further 4: 2 multiplexer (140) To 2bit 20Gbps data, and 2: 1 multiplexer (170) to 1bit, ie 40Gbps serial data. Then, 40 Gbps data is output to the outside via the final buffer (180).

  Next, examples of the 4: 2 multiplexer (140) and the 2: 1 multiplexer (170) will be described with reference to FIG. 11 for data conversion by the multiplexer of the data transmission circuit shown in FIG. 10 and data transmission / reception between the multiplexers.

  DT_IN [0], DT_IN [1], DT_IN [2], and DT_IN [3], which are 4-bit inputs from the previous 8: 4 multiplexer (130), are supplied to the subsequent 2: 1 multiplexer (170). The 20-GHz clock CLK_A is received by the latch circuit (141, 143, 151, 153) of the first stage of the 4: 2 multiplexer (140) in synchronization with the 10-GHz clock CLK_B, which is divided by half by the frequency divider (210). DT_IN [0] is supplied to the selector (146) via the latch circuit (142), DT_IN [2] is supplied to the selector (146) via the latch circuit (144,145), and DT_IN [1] is supplied to the DT_IN via the latch circuit (152). [3] is supplied to the selector (156) via the latch circuit (154, 155).

  The selector (146, 156) selects DT_IN [0] and DT_IN [1] at the rising edge of the clock CLK_B, respectively, and selects DT_IN [2] and DT_IN [3] at the falling edge of the clock CLK_B. Serial data of DT_IN [0] and DT_IN [2] at twice the speed of 10 GHz is obtained in the output DT. A similar output can be obtained for the output DTX of the selector (156).

  The DT and DTX, which are the outputs of the 4: 2 multiplexer (140), are received by the latch circuits (171 and 173) in the first stage of the 2: 1 multiplexer (170) in synchronization with the 20 GHz clock CLK_A. The signal is supplied to the selector (176) via the latch circuits (174, 175), and is selected by the selector (176) in synchronization with the rising and falling edges of the clock CLK_A, and is output as the output signal DT_OUT of the transmission circuit.

FIG. 12 is a timing chart when data transmission / reception is normally performed between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170 shown in FIG.
The clock CLK_A is a clock that defines the timing at which data is received by the subsequent 2: 1 multiplexer (170). The clock CLK_B is a clock that defines the timing at which data is output by the 4: 2 multiplexer (140), which is the previous stage, and is a divided clock that is synchronized with the rising edge of the clock CLK_A. Now, data is output from the 4: 2 multiplexer (140) at the rising edge of the clock CLK_B in synchronization with the rising edge of the clock CLK_A. The 2: 1 multiplexer (170) receives this data at the rising edge of the clock CLK_A in the next cycle. In the design, it is necessary to realize this timing chart under conditions that take into account process variations and power supply voltage / temperature fluctuations. In the case of the conventional technique, the physical distance between the multiplexers is shortened, and the circuit configuration of the multiplexer and the frequency divider is devised to realize the timing chart shown in FIG.

  However, in the example of a high-speed transmission circuit that finally outputs data at a speed of 40 Gbps shown in FIG. 10, it is difficult to reliably perform data transmission / reception between multiplexers. FIG. 13 shows a timing chart when data transmission / reception between multiplexers is not normally performed. As shown in FIG. 13, when the received data is displaced at the rising timing of the clock CLK_A, the first stage latch circuit (171, 173) of the 2: 1 multiplexer (170) cannot correctly latch the data, 1 Multiplexer (170) cannot receive data correctly.

  Conventional techniques relating to data transmission / reception between LSIs and the like are described in, for example, the following Patent Documents 1 to 3 and Non-Patent Document 1. Those described in Patent Documents 1 and 2 generally apply a circuit technology called DLL. The data transmission circuit adjusts the phase relationship between the output data and the output clock so that the data reception circuit can reliably receive the data. However, if the transfer distance is extended or the transfer speed is increased, it is difficult to reliably receive data in the data receiving circuit due to process variations and power supply voltage / temperature fluctuation effects.

On the other hand, in the data transmission / reception techniques described in Patent Document 3 and Non-Patent Document 1, the data reception circuit adjusts the phase of the clock that defines the data reception timing of the data reception circuit with respect to the output data from the data transmission circuit. Is. Therefore, if only data reception is considered, the data reception circuit can reliably receive data. However, when the clock frequency becomes high, the processing in the data reception circuit after data reception and the processing shown in FIG. In consideration of the accuracy of the multiplexer output of the transmission circuit, it is not preferable to adjust the clock on the reception side.
JP-A-10-112182 JP 2004-145999 A Japanese Patent Laid-Open No. 10-228449 Yasutaka Tamura, Kotaro Goto “High-Speed Signal Transmission Technology: SynfinityII” FUJITSU Vol.50 No.4 (07,1999) pp.235-241

  Therefore, a problem to be solved by the present invention is a timing adjustment circuit for realizing data transmission / reception that is not affected by process variations and power supply voltage / temperature fluctuations even when the data transfer rate becomes high, and such a timing adjustment circuit. An LSI and a data transmission / reception system including a timing adjustment circuit are provided.

  The timing adjustment circuit provided by the present invention compares the phase of the data output from the data transmission unit with the phase of the clock that defines the timing at which the data reception unit receives the data, and the data transmission unit according to the comparison result Adjusts the phase of the clock that defines the timing at which data is transmitted.

  The LSI according to the present invention sequentially transmits and receives data between a plurality of blocks, and detects a change in data output by the data transmission side block for each block on the transmission side and each block on the reception side. A data change detection unit; a phase comparison unit that performs phase comparison between a clock that defines a timing at which the data reception side block receives data and data output from the data transmission side block; and the data change detection unit includes the data A phase adjustment unit that changes a phase of a clock that defines a timing at which the data transmission side block transmits data according to a phase comparison result of the phase comparison unit when a change in data output from the transmission side block is detected A timing adjustment circuit having

  Further, the inter-LSI data transmission / reception system of the present invention includes a data change detection unit that detects a change in data output from the first LSI, a clock that defines a timing at which the second LSI receives data, and the first LSI. A phase comparison unit that performs phase comparison with data output from the LSI, and when the data change detection unit detects a change in data output from the first LSI, the phase comparison unit responds to the phase comparison result of the phase comparison unit. And a timing adjustment circuit having a phase adjustment unit that changes a phase of a clock that defines a timing at which the first LSI transmits data.

  According to the present invention, even when the data transfer rate becomes high, data transmission / reception between circuit blocks that perform data transmission / reception can be reliably performed without being affected by process variations and power supply voltage / temperature fluctuations.

  FIG. 1 shows the basic configuration of the present invention. In the present invention, the phase of the data transmitted from the data transmission unit (10) to the data reception unit (20) and the phase of the reception side clock that defines the timing of data reception at the data reception unit (20) is compared with the phase comparison unit (30 ) And the phase adjustment unit (40) adjusts the phase of the transmitting clock that defines the data transmission timing in the data transmission unit (10) according to the comparison result in the phase comparison unit (30). Supply to the transmitter (10).

  The data transmission unit (10) and the data reception unit (20) are used as a circuit for transmitting and receiving data between a plurality of elements and circuit blocks in an LSI such as the multiplexer shown in FIG. The present invention can be implemented as a data transmission / reception circuit that performs data transmission / reception between circuits and boards or between cases.

  2 is an application example of the basic configuration of the present invention shown in FIG. 1, and the input data input to the pre-stage latch unit (12) corresponding to the data transmission unit (10) of FIG. This is for the system that outputs as output data via the latter latch unit (22) corresponding to the receiver unit (20), and the phase of the clock that regulates the data reception timing of the latter latch unit (22) is adjusted. It is supplied as a clock that defines the data output timing of the pre-stage latch unit (12). A data change detection unit (52) is provided to detect the timing when the data value output from the previous latch unit (12) changes from “0” to “1” or “1” to “0”. When the signal is detected, an enable signal is sent to the phase comparator (32).

  When receiving the enable signal, the phase comparison unit (32) compares the phase of the output data of the preceding latch unit (12) and the clock that defines the data reception timing of the subsequent latch unit (22), and determines the phase according to the comparison result. The adjusting unit (42) adjusts the phase of the clock that defines the data output timing of the preceding latch unit (12).

  In place of providing the data change detection unit (52), a replica that always outputs data with data change is provided on the front latch unit (12) side with the same configuration as the previous stage, and the output is phase-compared. You may give to the part.

  As is clear from the comparison with FIG. 1, instead of providing the phase comparison unit (32) and the data change detection unit (52) or the data change detection unit (52) in FIG. The phase comparison unit that performs phase comparison of the clock that defines the timing of data reception of the output of the provided replica and the subsequent latch unit (22) corresponds to the phase comparison unit (30) of FIG.

  With the configuration described in FIG. 1 or FIG. 2, the present invention can realize a data transmission / reception system that is not affected by process variations and power supply voltage / temperature fluctuations regardless of the data transfer rate. When the configuration of FIG. 2 is applied to the transmission circuit shown in FIG. 10, for example, the 4: 2 multiplexer (140) corresponds to the front-stage latch unit (12), and the 2: 1 multiplexer (170) corresponds to the rear-stage latch unit (12). It corresponds to 22). In the data transmission / reception system for performing data transmission / reception, the present invention compares the phase of data output from the data transmission block corresponding to the preceding stage and the phase of the clock in the data reception block corresponding to the subsequent stage, and according to the comparison result, In the subsequent stage, the phase of the clock with respect to the previous stage is changed so that the data output from the previous stage can be received reliably.

  Hereinafter, as a timing adjustment circuit for data transmission / reception between the 4: 2 multiplexer (140) and the 2: 1 multiplexer (170) shown in FIG. 11, a circuit provided with a data change detection unit (52) is used. One embodiment is described in detail as a second embodiment of the present invention in which a replica that always outputs data with data changes is provided.

First, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 3 shows the configuration of the first embodiment of the present invention in detail. Those given the same reference numerals as those given in FIG. 11 are the same as those explained in FIG. The data change detection unit (52) and the phase comparison unit (32) show specific configuration examples of the data change detection unit (52) and the phase comparison unit (32) of the application example shown in FIG. A phase interpolator PI (Phase Interpolator) (421) and a PI control unit (422) having a function of changing the phase of the clock for the 4: 2 multiplexer (140) correspond to the phase adjustment unit (42) of FIG. .

Hereinafter, an outline of the operation of the configuration example shown in FIG. 3 will be described.
A 20 GHz clock CLK_A supplied from a PLL (not shown) is distributed to a frequency divider (210), a 2: 1 multiplexer (170), and a phase shifter (320).

  The frequency divider (210) divides the clock CLK_A and supplies a clock having a frequency of 10 GHz and phase differences of 0, 90, 180, and 270 degrees to the phase interpolator PI (421). The phase interpolator PI (421) supplies the 10 GHz clock CLK_B whose phase is adjusted by the control of the PI control unit (422) to the 4: 2 multiplexer (140).

  The data change detection unit (52) outputs the data change detection signal PI_EN to the PI control unit (422), and the PI control unit (422) outputs the 4: 2 multiplexer (140) only during the period when the data change detection signal PI_EN is High. The phase interpolator PI (421) having a function of changing the phase of the clock CLK_B with respect to () is enabled. In this embodiment, the phase interpolator PI (421) is adopted as means for changing the phase of the clock. However, the present invention is not limited to this. For example, instead of the phase interpolator PI (421), the clock phase may be changed by connecting a clock buffer to the series and adjusting the extraction port. This also applies to the following embodiments.

The phase shifter (320) supplies a clock CLK_A_DMY obtained by shifting the phase of the clock CLK_A by a fixed amount to the latch circuit (321) of the phase comparison unit (32).
The phase comparison in this embodiment is performed every time a data change is detected. This is because the data change reflects the phase of the clock in the 4: 2 multiplexer (140). The data change is detected by detecting the output of the latch circuit (522) and the latch circuit (523) with the XOR logic circuit (524) of the data change detection unit (52) for the continuous data output by the 4: 2 multiplexer (140). This is done by computing XOR logic.

FIG. 4 shows a timing chart relating to this data change detection.
The data change detection unit (52) takes out the output DT of the 4: 2 multiplexer (140) by 2 bits in synchronization with the clock CLK_B, and detects the presence or absence of data change.

  As shown in the figure, the output data DT “1” is latched by the latch circuit (521) at the falling edge of the clock CLK_B, and the output SFT0 becomes “1”. At the next rising edge of the clock CLK_B, the latch circuit (523) latches DT “0” of the second bit, and SFT0 which is data of the first bit is latched by the latch circuit (522). The output SFT1 and the output SFT2 of the latch circuit (523) are calculated by the XOR logic circuit (524), output as the PI_EN_TMP signal, delayed by one clock in the latch circuit (525), and the PI control unit (422) as the PI_EN signal Is input. Thereafter, the same processing is performed for the third bit and the fourth and subsequent bits of the output data DT, and a PI_EN signal is generated.

Next, the operation of the phase comparison unit (32) will be described.
The phase comparison target is the clock CLK_A_DMY obtained by shifting the phase of the output data DT of the 4: 2 multiplexer (140) and the clock CLK_A for the 2: 1 multiplexer (170) by the phase shifter (320). The phase of the clock CLK_B that outputs the output data DT is adjusted so that the change timing of the output data DT coincides with the change timing of the clock CLK_A_DMY. Here, when the clock CLK_A instead of the clock CLK_A_DMY is applied as the phase comparison target, the rising edge of the clock CLK_A is positioned at the change timing of the output data DT. In this state, the 2: 1 multiplexer (170) cannot reliably receive the output data of the 4: 2 multiplexer (140). Therefore, in the phase comparison, it is necessary to use a clock CLK_A_DMY obtained by shifting the phase of the clock CLK_A by a certain amount (added a phase offset). Also, the latch circuit (321) for receiving the output data DT at the rising edge of the clock CLK_A_DMY needs to be the same physical structure as the first stage latch circuit (171, 173) of the 2: 1 multiplexer (170). There is.

  The phase comparison is based on the continuous data output by the 4: 2 multiplexer (140), and the clock CLK_A_DMY for the output data DT depends on whether the data is received before or after the rising edge of the clock CLK_A_DMY. The phase lag or phase advance is determined. A timing chart of this phase comparison is shown in FIG.

  As shown in the figure, the clock CLK_B latches the latter half of the 2-bit output data DT shown in FIG. 4 in the latch circuit (323), and the second bit of output data DT "0 at the rising edge of the clock CLK_B. "Is latched by the latch circuit (323), and the value of the output DT_B0 is" 0 ". On the other hand, the value of the output data DT latched in the latch circuit (321) at the rising edge of the clock CLK_A_DMY is also “0”, which is the output data DT of the second bit. The output DT_A of the latch circuit (321) is latched by the latch circuit (322) at the rising edge of the clock CLK_B, and the output DT_B1 is subjected to the XOR logic operation by the output DT_B0 of the latch circuit (323) and the XOR logic circuit (324). The output PI_SFT_TMP is generated, delayed by one clock in the latch circuit (325), and input to the PI control unit (422) as the phase comparison result signal PI_SFT. In this case, the value of the phase comparison signal PI_SFT is “0”, which indicates that the data latched by the clock CLK_A_DMY is the latter half of the data. In the case of the output data DT of the third bit and the fourth bit, the output data DT latched in the latch circuit (321) at the rising edge of the clock CLK_A_DMY is the third bit, as shown in FIG. Data, that is, the first half of the output data DT of 2 bits each, and the value of the phase comparison signal PI_SFT is “1”.

  As described above, in this timing chart, when the clock CLK_A_DMY receives previous data in time, the phase comparison signal PI_SFT = 1 is output as the phase comparison result. In this case, the PI control unit (422) is instructed to advance the phase of the clock CLK_B. Conversely, when the clock CLK_A_DMY receives data that is later in time, the phase comparison signal PI_SFT = 0 is output. In this case, the PI control unit (422) is instructed to delay the phase of the clock CLK_B.

  In the PI control unit (422), even if the value of the phase comparison signal PI_SFT is “0”, if there is no data change in the continuous data described with reference to FIG. 4, the latch circuit (321) is detected at the rising edge of the clock CLK_A_DMY. Therefore, the phase comparison result signal is valid only for continuous data for which the data change detection unit (52) has detected a data change. A control signal is supplied to the phase interpolator PI (421) by integrating the comparison result signal, and the phase of the clock CLK_B is adjusted.

  By repeating the above series of operations, the phase of the output data DT and the clock CLK_A_DMY coincide, and the 2: 1 multiplexer (170) can reliably receive the 4: 2 multiplexer (140) output data. . According to this embodiment, it is possible to realize a data transmission / reception system that is not affected by process variations and power supply voltage / temperature fluctuations regardless of the data transfer rate.

Next, a second embodiment of the present invention will be described with reference to FIGS.
As described above, the present embodiment is provided with a replica that always outputs data with a change in data. FIG. 6 shows the configuration of the present embodiment in detail, and FIG. 3 shows a timing chart for phase comparison.

  Among the components shown in FIG. 6, those given the same reference numerals as those shown in FIG. 3 have different input data of the phase comparator (32) and clocks of the latch circuit (321). However, it is functionally the same as that described in FIG. As shown in FIG. 6, in the present embodiment, the data change detection unit (52) described in FIG. 3 does not exist, and instead, the same as the last stage selector (146, 156) of the 4: 2 multiplexer (140). A dummy data output unit (160), which is a block for generating 1010 repetition data using a selector (166) having a physical configuration, is provided. This 1010 repeated data runs in parallel with the 4: 2 multiplexer (140) output data, and although not shown, the dummy data output unit (160) is similar to the selector (146,156) in the 4: 2 multiplexer. (140).

  The physical configuration of the selector (166) is the same as the final stage selector (146, 156) of the 4: 2 multiplexer (140). The final stage selector (146, 156), which is the original output data of the 4: 2 multiplexer (140), is used. This is to accurately simulate the change timing of the output data.

Therefore, in general, a circuit having the same physical configuration as that of the final stage circuit of the data transmission unit is used as the dummy data output unit, not limited to the selector.
In the case of 1010 repetitive data, there is always a change in data, so there is no need to detect data change. The phase comparison is performed between the 1010 repetition data DT_DMY and the clock CLK_A for the 2: 1 multiplexer (170). In the first embodiment shown in FIG. 3, the clock CLK_A_DMY obtained by shifting the phase of the clock CLK_A by a fixed amount is used, but in this embodiment, the phase of the clock CLK_B is fixed by the phase shifter (167) instead. An amount phase shifted clock CLK_B_DMY is used. The reason for using the phase shifter (167) is the same as the reason for using the phase shifter (320) and can be replaced with each other.

Hereinafter, the phase comparison operation of this embodiment will be described with reference to FIG.
As shown in the figure, 1010 repeated data DT_DMY data “0” is latched in the latch circuit (323) at the rising edge of the clock CLK_B_DMY, while 1010 repeated data DT_DMY is latched in the latch circuit (321) at the rising edge of the clock CLK_A. The output DT_A is latched by the latch circuit (322) at the rising edge of the clock CLK_B_DMY. Then, the output DT_B1 of the latch circuit (322) and the output DT_B0 of the latch circuit (323) are compared by the XOR logic circuit (324) to generate a signal PI_SFT_TMP indicating coincidence mismatch, and the latch circuit (325) delays by one clock. Then, it is input to the PI control unit (423) as the phase comparison result signal PI_SFT. Since 1010 repeated data DT_DMY always has a data displacement, the PI control unit (423) has the same configuration as the PI_EN_TMP signal shown in FIG. The phase interpolator PI (421) adjusts the phase of the clock CLK_B with respect to the 4: 2 multiplexer (140) based on the control signal based on the phase comparison result.

  According to the present embodiment, since the data change detection block can be omitted, a data transmission / reception system that is not affected by process variations and power supply voltage / temperature fluctuations can be realized with a smaller circuit scale regardless of the data transfer rate. be able to.

  FIGS. 8 and 9 respectively show the timing adjustment circuit configuration for data transmission / reception between the 4: 2 multiplexer (140) and the 2: 1 multiplexer (170) in the first and second embodiments. 10 shows a third embodiment and a fourth embodiment applied between the multiplexers of the data transmission circuit shown in FIG. Here, the phase comparison mechanism is omitted.

The difference between the third embodiment shown in FIG. 8 and the fourth embodiment shown in FIG. 9 is the arrangement of the phase interpolators PI (421, 431, 441).
In the third embodiment of FIG. 8, each multiplexer is arranged so that the phase of the clock can be adjusted individually. For this reason, the influence of the change in the phase of the clock does not propagate to the preceding multiplexer.

  For example, to ensure data transmission and reception between the 4: 2 multiplexer (140) and the 2: 1 multiplexer (170), the output phase of the 10 GHz clock phase interpolator PI (421) to the 4: 2 multiplexer (140) Is changed, the phase relationship between the data and the clock between the 8: 4 multiplexer (130) and the 4: 2 multiplexer (140) in the preceding stage changes. Therefore, it may be necessary to sequentially adjust the output phases of the phase interpolator PI (431) and the phase interpolator PI (441).

  On the other hand, in the fourth embodiment of FIG. 9, the phase interpolator PI is arranged so that the output of the phase interpolator PI is supplied to the previous frequency divider as shown. If the output phase of the 10 GHz clock phase interpolator PI (421) is changed to ensure data transmission / reception between the 4: 2 multiplexer (140) and the 2: 1 multiplexer (170), it is in the previous stage. The phase relationship between the data and the clock between the 8: 4 multiplexer (130) and the 4: 2 multiplexer (140) is maintained. This is because the clock for the preceding 8: 4 multiplexer (130) is generated based on the clock for the 4: 2 multiplexer (140).

  According to the third embodiment and the fourth embodiment, the present invention can be applied to the entire data transmission circuit. In particular, the configuration of the fourth embodiment shown in FIG. 9 can provide an easy-to-use data transmission / reception system because the phase adjustment result does not propagate between other circuit blocks.

  The present invention is also applicable to data transmission / reception between LSIs. As the semiconductor process becomes finer, the influence of the process variation becomes more prominent. The circuit technology corresponding to the process variation such as the timing adjustment circuit of the present invention will be an important element technology for realizing the LSI in the future.

(Supplementary Note 1) A timing adjustment circuit that adjusts the timing of data transmission / reception between a data transmission unit that transmits data and a data reception unit that receives the data, and a phase of data output from the data transmission unit The phase of the clock that defines the timing at which the data receiving unit receives data is compared, and the phase of the clock that defines the timing at which the data transmitting unit transmits data is adjusted according to the comparison result. Timing adjustment circuit.
(Supplementary Note 2) Phase comparison between a data change detection unit that detects a change in data output from the data transmission unit, a clock that defines a timing at which the data reception unit receives data, and data output from the data transmission unit And when the data change detection unit detects a change in the data output from the data transmission unit, the data transmission unit transmits data according to the phase comparison result of the phase comparison unit. The timing adjustment circuit according to claim 1, further comprising a phase adjustment unit that changes a phase of a clock that defines the timing.
(Supplementary Note 3) The phase comparison unit is a circuit that receives data output from the data transmission circuit based on a clock that defines a timing at which the data reception unit receives data, as the first stage circuit, The timing adjustment circuit according to appendix 2, further comprising a latch circuit having the same configuration as the first stage circuit of the partial block.
(Additional remark 4) The said latch circuit receives the data which the said data transmission part outputs synchronizing with the clock which shifted the clock which prescribes | regulates the timing which the said data reception part receives data predetermined amount. 3. The timing adjustment circuit according to 3.
(Supplementary Note 5) Dummy data output circuit for outputting 1010 repetitive data always changing data based on a clock that defines the timing at which the data transmitting unit transmits data, and the timing at which the data receiving unit receives data A phase comparison unit that performs phase comparison between the clock that defines the data and the data output from the dummy data output circuit, and a timing at which the data transmission unit transmits data according to a phase comparison result of the phase comparison unit The timing adjustment circuit according to appendix 1, further comprising a phase adjustment unit that changes a phase of the clock.
(Additional remark 6) The said dummy data output circuit is the same structure as the last stage of the said data transmission part, The timing adjustment circuit of Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) The dummy data output circuit always outputs 1010 repeated data having a data change in synchronization with a clock obtained by phase-shifting a clock defining a timing at which the data transmitting unit transmits data by a predetermined amount. The timing adjustment circuit according to Supplementary Note 6 (Appendix 8) In an LSI that sequentially transmits and receives data between a plurality of blocks, a data transmission side block is provided for each block on the transmission side and each block on the reception side. A data change detection unit that detects a change in data to be output; a phase comparison unit that performs phase comparison between a clock that defines a timing at which the data reception side block receives data and data that is output from the data transmission side block; When the data change detection unit detects a change in data output from the data transmission side block, the phase ratio An LSI comprising: a timing adjustment circuit having a phase adjustment unit that changes a phase of a clock that defines a timing at which the data transmission side block transmits data according to a phase comparison result of a comparison unit.
(Supplementary Note 9) The phase adjustment is performed so that a clock subject to phase adjustment between a data transmission side block and a data reception side block affects data transmission / reception timing between another data transmission side block and the data reception side block. The LSI according to appendix 8, wherein a part is arranged.
(Supplementary Note 10) The phase is adjusted so that a clock subject to phase adjustment between a data transmission side block and a data reception side block does not affect the data transmission / reception timing between another data transmission side block and the data reception side block. The LSI according to appendix 8, wherein an adjustment unit is arranged.
(Supplementary Note 11) The plurality of blocks are a plurality of multiplexers that sequentially convert parallel data into serial data, and constitute a data transmission circuit that outputs data from the LSI to the outside. 8. The LSI according to 8.
(Supplementary note 12) The LSI according to supplementary note 11, wherein each multiplexer outputs data in which the bit width of the input data is halved and the speed is doubled.
(Additional remark 13) The clock which prescribes | regulates the timing which the multiplexer of the last stage among these multiplexers receives data is produced | generated by the clock generation means of the said LSI, and each said multiplexer which becomes the said multiplexer on the transmission side, and each said multiplexer on the receiving side Is provided with a 1/2 frequency divider, and the multiplexers other than the final stage are obtained by dividing the clock that defines the data reception timing of the subsequent stage multiplexer by half with the 1/2 frequency divider. 13. The LSI according to appendix 12, wherein a transmission timing of data to be transmitted to the multiplexer subsequent to the multiplexer is defined by the supplied clock.
(Supplementary Note 14) A clock generated by the clock generation means of the LSI is input to the final-stage multiplexer and the half-divider corresponding to the preceding-stage multiplexer, and the other half-divider The LSI according to appendix 13, wherein an output of a half-frequency divider in the subsequent stage is input to.
(Supplementary Note 15) A clock generated by the clock generation means of the LSI is input to the final stage multiplexer and the half frequency divider corresponding to the preceding stage multiplexer, and the other half frequency dividers are used. The LSI according to appendix 13, wherein the output of the half-frequency divider at the subsequent stage is input via a phase adjustment unit.
(Supplementary Note 16) In a data transmission / reception system that transmits and receives data between a first LSI and a second LSI, a data change detection unit that detects a change in data output from the first LSI, and the second LSI A phase comparison unit that performs phase comparison between a clock that defines a timing at which the LSI receives data and data output from the first LSI; and a change in data output from the first LSI by the data change detection unit. A timing adjustment circuit having a phase adjustment unit that, when detected, changes a phase of a clock that defines a timing at which the first LSI transmits data according to a phase comparison result of the phase comparison unit; A featured data transmission / reception system.
(Supplementary Note 17) The supplementary note 16 is characterized in that the first LSI includes a plurality of multiplexers that sequentially convert parallel data into serial data, and includes a data transmission circuit that outputs data from the first LSI to the outside. The data transmission / reception system described.
(Supplementary note 18) The data transmission / reception system according to supplementary note 17, wherein each multiplexer outputs data in which the bit width of the input data is halved and the speed is doubled.
(Supplementary Note 19) For each multiplexer on the transmission side and multiplexer on the reception side, a data change detection unit that detects a change in data output from the data transmission side multiplexer, and a timing at which the data reception side multiplexer receives data. A phase comparison unit that performs phase comparison between a prescribed clock and data output from the data transmission side multiplexer; and the phase comparison when the data change detection unit detects a change in data output from the data transmission side multiplexer. 19. The data according to claim 18, further comprising a timing adjustment circuit having a phase adjustment unit that changes a phase of a clock that defines a timing at which the data transmission side multiplexer transmits data according to a phase comparison result of the unit. Transmission / reception system.

The figure which shows the basic composition of this invention. The figure which shows the application example of the basic composition of this invention shown in FIG. The figure which shows the structure of the 1st Example of this invention. The figure which shows the timing chart of the data change detection of a 1st Example. The figure which shows the timing chart of the phase comparison of a 1st Example. The figure which shows the structure of the 2nd Example of this invention. The figure which shows the timing chart of the phase comparison of a 2nd Example. The figure which shows the 3rd Example of this invention. The figure which shows the 4th Example of this invention. The figure which shows the structural example of the conventional data transmission circuit The figure explaining the data transmission / reception between the multiplexers of the data transmission circuit shown in FIG. FIG. 12 is a timing chart when data transmission / reception between multiplexers shown in FIG. 11 is normally performed. The figure which shows the timing chart in case data transmission / reception between the multiplexers shown in FIG. 11 is not performed normally.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Data transmission part 12 Previous stage latch part 20 Data reception part 22 Later stage latch part 30, 32 Phase comparison part 40, 42 Phase adjustment part 52 Data change detection part 100 PLL
110 Data Buffer 120 16: 8 Multiplexer 130 8: 4 Multiplexer 140 4: 2 Multiplexer 160 Dummy Data Output Unit 170 2: 1 Multiplexer 180 Output Buffer

Claims (1)

A timing adjustment circuit that adjusts timing of data transmission / reception between a data transmission unit that transmits data and a data reception unit that receives the data,
The phase of the data output from the data transmission unit is compared with the phase of the clock that defines the timing at which the data reception unit receives data, and the timing at which the data transmission unit transmits data is determined according to the comparison result. Adjust the clock phase
A dummy data output circuit that outputs 1010 repeated data always having data changes based on a clock that defines the timing at which the data transmission unit transmits data;
A phase comparison unit that performs phase comparison between a clock that defines a timing at which the data reception unit receives data and data output by the dummy data output circuit;
A timing adjustment circuit comprising: a phase adjustment unit that changes a phase of a clock that defines a timing at which the data transmission unit transmits data according to a phase comparison result of the phase comparison unit.

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