JP4333492B2 - Method for manufacturing circuit module body - Google Patents

Description

  The present invention relates to a method of manufacturing a circuit module body in which a thin film laminated circuit body, which is thinned by forming fine wirings, high-precision passive elements, etc. at high density through an insulating layer by thin film formation technology, is mounted on a base substrate. About.

  In recent years, various types of mobile electronic devices such as personal computers, mobile phones, video devices, and audio devices have been reduced in size, weight, functionality, functionality, and speed. Various electronic components and circuit boards provided are also reduced in size and weight or mounted in high density. In mobile electronic devices, for this purpose, a wiring layer having a fine wiring pattern is formed in multiple layers using, for example, a thin film forming technique, and a passive element such as a capacitor, a resistor or an inductor, or a functional element such as a filter is provided in the wiring layer. A multifunctional circuit module body built in has been developed (for example, see Patent Document 1).

  In the high-frequency circuit module 200 for communication function shown in FIG. 38, in order to ensure high-frequency characteristics, measures are taken for wiring pattern routing, ground pattern placement, etc., and electromagnetic interference noise (EMI : Electromagnetic Interference). In the high-frequency circuit module 200, a high-frequency circuit unit 205 in which a capacitor element 202, a resistor 203, an inductor element 204, or the like is formed is laminated on a base circuit unit 201 in which a control circuit unit, a power supply circuit, a ground pattern, or the like is formed. The In the high-frequency circuit module 200, a high-frequency signal processing LSI 206 and a chip component 207 are mounted on the uppermost layer of the high-frequency circuit unit 205.

  In the high-frequency circuit module body 200, a shield case 208 is assembled on the uppermost layer of the high-frequency circuit unit 205. The shield case 208 is formed in a box shape with, for example, a nickel-plated copper plate or a stainless plate, and covers the high-frequency circuit unit 205 to block the influence of electromagnetic interference noise.

  By the way, in the high-frequency circuit module 200 described above, when the high-frequency circuit unit 205 having passive elements and functional elements is formed on the wiring board, the heat resistance, chemical resistance, flatness, warpage, thickness accuracy, etc. Because of this problem, the substrate material and the process for forming each element are limited, and it is difficult to form the substrate with high precision and high precision. In the high-frequency circuit module body 200, for example, a high-frequency circuit unit 205 having fine wiring with high accuracy using a glass substrate such as quartz having heat resistance and chemical resistance and capable of forming a highly accurate flat surface. A manufacturing method is also proposed in which only the high-frequency circuit unit 205 is transferred and mounted on a separate substrate (see, for example, Patent Document 2).

  On the other hand, the applicant previously provided a novel thin circuit module body and a method for manufacturing the same according to Patent Document 3, for example. Thin circuit module body can form a high-precision flat surface, has excellent heat resistance characteristics for heating treatment during thin film formation, good depth of focus during lithographic processing, and good contact alignment characteristics during masking. In addition, a silicon substrate or a glass substrate having chemical resistance is used as a dummy substrate. The thin circuit module body forms a thin film laminated circuit body having a multilayer wiring layer in which a wiring pattern and a thin film element are formed on a main surface of the dummy substrate via a peeling layer.

  The thin circuit module body is mounted on the main surface of the base substrate while the thin film laminated circuit body is peeled off from the dummy substrate via the peeling layer or inverted while being formed on the dummy substrate. Compared with the above-described high-frequency circuit module body 200 in which a wiring layer, a passive element, and the like are sequentially laminated on a base substrate, the thin circuit module body has fine wiring without being affected by substrate warpage or surface irregularities. A multilayer wiring layer in which a pattern and a high-precision thin film element are formed is formed.

JP 2002-368438 A JP 2003-142666 A JP 2002-164467 A

  As described above, the high-frequency circuit module 200 is formed thin with the high-frequency circuit unit 205 having a multilayer wiring layer in which fine wiring patterns, high-precision thin-film elements and functional elements are formed, and mobile electronics. It has the feature that it can be miniaturized, thinned, multi-functionalized, and highly functionalized by being used in equipment and the like.

  However, in the manufacturing method of the conventional high-frequency circuit module body 200 described above, since the high-frequency circuit unit 205 is extremely thin, the work of peeling from the glass substrate and mounting it on the base substrate is extremely troublesome. In the method of manufacturing the high-frequency circuit module body 200, the high-frequency circuit unit 205 is automatically mounted on a base substrate using a mounting machine or the like in the same manner as the high-frequency signal processing LSI 206 and the chip component 207. There was a problem that it could not be adopted.

  In the method for manufacturing the high-frequency circuit module 200, the high-frequency circuit unit 205 peeled off from the glass substrate is mounted on the main surface of the base substrate with an adhesive, and the electrical resistance at the bonding surface is low. There was a problem that the electrical characteristics deteriorated due to the increase. In the method of manufacturing the high-frequency circuit module body 200, the high-frequency circuit unit 205 is bent or wrinkled during the joining process, and positioning with the base substrate side cannot be performed with high accuracy, and the connection between the opposing terminal units is reliable. There was also a problem that sex was not secured.

  Therefore, according to the present invention, a thin film laminated circuit body having a fine wiring pattern manufactured on a dummy substrate and a multilayer wiring layer in which high-precision thin film elements and functional elements are formed is efficiently peeled from the dummy substrate. Thus, it is an object of the present invention to provide a method for manufacturing a circuit module body that reduces cost and improves reliability and electrical characteristics.

  A method of manufacturing a circuit module body according to the present invention that achieves the above-described object is a method of forming a multilayer wiring layer in which a thin film element or a functional element is formed on an insulating layer on a base substrate on which a wiring layer is formed. A circuit module body is manufactured by mounting at least one thin film laminated circuit body formed by the forming technique on the main surface. In the method of manufacturing a circuit module body, a thin film laminated circuit body is formed on a flattened main surface of a dummy substrate, and the thin film laminated circuit body is peeled off from the dummy substrate by a peeling process to be formed on the main surface of the base substrate or wiring. Implement in the layer.

  The manufacturing method of the thin film laminated circuit body includes a peeling layer forming step in which a peeling layer is formed on the planarized main surface of the dummy substrate, and a multilayer structure through an insulating layer on the peeling layer. A thin film circuit layer in which a wiring layer and a thin film element are formed by a thin film forming technique, and a plurality of thin film laminated circuit bodies formed by forming connection terminal portions on a mounting surface with respect to a base substrate are separated from each other through separation slits. A thin film laminated circuit body is pasted in a state where the respective separation slits and slits are aligned with the forming film and the holding film material in which a large number of slits are formed corresponding to each separation slit. Holding film material pasting step and the entire film is peeled off from the dummy substrate in a state where each thin film multilayer circuit body is held by the holding film material by dipping in a peeling solution for dissolving the metal layer of the peeling layer And a thin film layered circuit body peeling step of, consisting and a thin-film multilayer circuit body separation step of separating each of the thin film multilayer circuit body one by one from the holding film material through the separation slit.

  In the method of manufacturing a circuit module body, in the peeling layer forming step, an acid surface is formed on a main surface of a dummy substrate made of, for example, silicon or glass substrate, which is excellent in heat resistance and chemical resistance and capable of forming a highly accurate flat surface. Alternatively, a metal film soluble in an alkaline solution is formed, and a protective layer is formed on the metal film to form a release layer. In the release layer forming step, the above-described dummy substrate is used to form a release layer having a high-precision flat surface on the main surface.

  In the method of manufacturing a circuit module body, in the thin film circuit layer forming step, an insulating layer and a wiring layer are formed in a multilayer on the release layer, and a thin film passive element and a thin film functional element are formed in the wiring layer. In addition, a large number of thin-film laminated circuit bodies on which connection terminal layers and interlayer connection portions are formed are formed in a state of being separated from each other through separation slits. In the thin film circuit layer forming process, the above-mentioned dummy substrate is used on the main surface, which has the heat resistance characteristics, the maintenance of the depth of focus during lithographic processing, the contact alignment characteristics at the time of masking, and the insulating and chemical resistance characteristics. By forming a multilayer wiring layer and each element on the substrate, the wiring layer and each element are not affected by heat treatment or chemical treatment, or by warping of the substrate or surface irregularities. Wiring patterns and thin film elements are formed.

  In the method of manufacturing a circuit module body, in the holding film material sticking step, an adhesive layer whose adhesive strength is reduced by light irradiation or heat treatment is provided on the flexible film material and a plurality of slits corresponding to each separation slit are provided. A holding film material divided into a number of bonding regions for bonding each thin film laminated circuit body one by one is formed, and this holding film material is formed on each thin film laminated circuit body with each separation slit and slit. Are aligned and bonded with an adhesive layer. Further, in the holding film material sticking step, the holding film material may be used by fixing the outer peripheral portion to a ring-shaped holder member having an inner diameter larger than the outer diameter of the dummy substrate.

  In the method for manufacturing a circuit module body, in the thin film laminated circuit body peeling step, the dummy substrate on which the thin film laminated circuit body is formed and the holding film material is bonded is immersed in a peeling solution made of an acid solution or an alkali solution. In the method of manufacturing a circuit module body, the stripping solution penetrates the stripping layer from the inner portion through each slit and separation slit together with the outer peripheral portion of the dummy substrate, and efficiently dissolves the metal layer throughout. Thus, the peeling operation is performed in a state where the thin film laminated circuit body formed in the inner portion is also held by the holding film material from the dummy substrate. In the method for manufacturing a circuit module body, the flexible holding film material is deformed in accordance with the deformation state of each thin film laminated circuit body that is peeled from the dummy substrate via the peeling layer, thereby Even if there is variation in the bonding strength of the thin film multilayer circuit body, it will be possible to perform easy peeling, and the penetration of the stripping solution will be promoted, so that each thin film multilayer circuit body will be peeled efficiently and cleanly. .

  In the method of manufacturing a circuit module body, in the thin film laminated circuit body separation step, for example, the adhesive strength of the adhesive of the holding film material is lowered by performing ultraviolet irradiation or heat treatment, so that each thin film laminated circuit body is passed through the separation slit. Separate them one by one. In the method of manufacturing a circuit module body, the separated thin film laminated circuit body is mounted on a base substrate on which a power supply section, a signal wiring section, and the like are formed by joining opposing connection terminal sections.

  According to the method for manufacturing a circuit module body according to the present invention, a plurality of thin film laminated circuit bodies are formed on a dummy substrate through a separation layer and separated from each other through a separation slit, and corresponding to the separation slit. Since the holding film material on which the slit is formed is put on each thin film laminated circuit body and bonded together, in the thin film laminated circuit body peeling process, the peeling solution separates not only from the outer peripheral part of the dummy substrate but also from each slit. It is possible to efficiently peel the thin film laminated circuit body by penetrating the peeling layer also from the inner part through the slit and dissolving the metal layer over the whole. According to the method of manufacturing a circuit module body, since each thin film laminated circuit body is peeled off from the dummy substrate while being held by the holding film material, an unreasonable peeling force is not applied to each thin film laminated circuit body. It becomes possible to peel off, and the occurrence of damage to the wiring pattern and the thin film element is prevented, and handling after peeling becomes easy. According to the method of manufacturing a circuit module body, a thin, high-precision and efficient thin-film laminated circuit body having a multilayer wiring layer in which fine wiring patterns and high-precision thin-film elements are formed is mounted on a base substrate. As a result, the thin film laminated circuit body and the base substrate are electromagnetically separated to suppress mutual interference, and a circuit module body with improved functionality, increased functionality, or improved characteristics is manufactured.

  Hereinafter, a high-frequency circuit module body (circuit module body) 1 shown as an embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the drawings. The high-frequency circuit module body 1 shown in FIG. 1 has, for example, an information communication function, a storage function, and the like, and is mounted on various mobile electronic devices such as a personal computer, a mobile phone, or an audio device, or is inserted and removed as an option. The high-frequency circuit body of the ultra-small communication function module body is configured. Although not described in detail, the high-frequency circuit module body 1 performs transmission / reception of information signals without performing conversion to a high-frequency transmission / reception circuit unit or intermediate frequency by a superheterodyne method in which a transmission / reception signal is once converted to an intermediate frequency. A high-frequency transmission / reception circuit unit or the like based on the direct conversion method is formed.

  As will be described in detail later, the high-frequency circuit module body 1 uses a dummy substrate 2 in which a release layer 3 is formed on a main surface 2a, and a plurality of thin film laminated circuit bodies (manufactured on the release layer 3 by thin film technology ( (Thin Film Laminated Circuit Body) 4A to 4N are laminated, each thin film laminated circuit body 4 is peeled off from the dummy substrate 2 through the peeling layer 3, and each thin film laminated circuit body 4 is individually separated. After that, it is manufactured through a process of mounting on the base substrate 5 and the like. In the high-frequency circuit module body 1, the base substrate 5 constitutes a power supply system that supplies power, a control signal, and the like to the thin film multilayer circuit body 4 or a wiring section or a ground section of the control system.

  The high-frequency circuit module body 1 has a structure in which the thin film laminated circuit body 4 and the base substrate 5 are electrically and electromagnetically separated to improve the characteristics by suppressing mutual interference and have a sufficient area. A power supply pattern and a ground pattern are formed on the base substrate 5, and a circuit portion formed in the thin film laminated circuit body 4 performs a stable operation. The high-frequency circuit module body 1 has a thin film laminated circuit body 4 having a multilayer wiring layer through an insulating layer as will be described later. For example, the high frequency circuit module body 1 includes a thin film laminated circuit body having a single wiring layer. Also good.

  The base substrate 5 is an organic substrate based on glass epoxy, polyimide, polyphenylene ether, bismaletotriazine, polytetrafluoroethylene, or the like that is conventionally used as a multilayer wiring substrate, glass, alumina, ceramic, or the like. An inorganic substrate or a composite substrate of an organic material and an inorganic material is used. The base substrate 5 is formed at a low cost by being formed by a conventional general multi-layer wiring technique using a relatively inexpensive base material that does not require much accuracy. Although not described in detail on the base substrate 5, the signal wiring pattern 6, the power supply wiring pattern 7, the ground pattern 8, and the like are formed in multiple layers and the layers are connected to each other by vias 9.

  As shown in FIG. 1, the base substrate 5 is exposed to the uppermost layer 5 a covered with the solder resist layer 10 through the openings 10 a formed in the solder resist layer 10. A large number of mounting terminal portions 11 for mechanically and electrically connecting 4 are patterned. On the base substrate 5, solder bumps 12 are formed on the mounting terminal portions 11, respectively. The base substrate 5 is mounted on the lower layer 5b covered with the solder resist layer 13 from the opening formed in the solder resist layer 13, and the high frequency circuit module body 1 is mounted on an interposer (not shown). A large number of connecting terminal portions 14 are formed.

  As shown in FIG. 2, the thin film laminated circuit body 4 is manufactured by a manufacturing process using a thin film technique and a thick film technique, which will be described in detail later, and the first insulating layer 15 to the third insulating layer 17 have a fine width and pitch. A plurality of capacitor elements 21, register elements 22, inductor elements 23, etc. that are formed with high accuracy in the first to third wiring layers 20 to 20, in which the high-accuracy wiring patterns are formed, or the like are provided with high accuracy. It is built in. A plurality of mounting connection lands 24 to which the solder bumps 12 of the base substrate 5 are joined are formed in the thin film laminated circuit body 4 so as to face the terminal openings 15a provided in the first insulating layer 15, and the third insulation A large number of external electrodes 26 are formed facing the openings 25 a provided in the solder resist layer 25 formed on the layer 17.

  The thin film laminated circuit body 4 can directly mount electronic components such as a filter and chip components on the upper portion thereof via the external electrodes 26. Therefore, the thin film laminated circuit body 4 can be mounted on the uppermost layer with elements that could not be formed inside, and the wiring length can be shortened. Further, in the thin film laminated circuit body 4, each external electrode 26 is formed corresponding to each mounting terminal portion 11 on the base substrate 5 side, and each mounting connection land 24 and each mounting terminal portion 11 facing each other are connected. It is mounted on the base substrate 5 by connecting.

  In the thin film laminated circuit body 4, the interlayer connection between the mounting connection land 24 and the first wiring layer 18 is appropriately performed by the first via 28 formed in the first insulating layer 15, and the second via formed in the second insulating layer 16. 29, the first wiring layer 18 and the second wiring layer 19 are appropriately connected to each other, and the second wiring layer 19 and the third wiring layer 20 are connected via the third via 30 formed in the third insulating layer 17. The interlayer connection is appropriately performed. The high-frequency circuit module body 1 is provided with a so-called via-on-via structure in which the vias between the upper and lower wiring layers are directly formed in the thin film laminated circuit body 4, thereby reducing the wiring length. In addition, the attenuation of the transmission signal is reduced, and connection with a minimum signal delay is performed.

  The capacitor element 21 is, for example, a decoupling capacitor or a DC cut capacitor, and is formed of a tantalum oxide (TaO) film or a tantalum nitride (TaN) film by a process described in detail later. The register element 22 is, for example, a resistor for termination resistance, and is formed of a tantalum nitride film. The high-frequency circuit module body 1 is mounted with an extremely small and high-performance passive element or the like by forming various kinds of passive elements, which are conventionally supported by chip components, in the thin film multilayer circuit body 4. As a result, a reduction in size and thickness is achieved.

  The thin film multilayer circuit body 4 is positioned between the uppermost layer 5 a and the first insulating layer 15 by aligning the mounting connection land 24 and the mounting terminal portion 11 that face each other with respect to the base substrate 5. Thus, the underfill layer 27 is formed. The thin film laminated circuit body 4 is mounted by soldering the mounting connection land 24 and the mounting terminal portion 11 facing each other by melting the solder bumps 12 using, for example, a thermocompression bonding device or the like. Constitute. The high-frequency circuit module body 1 forms a low-speed signal circuit such as a power supply circuit, a ground, or a control signal on the base substrate 5 side, and forms a high-speed signal circuit between LSIs on the thin film laminated circuit body 4 side. In the high-frequency circuit module body 1, the power supply wiring pattern 7 and the ground pattern 8 having a sufficient area are formed on the base substrate 5 side, so that highly regulated power supply is performed to the thin film multilayer circuit body 4.

  The high-frequency circuit module body 1 is miniaturized because various passive elements are formed in the wiring layer to be multi-functional and the like is manufactured as a thin thin film laminated circuit body 4 and mounted on the base substrate 5. Thinning is achieved. Since the high-frequency circuit module body 1 is manufactured by improving the yield by simple equipment and simple steps, the cost can be reduced.

  The high-frequency circuit module body 1 configured as described above is manufactured through the manufacturing process shown in FIG. The high-frequency circuit module body 1 is manufactured by manufacturing a large number of thin film multilayer circuit bodies 4 having the same specifications on the dummy substrate 2 or simultaneously manufacturing a large number of thin film multilayer circuit bodies 4 having a plurality of specifications. You may make it do.

  The manufacturing process of the high-frequency circuit module body 1 includes a release layer forming step s-1 in which a dummy substrate 2 made of a silicon substrate or a glass substrate having a flat main surface 2a is supplied and a release layer 3 is formed on the main surface 2a. Have The manufacturing process of the high-frequency circuit module body 1 includes a process of manufacturing the thin film laminated circuit body 4 on the release layer 3. The manufacturing process of the high-frequency circuit module body 1 includes a process of peeling the manufactured thin film laminated circuit body 4 from the dummy substrate 2. The manufacturing process of the high-frequency circuit module body 1 includes a process of mounting the thin film laminated circuit body 4 on the base substrate 5.

  The manufacturing process of the thin film multilayer circuit body 4 includes a mounting connection land forming step s-2 for forming the mounting connection land 24 on the release layer 3, and a first insulating layer forming step s-3 for forming the first insulating layer 15. The first wiring layer forming step s-4 for forming the first wiring layer 18, the second insulating layer forming step s-5 for forming the second insulating layer 16, and the element forming step s- for forming each thin film element 6. The manufacturing process of the thin film multilayer circuit body 4 includes a second wiring layer forming step s-7 for forming the second wiring layer 19, a third insulating layer forming step s-8 for forming the third insulating layer 17, and a third step. A third wiring layer forming step s-9 for forming the wiring layer 20 and a solder resist layer / external electrode forming step s-10 for forming the solder resist layer 25 and the external electrode 26 are included.

  The manufacturing process of the high-frequency circuit module body 1 includes a peeling layer part removing step s-11 for removing a part of the peeling layer 3 and a thin film laminated circuit body 4 formed on the dummy substrate 2 so as to cover the holding film material. A holding film material laminating step s-12 for laminating 31, a peeling step s-13 for peeling from the dummy substrate 2 in a state where each thin film laminated circuit body 4 is held by the holding film material 31, and each from the holding film material 31 A thin film laminated circuit body separation step s-14 for separating the thin film laminated circuit bodies 4 one by one. The manufacturing process of the high-frequency circuit module body 1 includes a solder bump forming step s-15 in which a base substrate 5 on which predetermined wiring layers and the like are formed in multiple layers is supplied and solder bumps 12 are formed on the base substrate 5, and a base substrate 5 includes a thin film multilayer circuit body mounting step s-16 for mounting the thin film multilayer circuit body 4.

  As shown in FIG. 4, the holding film material 31 used in the holding film material laminating step s-11 has heat resistance, chemical resistance, and flexibility, for example, a synthetic resin base such as polyester, polyethylene terephthalate, and polyimide. It consists of a material fill 31a and an adhesive layer 31b formed on the entire surface of the substrate fill 31a. The holding film material 31 is formed by forming an adhesive layer 31b having a layer thickness of about 40 μm to 80 μm with respect to the base material film 31a having a thickness larger than the outer diameter of the dummy substrate 2 and having a thickness of 30 μm to 50 μm. A large number of slits 32 are formed in the holding film material 31 in a matrix shape, and a large number of pastes corresponding to the respective thin film laminated circuit bodies 4 manufactured on the dummy substrate 2 through the steps described later. It is divided into the matching area 33.

  In the holding film material 31, bubbles are generated inside when the adhesive layer 31 b irradiates, for example, ultraviolet rays or is subjected to heat treatment, and the light irradiation-reducing adhesive in which the bonding strength between the objects to be bonded decreases due to the presence of the bubbles. An adhesive or a heat-lowering adhesive is used. As will be described later, the holding film material 31 holds each thin film laminated circuit body 4 from the dummy substrate 2 and peels it together, and then, by applying light irradiation or heat treatment, each thin film laminated circuit body 4 is one by one. Make it easy to separate. The holding film material 31 is specifically a product name “Riva Alpha” manufactured by Nitto Denko Corporation. The holding film material 31 is a film material in which the substrate film 31a has light transmittance such as transparency when a light irradiation decreasing type adhesive is used for the adhesive layer 31b.

  The holding film material 31 constitutes a peeling jig 35 by holding the outer peripheral portion by the folder member 34 shown in FIG. For example, a metal plate having a thickness of about 0.5 mm to 2 mm is used for the folder member 34, and an opening 34 a having a diameter slightly smaller than the outer diameter of the holding film material 31 is formed. As shown in FIG. 6, the outer peripheral portion of the holding film material 31 combined so as to close the opening 34 a is joined to the folder member 34 over the entire circumference to constitute a peeling jig 35.

  The peeling jig 35 allows each thin film multilayer circuit body 4 formed with a small thickness to be accurately peeled and easily handled in the separation step s-12 to the thin film multilayer circuit body separation step s-14. Like that. Note that the peeling jig 35 may be formed by further bonding a reinforcing film material to the holding film material 31. As the reinforcing film material, for example, a dicing tape or the like used for surface polishing or dicing of the circuit board may be used.

  The release layer forming step s-1 is excellent in heat resistance and chemical resistance, can form a highly accurate flat surface, has good depth of focus during lithographic processing, and has good contact alignment characteristics during masking. This is a step of forming a release layer 3 over the entire surface of the main surface 2a of a dummy substrate 2 made of a silicon substrate or glass substrate of a certain insulating material. In detail, the peeling layer forming step s-1 includes a step of forming the first metal film 36 as shown in FIG. 7, a step of forming the second metal film 37 on the first metal film 36, A step of forming an insulating protective resin film 38 covering the two metal film 37.

  In the formation process of the first metal film 36, a metal film such as titanium, titanium nitride, or chromium having a uniform film thickness of about 200 to 500 mm is formed by, for example, sputtering or chemical vapor deposition (CVD). Form. The first metal film 36 has a function of improving adhesion with the dummy substrate 2. In the formation process of the second metal film 37, a metal film such as copper or aluminum having a uniform film thickness of about 1000 to 3000 mm is formed in the same manner. The second metal film 37 has a function of peeling the thin film laminated circuit body 4 from the dummy substrate 2 by being dissolved by the peeling solution.

  In the insulating resin film forming step, for example, an insulating synthetic resin material such as polyimide resin can be applied on the second metal film 37, for example, to maintain uniformity and thickness controllability, such as spin coating, curtain coating, roll A protective resin film 38 having a thickness of about 1 μm to 3 μm is formed by a coating method or a dip coating method. The protective resin film 38 functions as a protective film that protects the thin film multilayer circuit body 4 from a chemical solution in a peeling step s-12 described later. As described above, the release layer 3 includes the first metal film 36, the second metal film 37, and the protective resin film 38. In each of the drawings after FIG. Only.

  The mounting connection land forming step s-2 is a step of forming a mounting connection land 24 provided on the uppermost layer in the thin film laminated circuit body 4 for directly mounting electronic components such as filters and chip components. The mounting connection land forming step s-2 includes a base metal film forming step, a terminal metal film forming step, a patterning step, an etching step, a photoresist removing step, and the like.

  In the mounting connection land forming step s-2, a base metal film such as titanium for improving adhesion is formed on the release layer 3 over the entire surface with a uniform film thickness of about 200 to 3000 mm by, for example, sputtering. . In the mounting connection land forming step s-2, a metal film having good electrical characteristics as a terminal metal layer, such as a gold layer, is formed on the entire surface with a uniform film thickness of about 200 to 3000 mm by sputtering or the like. Form over.

  In the mounting connection land forming step s-2, a photolithography process is performed after a photoresist layer is further formed on the terminal metal layer. In the photolithographic process, the gold layer is exposed by performing exposure and development processes in a state where the corresponding portion of the mounting connection land 24 is masked, and the exposed gold layer is etched using an etching solution such as a potassium iodide solution. Do. In the photolithography process, a titanium layer exposed by etching gold is etched using an etching solution such as a diluted hydrofluoric acid solution. In the mounting connection land forming step s-2, the photoresist layer remaining on the gold layer is removed, for example, by performing a process of immersing in a photoresist stripping solution or an oxygen plasma process, and stripping as shown in FIG. A large number of mounting connection lands 24 are formed on the layer 3 with a predetermined pattern.

  In the first insulating layer formation step s-3, as shown in FIG. 9, the first insulating layer 15 is formed over the entire surface of the release layer 3 so as to cover the mounting connection lands 24. In the layer 15, first via holes 39 and first separation slits 40 constituting a large number of first vias 28 described later are formed. The first insulating layer forming step s-3 includes a step of forming the first insulating layer 15 on the release layer 3, and a patterning for forming the first via hole 39 and the first separation slit 40 in the first insulating layer 15. Process.

  In the first insulating layer forming step s-3, the first insulating layer 15 is made of a dielectric insulating material such as polyimide or benzocyclo, which has a low dielectric constant, low loss, excellent high frequency characteristics, and excellent heat resistance and chemical resistance. Using butene (BCB), polynorbornene (PNB), liquid crystal polymer (LCP), epoxy resin, or acrylic resin, the whole is formed on the release layer 3 by a spin coating method or the like so as to have a uniform film thickness. . The first insulating layer 15 is formed to have a film thickness of 5 μm to 30 μm in order to ensure high frequency characteristics of a capacitor element 21, a register element 22, or a thin film inductor element 23 described later.

  In the first insulating layer forming step s-3, when a photosensitive dielectric insulating material is used as the above-described dielectric insulating material, a photolithography process is performed on the dielectric insulating film formed on the release layer 3 to each of the predetermined values. A large number of first via holes 39 and first separation slits 40 are formed at the locations. In the first insulating layer forming step s-3, when a non-photosensitive dielectric insulating material is used as the dielectric insulating material, a reactive ion etching process or a dry etching process such as laser irradiation is performed on the dielectric insulating film. A large number of first via holes 39 and first separation slits 40 are formed at predetermined positions.

  In the first insulating layer formation step s-3, the first separation slit 40 forms the first insulating layer 15 on the dummy substrate 2 through the steps described later, and the respective formation regions of the multiple thin film multilayer circuit bodies 4 For example, it is formed in a grid pattern. The first separation slit 40 has a function of separating and peeling each thin film multilayer circuit body 4 manufactured on the dummy substrate 2 one by one in a peeling step s-12 to be described later, and allows the peeling solution 59 to enter the peeling layer 3. Thus, it functions as an intrusion passage for the stripping solution 59 that enables an efficient and highly accurate stripping operation. The first separation slit 40 is preferably formed with a larger opening width if the function of the infiltration passage of the stripping solution 59 is prioritized, but the manufacturing efficiency of each thin film multilayer circuit body 4 decreases as the first separation slit 40 increases. Therefore, the first separation slit 40 is preferably formed with an opening width of, for example, about 10 μm to 200 μm.

  The first wiring layer forming step s-4 is a step of forming the first wiring layer 18 and the first via 28 having a predetermined pattern on the first insulating layer 15. Specifically, the first wiring layer forming step s-4 includes a seed metal layer forming step of covering the first insulating layer 15, the first via hole 39, and the first slit 40 to form a seed metal layer 41 over the entire surface. A plating resist layer forming step for forming a plating resist layer 42 having a predetermined pattern on the seed metal layer 41, an electrolytic plating step for performing electrolytic copper plating, a step for removing unnecessary plating resist, and an unnecessary seed metal layer And the like.

  The seed metal layer forming step includes, for example, a step of forming a base metal film such as titanium, titanium nitride, or chromium having a uniform film thickness of about 200 to 3000 mm by a sputtering method or a chemical vapor deposition method, and a thickness of about 1000 to 3000 mm. A seed metal layer 41 having a two-layer structure shown in FIG. 10 is formed. In the seed metal layer 41, the base metal film functions to improve the adhesion with the first insulating layer 15, and the copper layer functions well as a seed metal in an electrolytic copper plating process described later.

  The seed metal layer 41 is preferably formed as thin as possible so as to have a thickness sufficient to exhibit the seed metal action in the electrolytic copper plating process because unnecessary portions are removed after the electrolytic copper plating process. On the other hand, the seed metal layer 41 is also formed on the uneven portion with respect to the uneven first insulating layer 15 by forming the first via holes 39 and the first separation slits 40 described above. It is preferable that the film be formed with a film thickness that retains electrical characteristics. Therefore, the seed metal layer 41 is formed on the first insulating layer 15 with a film thickness of about 5 μm.

  The plating resist layer forming step includes a step of forming a plating resist layer having a uniform film thickness over the entire surface by, for example, a spin coating method on the seed metal layer 41, and a step of subjecting the plating resist layer to a photolithography process. The plating resist layer 42 having a predetermined pattern is formed. As shown in FIG. 10, the plating resist layer 42 is an opening in which a corresponding portion 42 a of the wiring pattern of the first wiring layer 18 and a corresponding portion 42 b of the first via hole 39 are portions where an electrolytic copper plating layer to be described later is formed. Formed as. The plating resist layer 42 is formed by closing the opening portions of the first separation slit 40.

  In the electrolytic plating process, the seed metal layer 41 is energized through the opening of the plating resist layer 42 to perform electrolytic copper plating, thereby selectively forming the copper plating layer 43 in the opening as shown in FIG. It is. The copper plating layer 43 is formed to have a thickness sufficient for the first wiring layer 18 to maintain sufficient electrical characteristics, for example, about 5 μm thick. The copper plating layer 43 is also formed in the corresponding portion 42 b of each first via hole 39, so that the mounting connection land 24 and the first insulating layer 15 that face outward through the first via hole 39 are formed. A first via 28 for interlayer connection is formed.

  The plating resist removing step is a step of removing the unnecessary plating resist layer 42 by immersing it in a resist stripping solution such as acetone after the above-described electrolytic copper plating treatment. In the plating resist removal step, the unnecessary plating resist layer 42 is removed by a kind of wet etching method in which the resist stripping solution dissolves the plating resist. In the plating resist removing step, unnecessary plating resist may be removed by, for example, a dry etching method using oxygen plasma treatment or the like.

  The seed metal layer removal step is a step of removing unnecessary portions of the seed metal layer 41 formed on the first insulating layer 15. Since the seed metal layer 41 is formed over the entire surface of the first insulating layer 15 as described above, the first wiring layer 18 is formed in the region where the copper plating layer 43 is not formed by removing the plating resist layer 42. Unnecessary parts are exposed to constitute The unnecessary seed metal layer 41 is removed by applying the wet etching process so that the copper plating layer 43 acts as a mask. In the wet etching process, for example, the copper layer is removed with a mixed solution of nitric acid, acetic acid and sulfuric acid, and the titanium layer is removed with a dilute hydrofluoric acid aqueous solution.

  In the first wiring layer forming step s-4, after each of the steps described above, a predetermined wiring pattern is provided on the first insulating layer 15 as shown in FIG. The first wiring layer 18 having a large number of first vias 28 to be performed is formed.

  In the second insulating layer forming step s-5, the same dielectric insulating material as that used in the first insulating layer forming step s-3 is used, and the second insulating layer 16 is formed on the first wiring layer 18 through almost the same steps. Or a plurality of second via holes 44 and second separation slits 45 constituting the second via 29. The second insulating layer forming step s-5 includes a step of forming the second insulating layer 16 having a predetermined thickness on the first wiring layer 18 by, for example, a spin coating method, and the second insulating layer 16 described above. A step of forming a plurality of second via holes 44 and second separation slits 45 constituting the second via 29 by the same method as the method of forming the first via hole 39 and the first separation slit 40.

  Each second via hole 44 allows a predetermined portion of the wiring pattern of the first wiring layer 18 to face outward from the second insulating layer 16. Each second via hole 44 is formed with a diameter of 10 um to 50 um by, for example, a reactive ion etching method or a dry etching method using laser irradiation when the second insulating layer 16 is formed with a thickness of 10 um to 30 um. Is possible. Each second separation slit 45 is formed in a grid pattern so as to communicate with each first separation slit 40 on the first insulating layer 15 side. As shown in FIG. 13, each second separation slit 45 is formed with a groove width slightly larger than the groove width of the first separation slit 40.

  A second wiring layer forming step s-7, which will be described later, is performed on the second insulating layer 16 to form a second wiring layer 19, and a passive element built in the second wiring layer 19 is formed. Element formation process s-6 for forming 21-23 is performed. For example, the element forming step s-6 includes a receiving electrode forming step of forming the receiving electrode 46 of each capacitor element 21 and the receiving electrode 47 of each register element 22 as shown in FIG. 14, and each capacitor as shown in FIG. It includes a step of forming a dielectric 48 on the receiving electrode 46 of the element 21 and a resistor 49 on the receiving electrode 47 of each register element 22.

  In the receiving electrode forming step, an equivalent process is performed using the same material as the forming step of the first wiring layer 18 described above, so that a predetermined pattern is formed on the second insulating layer 16 as shown in FIG. Thus, receiving electrodes 46 and 47 are formed. That is, in the receiving electrode forming step, for example, a titanium layer and a copper layer are formed on the first wiring layer 18 by a sputtering method, a photoresist layer is formed by a spin coating method or the like, and a predetermined process is performed by a photolithography process. A patterning step and a step of etching the titanium layer and the copper layer into a predetermined pattern by a wet etching method.

  In the receiving electrode formation step, the titanium layer is formed with a thickness of 500 to 2000 mm and the copper layer is formed with a thickness of about 1000 to 3000 mm, as in the formation process of the seed metal layer 41 described above. In the receiving electrode forming step, the copper layer is removed by a wet etching step with a mixed solution of nitric acid, acetic acid and sulfuric acid, and the titanium layer is removed with a dilute hydrofluoric acid aqueous solution. In the receiving electrode forming step, similarly to the above-described step of removing the plating resist layer 42, an unnecessary photoresist layer is immersed in, for example, acetone or a resist stripping solution and dissolved in a wet etching method or tetrafluoromethane and oxygen plasma. It is removed by a dry etching method by treatment or the like.

  In the element formation step s-6, for example, by forming the dielectric 48 and the resistor 49 in the same layer using the same material of tantalum or tantalum nitride, it is possible to form the same in the same step. Reduction. In the resistor forming step, after the receiving electrode 47 is formed, a resistor layer such as tantalum, tantalum nitride, or nickel chrome is formed by sputtering or the like, and a photoresist is formed by spin coating or the like. A resistor 49 straddling between the pair of receiving electrodes 47 as shown in FIG. 15 is formed through a patterning process by photolithography and a process of removing unnecessary resistor material films by an etching method or the like. The resistor 49 is formed with a film thickness of about 2000 mm.

  The dielectric forming step is the same as the resistor forming step, the tantalum or tantalum nitride film forming step, and the step of forming a photoresist by spin coating or the like and patterning it by photolithography. Then, an unnecessary tantalum or tantalum nitride film is removed by an etching method or the like, and a dielectric 48 is formed on the receiving electrode 46 as shown in FIG.

  In the anodic oxidation step described above, an electric field of about 100 V to 200 V is applied for about 10 to 60 minutes so that the resistor material film becomes an anode in an electrolytic solution such as ammonium borate. In the anodic oxidation step, tantalum or tantalum nitride is oxidized to form a tantalum oxide layer, whereby the dielectric 48 is obtained. The capacitor element 21 is formed with an upper electrode 50 facing the receiving electrode 46 via a dielectric 48 in a third wiring layer forming step s-9 described later.

  In the second wiring layer forming step s-7, the second wiring layer 19 having a predetermined wiring pattern is formed on the second insulating layer 16, the capacitor element 21 or the register element 22 formed on the second insulating layer 16. Form. The second wiring layer forming step s-7 has substantially the same steps as the first wiring layer forming step s-4 described above, and the seed metal layer is spread over the entire surface of the second insulating layer 16 by the sputtering method. And a step of forming a plating resist layer having a predetermined thickness on the seed metal layer.

  The second wiring layer forming step s-7 includes a step of performing a predetermined patterning for opening a portion corresponding to a wiring pattern or the like by removing the unnecessary plating resist layer by performing a photolithography process on the plating resist layer; And a step of forming a copper plating layer having a predetermined thickness in the opening from which the plating resist layer is removed by a patterning step after performing an electrolytic copper plating treatment. The second wiring layer forming step s-7 is shown in FIG. 16 through a process of removing an unnecessary plating resist by performing an appropriate etching process and a process of removing an unnecessary seed metal layer by performing a wet etching process. Thus, the second wiring layer 19 is formed.

  In the second wiring layer forming step s-7, a copper plating layer is formed in the second via hole 44 formed in the second insulating layer 16 by electrolytic copper plating, and the second wiring layer 19 and the first wiring layer 18 are formed. A second via 29 is also formed at the same time as appropriate. In the second wiring layer forming step s-7, when the wiring pattern of the second wiring layer 19 is formed, the spiral inductor element 23 is also formed simultaneously as shown in FIG. In the second wiring layer forming step s-7, each wiring pattern of the second wiring layer 19 retains electrical characteristics and reliably connects the first wiring layer 18 with the second via 29. Similarly, the electrolytic copper plating process is controlled so as to be formed with a thickness of about 5 μm. The inductor element 23 is also formed on the first wiring layer 18 as necessary.

  In the third insulating layer forming step s-8, the third insulating layer 17 is formed on the second wiring layer 19, and a third via hole 51 that configures the third via 30 at an appropriate position of the third insulating layer 17 is formed. And the third separation slit 52 and the opening 53 that allows the dielectric 48 of the capacitor element 21 to face outward. The third insulating layer forming step s-8 is also the same as that shown in FIG. 17 using the same dielectric insulating material as the first insulating layer forming step s-3 and the second insulating layer forming step s-5. Three insulating layers 17 are formed. The third insulating layer forming step s-8 includes a step of forming the third insulating layer 16 having a uniform thickness over the entire surface of the second wiring layer 19 by, for example, a spin coating method, and the third insulating layer 16 The step of forming a large number of third via holes 51, third separation slits 52, and openings 53 by, for example, a reactive ion etching method or a dry etching method by laser irradiation.

  Each third via hole 51 is formed in the third insulating layer 17 with a predetermined wiring pattern of the second wiring layer 19 facing outward. Each of the third separation slits 52 is formed in a grid pattern so as to communicate with the opposing second separation slit 45 and the first separation slit 40, and each groove width has a second separation slit as shown in FIG. It is formed slightly larger than the groove width of 45. The opening 53 is formed in the third insulating layer 17 with the dielectric 48 of each capacitor element 21 formed in the second wiring layer 17 described above facing outward. In addition, you may make it form in the 3rd insulating layer 16 the opening part which makes the resistor 49 of the resistor element 22 face outward as needed.

  The third wiring layer forming step s-9 is a step of forming the third wiring layer 20 on the third insulating layer 17. The third wiring layer forming step s-9 also includes substantially the same steps as the first wiring layer forming step s-4 and the second wiring layer forming step s-7 described above, and the third insulating layer 17 is formed by sputtering. The method includes a step of forming a seed metal layer over the entire surface and a step of forming a plating resist layer having a predetermined thickness on the seed metal layer. The third wiring layer forming step s-9 is a step of performing a predetermined patterning for opening a portion corresponding to a wiring pattern or the like by performing a photolithographic process on the plating resist layer to remove an unnecessary plating resist layer; And a step of forming a copper plating layer having a predetermined thickness in the opening from which the plating resist layer is removed by a patterning step after performing an electrolytic copper plating treatment. The third wiring layer forming step s-9 is performed through a process of removing an unnecessary plating resist by performing an appropriate etching process, a process of removing an unnecessary seed metal layer by performing a wet etching process, and the like. The third wiring layer 20 shown is formed.

  In the third wiring layer forming step s-9, a copper plating layer is formed in each third via hole 51 formed in the third insulating layer 17 by electrolytic copper plating, and the third wiring layer 20 and the second wiring layer 19 are formed. Are also formed at the same time as appropriate. In the third wiring layer forming step s-9, a copper plating layer is formed in each opening 53 formed in the third insulating layer 17 by electrolytic copper plating, and the third wiring layer is formed on the dielectric 48 of each capacitor element 21. An upper electrode 50 appropriately connected to the wiring pattern of the wiring layer 20 and a third via 30 integrated with the upper electrode 50 are also formed. Each capacitor element 21 has a predetermined capacitance characteristic by forming the upper electrode 50 having an arbitrary shape by forming the opening 53 having an appropriate opening shape in the third insulating layer forming step s-8. It is possible to have.

  In the third wiring layer forming step s-9, when the wiring pattern of the second wiring layer 19 is formed, the spiral inductor element 23 may be formed at the same time as shown in FIG. In the third wiring layer forming step s-9, the capacitor element 21 and the register element 22 can be formed in the third wiring layer 20 by performing the element forming step s-6 in advance. It is. In the manufacturing process of the high-frequency circuit module body 1, the above-described insulating layer forming process and wiring layer forming process or element forming process are repeated to manufacture the thin film laminated circuit body 4 having a multilayer wiring.

  In the solder resist layer / external electrode formation step s-10, the solder resist layer 25 constituting the outermost layer portion of the thin film multilayer circuit body 4 and the external electrode 26 are formed on the third wiring layer 20 described above. The solder resist layer / external electrode forming step s-10 includes a step of forming the solder resist layer 25 and a step of patterning the solder resist layer 25 to form a large number of openings 25a and fourth separation slits 54. And a step of performing an electrode forming process on each terminal pattern 20a formed in the wiring pattern of the third wiring layer 20 exposed outward through the opening 25a.

  The solder resist layer forming step is performed by applying a solder resist over the entire surface of the third insulating layer 17 and the third wiring layer 20 by an appropriate printing method such as a spin coat method or a roll coat method, for example, as shown in FIG. The solder resist layer 25 shown is formed. The solder resist layer 25 constitutes the outermost layer portion of the thin film multilayer circuit body 4 and mechanically protects the third wiring layer 20 and has a function of maintaining electrical insulation. Therefore, the solder resist layer 25 has a predetermined thickness. It is formed.

  In the patterning step, a large number of openings 25a and fourth separation slits 54 are formed by performing, for example, a photolithography process on the solder resist layer 25. Each opening 25a allows each terminal pattern 20a formed in the third wiring layer 20 to face outward. The fourth separation slit 54 is formed in a grid pattern so as to communicate with the third separation slit 52, the second separation slit 45, and the first separation slit 40 facing each other, as shown in FIG. The groove width is slightly larger than the groove width of the third separation slit 52.

  In the electrode forming step, the external electrode 26 is formed as shown in FIG. 20 by imparting rust prevention characteristics and solderability to each terminal pattern 20a exposed to the outside through each opening 25a. Specifically, the electrode forming step is performed by performing surface treatment such as electrolytic copper plating or electroless copper plating, so that the terminal pattern of the third wiring layer 20 exposed outward through each opening 25a. A gold-nickel layer that improves solderability with respect to 20a is formed. In addition, about the surface treatment which forms the external electrode 26, the process which forms a solder coat layer, a water-soluble heat-resistant flux layer, etc. in each terminal pattern 20a may be sufficient, for example.

  In the manufacturing process of the high-frequency circuit module body 1, a large number of thin-film laminated circuit bodies 4 having a multilayer structure are manufactured on the main surface 2 a of the dummy substrate 2 through the release layer 3 through the above-described processes. In the manufacturing process of the high-frequency circuit module body 1, each thin film laminated circuit body 4 is a multifunctional thin film laminated thinned with high precision by thin film technology using a dummy substrate 2 having a flattened main surface 2a. The circuit body 4 can be manufactured. In the manufacturing process of the high-frequency circuit module body 1, each thin film multilayer circuit body 4 can inspect the operation characteristics and the like on the dummy substrate 2 by using the external electrode 26 as an inspection terminal.

  In the manufacturing process of the high-frequency circuit module body 1, various inspections can be performed in the previous process of mounting each thin film laminated circuit body 4 on the base substrate 5, so that only non-defective products are supplied to the next process. This makes it possible to reduce man-hours and material costs. In the manufacturing process of the high-frequency circuit module body 1, various inspections are performed such as whether each wiring layer or the like is normally formed for each thin film laminated circuit body 4 and whether there is a disconnection portion.

  In the manufacturing process of the high-frequency circuit module body 1, in order to efficiently peel each thin film laminated circuit body 4 from the dummy substrate 2, a peeling layer partial removal step s-11 for partially removing the peeling layer 3, Holding film material bonding step s-12 for bonding the above-described holding film material 31 to the thin film laminated circuit body 4, a peeling step s-13 for peeling each thin film laminated circuit body 4 from the dummy substrate 2, and each thin film A thin film laminated circuit body separation step s-14 for separating the laminated circuit bodies 4 from the holding film material 31 one by one is performed.

  As described above, each thin film multilayer circuit body 4 includes a first separation slit 40 that communicates with the first insulating layer 15, the second insulating layer 16, the third insulating layer 17, and the solder resist layer 25 in the height direction. The second separation slit 45, the third separation slit 52, and the fourth separation slit 54 are formed. In each thin film laminated circuit body 4, a release layer 3 is formed over the entire main surface 2 a of the dummy substrate 2. No separation slit is formed in advance in the release layer 3 so that chemicals or the like enter when the thin film laminated circuit body 4 is manufactured and the release operation or thickness change does not occur.

  The peeling layer partial removing step s-11 is a step of forming, in the peeling layer 3, a large number of fifth separation slits 55 that communicate with each separation slit formed in the upper layer as shown in FIG. In the peeling layer partial removing step s-11, the fifth separation slit 55 is formed in the peeling layer 3 by a dry etching method such as oxygen plasma treatment or laser irradiation. In the peeling layer portion removing step s-11, plasma or laser is introduced from the opening of the fourth separation slit 54 formed in the solder resist layer 25, reaches the peeling layer 3 facing each other through each separation slit, and protection thereof. Only the resin film 38 is partially etched.

  In the manufacturing process of the high-frequency circuit module body 1, a plurality of thin film laminated circuit bodies 4 divided by a large number of separation slits are manufactured on the main surface 2a of the dummy substrate 2 through the above-described steps, as shown in FIG. A first intermediate 56 is produced. As described above, the first intermediate 56 includes the separation slits 40, 45, 52, 54, 55 that communicate with the insulating layers 15, 16, 17 and the solder resist layer 25 and the release layer 3 in the height direction. These separation slits constitute a separation slit 57 as a whole. The separation slit 57 is configured as a tapered separation slit whose opening diameter gradually decreases in the height direction from the configuration of each separation slit 40, 45, 52, 54, 55 of each layer described above.

  In the holding film material laminating step s-12, as described above, the peeling jig 35 composed of the holding film material 31 and the folder member 34 is used. As shown in FIG. 22, the peeling jig 35 is configured so that a large number of slits 32 formed in the holding film material 31 are aligned with the opposing separation slits 57 on the thin film multilayer circuit body 4 side with respect to the first intermediate body 56. The folder member 34 is positioned by appropriate positioning means. As for the peeling jig | tool 35, the holding | maintenance film material 31 joins the base film 31a on the solder resist layer 25 of each thin film laminated circuit body 4 via the adhesive bond layer 31b.

  Since the peeling jig 35 has a structure in which the outer peripheral portion of the holding film material 31 is held by the rigid folder member 34 as described above, the holding film material 31 is attached to each thin film multilayer circuit body 4 via the folder member 34. It is possible to strongly press the upper portion and firmly bond to the first intermediate body 56 by the adhesive layer 31b. The peeling jig 35 is designed to improve the handling property of the first intermediate body 56 on which a thin film laminated circuit body 4 to be described later is subjected to a peeling process. Since the holding film material 31 is flexible, the peeling jig 35 is familiar to the solder resist layer 25 of each thin film laminated circuit body 4 even if there are some irregularities, and is bonded over the entire surface. Like that.

  In the peeling step s-13, as shown in FIG. 23, the peeling jig 35 holding the first intermediate body 56 made of the dummy substrate 2 on which a large number of thin film multilayer circuit bodies 4 are manufactured on the main surface 2a is used as a peeling solution. In this step, the thin film laminated circuit body 4 is peeled off from the dummy substrate 2 by the peeling jig 35 via the peeling layer 3. The peeling jig 35 holds the folder member 34 by appropriate handling, so that the first intermediate body 56 is put into the peeling tank 58 safely and efficiently.

  In the peeling step s-13, when the first metal film 36 is a copper film, an acidic solution such as a diluted hydrochloric acid solution or a diluted nitric acid solution is used as the peeling solution 59. In the peeling step s-13, when the first metal film 36 is an aluminum film, an alkaline solution such as a sodium hydroxide solution is used as the peeling solution 59. The stripping solution 59 penetrates into the stripping layer 3, and each thin film laminated circuit body held by the dummy substrate 2 and the stripping jig 35 from the interface between the second metal film 37 and the protective resin film 38 as shown in FIG. 4 is separated.

  As described above, the first intermediate body 56 is formed with a large number of separation slits 57 that reach the release layer 3 from the uppermost solder resist layer 25 so as to divide each thin film multilayer circuit body 4. The holding film material 31 is joined to the first intermediate body 56 by aligning the slits 32 with respect to the separation slits 57. Accordingly, the release solution 59 enters the first intermediate body 56 into each separation slit 57 that separates each thin film laminated circuit body 4 through each slit 32 of the holding film material 31 and reaches the release layer 3. The first intermediate body 56 is not only the outer peripheral portion but also the separation slit 57 having a taper, so that the stripping solution 59 permeates from the inner region to the entire thin film laminated circuit from the dummy substrate 2. The body 4 is peeled off efficiently.

  The first intermediate 56 is subjected to a peeling operation in which the thin film multilayer circuit body 4 is peeled off from the dummy substrate 2 in a state where the penetration of the peeling solution 59 has progressed to some extent in the peeling layer 58. The first intermediate body 56 has a peeling treatment in which each thin film laminated circuit body 4 is bonded to the flexible holding film material 31 as described above and the outer peripheral portion of the holding film material 31 is held by the folder member 34. It is held by the tool 35. Therefore, the first intermediate body 56 is peeled off through the folder member 34, and at this time, the holding film material 31 is peeled off from the dummy substrate 2 through the release layer 3 of each thin film multilayer circuit body 4. By deforming according to the deformed state, even if the bonding strength of each thin film multilayer circuit body 4 with respect to the dummy substrate 2 varies, it is possible to perform the easy peeling, and further the penetration of the peeling solution 59 is promoted. It becomes like this.

  In the peeling step s-13, the first intermediate body 56 comes to be peeled off efficiently and cleanly in a state where each thin film laminated circuit body 4 is held by the peeling jig 35 with respect to the dummy substrate 2. . Each thin film multilayer circuit body 4 is held by the peeling jig 35 in a state of being individually divided through the separation slit 57 without performing a dicing process or the like.

  In the manufacturing process of the high-frequency circuit module body 1, the thin film multilayer circuit bodies 4 are all peeled from the dummy substrate 2 to obtain the second intermediate body 60 shown in FIG. 25. In the second intermediate 60, the protective resin layer 38 of the release layer 3 remains in a thin state on the surface of the first insulating layer 15 as each thin film multilayer circuit body 4 is peeled from the dummy substrate 2. The second intermediate 60 is subjected to, for example, oxygen plasma treatment, whereby the remaining protective resin layer 38 is removed and the first insulating layer 15 is exposed over the entire surface. Further, in the second intermediate body 60, the connection lands 24 are also exposed in the plane of the first insulating layer 15 of each thin film multilayer circuit body 4.

  In each thin film laminated circuit body 4, since each connection land 24 is composed of two layers of a titanium layer and a gold layer as described above, the titanium layer is exposed by removing the protective resin layer 38. Therefore, in the manufacturing process of the high-frequency circuit module body 1, the second intermediate 60 is subjected to an etching process using a dilute hydrofluoric acid solution to remove the titanium layer to expose the gold layer, thereby forming a terminal.

  In the thin film laminated circuit body separation step s-14, the second intermediate 60 is subjected to, for example, ultraviolet irradiation treatment or heat treatment, so that a large number of pieces are attached to the holding film material 31 of the peeling jig 35 and held. The thin film laminated circuit bodies 4A to 4N are individually separated through the separation slits 57 as shown in FIG. In the thin film laminated circuit body separation step s-14, when a light irradiation reducing adhesive is used as the adhesive layer 31b of the holding film material 31, a process of irradiating ultraviolet rays of about 500 mJ to 3000 mJ is performed. Further, in the thin film laminated circuit body separation step s-14, when a heat-decreasing adhesive is used as the adhesive layer 31b of the holding film material 31, it is heated to about 100 ° C. to 150 ° C. by an oven or a hot plate. Perform the process.

  Each of the thin film laminated circuit bodies 4A to 4N is peeled off from the holding film material 31 due to a decrease in the adhesive force of the adhesive layer 31b by being subjected to the above-described ultraviolet irradiation treatment or heat treatment, and the separation slits 57 are separated. Are separated individually. Even if the adhesive force of the adhesive layer 31b varies when the thin film laminated circuit bodies 4A to 4N are peeled off from the holding film material 31, each thin film laminated circuit body 4A to 4N is deformed by the deformation operation of the flexible holding film material 31. The exfoliation operation is performed with high accuracy in such a manner that a sudden peeling force on the body 4 is not applied.

  In the thin film multilayer circuit body separation step s-14, since a large number of thin film multilayer circuit bodies 4A to 4N are separated from each other by, for example, dicing processing on the dummy substrate 2, the separation is efficient. Will be done. The dummy substrate 2 has a high-precision flattening process on the main surface 2a, and the main surface 2a is scratched by the dicing process, so that repair or the like becomes necessary or cannot be reused. However, this inconvenience is solved. Note that the thin film laminated circuit body separation step s-14 may be performed immediately before a mounting step s-16 for the base substrate 5 described later, for example.

  In the manufacturing process of the high-frequency circuit module body 1, a base substrate 5 on which the thin film laminated circuit body 4 manufactured through the above-described processes is mounted is supplied. The base substrate 5 is formed by a well-known multilayer wiring substrate forming process, and thus the details thereof are omitted. However, a multilayer wiring layer is formed on an organic multilayer substrate, an inorganic substrate, or a composite substrate. In the manufacturing process of the high-frequency circuit module body 1, a solder bump forming step s-15 is performed in order to mount the thin film laminated circuit body 4 on the base substrate 5. Solder bump formation process s-15 has a solder printing process and a reflow process.

  As shown in FIG. 27, the solder printing step is a step of squeezing the solder paste 62 with the squeegee 63 after the metal mask 61 is placed in close contact with the uppermost layer 5 a of the base substrate 5, specifically, the solder resist layer 10. It is. In the solder printing process, a metal mask 61 in which a large number of openings 64 are formed corresponding to the mounting terminals 11 facing outward from the openings 10a formed in the solder resist layer 10 of the base substrate 5. Is used. In the solder printing process, the solder paste 62 is supplied onto the main surface of the metal mask 61 and the squeegee 63 is squeezed along the main surface of the metal mask 61 as indicated by the arrows in the figure. In the solder printing process, the solder paste 62 is thereby filled in the opening 64 to form a solder paste layer corresponding to the thickness of the metal mask 61 on the mounting terminal 11.

  In the reflow process, the solder paste 62 printed on each mounting terminal 11 is melted and solidified by performing a reflow process on the base substrate 5 subjected to the solder printing. As a result, the solder paste 62 is solidified in a substantially hemispherical shape from the opening 10a of the solder resist layer 10 as shown in FIG.

  Note that the solder bump forming step s-15 is not limited to the above-described steps, and the solder bumps 12 can be formed by, for example, a plating method. Further, in the solder bump forming step s-15, for example, the solder bumps 12 positioned with higher accuracy can be formed by using a vacuum printer or a press-fitting printer.

  The thin film multilayer circuit body mounting step s-16 includes an underfill layer forming step of applying an underfill material on the solder resist layer 10 of the base substrate 5 to form the underfill layer 27, and the underfill layer 27. A plurality of thin film laminated circuit bodies 4 </ b> A to 4 </ b> N are mounted on the base substrate 5. The underfill layer 27 is formed by applying an epoxy resin containing a flux component to a peripheral portion of the solder bump 12 formed on each mounting terminal 11 as shown in FIG. The underfill layer 27 temporarily holds the thin film laminated circuit body 4 that is positioned and placed on the base substrate 5.

  In the thin film multilayer circuit body mounting step s-16, the thin film multilayer circuit body 4 is aligned with the corresponding solder bumps 12 and the respective mounting connection lands 24 by using appropriate positioning mounting means with respect to the base substrate 5. Are combined. The thin film laminated circuit body 4 is temporarily held on the base substrate 5 by the underfill layer 27 as described above. In the thin film multilayer circuit body mounting step s-16, the thin film multilayer circuit body 4 is bonded and fixed to the base substrate 5 using, for example, a thermocompression bonding apparatus (not shown).

  In the thin film multilayer circuit body mounting step s-16, the thermocompression bonding apparatus melts the solder bumps 12 by heating the thin film multilayer circuit body 4 against the base substrate 5 while heating to about 240 ° C. to 260 ° C. Resolidify. In the thin film multilayer circuit body mounting step s-16, as shown in FIG. 30, each mounting terminal 11 on the base substrate 5 side and each mounting connection land 24 on the thin film multilayer circuit body 4 side are electrically connected by solder that is melted and solidified. The high-frequency circuit module body 1 in which the thin film laminated circuit bodies 4A to 4N are mounted on the base substrate 5 is manufactured by being mechanically and mechanically coupled.

  In the high-frequency circuit module body 1, an underfill layer 27 that is solidified by heating firmly fixes the base substrate 5 and each thin film laminated circuit body 4. In the high-frequency circuit module body 1, good soldering is performed between each mounting terminal 11 and each mounting connection land 24 by the flux component of the underfill layer 27. In the high-frequency circuit module body 1, each mounting connection land 24 is formed of a gold layer having good solder wettability and rust prevention, so that the solder characteristics are improved and the reliability is ensured. Is done.

  Note that the thin film multilayer circuit body mounting step s-16 is not limited to the mounting method using the above-described thermocompression bonding apparatus, but is used, for example, as a semiconductor chip mounting method, such as reflow soldering, flip chip bonding, TAB ( The thin film laminated circuit body 4 may be mounted on the base substrate 5 by a face-down mounting method such as a tape automated bonding method or a beam lead bonding method.

  A high-performance high-frequency circuit module body 100 shown in FIG. 31 uses the above-described high-frequency circuit module body 1 as a base body, and a plurality of thin film laminated circuit bodies 4T1, 4T2, surface mount electronic components, This is a high-frequency circuit module body in which a thin film laminated circuit body 4 is mounted on an inner layer and an outer layer by mounting a relatively large mounting component 101 such as an LSI, thereby achieving high functionality. The high-performance high-frequency circuit module body 100 is intended to improve noise resistance characteristics by providing, for example, a thin film laminated circuit body 4 that constitutes a filter circuit, a matching circuit, and the like in an insulating layer, and constitutes a drive circuit such as a mounting component 101. The thin film laminated circuit bodies 4T1 and 4T2 to be mounted are mounted at close positions so that the line loss is reduced.

  The manufacturing process of the high-functional high-frequency circuit module body 100 is performed subsequent to the manufacturing process of the high-frequency circuit module body 1 described above, and an insulating layer forming step s for forming the insulating layer 102 on the base substrate 5 as shown in FIG. -20, a via formation step s-21 for forming the via 103 for interlayer connection in the insulating layer 102, a wiring layer forming step s-22 for forming the wiring layer 104 on the insulating layer 102, and the wiring layer 104 A solder resist layer forming step s-23 for forming a solder resist layer 105 to be coated. Furthermore, the manufacturing process of the high-performance high-frequency circuit module body 100 includes a solder bump forming step s-24 for forming a large number of solder bumps 106, and a mounting for mounting the thin film laminated circuit bodies 4T1, 4T2 and the mounting component 101 on the uppermost layer. Step s-25 and the like. In addition, the manufacturing process of the high-functional high-frequency circuit module body 100 is almost equivalent to the corresponding process of the high-frequency circuit module body 1 described above.

  In the insulating layer forming step s-20, the insulating layer 102 having a predetermined thickness is formed on the base substrate 5 of the high-frequency circuit module body 1 on which the thin film laminated circuit bodies 4A and 4B manufactured through the above-described steps are mounted. It is a process. In the insulating layer forming step s-20, a prepreg made of the same insulating material as that of the base substrate 5 is used, and this prepreg is overlaid on the upper layer 5a of the base substrate 5, specifically, the solder resist layer 10. The prepreg is formed of an organic material such as glass epoxy, polyimide, polyphenylene ether, bismaletotriazine, or polytetrafluoroethylene, an inorganic material such as glass, alumina, or ceramic, or a composite material of an organic material and an inorganic material.

  In the insulating layer forming step s-20, the prepreg is heated and pressurized by a vacuum press machine, so that the insulating layer 102 covering the thin film laminated circuit bodies 4A and 4B as shown in FIG. 5 is formed. In the high-frequency circuit module body 1, since the thin film laminated circuit bodies 4 </ b> A and 4 </ b> B manufactured by thin film technology are formed with a small thickness, the main surface of the insulating layer 102 does not have a large unevenness.

  The via formation step s-21 is a step of forming an appropriate via 103 in the insulating layer 102 for interlayer connection between the base substrate 5 and the thin film laminated circuit bodies 4A and 4B and a wiring layer 104 described later. Specifically, the via formation step s-21 includes a step of forming a via hole 103a in the insulating layer 102 and a step of filling the via hole 103a with copper plating in a wiring layer formation step s-22 described later. In the via formation step s-21, irradiation with, for example, a carbon dioxide laser or a YAG laser is performed from a position facing a connection land on which the details formed on the base substrate 5 and the thin film multilayer circuit bodies 4A and 4B are omitted, as shown in FIG. In this manner, a via hole 103a is formed in the insulating layer 102 so that the connection land faces outward.

  The wiring layer forming step s-22 is a step of performing a predetermined patterning process on the copper plating layer on the main surface 102a of the insulating layer 102 to form a predetermined wiring pattern as shown in FIG. At the same time, the via hole 103a is also made conductive to form the via 103. Specifically, the wiring layer forming step s-22 includes a step of forming a copper layer having a predetermined thickness over the entire main surface 102a of the insulating layer 102 by performing an electrolytic copper plating process and an electroless copper plating process. The method includes patterning the copper layer, an etching process for removing an unnecessary copper layer, a process for removing an etching resist, and the like.

  In the wiring layer forming step s-22, after forming a thin copper film over the entire surface of the insulating layer 102 by electroless copper plating, the copper film is used as a seed metal to perform electrolytic copper plating, thereby providing a thickness of 10 μm to 10 μm. A copper layer of about 30 μm is formed. In the wiring layer forming step s-22, not only the photoresist used in the above-described manufacturing process of the thin film laminated circuit body 4 but also a film-like resist called a so-called dry film can be used. In the wiring layer forming step s-22, when a dry film is used, after copper plating, the dry film is attached to, for example, a laminator and developed with a 0.5% to 1% sodium carbonate solution after the exposure process. As a result, the copper layer is patterned. The dry film can be easily peeled by using a 1.5% to 5% sodium hydrogen carbonate solution adjusted to 45 ° C. to 60 ° C. as a peeling solution.

  In the wiring layer formation step s-22, an unnecessary copper layer is removed by etching, but not only the above-mentioned mixed solution of sulfuric acid, nitric acid, and acetic acid but also a ferric chloride solution, for example, is used. It is possible.

  In the solder resist layer forming step s-23, a solder resist layer 105 that covers the wiring layer 104 formed by the above-described steps is formed, and the mounting connection lands 107 formed on the wiring layer 104 are formed outwardly on the solder resist layer 105. This is a step of forming the opening 105a to be exposed to. In the solder resist layer forming step s-23, for example, the wiring layer 104 is covered by a spin coating method or the like, and a solder resist is applied over the entire surface of the insulating layer 102 to form the solder resist layer 105.

  In the solder resist layer forming step s-23, the solder resist layer 105 is subjected to photolithography processing, exposed and developed to form an opening 105a that allows the mounting connection land 107 to face outward as shown in FIG. . In the solder resist layer forming step s-23, a terminal forming process for forming a gold layer or a nickel layer having good rust prevention and solder wettability by plating or the like on the surface of the mounting connection land 107 exposed from the opening 105a is performed. Done.

  The solder bump forming step s-24 is a step of performing a reflow process after filling the opening 105a with a solder paste by a printing method or the like. In the solder bump forming step s-24, the solder paste printed on each mounting connection land 107 is melted and solidified by the reflow process, and is substantially hemispherical from the opening 105a of the solder resist layer 105 as shown in FIG. The solder bumps 106 are formed by solidifying in a raised state.

  The mounting step s-25 is a step of mounting the thin film laminated circuit bodies 4T1 and 4T2 and the mounting component 101 on the insulating layer 102 by electrically and mechanically coupling to the mounting connection land 107 using the solder bump 106. . In the mounting step s-25, an underfill layer 108 is formed on the insulating layer 102 by applying an underfill material around the solder bumps 106. In the mounting step s-25, the thin film laminated circuit bodies 4T1 and 4T2 and the mounting component 101 are positioned and mounted on the insulating layer 102 using an appropriate positioning mounting means. In the mounting step s-25, the solder bumps 106 are melted and solidified by heating and pressing the thin film laminated circuit bodies 4T1 and 4T2 and the mounting component 101 against the insulating layer 102 using a thermocompression bonding apparatus or the like, thereby insulating layer. The thin film laminated circuit bodies 4T1 and 4T2 and the mounting component 101 are mounted on the 102.

  In the mounting step s-25, the circuit portion formed on the base substrate 5 side or the thin film laminated circuit bodies 4A to 4N built in the insulating layer 102, the wiring layer 104 formed on the insulating layer 102, or the thin film laminated layer. The circuit bodies 4T1 and 4T2 and the mounting component 101 are interlayer-connected by the via 103, and the high-functional high-frequency circuit module 100 shown in FIG. 31 is manufactured. In the high-functional high-frequency circuit module 100, the underfill layer 108 that is solidified by being heated by the thermocompression bonding apparatus firmly fixes the thin film multilayer circuit bodies 4T1 and 4T2 and the mounted component 101 on the insulating layer 102.

  The high-functional high-frequency circuit module 100 is not limited to the method of mounting the thin film laminated circuit bodies 4T1 and 4T2 and the mounting component 101 on the insulating layer 102 using the above-described thermocompression bonding apparatus. For example, a semiconductor chip mounting method It is also possible to mount by a face-down mounting method such as a reflow soldering process, a flip chip bonding method, a TAB method or a beam lead bonding method. In addition, the high-functional high-frequency circuit module 100 can form the insulating layer 102 in multiple layers and incorporate a wiring layer and the thin film laminated circuit body 4 in each insulating layer.

  In the thin film multilayer circuit body mounting step s-16, for example, the thin film multilayer circuit body 4 is bonded and fixed to the base substrate 5 (not shown). In the thin film multilayer circuit body mounting step s-16, the thermocompression bonding apparatus melts the solder bumps 12 by heating the thin film multilayer circuit body 4 against the base substrate 5 while heating to about 240 ° C. to 260 ° C. Resolidify. In the thin film multilayer circuit body mounting step s-16, as shown in FIG. 30, each mounting terminal 11 on the base substrate 5 side and each mounting connection land 24 on the thin film multilayer circuit body 4 side are electrically connected by solder that is melted and solidified. The high-frequency circuit module body 1 in which the thin film laminated circuit bodies 4A to 4N are mounted on the base substrate 5 is manufactured by being mechanically and mechanically coupled.

It is a longitudinal cross-sectional view of the high frequency circuit module body shown as embodiment of this invention. It is a longitudinal cross-sectional view of the thin film laminated circuit body mounted in the high frequency circuit module body. It is a manufacturing process figure of a high frequency circuit module body. The holding | maintenance film material used for a manufacturing process is shown, The figure (A) is a top view, The figure (B) is a longitudinal cross-sectional view. It is a top view of the folder member holding a holding film material. It is a top view of the peeling jig | tool which consists of a holding film material and a folder member. It is the figure which formed the peeling layer in the dummy board | substrate. It is the figure which formed the mounting connection land. It is the figure which formed the 1st insulating layer. It is the figure which formed the seed metal layer. It is the figure which formed the copper plating layer. It is the figure which formed the 1st wiring layer. It is the figure which formed the 2nd insulating layer. It is the figure which formed the receiving electrode. It is the figure which formed the passive element. It is the figure which formed the 2nd wiring layer. It is the figure which formed the 3rd insulating layer. It is the figure which formed the 3rd wiring layer. It is the figure which formed the soldering resist layer. It is the figure which formed the external electrode. It is the figure which formed the 5th separation slit in the peeling layer. It is the figure which combined the 1st intermediate body and the peeling jig | tool. It is the figure immersed in the peeling tank. It is a figure which shows the state which a thin film laminated circuit body peels from a dummy substrate through a peeling tank in a peeling tank. It is a longitudinal cross-sectional view of the 2nd intermediate body peeled from the dummy substrate. It is a figure which shows the thin film laminated circuit body separated from the peeling jig one by one. It is a figure which prints a solder paste on a base substrate. It is the figure which formed the solder bump. It is the figure which formed the underfill layer. It is a figure which mounts a thin film laminated circuit body on a base substrate. It is a longitudinal cross-sectional view of the high frequency circuit module body shown as 2nd Embodiment. It is a manufacturing process figure of the high frequency circuit module body. It is the figure which formed the insulating layer. It is the figure which formed the via hole. It is the figure which formed the wiring layer. It is the figure which formed the soldering resist layer. It is the figure which formed the solder bump. It is a longitudinal cross-sectional view of the conventional high frequency circuit module body.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High frequency circuit module body, 2 Dummy board, 3 Release layer, 4 Thin film laminated circuit body, 5 Base board, 6 Signal wiring pattern, 7 Power supply wiring pattern, 8 Ground pattern, 9 Via, 10 Solder resist layer, 11 Mounting terminal Part, 12 solder bump, 13 solder resist layer, 14 connection terminal part, 15 first insulating layer, 16 second insulating layer, 17 third insulating layer, 18 first wiring layer, 19 second wiring layer, 20 third Wiring layer, 21 capacitor element, 22 resistor element, 23 inductor element, 24 mounting connection land, 25 solder resist layer, 26 external electrode, 27 underfill layer, 28 first via, 29 second via, 30 third via, 31 Holding film material, 32 slit, 34 folder member, 35 peeling jig, 36 first metal film, 37 second metal film, 38 protective resin layer, 40 first Separation slit, 41 seed metal layer, 42 plating resist layer, 43 copper plating layer, 45 second separation slit, 48 dielectric, 49 resistor, 52 third separation slit, 54 fourth separation slit, 55 fifth separation slit, 56 1st intermediate body, 57 Separation slit, 58 Stripping tank, 59 Stripping liquid, 60 2nd intermediate body, 61 Metal mask, 62 Solder paste, 64 Opening part, 100 High-performance high-frequency circuit module body, 101 Mounting component, 102 Insulation Layer, 103 via, 104 wiring layer, 105 solder resist layer, 106 solder bump, 107 mounting connection land, 108 underfill layer

Claims (4)

One or more thin film laminated circuit bodies in which a multilayer wiring layer in which thin film elements and functional elements are formed via an insulating layer are formed on a base substrate on which a wiring layer is formed are formed on the main surface. In the method of manufacturing a circuit module body,
The manufacturing process of the thin film laminated circuit body is as follows:
A release layer forming step of forming a release layer on the planarized main surface of the dummy substrate;
A plurality of thin film laminated circuit bodies in which a multilayer wiring layer, a thin film element, or a functional element is formed on the release layer via an insulating layer by a thin film forming technique and mounting connection lands are formed on the mounting surface with respect to the base substrate. Forming a thin film circuit layer in a state of being separated from each other through a separation slit;
A holding film material in which a plurality of slits corresponding to each of the separation slits is formed is used, and each of the opposing separation slits and the slits are aligned and attached onto each of the thin film laminated circuit bodies. Material pasting process;
A thin film laminated circuit body peeling step for peeling the whole from the dummy substrate in a state where each thin film laminated circuit body is held by the holding film material by immersing in a peeling solution for dissolving the peeling layer,
A thin film laminated circuit body separation step of separating each thin film laminated circuit body from the holding film material one by one through the separation slit,
A circuit characterized in that the thin film laminated circuit body manufactured through the above steps is mounted on the base substrate by coupling the mounting connection lands to opposing mounting terminal portions formed on the base substrate. A method for manufacturing a module body.   2. The circuit module body according to claim 1, wherein the holding film material constitutes a peeling jig by fixing an outer peripheral portion by a ring-shaped holder member having an inner diameter larger than an outer diameter of the dummy substrate. Manufacturing method.   2. The method of manufacturing a circuit module body according to claim 1, wherein the holding film material is used in which an adhesive layer having a reduced adhesive strength by light irradiation or heating is formed on the surface of the film substrate. Using the circuit module body formed by mounting the thin film laminated circuit body on the base substrate as a base body,
An insulating layer forming step of forming an insulating layer covering the thin film laminated circuit body on the main surface of the base body;
A via forming step of forming a via in the insulating layer for interlayer connection with the thin film multilayer circuit body and the base substrate;
A wiring layer forming step of forming a wiring layer having a mounting connection land and a wiring pattern connected to the via on the insulating layer;
A mounting step of mounting the thin film laminated circuit body and the surface mount electronic component on the wiring layer via the mounting connection land;
2. The method of manufacturing a circuit module body according to claim 1, wherein the thin film laminated circuit body is mounted on an inner layer and an outer layer of an insulating layer.

Images