JP4322479B2 - Flat panel display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flat display device in which a plurality of display pixels are arranged in a matrix, and more particularly to a flat display device including a memory element in which each display pixel holds image data.
[0002]
[Prior art]
In recent years, active matrix liquid crystal display panels have come to be widely used as monitor displays for notebook PCs and portable terminal devices because of their beautiful display and high product reliability. This liquid crystal display panel is generally held between an array substrate in which a plurality of pixel electrodes are arranged in a matrix, a counter substrate in which a counter electrode is disposed to face the plurality of pixel electrodes, and the array substrate and the counter substrate. It consists of a liquid crystal layer. In addition to a plurality of pixel electrodes, the array substrate includes a plurality of scanning lines arranged along the rows of the pixel electrodes, a plurality of signal lines arranged along the columns of the pixel electrodes, and the scanning lines and the signal lines. And a plurality of pixel switches arranged in the vicinity of the intersection position. Each pixel switch is connected to apply the signal voltage of the corresponding signal line to the corresponding pixel electrode when driven through the corresponding scanning line. By using this pixel switch, it is possible to sufficiently reduce crosstalk between adjacent pixels and obtain a high-contrast image.
[0003]
The pixel switch is generally composed of a thin film transistor using an amorphous silicon semiconductor thin film. Recently, due to advances in manufacturing technology, it has become possible to form polysilicon semiconductor thin films having higher carrier mobility than amorphous silicon. If this thin film formation technology is used, not only a pixel switch for pixel electrodes but also, for example, a vertical driver and a horizontal driver can be incorporated into the array substrate.
[0004]
By the way, for example, a portable terminal such as a cellular phone is mainly operated by a battery power source, so that it is preferable that the power consumption is as low as possible. For this reason, it is common practice to reduce the brightness of the display screen in the standby state of the mobile phone. Recently, a technique capable of further stopping the vertical driver and the horizontal driver is known. In this technique, a plurality of memory elements are respectively provided in display pixels constituting a display screen, and hold image data representing the same image in a standby state. The vertical driver and the horizontal driver are stopped while the same image is displayed corresponding to the contents of these memory elements. As a result, the power consumption of the display can be suppressed.
[0005]
[Problems to be solved by the invention]
However, if these vertical and horizontal drivers are completely stopped, it becomes difficult to update only a part of the display image.
[0006]
In view of the above technical problems, an object of the present invention is to provide a flat display device capable of updating a part of a display image with low power consumption.
[0007]
[Means for Solving the Problems]
According to one aspect of the present invention, a matrix array of a plurality of display pixels each having a memory element and displaying an image corresponding to the contents of the memory elements and a row block of the plurality of display pixels are selectively designated and selected. A vertical scanning circuit that enables writing to the memory element of the display pixel corresponding to the row block, and a column block of a plurality of display pixels are selectively specified, and image data is stored in the memory element of the display pixel corresponding to the selected column block. Horizontal scanning circuit for writing, interface for writing and reading address data and image data for each display pixel supplied from outside to video memory, and operation of vertical and horizontal scanning circuit with reference to address data and image data supplied from the interface A controller that controls the image, and the interface The display pixel portion address data corresponding to the image data supplied from the outside is detected, and the row and column block including the display pixel portion specified by the detected address data is determined as the rewrite range. Then, a flat display device having an operation mode for supplying partial image data corresponding to the rewriting range to the controller is provided.
[0008]
In this flat display device, the interface is different from the image data in the video memory, and the display pixel specified by the detected address data is detected by detecting the address data of the display pixel corresponding to the image data supplied from the outside. Therefore, the addressing of the vertical scanning circuit and the horizontal scanning circuit is simplified by determining the row and column blocks including the above-mentioned parts as the rewriting range and supplying the partial image data corresponding to the rewriting range to the controller. Thereby, even if the display pixel portion is insufficient for rewriting the image data for the display pixels of each block, the shortage of the image data can be supplemented with the contents of the video memory. That is, when image data of one address format is supplied from the outside to update a part of the image data held in the video memory, this address format can be adapted to the addressing system of the controller. Therefore, a part of the display image can be updated without requiring power consumption as in the case of rewriting the memory elements of all display pixels.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a flat display device according to an embodiment of the present invention will be described with reference to the drawings. This flat display device is configured to be operable in a normal writing mode in which the entire screen is updated and a random writing mode in which a part of the image is updated in units of blocks.
[0010]
FIG. 1 schematically shows the structure of the flat display device, FIG. 2 shows the structure of the display pixel of the liquid crystal display panel shown in FIG. 1, and FIG. 3 shows the partial cross-sectional structure of the display pixel shown in FIG. .
[0011]
The flat display device includes, for example, a reflective liquid crystal display panel LCD having a display area DA in which a plurality of display pixels PX are arranged in a matrix and a drive area DR for driving the display pixels PX, and controls the liquid crystal display panel LCD. And an external control circuit PCB. The liquid crystal display panel LCD includes an array substrate 10, a counter substrate 20 facing the array substrate 10, and a liquid crystal layer 30 as a light modulation layer sandwiched between the array substrate 10 and the counter substrate 20. The liquid crystal layer 30 is obtained by injecting a liquid crystal composition into the gap between the array substrate 10 and the counter substrate 20 and sealing the liquid crystal composition. The light transmittance of the liquid crystal layer 30 is set corresponding to the potential difference between the pixel electrode 11 and the counter electrode 22. The array substrate 10 and the counter substrate 20 have polarizing plates PL1 and PL2 on their outer surfaces.
[0012]
The counter substrate 20 is a light transmissive insulating substrate GL2 such as a glass plate, a color filter 21 formed on the insulating substrate GL2, a counter electrode 22 facing the plurality of pixel electrodes 11 and covering the color filter 21, and a counter electrode 22 Including an alignment film 23B.
[0013]
Next, the array substrate 10 will be described. The display area DA of the array substrate 10 includes a light-transmissive insulating substrate GL1 such as a glass plate, a plurality of pixel electrodes 11 arranged corresponding to the display pixels PX, and a plurality of scans arranged along the rows of these pixel electrodes 11. It has a plurality of signal switches 13 arranged along the lines 12, the columns of these pixel electrodes 11, and a plurality of pixel switches 14 arranged in the vicinity of the intersection positions of these scanning lines 12 and signal lines 13. Further, the display area DA is arranged in the vicinity of the substantially intersection of the input gate line 19A and the output gate line 19B, the signal line 13 and the input gate line, which are arranged in the column direction of the plurality of display pixels PX and parallel to the plurality of scanning lines 11. The memory input switch 16 arranged, the memory input 15 connected to the memory input switch 16 and holding the image data VD supplied from the corresponding signal line 13 is connected to the memory element 15 such as a static RAM via the polarity inversion circuit 17. A memory output switch 18. Each of the pixel switch 14 and the memory output switch 18 is connected to an auxiliary capacitor CS formed by capacitively coupling the corresponding pixel electrode 11 and an auxiliary capacitor line arranged in parallel with the corresponding scanning line 12. Image data is written to the pixel electrode 11 and the auxiliary capacitor CS via the pixel switch 14 in the normal writing mode and via the memory output switch 18 in the random writing mode.
[0014]
Each pixel switch 14 and each memory output switch 18 are formed of thin film transistors formed on an insulating substrate GL1 using a polysilicon semiconductor thin film, and are driven via the corresponding scanning line 12 or output gate line 19B. Are connected so as to apply the signal voltage of the corresponding signal line 13 to the corresponding pixel electrode 11. Similarly to the counter substrate 20, the plurality of pixel electrodes 11 are covered with an alignment film 23A as shown in FIG.
[0015]
The drive region DR of the array substrate 10 includes a vertical driver 40 that drives the plurality of scanning lines 12, a horizontal driver 50 that drives the plurality of signal lines 13, and a vertical decoding unit 110 that controls the vertical driver 40 to operate for each unit row. , A horizontal decoding unit 120 that controls the horizontal driver 50 to operate for each unit column, and a controller 60 that controls these operations. Note that the vertical driver 40, the horizontal driver 50, the controller 60, the vertical decoding unit 110, and the horizontal decoding unit 120 are arranged outside the display area DA constituted by a plurality of display pixels PX, and are formed of polysilicon as with the pixel switch 14. The thin film transistor using the semiconductor thin film is formed as a segment, and is formed in the same process as the pixel switch 14.
[0016]
The external control circuit PCB is composed of a video RAM 80 and an interface IC 90 arranged on a printed wiring board provided outside the liquid crystal display panel LCD. The video RAM 80 holds address data and image data for one frame written to the plurality of display pixels PX. The interface IC 90 temporarily stores address data and image data supplied from the outside in the video RAM 80, sequentially extracts data from the video RAM 80 according to the operation mode, and supplies the data to the controller 60 of the liquid crystal display panel LCD. That is, in the normal writing mode, data corresponding to all display pixels PX is output to the controller 60, and in the random writing mode, data corresponding to the block to be rewritten is used as block address data and update image data. Output to the controller.
[0017]
Next, the display operation in the normal writing mode will be described. The controller 60 supplies a vertical start pulse and a plurality of vertical clock pulses generated in synchronization with an image frame period in the normal writing mode to the vertical driver 40 as a vertical scanning control signal CTY. Further, the controller 60 uses the horizontal start pulse and a plurality of horizontal clock pulses generated in synchronization with the horizontal scanning period of the image as the horizontal scanning control signal CTX along with the image data VD whose polarity is inverted every frame period or horizontal scanning period. Supply to the driver 50. The vertical driver 40 sequentially drives the scanning lines 12 by shifting the vertical start pulse in response to these vertical clock pulses. On the other hand, the horizontal driver 40 sequentially drives the signal lines 13 by shifting the horizontal start pulse in response to these horizontal clock pulses. Thereby, the image data is written to the pixel electrodes 11 of the display pixels PX while the display pixels PX of each row are driven, and the potentials of the pixel electrodes 11 are set. Note that the memory input switch 16 and the memory output switch 18 also function in the normal writing mode, and write the image data supplied to the signal line 13 to the memory element 15 and supply the voltage of this image data to the pixel electrode 11.
[0018]
Next, the display operation in the random writing mode will be described. FIG. 5 shows an example of the rewrite range set for the received image data. Block address data and update image data of a block corresponding to the rewrite range are supplied from the interface IC of the external drive circuit PCB to the controller. In the example shown in FIG. 5, display pixels PX for four blocks indicated by diagonal lines are set in the rewrite range, and block address data and update image data representing the leading positions B1 to B4 of these blocks are supplied to the controller 60.
[0019]
The controller 60 generates a vertical address signal ADY and a horizontal address signal ADX based on the block address data. The vertical clock signal CKY and the vertical address signal ADY are supplied to the vertical decoding unit 110, and the horizontal address signal ADX and the horizontal clock signal CKX are supplied to the horizontal decoding unit 120. Further, the polarity inversion signal POL that is inverted at a predetermined cycle such as a frame period or a horizontal scanning period is supplied to the polarity inversion circuit 17.
[0020]
Accordingly, the vertical decoding unit 110 sequentially selects the rows of the display pixels PX in the row block corresponding to the vertical address signal ADY, and drives the corresponding gate lines 19A and 19B. While the display pixels PX in each row are selected, the horizontal decoding unit 120 controls the horizontal driver 50 to sequentially select the columns of the display pixels PX in the column block corresponding to the horizontal address signal ADX and drive the corresponding signal line 13. To do. The horizontal driver 50 supplies the image data supplied from the controller 60 to the signal line 13 corresponding to the display pixel PX in the selected column under the control of the horizontal decoding unit 120.
[0021]
More specifically, the horizontal decoding unit 120 decodes a shift register circuit 120A composed of a plurality of shift registers S / R connected in cascade so as to divide a plurality of display pixels PX into a plurality of column blocks, and a horizontal address signal ADX. The horizontal decoder 120B is included. The horizontal decoder 120B outputs the scanning pulse SP to the shift register S / R corresponding to the horizontal address signal ADX. The shift register S / R shifts the scanning pulse SP in response to the horizontal clock signal CKX, and controls the horizontal driver 50 so as to sequentially drive the number of signal lines 13 corresponding to the number of display pixels in the column block.
[0022]
The vertical decoding unit 110 is configured in substantially the same manner as the horizontal decoding unit 120, and includes a shift register circuit and a vertical address configured by a plurality of shift registers connected in series so as to divide a plurality of display pixels PX into a plurality of row blocks. A vertical decoder for decoding the signal ADY is included. The vertical decoder outputs a scan pulse to the shift register corresponding to the vertical address signal ADY. This shift register shifts this scanning pulse in response to the vertical clock signal CKY, and sequentially drives the input gate line 19A and the output gate line 19B corresponding to the number of display pixels in the row block. Here, the input gate line 19A and the output gate line 19B are set in a complementary potential relationship.
[0023]
In the display pixel PX, the memory input switch 16 is driven via the input gate line 19A and the memory output switch 18 is driven via the output gate line 19B with the pixel switch 14 turned off. The polarity inversion circuit 17 is controlled by a polarity inversion signal POL from the controller 60.
[0024]
Thus, the memory input switch 16 is turned on prior to the memory output switch 18, and the image data on the signal line 13 is written to the memory element 15. When this writing is completed, the memory output switch 18 becomes conductive in place of the memory input switch 16. As a result, the image data is supplied from the memory element 15 to the pixel electrode 11 via the polarity inversion circuit 17. The polarity inversion circuit 17 periodically inverts the voltage polarity of the image data.
[0025]
In the configuration as described above, once the entire image is displayed in the normal writing mode, a part of the image can be updated in the random writing mode. In the random writing mode, the operation of the vertical driver 40 and the horizontal driver 50 can be partially stopped or restricted by the controller 60 controlling the supply of the clock signal.
[0026]
Next, data transmission from the computer set side serving as an image data source to the external drive circuit PCB will be described. Data transmitted from the computer set side to the external control circuit PCB is transmitted in a packet format as shown in FIG. 4, for example. Here, for example, three display pixels PX (for one dot) corresponding to R, G, and B are transmitted as a set, and address data and image data are transmitted respectively.
[0027]
For example, data transmission from the computer set side to the external drive circuit PCB is switched between the normal writing mode and the random writing mode. In the normal writing mode, data for all display pixels is transmitted in a packet format, and random writing is performed. In the embedded mode, only the data (hereinafter referred to as received data) that is changed compared to the previous frame is transmitted in the packet format. The interface IC updates part of the image data stored in the video RAM 80 with the received data in order to rewrite the display pixels PX in units of rows and columns, and displays the rows of the display pixels PX including the display area to which the received data is assigned. Partial image data corresponding to the rewrite range specifying the column block is output to the controller 60.
[0028]
FIG. 6 shows in detail the operation of the interface IC 90 performed in the random write mode. In step ST1, the interface IC 90 updates a part of the image data held in the video RAM 80 with the received data. In step ST2, the interface IC 90 determines a rewrite range for specifying the row and column blocks based on the address data for the received data. In step ST3, each block of the partial image data VD corresponding to the rewrite range is read, and the block of the partial image data VD is supplied to the controller 60 together with the block address data assigned thereto. Since the display area of the received data is only a part of the rewrite range, the shortage of the received data is supplemented by the contents of the video RAM 80.
[0029]
In the flat display device of the present embodiment, the addressing of the vertical decoding unit 110 and the horizontal decoding unit 120 is simplified by designating the rewrite range of the display pixel in units of blocks. On the other hand, since the interface IC 90 supplements the image data that is insufficient by such block-unit rewriting with the contents of the video RAM 80, rewriting can be performed normally. That is, the addressing format of the partial image data supplied from the outside can be matched with the addressing system of the controller. This makes it possible to update a part of the display image without requiring power consumption as in the case of rewriting the memory elements 15 of all the display pixels PX.
[0030]
The present invention is not limited to the above-described embodiment, and can be variously modified.
[0031]
For example, in the above-described embodiment, the case where the data transfer from the computer set side to the interface IC 90 differs according to the operation mode has been described, but one frame of data is transmitted from the computer set side to the interface IC 90 regardless of the operation mode. It may be a thing. In this case, the interface IC 90 reads the previous frame stored in the video RAM 80 and stores the transmitted data in the video RAM 80. Then, it compares the image data of the next frame with the image data of the previous frame, and detects the changed portion. Based on the changed portion, control is performed so as to operate in the normal writing mode or the random writing mode. In this control, it is desirable to set appropriately according to the use of the flat display device. When operating in the random writing mode, image data corresponding to the display pixels PX of all blocks including the changed portion is supplied to the controller 60 together with the block address data.
[0032]
As described above, when the random writing mode is performed, the changed part can be updated in units of blocks, and the power consumption required for data transfer between the external drive circuit PCB and the liquid crystal display panel LCD can be reduced. It becomes. In the liquid crystal display panel LCD, only the drive circuit corresponding to the block to be changed can be partially operated, and the power consumption can be further reduced.
[0033]
Further, when the random writing mode continues for a predetermined time or longer, all the display pixels PX may be periodically rewritten even if the changed portion of the image is a part of the display area DA.
[0034]
Moreover, although the above-mentioned embodiment demonstrated the flat display apparatus using liquid crystal display panel LCD, it can apply to the active matrix type display apparatus in general, for example, can also apply to an organic electroluminescence display panel.
[0035]
For example, when applied to an organic EL display panel, the polarity inversion circuit 17 shown in FIG. 2 is not necessary, and the display pixel P shown in FIG. 7 can be used. In this example, the display pixel P is an organic EL light emitting element P1, a driving transistor P2 which is a P channel thin film transistor connected in series to the organic EL light emitting element P1 between the power supply terminals VDD and VSS, and between the gate and source of the driving transistor P2. Has a capacitor P3 connected to. Moreover, it can also comprise as shown in FIG. 8 and can reduce the number of wiring. In this example, the OR gate circuit MX is connected so as to be shared with the gate line 19A driven by the vertical decoding unit 110 and the scanning line 12 driven by the vertical driver 40. An output line 12 ′ of the OR gate circuit MX is connected to a gate of a pixel switch 14 composed of an N channel thin film transistor and a gate of a memory output switch 18 ′ composed of a P channel thin film transistor. Connected between the memory output switches 18 '. When the output line 12 ′ of the OR gate circuit MX rises to a high level, the pixel switch 14 is turned on and the memory output switch 18 ′ is turned off. As a result, the image data is written from the signal line 13 to the memory element 15 via the pixel switch 14. When the output line 12 ′ of the OR gate circuit MX falls to a low level, the pixel switch 14 becomes non-conductive and the memory output switch 18 ′ becomes conductive. As a result, the image data is supplied from the memory element 15 to the gate of the drive transistor P2 via the memory output switch 18 ′.
[0036]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a flat display device capable of updating a part of a display image with low power consumption.
[Brief description of the drawings]
FIG. 1 is a circuit diagram schematically showing a configuration of a flat display device according to an embodiment of the present invention.
2 is a circuit diagram showing a configuration of display pixels of the liquid crystal display panel shown in FIG. 1. FIG.
3 is a diagram showing a partial cross-sectional structure of the display pixel shown in FIG. 2;
4 is a diagram showing a format of a packet supplied from the outside to the interface IC shown in FIG. 1. FIG.
FIG. 5 is a diagram showing a rewrite range set for the received image data shown in FIG. 4;
6 is a flowchart showing in detail an operation performed by the interface IC shown in FIG. 1 in a random write mode. FIG.
7 is a circuit diagram showing a configuration of display pixels of an organic EL panel according to a first modification of the flat display device shown in FIG.
8 is a circuit diagram showing a configuration of display pixels of an organic EL panel according to a second modification of the flat display device shown in FIG.
[Explanation of symbols]
PX ... Display pixel 10 ... Array substrate 12 ... Scanning line 13 ... Signal line 60 ... Controller 80 ... Video RAM
90 ... Interface IC
110 ... Vertical decoding unit 120 ... Horizontal decoding unit

Claims (1)

A matrix array of a plurality of display pixels each having a memory element and displaying an image corresponding to the contents of these memory elements, and a row block of the plurality of display pixels are selectively designated, and a display pixel corresponding to the selected row block is displayed. A vertical scanning circuit that enables writing to a memory element; a horizontal scanning circuit that selectively designates a column block of the plurality of display pixels and writes image data to a memory element of a display pixel corresponding to the selected column block; An interface for writing and reading address data and image data for each display pixel supplied from the video memory, and a controller for controlling operations of the vertical and horizontal scanning circuits with reference to the address data and image data supplied from the interface Prepared,
The interface detects address data of a display pixel in a portion different from the image data in the video memory, and includes a portion of the display pixel specified by the detected address data. And a flat display device having an operation mode for determining a column block as a rewrite range and supplying partial image data corresponding to the rewrite range to the controller.

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