JP4390732B2 - Semiconductor wafer appearance inspection system - Google Patents

Description

  The present invention relates to an appearance inspection apparatus for detecting a defect in a circuit pattern formed on a semiconductor wafer, and more particularly to image processing in the appearance inspection apparatus.

  In the appearance inspection of repetitive patterns represented by semiconductor wafers, the appearance of the inspection object is imaged, the reference image as the inspection standard is compared with the image data of the inspection image to be inspected, and there is a difference in the compared data. A comparison method for extracting a case as a defect is known. Such a comparison method is based on the premise that the reference image and the inspection image have the same pattern, and is an effective technique for an inspection target in which the same circuit pattern is repeatedly mounted, such as a semiconductor wafer. As the reference image, an actual pattern adjacent to or close to the design information or the inspection image may be used. When the object to be inspected is a semiconductor wafer, a large number of chips (one device) having the same circuit pattern are arranged on one wafer, and a method of comparing captured images of these chips as a reference image and an inspection image, respectively. The comparison and the case where the captured images of the patterns repeatedly arranged in the same chip are respectively compared as the reference image and the inspection image are called cell comparison.

JP-A-9-89794

The image data transferred to the defect analysis unit needs to be transferred as a pair of the reference image and the inspection image in both the cell comparison and the die comparison. In the case of die comparison, the reference image is the image of one chip before the chip to the chip to obtain an inspection image is generally used, for example, the first chip shown in FIG. 6 (a) when a chip to acquire the inspection images, 1 not present in the chip before the image of the chip is the same wafer on, because there is no reference picture, 1 defect analysis of th chip is impossible. Further, when the (n + 1) -th chip at the edge of the wafer as shown in FIG. 6A is a chip for obtaining an inspection image, the n-th chip data before one chip exists on the same wafer as the image data. However, in the case of semiconductor wafer appearance inspection, the reference image for the inspection image has different peripheral conditions at the time of image acquisition as the physical distance increases. It cannot be used as a reference image. Therefore, even when the (n + 1) th chip at the edge of the wafer is a chip for obtaining an inspection image, the data of the nth chip before the first chip cannot be used as a reference image, so that defect analysis is impossible.

Similarly, in the die comparison, as shown in FIG. 6B, when the scan on the wafer is turned back and forth at the edge of the wafer and reciprocates to take an image, the (n + 1) th chip is the inspection image. When the comparison is made with the reference image using the n-th chip image one chip before , the inspection is compared with the relationship between the (n + 1) -th chip and the n-th chip in FIG. Although the physical positions of the image and the reference image are close to each other, the (n + 1) chip and the n chip in FIG. 6B are adjacent to each other in the same column because the columns of the chip arrangement on the wafer are different. Compared with the relationship between chips (for example, n chip and (n-1) chip), the conditions at the time of image acquisition are different and more misalignment errors are included. This error only needs to be within the correction range of the image processing function. Otherwise, even in the case of FIG. 6B, the (n + 1) th chip reference image cannot be used as the (n + 1) th chip reference image. It is possible.

As described above, when a defect including a defect candidate to be described later is extracted on the chip at the end of the semiconductor wafer and becomes a defect analysis target, a reference image does not exist because there is no image one chip before, and the defect analysis cannot be performed. Will occur.

Further, in the cell comparison, as shown in FIG. 5, when a defect is extracted in each of the circuit patterns having different cell pitch A regions 503 and cell pitch B regions 504 mounted on one chip, they are detected in the cell pitch A region. The defect analysis image data requires image data at positions separated by the cell pitch A as a reference image for the inspection image , and the defect analysis image data detected in the cell pitch B region includes the image data for the inspection image. As the reference image, image data at a position separated by the cell pitch B is required. That is, in the case of cell comparison, the position of the reference image with respect to the inspection image differs depending on which cell pitch region the extracted defect belongs to. However, conventionally, a plurality of cell pitches for cell comparison cannot be designated. Therefore, the inspection of the cell pitch A area and the inspection of the cell pitch B area cannot be performed at the same time, and the inspection of the areas having different cell pitches is performed by setting the cell pitch for each cell pitch area as shown in the flow of FIG. It had to be re-executed and was very inefficient.

  Furthermore, since the definition of the reference image required for the inspection image is different between the die comparison and the cell comparison, the cell comparison and the die comparison cannot be mixed and executed.

  The present invention solves the problem of the prior art that in a die comparison inspection, a reference image cannot be defined and a defect analysis cannot be performed because there is no previous chip for a chip at the end of a semiconductor wafer. The purpose is to do. Another object of the present invention is to efficiently analyze defects existing in different cell pitch regions at high speed in cell comparison inspection. Furthermore, it aims at enabling mixed comparison of cell comparison and die comparison.

  In order to solve the above-mentioned problem, in the present invention, as information for reading out image data for an inspection image and a reference image from an image memory, in addition to position information of the inspection image, identification information for cell comparison / die comparison, Reference image information including cell pitch for cell comparison, chip relative position information for die comparison, and the like can be individually set for each inspection image.

A semiconductor wafer appearance inspection apparatus according to the present invention compares an image memory for storing image data obtained by imaging a semiconductor wafer, a memory controller for controlling cutout and transfer of the image data from the image memory, and comparison on the semiconductor wafer. A positional deviation detection unit that calculates the positional deviation amount of the partial images of two areas, and obtains a difference image between the partial images of the two areas by using the positional deviation amount as a correction value, and extracts defect candidates from the difference image A defect determination unit, a defect analysis unit that analyzes an image extracted as the defect candidate, and an overall controller that controls the overall operation , wherein the defect controller is extracted by the defect determination unit. The position of the inspection image in the image memory necessary for defect analysis of the defect candidate is calculated based on the defect feature amount calculated at the time, and the inspection image A reference representing a relative positional relationship between a start address on the image memory, a cut-out image size, a region on the semiconductor wafer including the inspection image, and a region on the semiconductor wafer including a reference image corresponding to the inspection image. and outputs the image position information to the memory controller, the memory controller, for each defect candidate, cut out test image from the image data of said image memory by using the clipped image size and the start address, before Kisaki head using the address and the cutout image size and the reference image position information to cut out the references images from the image data of said image memory, transfers the test and reference images cut into the defect analyzer. The reference image position information may be chip relative position information in die comparison or cell pitch in cell comparison.

In addition, a semiconductor wafer appearance inspection apparatus according to the present invention includes an image memory that stores image data obtained by imaging a semiconductor wafer on which a plurality of chips are formed, and a memory controller that controls the extraction and transfer of the image data from the image memory. And a misregistration detection unit that calculates the misregistration amount of the partial images of the two regions to be compared on the semiconductor wafer, and obtains a difference image of the partial images of the two regions using the misregistration amount as a correction value. , a defect determination unit for extracting the defect candidate from the difference image, comprising: a defect analyzing unit for analyzing the image extracted as the defect candidate, and a total controller for controlling the entire operation, the said overall controller chip Information about the inspection image comparison method in each area is stored, and the overall controller extracts defect candidates by the defect determination unit. The position of the inspection image necessary for defect analysis of the defect candidate is calculated on the basis of the defect feature amount calculated at the time, and the position of the defect candidate is any region in the chip. The identification information corresponding to cell comparison or die comparison is set based on whether the inspection image corresponds to the start address on the image memory of the inspection image, the cut-out image size, and the semiconductor wafer including the inspection image. Reference image position information indicating the relative positional relationship between the region and the region on the semiconductor wafer containing the reference image corresponding to the inspection image, and identification information indicating whether the set cell comparison or die comparison is output to the memory controller and the memory controller, for each defect candidate, the start address and the cutout image size and the inspection image by using the image data of said image memory Cut, by using said first address and said clipped image size and the reference image position information whether the cell comparison or die comparison identification information cut out a reference image from the image data of the image memory, the defect analyzer The inspection image and the reference image cut out are transferred . The reference image information in this case may include identification information indicating cell comparison or die comparison, cell pitch in the case of cell comparison, and reference image position information representing a relative positional relationship of chips in the case of die comparison. The memory controller holds a memory table that records the reference image position information corresponding to the leading address of the defect image, the cut-out image size, and the identification information for cell comparison or die comparison for each defect.

  According to the present invention, it is possible to avoid the existence of a non-inspectable area at the time of die comparison, and it is possible to inspect within one inspection even when a defect image is extracted in a different cell pitch area. Furthermore, mixed inspection of cell comparison and die comparison is possible, and inspection efficiency is improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a functional block diagram of a semiconductor wafer appearance inspection apparatus according to the present invention. An external appearance of the semiconductor wafer 100 that is an object to be inspected is imaged by the sensor 101. The captured image is stored in the image memory 105 of the image processing unit 103 as digital image data by the A / D conversion 102. In addition to the image memory 105, the image processing unit 103 is configured with a misregistration detection unit 106 that calculates the misregistration amount of two image data to be compared, and the misregistration amount calculated by the misregistration detection unit. A difference determination unit 107 that obtains a difference image between two images using as a value and extracts a defect candidate from the difference image, a defect analysis unit 108 that analyzes an image extracted as a defect candidate in more detail, and stores image data There is a memory controller 104 that controls the memory to be operated, and an overall controller 109 that controls the overall operation.

The overall controller 109 collects information of each unit of the misalignment detection unit 106, the defect determination unit 107, and the defect analysis unit 108, and monitors the role of distributing necessary information to the necessary locations and the operation status of each function. Play an integrated role. In addition, the overall controller 109 provides information on the arrangement of the chips on the wafer, information on the comparison method of the inspection image in each area in the chip (which area in the chip is the die comparison area, which area is the cell comparison with the cell pitch A). In the die comparison, the chip for obtaining the inspection image is at the edge of the wafer and there is no previous chip. In this case, information on a reference image acquisition method is stored. Information on the arrangement of the chips on the wafer and information on the comparison method of the inspection image in each region in the chip is set from design information or by the user observing the wafer. The reference image acquisition method in the case of die comparison is, for example, normally specifying a chip one chip before the inspection image as a reference image, and the first chip shown in FIG. 6A or FIG. when the n + 1) there is no previous chip in the wafer edge as the chip first is a one chip after the chip inspection image is designated as a chip to obtain a reference image. The reference image acquisition method may be set to the entire controller by default, or may be set by the user.

The misregistration detection unit 106 obtains a correlation value between the reference image that is two images to be compared and the inspection image, and calculates the misalignment amount of the two images. For imaging a circuit pattern of a semiconductor wafer, a technique such as SEM type or optical type is known.For example, in the case of an SEM type external appearance device, an electron beam is curved due to charging of the semiconductor wafer, and an acquired image and There may be an error in the positional information relationship. In the case of the comparative inspection, it is necessary to accurately match the comparison positions of the two images to be compared, and the misalignment detection unit 106 calculates the misalignment amounts of the two images to be compared in the x direction and the y direction by correlation calculation or the like. Then, the information is transferred to the defect determination unit 107. The defect determination unit 107 applies the deviation amount provided from the misregistration detection unit to the inspection image, corrects the misregistration, obtains a difference image from the reference image, extracts defect candidates, and extracts defect candidate feature amounts. Is calculated. As the feature amounts of the defect candidate, the center coordinates of the image extracted as a defect candidate, the area, etc. are determined. In the following description, the defect candidate extracted by the defect determination unit 107 is simply referred to as a defect.

In order to analyze the defect extracted by the defect determination unit 107, the memory controller 104 cuts out the image data for analysis of the defective part (inspection image and reference image ) from the image memory 105 and transfers it to the defect analysis unit 108. The cut-out position of the inspection image transferred from the image memory 105 to the defect analysis unit 108 is determined based on the center coordinates and the defect area of the defect, which are the calculation results of the defect determination unit 107. Is located in the image memory 105 and set in the memory controller 104. At this time, the data set in the memory controller 104 is a memory address indicating the position of the read data or a chip address and an in-chip address when the inside of the memory is managed in units of chips. Based on the set position information and the like, the memory controller 104 reads data from the image memory 105 and transfers the defect analysis image data to the defect analysis unit 108. As the transfer data to the defect analysis unit, the inspection image and the reference image are transferred in pairs, but the relative position of the reference image with respect to the inspection image and the comparison method may differ depending on conditions.

  FIG. 2 is a schematic top view of a semiconductor wafer to be inspected, and FIG. 3 is a map diagram in the image memory when image data when the wafer of FIG. 2 is imaged is stored in the image memory. After imaging the circuit pattern of the semiconductor wafer 100 shown in FIG. 2, the image data transferred to the image processing unit is stored in the image memory for each chip. For example, the image data obtained by scanning the (n-1) chip with the sensor 101 in FIG. 2 is stored in the (n-1) image area 301 on the memory map 300 in FIG. 3, and on the n chip in FIG. The image data obtained by scanning is sequentially stored in the n image region 302 on the memory map of FIG.

  In order for the image processing function units of the misregistration detection unit 106, the defect determination unit 107, and the defect analysis unit 108 to perform processing and perform the respective functions, the functions of the entire apparatus are efficiently pipelined and executed. The image data stored in the image memory 105 must be provided to each image processing function unit at a necessary timing. The memory controller 104 controls the image data stored in the image memory 105 in units of chips as described above so as to provide desired image data at a timing at which the three image processing function units operate optimally and efficiently.

  FIG. 4 represents a flow in which image data stored in the image memory in units of chips is transferred to each image processing function unit and processed by each image processing function unit.

  The image data of the (n−1) th chip stored in the image memory 105 is first transferred from the memory controller 104 to the misregistration detection unit 106, and the misregistration amount is calculated by arithmetic processing. Forwarded to After the calculation processing of the (n−1) th chip is completed in the misregistration detection unit 106, the image data of the nth chip that is the next calculation target is transferred, the calculation processing is performed, and the result is again the defect determination unit. Forwarded to 107. This operation is sequentially repeated in the position deviation detection unit.

  Next, in the defect determination unit 107, the image data of the (n-1) th chip is transferred from the image memory 105 at the timing of receiving the deviation amount which is the calculation result of the (n-1) th chip from the positional deviation detection unit 106. The defect determination processing calculation is performed. After the calculation process of the (n-1) th chip is completed in the defect determination unit 107, the deviation amount is transferred from the n-th chip image data and the positional deviation detection unit 106 in order to perform the next n-th chip calculation process. The defect determination process for the nth chip is executed. In the defect determination unit 107, this operation is sequentially repeated.

Further, based on the information of the part extracted as a defect by the defect determination unit 107 ( that is, the feature amount of the defect such as the center coordinates and area of the defect ), only the image of the part is cut out from the image memory 105 this time. Then, it is transferred to the defect analysis unit 108, and defect analysis processing is performed. As described above, among the three image processing function units, regarding the misregistration detection unit 106 and the defect determination unit 107, all the images stored in the image memory 105 are performed in order to perform image processing calculation on all captured images. Data is sequentially transferred and image calculation is performed. In the defect analysis unit 108, only the image extracted as a defect is transferred from the image memory 105 based on the image processing calculation result of the defect determination unit 107, and defect analysis processing is executed. The

  Therefore, the memory controller 104 is given position information of the defect image detected from the calculation result of the defect determination unit 107 via the overall controller 109, and the desired image data is sent to the defect analysis unit 108 based on the position information. Will be transferred. In the case of die comparison processing, the reference image is compared with the adjacent chip with respect to the inspection image, and therefore, data at the same address location of different chips is transferred to the defect analysis unit 108. For example, when a defect is detected in the die comparison area 505 of the (n + 1) th chip in FIG. 5, the comparison is made with image data at the same location (same address) of the nth chip. On the other hand, in the case of cell comparison, since the reference image is a comparison between adjacent cells with respect to the inspection image, the transfer data to the defect analysis unit is the image data separated by the cell pitch of the same chip. .

FIG. 9 is an explanatory diagram showing an example of die comparison inspection according to the present invention. FIG. 9A is a diagram illustrating an example of information set in the memory table inside the memory controller 104 by the overall controller 109. In the memory table in the memory controller, the defect image head address, the cutout image size, and the reference image position information are set for each defect by the number of defects. The defect image head address and the cut-out image size are set by the overall controller 109 based on the information acquired from the defect determination unit 107 , that is, the feature amount of the defect (defect candidate) . The reference image position information is set by the overall controller 109 based on chip arrangement information on the wafer and information on a reference image acquisition method. Here, as a method for acquiring a reference image at the time of die comparison, a chip that is one chip before the inspection image is normally used as a reference image, and a chip in which a defect is detected is located at the edge of the wafer and there is no previous chip. Will be described assuming that the chip after one chip of the inspection image is set as the reference image.

FIG. 9B is an explanatory diagram showing the positional relationship between the inspection image and the reference image cut out from the image memory 105 by the memory controller 104 when the defect 1 is detected on the first chip located at the edge of the wafer. At this time, a code indicating a chip after one chip is entered by the overall controller 109 at the location of the reference image position information in FIG. As a result, the memory controller 104 cuts out an image of the size specified by the cut-out image size from the image memory as the inspection image from the defective image start address of the first chip specified by the memory table. Also, based on the reference image position information (in this case, a code meaning a chip after one chip) , an image of the same size is cut out as a reference image from the same chip address of the second chip data. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  In the die comparison inspection, the image data for one chip before is generally used as the reference image for the inspection image. However, according to the present invention, the position of the reference image is added to the position information of the inspection image. Information can be set. When a defect is detected on the first chip, the conventional method of designating the chip one chip before as the reference image cannot analyze the defect because the image one chip before serving as the reference image does not exist. According to the present invention, it is possible to set the reference image position information such that the second chip is read from the image memory as the reference image as the reference image of the defect image of the first chip.

FIG. 9C is an explanatory diagram showing the positional relationship between the inspection image and the reference image cut out from the image memory 105 by the memory controller 104 when the defect 2 is detected in the n-th chip not located at the wafer edge. At this time, in the reference image position information portion of FIG. 9A, a code indicating the chip one chip before is written by the overall controller 109. As a result, the memory controller 104 cuts out, from the image memory 105, an image of the size specified by the cut-out image size as the inspection image from the defect image head address of the n-th chip specified by the memory table. Also, based on the reference image position information (in this case, a code meaning the chip one chip before) , images of the same size from the same chip address of the previous (n-1) chip data are referred to as the reference image. Cut out as. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  Further, according to the present invention, the position of the reference image with respect to the inspection image can be given in units of cell pitch in the cell comparison similarly to the die comparison. FIG. 10 is an explanatory diagram showing an example of cell comparison inspection according to the present invention.

FIG. 10A is a diagram illustrating an example of information set in the memory table inside the memory controller 104 by the overall controller 109. In the memory table inside the memory controller, a set of information including a defect image head address, a cut-out image size, and a cell pitch is set for each defect by the number of defects. The defect image head address and the cut-out image size are set by the overall controller 109 based on the information acquired from the defect determination unit 107 , that is, the feature amount of the defect (defect candidate) . The overall controller 109 sets the cell pitch by matching the detected defect position with information relating to the inspection image comparison method in each area in the chip. Here, it is assumed that the defect 3 exists in the cell pitch A region and the defect 4 exists in the cell pitch B region. In this case, the cell pitch is set to A for the defect 3 and the cell pitch is set to B for the defect 4.

  FIG. 10B shows the inspection image and reference image of the defect 3 and the inspection image and reference of the defect 4 that are cut out from the image memory 105 by the memory controller 104 based on the information in the memory table shown in FIG. It is explanatory drawing which shows the relationship of an image.

  Regarding the defect 3, the memory controller 104 cuts out, from the image memory, an image for the size specified by the cut-out image size from the defect image start address specified by the memory table as an inspection image. Also, an image of the same size is cut out as a reference image from an address preceding by the cell pitch A. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  For the defect 4, the memory controller 104 cuts out, from the image memory, an image for the size specified by the cut-out image size from the defect image start address specified by the memory table as an inspection image. Also, an image of the same size is cut out as a reference image from an address preceding by the cell pitch B. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  As described with reference to FIGS. 9 and 10, according to the present invention, the reading position of the reference image from the image memory can be set for each inspection image, and when a defect is extracted from the chip at the edge of the wafer, By setting the reference image to a chip different from the normal setting, defect analysis by die comparison can be performed on the end chip. Similarly, in the cell comparison, even when a defect is extracted for an image area having a different cell pitch, by setting a cell pitch for each read defect image, a defect in a different cell pitch area is detected. In addition, image transfer to the defect analysis unit is continuously performed.

  FIG. 8 is a diagram showing a cell comparison flow according to the present invention. First, an image captured by the sensor is stored in the image memory 105 (S801). Next, defect determination is performed by the defect determination unit 107, and defect information is passed to the overall controller 109. The overall controller 109 determines a cell pitch for each defect image from the defect position in the chip, and sets the inspection image cut-out position and reference image position information in the memory table of the memory controller 104 (S802). The memory controller 104 cuts out the inspection image and the reference image from the image memory 105 according to the information set in the memory table, and transfers them to the defect analysis unit 108 (S803). As described above, according to the present invention, even when defects are detected in regions having different cell pitches, all defects can be inspected by one operation.

  FIG. 11 is an explanatory view showing an example of a mixed inspection of a cell comparison inspection and a die comparison inspection according to the present invention. According to the present invention, in addition to the position information of the defect image and the relative position information of the reference image with respect to the inspection image, information for identifying whether the image is for die comparison or cell comparison is provided, and the reference image position for reading from the image memory is determined. By setting each defect image, cell comparison and die comparison can be mixed and executed.

  FIG. 11A shows an example of information set in the memory table inside the memory controller by the overall controller 109 in this case. In the memory table in the memory controller, a set of information including a defect image head address, a cut-out image size, reference image position information, and cell comparison / die comparison is set for each defect by the number of defects. The defect image head address and the cut-out image size are set by the overall controller 109 based on information acquired from the defect determination unit 107. In the cell comparison / die comparison, the overall controller 109 sets whether the cell comparison or the die comparison by matching the detected defect position with information on the comparison method of the inspection image in each region in the chip. In addition, in the reference image position information, in the case of die comparison, which chip is used as a reference image before or after the inspection image is set, and in the case of cell comparison, a cell pitch is set.

  FIG. 11B shows the inspection image and reference image of the defect 5 and the inspection image and reference of the defect 6 cut out from the image memory 105 by the memory controller 104 based on the information in the memory table shown in FIG. It is explanatory drawing which shows the relationship of an image. Here, it is assumed that the defect 5 is detected in the cell pitch A area and the defect 6 is detected in the die comparison area. In this case, the overall controller 109 sets the cell pitch A as reference image position information for the defect 5 in the memory table of the memory controller 104, and sets a code representing cell comparison for cell comparison / die comparison. For the defect 6, for example, a code representing one chip before is set as reference image position information, and a code representing die comparison is set for cell comparison / die comparison.

  For the defect 5, the memory controller 104 cuts out, from the image memory 105, an image for the size specified by the cut-out image size from the defective image start address specified by the memory table as an inspection image. Also, an image of the same size is cut out as a reference image from an address preceding by the cell pitch A. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  For the defect 6, the memory controller 104 cuts out, from the image memory 105, an image for the size specified by the cut-out image size from the defect image start address specified by the memory table as an inspection image. Also, an image of the same size is cut out as a reference image from the same address of the previous chip. The cut out inspection image and reference image are transferred from the memory controller 104 to the defect analysis unit 108.

  The position information for reading out these defect images, the relative position information of the reference image with respect to the inspection image, cell comparison, and die comparison need to be set in the memory controller for each extracted defect. High speed is required for image transfer to the defect analysis unit. Therefore, if such information can be stored in a table so that it can be stored together to some extent, memory read of defective images can be performed sequentially. Furthermore, by extracting the defect image read-out table into two (two sides) so that the information for reading the next defect image can be set simultaneously with the operation of reading the defect image from the image memory, the extracted defect Even when a large number of occurrences occur in succession, it is possible to continuously read data from the image memory and transfer image data to the defect analysis unit.

  FIG. 12 is an explanatory diagram showing an example in which the memory table is duplicated. FIG. 12A shows a case where memory table A provides information for extracting an inspection image and a reference image from an image memory when there are memory tables A and B in which a plurality of image extraction information can be set. In this example, the other memory table B receives information from the overall controller 109 in order to temporarily store the next cutout information. Further, in FIG. 12B, contrary to FIG. 12A, while the memory table B provides information for extracting the inspection image and the reference image from the image memory, the other memory table A An example is shown in which information is received from the overall controller 109 to temporarily store cutout information.

  FIG. 13 shows the contents of these memory tables A and B. Individual defect cutout information in the memory table includes items shown in FIG. 9A, FIG. 10A, or FIG.

  The data for generating the inspection image and the reference image for the defect analysis is initially set as the cut-out information of the defect No. 1 in the memory table A, and the information for the memory controller to read the image data from the image memory. Use as The processing proceeds with the information for cutting out defect No. 2 and the information for cutting out defect No. 3. After the processing of the cutting information of the last defect No. n set in the memory table A is finished, the roles of the memory tables A and B are changed, and this time, the cutting information of the defect No. (n + 1) of the memory table B Is used to generate defect analysis data from the image memory.

The functional block diagram of the external appearance inspection apparatus of the semiconductor wafer by this invention. The upper surface schematic diagram of a semiconductor wafer. The map figure in an image memory. The image processing operation | movement flowchart. The upper surface schematic diagram of a semiconductor wafer. The upper surface schematic diagram of a semiconductor wafer. The conventional cell comparison flowchart. The cell comparison flowchart by this invention. Explanatory drawing which shows the example of the die comparison inspection by this invention. Explanatory drawing which shows the example of the cell comparison test | inspection by this invention. Explanatory drawing which shows the example of the mixing inspection of the cell comparison inspection by this invention, and die | dye comparison inspection. Explanatory drawing which shows the example which duplicated the memory table. The figure which shows the content of the duplicated memory table.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100: Semiconductor wafer, 101: Sensor, 103: Image processing unit, 104: Memory controller, 105: Image memory, 106: Position shift detection part, 107: Defect determination part, 108: Defect analysis part, 109: Whole controller, 300 : Memory map

Claims (6)

An image memory for storing image data obtained by imaging a semiconductor wafer;
A memory controller that controls the extraction and transfer of image data from the image memory ;
A misregistration detection unit for calculating a misregistration amount of partial images of two regions to be compared on the semiconductor wafer;
A defect determination unit that acquires a difference image of the partial images of the two regions using the positional deviation amount as a correction value, and extracts a defect candidate from the difference image;
A defect analysis unit for analyzing the image extracted as the defect candidate;
An overall controller that controls the overall operation , and
The overall controller calculates a position on the image memory of an inspection image necessary for defect analysis of the defect candidate based on the defect feature amount calculated when the defect candidate is extracted by the defect determination unit. , Relative to the start address on the image memory of the inspection image, the cut-out image size, the region on the semiconductor wafer including the inspection image, and the region on the semiconductor wafer including the reference image corresponding to the inspection image Reference image position information representing the positional relationship is output to the memory controller,
The memory controller for each defect candidate, the start address and by using the clipped image size cut out test image from the image data of said image memory, before Kisaki the reference image position information and the head address and the clipped image size using the preparative and cut out referential image from the image data of said image memory, visual inspection of the semiconductor wafer, characterized in <br/> transfer that test and reference images cut into the defect analyzer apparatus. 2. The semiconductor wafer appearance inspection apparatus according to claim 1, wherein the reference image position information is chip relative position information in die comparison. 2. The semiconductor wafer appearance inspection apparatus according to claim 1, wherein the reference image position information is a cell pitch in cell comparison. An image memory for storing image data obtained by imaging a semiconductor wafer on which a plurality of chips are formed;
A memory controller that controls the extraction and transfer of image data from the image memory ;
A misregistration detection unit for calculating a misregistration amount of partial images of two regions to be compared on the semiconductor wafer;
A defect determination unit that acquires a difference image of the partial images of the two regions using the positional deviation amount as a correction value, and extracts a defect candidate from the difference image;
A defect analysis unit for analyzing the image extracted as the defect candidate;
An overall controller that controls the overall operation , and
The overall controller holds information about the inspection image comparison method in each area in the chip,
The overall controller calculates a position on the image memory of an inspection image necessary for defect analysis of the defect candidate based on the defect feature amount calculated when the defect candidate is extracted by the defect determination unit. And setting identification information corresponding to cell comparison or die comparison based on which region in the chip the position of the defect candidate corresponds to, the start address on the image memory of the inspection image, The cut-out image size, the reference image position information indicating the relative positional relationship between the region on the semiconductor wafer including the inspection image and the region on the semiconductor wafer including the reference image corresponding to the inspection image, and the set Output identification information of cell comparison or die comparison to the memory controller,
The memory controller for each defect candidate, by using said clipped image size as the head address excised test image from the image data of said image memory, before the reference picture position and Kisaki head address and the clipped image size using the information and the cell comparison or die comparison of the identification information cut out a reference image from the image data of said image memory, transfers the test and reference images cut into the defect analyzer <br / > A visual inspection apparatus for semiconductor wafers. In the appearance inspection apparatus for a semiconductor wafer according to claim 4, wherein the reference-image position information, in the case of cell Le comparison cell pitch, visual inspection of the semiconductor wafer, which comprises a relative position information of the chip in the case of die comparison apparatus. In the appearance inspection apparatus for a semiconductor wafer according to claim 4 or 5, wherein said memory controller, and the start address and clipping the image size and the reference image position information and the cell comparison or die comparison of identification information for each defect A semiconductor wafer visual inspection apparatus characterized by holding a recorded memory table.

Images