JP4381880B2 - Timing adjustment circuit - Google Patents

Description

  The present invention generally relates to a timing adjustment circuit in a clock synchronous apparatus, and more particularly to a timing adjustment circuit that adjusts a clock synchronization timing of a data input / output interface.

  FIG. 1 is a diagram showing an example of a configuration in which clock synchronous semiconductor chips are connected. Chips 10 to 13 shown in FIG. 1 operate in synchronization with a clock signal. Data signals output from the chip 10 in synchronization with the clock signal are input to the chips 11 to 13. At this time, input setup time, hold time, maximum output delay, etc. are defined based on the timing of the clock signal, and the chips 10 to 13 perform data signal input / output operations at timings satisfying these specifications. It is required to execute.

  Semiconductor devices have manufacturing variations, and delay fluctuations due to manufacturing variations exist in input / output cells for inputting and outputting data signals. Conventionally, such delay variation has not been a significant problem. However, when the frequency of the clock signal is increased to increase the operation speed of the semiconductor device, the problem of delay variation of input / output cells becomes obvious. In other words, if input / output cell delay variation exists under a high operating frequency, requirements such as input setup time, hold time, and maximum output delay may not be satisfied, and data transmission / reception between chips may not be successful. is there. In addition, it is difficult to accurately transmit and receive data due to differences in signal flight time due to differences in the path length between chips and increased load due to the connection of multiple chips to one output. Become.

  FIG. 2 is a diagram illustrating an example of a timing adjustment circuit that corrects the clock synchronous input / output interface timing. 2 includes a clock input circuit 21, a PLL (Phase Locked Loop) circuit 22, a clock tree 23, a feedback tree 24, an output flip-flop 25, an input flip-flop 26, a data output circuit 27, and A data input circuit 28 is included.

  The clock input circuit 21 receives a clock signal Clock input from the outside of the chip and supplies it to the PLL circuit 22 as an input clock signal ck0. The clock input circuit 21 has a unique delay time A. When the clock input circuit 21 is supplied to the PLL circuit 22, the input clock signal ck0 is delayed by the delay time A from the clock signal Clock. The PLL circuit 22 adjusts the phase of the input clock signal ck0 and outputs the phase-adjusted clock signal ckr. The phase-adjusted clock signal ckr propagates through the clock tree 23 and is then supplied to the output flip-flop 25 and the input flip-flop 26 as the synchronization clock signal ck1. The phase-adjusted clock signal ckr is supplied to the other input of the PLL circuit 22 as a delayed clock signal ckf via the feedback tree 24 having the same delay C ′ as the delay C of the clock tree 23. The PLL circuit 22 performs phase control so that the phases of the input clock signal ck0 and the delayed clock signal ckf are the same, and generates a phase-adjusted clock signal ckr.

  The output flip-flop 25 outputs the output data d0 at the edge timing of the synchronization clock signal ck1. The output data d0 is output to the outside of the chip as a data output signal DataOut by the data output circuit 27. The data output circuit 27 has a unique delay time B, and the data output signal DataOut is delayed by the delay time B from the output data d0.

  The data input circuit 28 receives a data input signal DataIn supplied from the outside of the chip and supplies it as input data d1 to the input flip-flop 26. The input flip-flop 26 takes in the input data d1 at the edge timing of the synchronization clock signal ck1. The data input circuit 28 has a unique delay time A, and the input data d1 is delayed by the delay time A from the data input signal DataIn. Here, the delay time of the data input circuit 28 and the delay time of the clock input circuit 21 are the same.

  FIG. 3 is a timing chart showing the operation timing of the timing adjustment circuit 20 of FIG. As shown in FIG. 3, the input clock signal ck0 is delayed by a delay time A from the clock signal Clock. The phase-adjusted clock signal ckr is phase-adjusted so that the phases of the delayed clock signal ckf and the input clock signal ck0 are the same. Since the delay time C ′ included in the delay clock signal ckf and the delay time C included in the synchronization clock signal ck1 are the same, the phase of the synchronization clock signal ck1 matches the phase of the input clock signal ck0.

  The input data d1 is taken in at the edge timing of the synchronization clock signal ck1. Here, the delay of the synchronizing clock signal ck1 from the clock signal Clock and the delay of the input data d1 from the data input signal DataIn are the same delay time A. Therefore, when the data input signal DataIn is supplied in synchronization with the clock signal Clock, a fixed setup time and hold time can be ensured regardless of the length of the delay time A. In this manner, the timing adjustment circuit 20 of FIG. 2 enables data input at a fixed timing that is not affected by manufacturing variations.

  In FIG. 3, the timing at which the data output signal DataOut is output is the timing delayed by the delay time B from the synchronizing clock signal ck1, that is, the timing delayed by the delay time A + B from the clock signal Clock. The data output signal DataOut is propagated from the chip 10 shown in FIG. 1 to the chip 20 over the flight time FT, for example, and is received by the chip 20 as the data input signal DataIn. When the delay time A + B of the data output signal DataOut increases due to manufacturing variations, the input timing of the data input signal DataIn in the chip 20 is delayed accordingly. In this case, a sufficient setup time cannot be ensured and a data input error may occur.

  FIG. 4 is a diagram illustrating another example of a timing adjustment circuit that corrects the clock synchronous input / output interface timing. 4, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted.

  In the timing adjustment circuit 20A in FIG. 4, a dummy input / output circuit 29 is provided in addition to the configuration of the timing adjustment circuit 20 in FIG. The dummy input / output circuit 29 includes a dummy input circuit 21A having the same delay time A as the clock input circuit 21 and a dummy output circuit 27A having the same delay time B as the data output circuit 27. As a result, the dummy input / output circuit 29 has a delay time of A + B as a whole. By inserting the dummy input / output circuit 29 into the feedback path for phase control, the delayed clock signal ckf input to the PLL circuit 22 has a delay time of A + B + C ′ with respect to the phase-adjusted clock signal ckr. It will be.

  FIG. 5 is a timing chart showing the operation timing of the timing adjustment circuit 20A of FIG. As shown in FIG. 5, the input clock signal ck0 is delayed by a delay time A from the clock signal Clock. The phase-adjusted clock signal ckr is phase-adjusted so that the phases of the delayed clock signal ckf and the input clock signal ck0 are the same. The delayed clock signal ckf is delayed from the phase-adjusted clock signal ckr by a delay time A + B + C ′, and the data output signal DataOut is output from the phase-adjusted clock signal ckr by a delay time C + B. Therefore, the data output signal DataOut is output at a timing earlier by the time A than the delayed clock signal ckf. Since the delayed clock signal ckf is delayed from the clock signal Clock by the delay time A, the output timing of the data output signal DataOut is eventually equal to the edge timing of the clock signal Clock. This state of matching timing is maintained even if the delay times A, B, C, and C ′ vary due to manufacturing variations.

  The data output signal DataOut is propagated from the chip 10 shown in FIG. 1 to the chip 20 over the flight time FT, for example, and is received by the chip 20 as the data input signal DataIn. Since the timing of the data output signal DataOut is fixed with respect to the clock signal Clock regardless of manufacturing variations, the input timing of the data input signal DataIn in the chip 20 is also fixed with respect to the clock signal Clock. Therefore, an appropriate setup time can be ensured and data input can be executed reliably.

  On the data input side of the timing adjustment circuit 20A shown in FIG. 4, the input data d1 is captured at the edge timing of the synchronization clock signal ck1. Here, the input data d1 is delayed from the data input signal DataIn by a delay time A, whereas the synchronization clock signal ck1 is earlier than the clock signal Clock by time B (in FIG. 3, the synchronization clock signal Although ck1 is delayed by a time A from the clock signal Clock, it is earlier than the timing by a delay time A + B of the dummy input / output circuit 29 in FIG. Therefore, when the data input signal DataIn is supplied in synchronization with the clock signal Clock, the setup time and the hold time vary due to variations in the time A and the time B, and it becomes difficult to ensure a prescribed timing condition.

Patent Document 1 shows an example in which a timing adjustment circuit that corrects a clock synchronous input / output interface timing is applied to a memory.
JP-A-10-112182

  As described above, when the timing is controlled by the timing adjustment circuit so that the data input timing is not affected by the manufacturing variation, the data output timing is affected by the manufacturing variation, and an appropriate input timing is set on the data receiving side of the partner semiconductor device. It cannot be secured. If the timing is controlled by the timing adjustment circuit so that the data output timing is not affected by the manufacturing variation, the data input timing is affected by the manufacturing variation and an appropriate input timing cannot be ensured.

  In view of the above, an object of the present invention is to provide a timing adjustment circuit that realizes an operation at an appropriate timing for both data input and data output without being affected by manufacturing variations.

A timing adjustment circuit according to the present invention includes a PLL circuit that generates a clock signal whose phase is adjusted in accordance with a phase comparison between an input clock signal and a delayed clock signal, and the delayed clock signal by delaying the phase-adjusted clock signal. As a feedback path to be supplied to the PLL circuit, a first timing correction circuit for delaying a signal by a predetermined delay time on the feedback path, and output data to be output to the outside according to the phase-adjusted clock signal An output data circuit provided at a first timing; a second timing correction circuit that delays the first timing by the predetermined delay time to generate a second timing different from the first timing; and an external input an input data circuit for taking the input data at the timing of the second, first delay external clock signal A clock input circuit that supplies the PLL circuit as an input clock signal with a delay, and a data output circuit that outputs the output data supplied from the output data circuit to the outside with a second delay time; A data input circuit for delaying external data by the first delay time and supplying the input data to the input data circuit as the input data, the predetermined delay time of the first and second timing correction circuits being It is characterized by being substantially equal to the sum of the first delay time and the second delay time .

  As suggested by the timing adjustment circuit described above, according to at least one embodiment of the present invention, a first timing correction circuit having a predetermined delay time is inserted into a feedback path for phase control, and input synchronization is performed. A second timing correction circuit having the predetermined delay time is inserted in the path through which the clock signal for propagation is propagated. By the operation of the first timing correction circuit, the output data is always output at a fixed timing with respect to the external clock signal without being affected by manufacturing variations. Also, by canceling the delay time of the first timing correction circuit by the action of the second timing correction circuit, the input data is always captured at a fixed timing with respect to the external clock signal without being affected by manufacturing variations. . Thereby, it is possible to realize a stable and reliable data input / output operation for both data input and data output without being affected by delay variation of the data input / output circuit due to manufacturing variations.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 6 is a diagram showing an example of a timing adjustment circuit according to the present invention. 6 includes a clock input circuit 31, a PLL circuit 32, a clock tree 33, a feedback tree 34, an output flip-flop (output data circuit) 35, an input flip-flop (input data circuit) 36, and a data output. Circuit 37, data input circuit 38, dummy input / output circuit (first timing correction circuit) 39, and input timing correction circuit (second timing correction circuit) 40.

  The clock input circuit 31 receives a clock signal Clock input from the outside of the chip and supplies it to the PLL circuit 32 as an input clock signal ck0. The clock input circuit 31 has a unique delay time A. When the clock input circuit 31 is supplied to the PLL circuit 32, the input clock signal ck0 is delayed by the delay time A from the clock signal Clock. The PLL circuit 32 adjusts the phase of the input clock signal ck0 and outputs a phase-adjusted clock signal ckr. The phase-adjusted clock signal ckr propagates through the clock tree 33 and is then supplied to the output flip-flop 35 as the synchronization clock signal ck1. The synchronization clock signal ck1 is further supplied as the synchronization clock signal ck11 to the input flip-flop 36 via the input timing correction circuit 40. The input timing correction circuit 40 includes a dummy input circuit 31B having the same delay time A as the clock input circuit 31 and a dummy output circuit 37B having the same delay time B as the data output circuit 37. As a result, the input timing correction circuit 40 provides a delay time of A + B as a whole.

  Further, the phase-adjusted clock signal ckr propagates through the feedback tree 34 having the same delay C ′ as the delay C of the clock tree 33, and then passes through the dummy input / output circuit 39 and then as the delayed clock signal ckf to the other side of the PLL circuit 32. Supplied to the input. The dummy input / output circuit 39 includes a dummy input circuit 31A having the same delay time A as the clock input circuit 31 and a dummy output circuit 37A having the same delay time B as the data output circuit 37. As a result, the dummy input / output circuit 39 provides a delay time of A + B as a whole. The PLL circuit 32 performs phase control so that the phases of the input clock signal ck0 and the delayed clock signal ckf are the same, and generates a phase-adjusted clock signal ckr.

  The output flip-flop 35 outputs the output data d0 at the edge timing of the synchronization clock signal ck1. The output data d0 is output to the outside of the chip as a data output signal DataOut by the data output circuit 37. The data output circuit 37 has a unique delay time B, and the data output signal DataOut is delayed by the delay time B from the output data d0.

  The data input circuit 38 receives a data input signal DataIn supplied from the outside of the chip and supplies it as input data d1 to the input flip-flop 36. The input flip-flop 36 takes in the input data d1 at the edge timing of the synchronization clock signal ck11. The data input circuit 38 has a unique delay time A, and the input data d1 is delayed by the delay time A from the data input signal DataIn. Here, the delay time of the data input circuit 38 and the delay time of the clock input circuit 31 are the same.

  FIG. 7 is a timing chart showing the operation timing of the timing adjustment circuit 30 of FIG. As shown in FIG. 7, the input clock signal ck0 is delayed by a delay time A from the clock signal Clock. The phase-adjusted clock signal ckr is phase-adjusted so that the phases of the delayed clock signal ckf and the input clock signal ck0 are the same. The delayed clock signal ckf is delayed by a delay time A + B + C ′ from the phase-adjusted clock signal ckr, and the synchronization clock signal ck11 is delayed by a delay time A + B + C from the phase-adjusted clock signal ckr. Since the delay time C ′ included in the delay clock signal ckf and the delay time C included in the synchronization clock signal ck11 are the same, the phase of the synchronization clock signal ck11 matches the phase of the delay clock signal ckf, and Corresponds to the phase of the input clock signal ck0.

  The input data d1 is taken in at the edge timing of the synchronization clock signal ck11. Here, the delay of the synchronizing clock signal ck11 from the clock signal Clock and the delay of the input data d1 from the data input signal DataIn are the same delay time A. Therefore, when the data input signal DataIn is supplied in synchronization with the clock signal Clock, a fixed setup time and hold time can be ensured regardless of the length of the delay time A. In this manner, the timing adjustment circuit 30 in FIG. 6 enables data input at a fixed timing that is not affected by manufacturing variations.

  The delayed clock signal ckf is delayed from the phase-adjusted clock signal ckr by a delay time A + B + C ′, and the data output signal DataOut is output from the phase-adjusted clock signal ckr by a delay time C + B. Therefore, the data output signal DataOut is output at a timing earlier by the time A than the delayed clock signal ckf. Since the delayed clock signal ckf is delayed from the clock signal Clock by the delay time A, the output timing of the data output signal DataOut is eventually equal to the edge timing of the clock signal Clock. This state of matching timing is maintained even if the delay times A, B, C, and C ′ vary due to manufacturing variations.

  This data output signal DataOut propagates from the first chip to the second chip over the flight time FT and is received by the second chip as the data input signal DataIn. Since the timing of the data output signal DataOut is fixed with respect to the clock signal Clock regardless of manufacturing variations, the input timing of the data input signal DataIn in the second chip is also fixed with respect to the clock signal Clock. Therefore, an appropriate setup time can be ensured and data input can be executed reliably.

  As described above, in the above embodiment of the present invention, the dummy input / output circuit (first timing correction circuit) 39 having the delay time A + B is inserted in the feedback path of the phase control, and the synchronization clock signal for input is propagated. An input timing correction circuit (second timing correction circuit) 40 having a delay time A + B is inserted in the path to be transmitted. Due to the function of the dummy input / output circuit 39, the data output signal is always output at a fixed timing with respect to the clock signal Clock without being affected by manufacturing variations. Further, by canceling the delay time of the dummy input / output circuit 39 by the operation of the input timing correction circuit 40, the data input signal is always fetched at a fixed timing with respect to the clock signal Clock without being affected by manufacturing variations. Thereby, it is possible to realize a stable and reliable data input / output operation for both data input and data output without being affected by delay variation of the data input / output circuit due to manufacturing variations.

  FIG. 8 is a diagram showing a modification of the timing adjustment circuit according to the present invention. In FIG. 8, the same components as those of FIG. 6 are referred to by the same reference numerals, and a description thereof will be omitted.

  The timing adjustment circuit 30A in FIG. 8 includes a phase compensation circuit 41, external terminals 51 and 52, a flight time compensation signal line 53, external terminals 54 and 55, flight time, in addition to the configuration of the timing adjustment circuit 30 in FIG. A compensation signal line 56 is included. Here, the flight time compensation signal lines 53 and 56 may be provided outside the chip when the chip is mounted on a printed circuit board or the like as shown in FIG. Therefore, the flight time compensation signal lines 53 and 56 are an essential component of the timing adjustment circuit according to the present invention in that they are not provided as a part of individual chips on which the timing adjustment circuit according to the present invention is mounted. Not necessary.

  The dummy input / output circuit 39A includes the external terminals 51 and 52 and the flight time compensation signal line 53, thereby providing a delay time of A + B + FT. Here, the flight time compensation signal line 53 is a signal line that extends from the external terminal 52 halfway and returns to the external terminal 51 in the path toward the counterpart chip to which the data output signal DataOut is supplied. Good.

  The input timing correction circuit 40A includes the external terminals 54 and 55 and the flight time compensation signal line 56, thereby providing a delay time of A + B + FT. Here, the flight time compensation signal line 56 is a signal line that extends from the external terminal 54 to the middle and then returns to the external terminal 55 in the path toward the counterpart chip to which the data output signal DataOut is supplied. Good.

  The phase compensation circuit 41 is an inverter in the example of FIG. 8 and realizes a phase delay of 180 degrees by inverting the synchronization clock signal ck1. As a result, it becomes easy to set the input data d1 capture timing at a position substantially in the middle of the data valid period. In general, the optimum setup time and data hold time can be realized by taking in data at a position approximately in the middle of the data valid period.

  FIG. 9 is a timing chart showing the operation timing of the timing adjustment circuit 30 of FIG. As shown in FIG. 9, there is a time difference of A + B + C ′ + FT between the phase-adjusted clock signal ckr and the delayed clock signal ckf. Therefore, there is a time difference of B + C ′ + FT between the clock signal Clock and the phase-adjusted clock signal ckr. The data output signal DataOut is output at a timing after the delay time C + B from the phase-adjusted clock signal ckr. Since C and C ′ are equal, the output timing of the data output signal DataOut is FT time before the edge timing of the clock signal Clock. When the data output signal DataOut reaches the second chip from the first chip over the flight time FT, the reception timing of the data input signal DataIn in the second chip is aligned with the edge timing of the clock signal Clock.

  The phase-adjusted clock signal ckr is delayed by a time C to become a synchronizing clock signal ck1, and this synchronizing clock signal ck1 is further delayed by T / 2 by inversion to become a synchronizing clock signal ck10. Here, T is the cycle of the clock signal Clock. The synchronization clock signal ck10 is delayed by the delay time A + B + FT by the input timing correction circuit 40A to become the synchronization clock signal ck11. As a result, the synchronization clock signal ck11 has an edge timing delayed by time A + T / 2 from the clock signal Clock. When the input data d1 delayed by the time A from the data input signal DataIn is fetched at the edge timing of the synchronizing clock signal ck11, the time A is canceled and the time difference of T / 2 is at the midpoint of the data valid period. Data can be imported. In this case, it is assumed that the data input signal DataIn is supplied in synchronization with the edge of the clock signal Clock.

  FIG. 10 is a diagram illustrating a configuration when the data input terminal and the data output terminal are common. 10, the same elements as those in FIG. 6 and the like are referred to by the same numerals, and a description thereof will be omitted.

  As shown in FIG. 10, when the data input terminal and the data output terminal are common, it is necessary to use the data output circuit 37C that can set the output to the HIGH impedance state. In the data output circuit 37C, by switching the input to the control terminal 60, it is possible to control whether the circuit output is set to a HIGH impedance state or a state in which a HIGH / LOW data level is output. it can. In this case, a flip-flop 35C having the same configuration as that of the output flip-flop 35 is provided, and the flip-flop 35C is operated in synchronization with the synchronization clock signal ck1, and the output of the flip-flop 35C is used as a control signal input to the control terminal 60. To do. Thereby, the input timing of the control signal to the control terminal 60 can be synchronized with the timing of the data input / output signal.

  FIG. 11 is a circuit diagram showing an example of the configuration of the phase compensation circuit 41. In FIG. 8, the case where the phase compensation circuit 41 is an inverter is shown as an example. However, since the inverter is accompanied by a slight delay, a phase delay of 180 degrees cannot be realized accurately. The phase compensation circuit 41 in FIG. 11 is an example of a circuit that can realize a phase delay of exactly 180 degrees.

  11 includes flip-flops 71 and 72, an inverter 73, and a NAND gate 74. The flip-flops 71 and 72 receive a clock signal CLK2 having a double frequency from the PLL circuit 32 (see FIG. 6), and operate in synchronization with the clock signal at the edge timing. Accordingly, the synchronization clock signal ck1 that is the output of the flip-flop 71 and the synchronization clock signal ck10 that is the output of the flip-flop 72 completely coincide with each other in edge timing. The synchronization clock signal ck 1 is inverted by the inverter 73 and supplied to the input terminal of the flip-flop 72. The synchronizing clock signal ck10 is inverted by the NAND gate 74 and supplied to the input terminal of the flip-flop 71. The synchronization signal input to the NAND gate 74 is normally HIGH, and the NAND gate 74 operates as an inverter.

  FIG. 12 is a timing chart for explaining the operation of the phase compensation circuit 41 of FIG. As shown in FIG. 12, the synchronization clock signal ck1 synchronized with the edge timing of the clock signal CLK2 is inverted to become a signal b, and this signal b is synchronized with the edge timing of the clock signal CLK2, thereby synchronizing clock. Signal ck10 is obtained. Further, the synchronizing clock signal ck10 synchronized with the edge timing of the clock signal CLK2 is inverted to become a signal a, and this signal a becomes the synchronizing clock signal ck10 by synchronizing with the edge timing of the clock signal CLK2.

  With the above operation, the synchronization clock signal ck10 is a signal that is accurately 180 degrees out of phase with the synchronization clock signal ck1.

  FIG. 13 is a diagram illustrating an example of the configuration of the PLL circuit 32. 13 includes a phase difference detection circuit 81, a control voltage generation circuit 82, and a VCO (voltage control oscillator) 83. The phase difference detection circuit 81 is a circuit that detects the phase difference between the input clock signal ck0 and the delayed clock signal ckf. Specifically, when the phase of the delayed clock signal ckf is earlier than the phase of the input clock signal ck0, the control voltage generation circuit 82 is controlled so as to lower the oscillation frequency of the VCO 83. When the phase of the delayed clock signal ckf is later than the phase of the input clock signal ck0, the control voltage generation circuit 82 is controlled to increase the oscillation frequency of the VCO 83. Further, when the phase of the delayed clock signal ckf matches the phase of the input clock signal ck0, the control voltage generation circuit 82 is controlled to maintain the current oscillation frequency of the VCO 83. Based on the output of the phase difference detection circuit 81, the control voltage generation circuit 82 generates a control voltage vcntl that is a signal for controlling the oscillation frequency of the VCO 83. The VCO 83 adjusts the frequency of the phase-adjusted clock signal ckr based on the voltage value of the control voltage vcntl.

  FIG. 14 is a diagram illustrating another example of the configuration of the PLL circuit 32. The configuration of FIG. 14 is a circuit generally called a DLL (delay locked loop), and is a form of a PLL circuit in a broad sense. The PLL circuit 32 of FIG. 14 includes a phase difference detection circuit 91, a delay control circuit 92, and a variable delay circuit 93. The phase difference detection circuit 91 is a circuit that detects the phase difference between the input clock signal ck0 and the delayed clock signal ckf. Specifically, when the phase of the delay clock signal ckf is earlier than the phase of the input clock signal ck0, the delay control circuit 92 is controlled so as to increase the delay time of the variable delay circuit 93. When the phase of the delayed clock signal ckf is later than the phase of the input clock signal ck0, the delay control circuit 92 is controlled so as to shorten the delay time of the variable delay circuit 93. Further, when the phase of the delay clock signal ckf matches the phase of the input clock signal ck0, the delay control circuit 92 is controlled to maintain the current delay time of the variable delay circuit 93. The delay control circuit 92 generates a control pointer that is a signal for controlling the delay time of the variable delay circuit 93 based on the output of the phase difference detection circuit 91. The variable delay circuit 93 adjusts the delay time of the phase-adjusted clock signal ckr based on the value indicated by the control pointer.

  The PLL circuit 32 (DLL circuit) in FIG. 14 only adjusts the delay time, whereas the PLL circuit 32 in FIG. 13 has a difference that the phase is adjusted by adjusting the oscillation frequency. The PLL circuit 32 of FIG. 13 has an advantage that a frequency signal can be obtained at the output portion of the VCO 83 by further providing a frequency divider at the output portion of the VCO 83 to divide the oscillation frequency. Such a multiplied frequency signal can be used as, for example, the clock signal CLK2 shown in FIGS.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of the structure which connected the clock synchronous type semiconductor chip. It is a figure which shows an example of the timing adjustment circuit which correct | amends a clock synchronous input / output interface timing. FIG. 3 is a timing chart showing operation timing of the timing adjustment circuit of FIG. 2. It is a figure which shows another example of the timing adjustment circuit which correct | amends a clock synchronous input / output interface timing. FIG. 5 is a timing chart showing operation timing of the timing adjustment circuit of FIG. 4. It is a figure which shows an example of the timing adjustment circuit by this invention. FIG. 7 is a timing chart showing operation timing of the timing adjustment circuit of FIG. 6. It is a figure which shows the modification of the timing adjustment circuit by this invention. FIG. 9 is a timing chart showing operation timing of the timing adjustment circuit of FIG. 8. It is a figure which shows a structure in case a data input terminal and a data output terminal are common. It is a circuit diagram which shows an example of a structure of the circuit for phase compensation. FIG. 12 is a timing chart for explaining the operation of the phase compensation circuit of FIG. 11. It is a figure which shows an example of a structure of a PLL circuit. It is a figure which shows another example of a structure of a PLL circuit.

Explanation of symbols

30 timing adjustment circuit 31 clock input circuit 32 PLL circuit 33 clock tree 34 feedback tree 35 output flip-flop 36 input flip-flop 37 data output circuit 38 data input circuit 39 dummy input / output circuit 40 input timing correction circuit

Claims (9)

A PLL circuit that generates a phase-adjusted clock signal according to a phase comparison between an input clock signal and a delayed clock signal;
A feedback path for delaying the phase-adjusted clock signal and supplying the delayed clock signal to the PLL circuit;
A first timing correction circuit for delaying a signal by a predetermined delay time on the feedback path;
An output data circuit for providing output data to be output to the outside at a first timing according to the phase-adjusted clock signal;
A second timing correction circuit for generating a second timing different from the first timing by delaying the first timing by the predetermined delay time;
An input data circuit that captures input data input from the outside at the second timing ;
A clock input circuit that delays an external clock signal by a first delay time and supplies the external clock signal to the PLL circuit as the input clock signal;
A data output circuit for outputting the output data supplied from the output data circuit to the outside with a second delay time;
Data input circuit for delaying external data by the first delay time and supplying the input data to the input data circuit as the input data
And the predetermined delay time of the first and second timing correction circuits is substantially equal to the sum of the first delay time and the second delay time . Each of the first timing correction circuit and the second timing correction circuit has a configuration in which a circuit having the same configuration as the clock input circuit and a circuit having the same configuration as the data output circuit are connected in series. The timing adjustment circuit according to claim 1 . The terminal for outputting the output data to the outside and the terminal for inputting the input data from the outside are common, and the data output circuit is configured to be set to a HIGH impedance state, and the setting of the HIGH impedance state is the first 2. The timing adjustment circuit according to claim 1 , wherein the timing adjustment circuit is controlled at a timing of 1 .   Each of the first timing correction circuit and the second timing correction circuit further includes an externally connectable terminal for connecting the long distance wiring to further include a delay time due to the long distance wiring. The timing adjustment circuit according to claim 1, wherein:   2. The timing adjustment circuit according to claim 1, further comprising a phase compensation circuit for shifting the phase of the signal by approximately 180 degrees in the path for generating the second timing. 6. The timing adjustment circuit according to claim 5 , wherein the phase compensation circuit is an inverter. 6. The timing adjustment circuit according to claim 5 , wherein the phase compensation circuit includes two flip-flops that operate in synchronization with a clock signal having a frequency twice that of the input clock signal. The PLL circuit
A phase difference detection circuit for detecting a phase difference between the input clock signal and the delayed clock signal;
A control voltage generation circuit for generating a control voltage in accordance with the output of the phase difference detection circuit;
A VCO that generates the phase-adjusted clock signal by oscillating at a frequency according to the control voltage
The timing adjustment circuit according to claim 1, further comprising: The PLL circuit
A phase difference detection circuit for detecting a phase difference between the input clock signal and the delayed clock signal;
A delay control circuit that generates a control signal according to the output of the phase difference detection circuit;
2. The timing adjustment circuit according to claim 1, further comprising a variable delay circuit that generates the phase-adjusted clock signal by delaying the input clock signal by a delay time corresponding to the control signal.

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