JP4374892B2 - Variable capacitance circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a MOS capacitance circuit having a high variable sensitivity and a wide variable range of capacitance by applying a control voltage and an output voltage, obtained by amplifying the control voltage through an inversion amplifier, directly or through an input resistance to one and the other terminals of a MOS capacitive element, respectively. <P>SOLUTION: A control voltage and an output voltage, obtained by amplifying the control voltage through an inversion amplifier, are applied directly or through an input resistance to one and the other terminals of the MOS capacitive element, respectively. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable capacitance circuit, and more particularly to a variable capacitance circuit used for frequency temperature compensation, frequency voltage control, or center frequency adjustment in a piezoelectric oscillator or the like.
[0002]
[Prior art]
Conventionally, a variable capacitance element is used as a frequency adjusting means in an oscillation circuit such as a crystal oscillator, and a bipolar type varicap diode is most commonly used as the variable capacitance element. On the other hand, with respect to crystal oscillators and the like, ICs of oscillation circuits are being advanced in order to meet demands for miniaturization and cost reduction. In order to make this oscillation circuit into an IC, a MOS process is generally adopted. On the other hand, since a varicap diode is a bipolar type, two different processes are required for making a one-chip IC. It is in a situation where it becomes inevitably expensive as complexity increases.
[0003]
In view of this, MOS capacitors are currently attracting attention as variable capacitors that replace varicap diodes. This MOS capacitance element can be manufactured by the same process as a C-MOS type inverter amplifier or the like generally used as an oscillation amplifier circuit. Furthermore, the MOS capacitor element has a feature that a large capacitance change can be obtained even with a small voltage change. Under the circumstances where the voltage applied to the variable capacitor element is inevitably reduced as the voltage of the circuit progresses, for example, When used in a voltage controlled crystal oscillator, a sufficiently large frequency variable sensitivity can be expected in practical use.
[0004]
FIG. 7 shows an example of the capacitance characteristic of the MOS capacitance element, and it can be seen that a high variable sensitivity of about 30 pF / V is exhibited between −1V and + 0.5V. Also, in this example, the capacitance value tends to increase as the control voltage increases. However, the polarity of the capacitance characteristics changes depending on the difference between the N-type and P-type MOS capacitance elements and the direction of the applied voltage. It is also possible to realize a variable capacitance element whose capacitance value decreases as the voltage increases.
[0005]
As an example of use of the MOS capacitor element, as disclosed in JP-A-11-17114, a control voltage is connected to one terminal of the MOS capacitor element via an input resistor, and an input resistor is connected to the other terminal. In general, a reference voltage is connected. FIG. 8 shows an example of use of a conventional MOS capacitor element. At this time, when the reference voltage is set near the center of the variable width of the control voltage and the control voltage is swept from the negative voltage to the positive voltage with respect to the reference voltage, the capacitance changes as shown in FIG. Appears.
[0006]
However, when this MOS capacitor element is used in an oscillation circuit, that is, when the AC component is superimposed on the control voltage as shown in the circuit diagram of FIG. The steepness of variable sensitivity of the capacitive element is lost.
[0007]
The mechanism will be described with reference to FIG. FIG. 4A shows the MOS capacitance characteristics, where the horizontal axis is the control DC voltage and the vertical axis is the capacitance value. Here, for the sake of simplicity, the capacitance characteristic is a complete step characteristic and is shown by a solid line 101. Since the voltage applied to both ends of the MOS capacitor element is the difference between the reference voltage and the control voltage, it is assumed here that the reference voltage is 0 V and only the control voltage changes.
FIG. 5B shows a change in a control voltage (hereinafter referred to as an AC superimposed control voltage) on which an AC voltage is superimposed. In FIG. 5B, the AC superposition control voltage when the same AC component is superposed for one period is overwritten on three different control voltages (DC components).
[0008]
Now, when the control voltage (DC component) is shifted from the point 102 on the step characteristic 101 shown in FIG. 10A to the point 103 and then to the point 104 in the direction in which the voltage decreases, the AC superposition control voltage also changes. The waveform 106 having the center value 105 shifts to the waveform 108 having the center value 107 and the waveform 110 having the center value 109.
When the control voltage is at point 102, the AC superposition control voltage operates only with a positive voltage in the region to the right of the vertical axis as in the waveform of 106, so that its capacitance value does not change constantly and remains at the value at point 102. is there.
[0009]
However, when the control voltage is shifted to the point 103, the AC superposition control voltage 108 has a time region spanning the negative voltage, and the capacitance value becomes 0 for the time of the shaded area 111 region. Therefore, the average capacitance value at that time moves to the lower point 112 than the capacitance value at the point 103.
[0010]
Further, when the control voltage is shifted to the point 104 of 0V, the AC superposition control voltage is shifted to 110, but the shaded portion 113 in the time region spanning the negative voltage has the same area as the time region spanning the positive voltage, so the average capacitance value is It does not change. Further, when the control voltage is further shifted to the point 114, the capacity value is increased by the time region in which the AC superposition control voltage spans the positive voltage as in the case of the point 103, and the average capacity value is shifted to the point 115. .
[0011]
This phenomenon is the same even if the capacity characteristic is not a perfect step characteristic, and the steepness of the capacity characteristic tends to be lost.
[0012]
In addition, as the output level of the superimposed AC voltage increases, the steepness tends to be lost. As described above, it can be easily understood in view of the fact that there is a time region spanning a negative voltage when the amplitude of the AC component of the AC superimposed voltage 106 increases. The effect is shown in FIG. This is a simulation result when the amplitude level of the AC component in the circuit configuration of FIG. 9 is increased in steps of 0.4 V from 0.2 Vp-p to 2.0 Vp-p.
[0013]
[Problems to be solved by the present invention]
As described above, when a MOS capacitor circuit having this configuration is inserted into an oscillation loop such as a crystal oscillator, it can be seen that the variable sensitivity deteriorates due to the influence of the AC component. Further, if the capacitance characteristic is large and loses its steepness and is smoothed, the variable capacitance range becomes narrow in a certain variable range of the control voltage. In this situation, there is a possibility that sufficient frequency control may be difficult under a situation where the circuit voltage is lowered and a sufficient variable range of the control voltage cannot be secured.
[0015]
According to the first aspect of the present invention, in a parallel circuit composed of a plurality of MOS capacitors connected in parallel with the same polarity, a control voltage is inverted and amplified by an inverting amplifier at one end of the parallel circuit and the control voltage at the other end. The output voltage is applied directly or via an input resistor, respectively.
[0016]
According to a second aspect of the present invention, there is provided a parallel circuit in which a series circuit in which a MOS capacitor element and a DC blocking fixed capacitor are connected in series is provided in parallel with a plurality of MOS capacitor elements having the same polarity. A control voltage is applied to one end of each MOS capacitance element, and an output voltage obtained by inverting and amplifying the control voltage with an inverting amplifier is applied to the other end, either directly or via an input resistor.
[0019]
[Embodiments of the Invention]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This is a simple example in which an inverting amplifier is composed of an OP amplifier. A control voltage is connected to one terminal of a MOS capacitor via an input resistor 1 and the control voltage is inverted and amplified by the inverting amplifier. Is connected to the other terminal via the input resistor 2. The AC blocking input resistors 1 and 2 may be omitted when the control voltage and the output impedance of the inverting amplifier are sufficiently high in practical use and are not affected by the AC component, and the polarity of the MOS capacitor element is reversed. It does not matter.
[0020]
Here, the OP amplifier is used with a single power supply, the positive power supply side is connected to Vcc, the negative power supply side is connected to GND, and Vb is applied to the non-inverting input terminal as a bias. The output terminal 3 and the inverting input terminal of the OP amplifier are negative-feedback connected via a resistor R2, and a control voltage is connected to the inverting input terminal via a resistor R1. The operation of the OP amplifier is already well known and will not be described. However, the operation of the circuit of this inverting amplifier is the difference in potential between the control voltage applied to the input terminal 4 and the bias Vb applied to the non-inverting input terminal. Is output to the output terminal 3. The gain is-(R1 / R2) times and can be easily adjusted.
[0021]
Hereinafter, the variable range of the voltage that can be applied to both ends of the MOS capacitor element of this circuit and the variable sensitivity of the capacitor with respect to the control voltage will be described with reference to FIG.
The horizontal axis in FIG. 2 represents the displacement time, and the vertical axis represents the voltage. Here, the control voltage variable range is set to GND to Vcc indicated by an arrow 21 in the figure, and changes as shown by a straight line 22 in the figure. Further, the output voltage active range that is a voltage range in which the output of the inverting amplifier is possible is a range from the saturation voltage Vs1 on the negative voltage side to the saturation voltage Vs2 on the positive voltage side indicated by an arrow 23 in the drawing.
[0022]
Now, when the gain of the inverting amplifier is set to −1, it can be seen that the output 24 of the inverting amplifier decreases as the control voltage 22 increases with time. That is, the direction of the voltage applied to the MOS capacitance element is reversed at the point of Vb, and when the control voltage 22 is lower than Vb, that is, in the region on the left side of the vertical axis in FIG. Thus, in the state where the voltage is applied from the output 24 side of the inverting amplifier toward the control voltage 22 side and the control voltage 22 is higher than Vb, that is, in the region on the right side of the vertical axis in FIG. As shown, a voltage is applied from the control voltage 22 side toward the output 24 side of the inverting amplifier.
Conventionally, since the reference voltage is fixed at Vb, the control voltage 22 is applied to one end of the MOS capacitor and the reference voltage Vb is always applied to the other end (arrows 25a and 26a in the figure). .
In other words, in the case of this embodiment, a voltage about twice that of the conventional case can be applied across the MOS capacitor element.
[0023]
In the output voltage active range, even when the gain of the inverting amplifier is −1, the voltage displacement speed at both ends of the MOS capacitor element corresponds to twice that when only the control voltage is varied as in the prior art, that is, variable. Sensitivity is also equivalent to twice.
Further, the output of the inverting amplifier when the gain is -2 times follows the saturation voltage Vs2 on the positive voltage side as the control voltage 22 increases from GND to Vcc, and is indicated by a straight line 27 in the figure. Thus, from point A to point B that reaches saturation voltage Vs1 on the negative voltage side, it decreases at a displacement rate twice that of control voltage 22 and follows saturation voltage Vs1 on the negative voltage side. Therefore, in the output voltage active range (from point A to point B), the displacement speed of the voltage across the MOS capacitor element is tripled, that is, the variable sensitivity is tripled.
[0024]
Similarly, the output voltage of the inverting amplifier when the gain of the inverting amplifier is −3 times is shown by a straight line 28 in the figure, a straight line 29 when the gain is −4 times, and a straight line 30 when the gain is −5 times. Therefore, a high variable sensitivity of (| gain | +1) times is realized in each output voltage active range.
[0025]
This is an effect limited to the active range of the output voltage. However, since the MOS capacitor element only needs to exhibit a steep capacitance characteristic in the vicinity of 0 V, in this case, in the vicinity of the bias Vb of the inverting amplifier, no problem occurs.
[0026]
Therefore, by adjusting the gain of the inverting amplifier, the steepness of the capacitance characteristic lost due to the superimposed AC voltage can be recovered, and the effect is shown in FIG. This shows a capacitance characteristic when the reference voltage of one terminal of the conventional MOS capacitor is fixed, and a capacitance characteristic when the gain is changed from -1 to -5 times when an inverting amplifier is used. It can be seen that the variable sensitivity increases as the absolute value of the gain increases.
[0027]
FIG. 4 shows a second embodiment of the variable capacitance circuit according to the present invention. This is because a control voltage is connected to one connection terminal of a parallel circuit composed of three MOS capacitors connected in parallel with the same polarity via an input resistor 41, and the control voltage is connected to the other terminal via an input resistor 42. In this configuration, an output voltage obtained by inverting and amplifying the voltage with an inverting amplifier is connected. The AC blocking input resistors 41 and 42 may be omitted if the voltage source of the control voltage and the output impedance of the inverting amplifier are practically high and are not affected by the AC component, and the polarity of the MOS capacitor element. Of course, all may be reversed.
[0028]
This realizes a wider variable range by controlling the parallel combined capacitance of a plurality of MOS capacitance elements. For example, when three MOS capacitance elements having capacitance characteristics varying from 15 pF to 60 pF are connected in parallel as shown in FIG. 4, a MOS capacitance circuit having a wide variable range of 45 pF to 180 pF is obtained. It is also possible to obtain desired capacitance characteristics by combining MOS capacitance elements having different capacitance characteristics.
Although the description has been given here with three MOS capacitance elements, there is no limitation on the number of the MOS capacitance elements.
[0029]
FIG. 5 shows a third embodiment of the variable capacitance circuit according to the present invention. This is because a MOS capacitor element 51 and a DC capacitor fixed capacitor 52 connected in series, a MOS capacitor element 53 and a fixed capacitor 54 series circuit, and a MOS capacitor element 55 and a fixed capacitor 56 series circuit are connected to the MOS. In a parallel circuit in which the polarities of the capacitive elements are aligned and connected in parallel, a control voltage is connected to a common end of each MOS capacitive element of the parallel circuit, that is, a connection point A of the parallel circuit via an input resistor 57, and this control is performed. An output voltage obtained by inverting and amplifying the voltage by each inverting amplifier is connected to a connection midpoint between each MOS capacitor element and a fixed capacitor via input resistors 58, 59 and 60.
[0030]
Here, the DC blocking fixed capacitors 52, 54 and 56 are for preventing the output voltages from the respective inverting amplifiers from interfering with each other via the connection point B of the parallel circuit. It is possible to omit only.
Here, the AC blocking input resistors 57, 58, 59, 60 may be omitted if the voltage source of the control voltage and the output impedance of each inverting amplifier are practically high and are not affected by the AC component. Of course, all the polarities of the MOS capacitor elements may be reversed.
[0031]
Similar to the second embodiment, a wide range of variable width is realized by controlling the parallel combined capacitance of a plurality of MOS capacitance elements, and a desired capacitance can be obtained by combining MOS capacitance elements having different capacitance characteristics. Capacitance characteristics can also be obtained. In addition, the variable sensitivity can be adjusted by using inverting amplifiers having different gains or by adjusting the gains of the respective inverting amplifiers, and can be further adjusted to a desired capacitance characteristic.
Although the description has been given here with three MOS capacitance elements, there is no limitation on the number of the MOS capacitance elements.
[0032]
FIG. 6 shows a fourth embodiment of the variable capacitance circuit according to the present invention. This is because in a series circuit in which the MOS capacitor elements 61 and 62 are connected to each other, the MOS capacitor elements 62 and 63 are connected to each other, and three MOS capacitor elements are connected in series. A control voltage is connected to the gate electrode side connection points A1 and A2 via input resistors 64 and 66, and a control voltage is connected to the connection points B1 and B2 on the counter electrode side of the MOS capacitance element via input resistors 65 and 67. Is connected to the output voltage inverted by an inverting amplifier.
[0033]
Here, the input resistors 64 and 66 connected to the gate electrode side and the input resistors 65 and 67 connected to the counter electrode side are practically sufficiently high in the output voltage of the control voltage source and the inverting amplifier, and are influenced by the AC component. If there is no, only one can be omitted on each electrode side. Naturally, the polarities of the MOS capacitor elements may be reversed.
[0034]
This realizes a variable capacitance range from a low capacitance value by controlling the series combined capacitance of a plurality of MOS capacitance elements. For example, if three MOS capacitance elements having capacitance characteristics varying from 15 pF to 60 pF are connected in series as shown in FIG. 6, the capacitance is from 5 pF to 20 pF. It is also possible to obtain desired capacitance characteristics by combining MOS capacitance elements having different capacitance characteristics.
Although the description has been given here with three MOS capacitance elements, there is no limitation on the number of the MOS capacitance elements.
[0035]
1, FIG. 4, FIG. 5 and FIG. 6 described in the above embodiments of the variable capacitance circuit according to the present invention, means for adjusting the gain as an inverting amplifier included in each circuit diagram, for example, the feedback of FIG. By adopting a variable resistance element as the resistance R2, each variable sensitivity can be set to an arbitrary value.
[0036]
【The invention's effect】
As described above, when the MOS capacitor is used as a variable capacitor for adjusting the frequency of the oscillation circuit, there is a possibility that the variable sensitivity characteristic is deteriorated due to the influence of the superimposed AC voltage. However, by using the circuit method proposed this time, it became possible to realize a larger variable sensitivity even at a low voltage and to improve the deterioration of the variable sensitivity.
In addition, in order to obtain the conventional capacity characteristics, the required control voltage is about half or less (| gain | = 1, about half, and more than that is half or less). The effect is great.
This circuit configuration is also used when digitally used in a saturation region where the MOS capacitor element is a fixed capacitor (in the MOS capacitance characteristics, the capacitance does not change with respect to the voltage, on the high voltage side or on the low voltage side). By using this, the saturation region can be set widely, and the control voltage can be designed small.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is an explanatory diagram of an effect principle of an inverting amplifier. FIG. 3 is an effect graph of an inverting amplifier. FIG. 5 is a circuit diagram showing a third embodiment of the present invention. FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. FIG. 7 is an example of characteristics of a MOS capacitor. Example of use of conventional MOS capacitor element [FIG. 9] Measurement circuit diagram of MOS capacitor element [FIG. 10] Explanation of influence of AC superimposed voltage [FIG. 11] Graph of influence of amplitude of AC superimposed voltage [Explanation of symbols]
R1, R2, 1, 2, 41, 42, 57, 58, 59, 60, 64, 65, 66, 67 Resistor, 52, 54, 56 Capacitor, 51, 53, 55, 61, 62, 63 MOS capacitance element

Claims (2)

In a parallel circuit composed of a plurality of MOS capacitors connected in parallel with the same polarity, a control voltage is applied to one end of the parallel circuit, and an output voltage obtained by inverting and amplifying the control voltage with an inverting amplifier is applied directly or to an input resistor, respectively. A variable capacitance circuit characterized by being applied via In a parallel circuit comprising a plurality of series circuits in which a MOS capacitor element and a fixed capacitor for DC blocking are connected in series with the polarity of the MOS capacitor element aligned, a control voltage is applied to one end of each MOS capacitor element constituting the parallel circuit. A variable capacitance circuit characterized in that an output voltage obtained by inverting and amplifying the control voltage by an inverting amplifier is applied to the other end directly or via an input resistor.

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