JP4367523B2 - Insulated gate field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same.

  At present, the miniaturization of transistors based on a so-called scaling law is aimed at higher integration of semiconductor devices and improvement in operation speed. In miniaturization of an insulated gate field effect transistor (MISFET: Metal Insulator Semiconductor FET), it is necessary to suppress the influence of the so-called short channel effect. As long as the gate electrode is made of a semiconductor material, depletion of the gate electrode, which is one of the causes of the short channel effect, cannot be effectively suppressed. Therefore, it has been proposed that the gate electrode is made of a conductive material such as a metal or a metal compound. As a method of forming the gate electrode from a conductive material, for example, a metal film is formed instead of the polycrystalline silicon film, and the gate electrode is formed by patterning the metal film in the same manner as in the prior art. There has also been proposed a method of forming a gate electrode by a so-called damascene process in which a conductive material is embedded in an opening for a work (eg, Atsushi Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime”, International Electron Devices Meeting 1998 Technical Digest pp.785-788 (1998) (see Non-Patent Document 1)). In the method of forming a gate electrode by a damascene process, an insulating material (for example, hafnium oxide, etc.) having a relative dielectric constant larger than that of silicon oxide, for example, is formed in the gate electrode forming opening formed by removing the dummy gate electrode. A gate insulating film is formed, and then a gate electrode is formed. As a result, the characteristics of the insulated gate field effect transistor can be improved.

  Further, in order to achieve both optimization of the work function of the gate electrode and reduction in resistance of the gate electrode, when forming the gate electrode by the damascene process, first, a work function suitable for the gate electrode forming opening is used. Forming a thin film-like first layer (work function control layer) made of a conductive material having a thickness of 2 and then forming a second layer made of another conductive material having a lower resistivity (specific resistance), Has also been proposed.

  Along with the miniaturization of insulated gate field effect transistors, the alignment margin when forming a contact plug connected to the top surface of the gate electrode or the source / drain region in the interlayer insulating layer covering the gate electrode or the source / drain region is increased. The degree decreases. Therefore, it is preferable to form these contact plugs simultaneously based on a series of processes. The contact plug is formed by forming, in the interlayer insulating layer, a contact plug forming opening in which the top surface of the gate electrode is exposed at the bottom and a contact plug forming opening in which the source / drain regions are exposed at the bottom. It is formed by embedding tungsten or the like in the contact plug forming opening. The contact plug forming opening is formed based on a well-known lithography technique and etching technique.

  In the following, an outline of a method for forming a gate electrode by a conventional damascene process is a schematic partial end view of a silicon semiconductor substrate or the like, which is shown in FIGS. 2A, 20A, and 20B. 21 (A) and (B), FIG. 22 (A) and (B), and FIG. 23 (A) and (B).

[Step-10]
First, a base 10 having a channel forming region 12 and source / drain regions 13, a lower insulating layer 21 made of SiO ₂ , and a gate electrode forming opening 22 above the channel forming region 12 is prepared (FIG. 2). (See (A)).

The method for manufacturing the substrate 10 will be described in detail in Example 1. Reference numeral 11 is a silicon semiconductor substrate, reference numeral 13A is a silicide layer formed in the upper part of the source / drain region 13, reference numeral 17 is an offset spacer made of SiN, and reference numeral 18 is SiO _2. Reference numeral 19 is a second sidewall made of SiN, and reference numeral 20 is a stress liner layer made of SiN.

[Step-20]
Next, on the entire surface, for example, a gate insulating film 630 made of hafnium oxide, a first thin film layer (work function control layer) 631 made of a metal material (hafnium silicide) for defining the work function of the gate electrode, TiN Are sequentially formed (see FIG. 20A).

[Step-30]
After that, a second layer 632 made of tungsten is formed on the entire surface based on the so-called blanket tungsten CVD method, and then a planarization process is performed based on the CMP method, so that the lower insulating layer 21, the offset spacer 17, the first side The second layer 632, the barrier layer 632A, the first layer 631, and the gate insulating film 630 on the wall 18 and the second sidewall 19 are removed (see FIG. 20B). Thus, the gate electrode 623 can be obtained. Here, the gate electrode 623 is formed above the channel formation region 12 via the gate insulating film 630, and includes a first layer 631, a barrier layer 632 A, and a second layer 632. The gate insulating film 630 is formed from the surface of the semiconductor substrate 11 to the side wall of the gate electrode forming opening 22.

[Step-40]
Next, an interlayer insulating layer 34 is formed on the entire surface (see FIG. 21A).

[Step-50]
Thereafter, contact plug formation openings 35A and 35B are formed in the portions of the interlayer insulating layer 34 / lower insulating layer 21 above the gate electrode 623 and above the source / drain region 13 based on the photolithography technique and the dry etching technique. Form. FIG. 21B illustrates a state at the time when the formation of the contact plug formation opening 35A is completed and a state in the middle of the formation of the contact plug formation opening 35B, and FIG. The state at the time when the formation of the contact plug forming opening 35B is completed is illustrated. Here, an etching resist layer is actually formed, but the resist layer is not shown.

[Step-60]
Next, in order to form a contact plug, a pretreatment for removing a natural oxide film or the like is performed. The state when the preprocessing is completed is shown in FIG.

[Step-70]
Thereafter, a second barrier layer 36 made of Ti (lower layer) / TiN (upper layer) is formed on the entire surface (see FIG. 23A), and a tungsten layer is formed on the entire surface based on a blanket tungsten CVD method. The contact plugs 37A and 37B can be obtained in the contact plug forming openings 35A and 35B by performing a planarization process based on the CMP method (see FIG. 23B).

Atsushi Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.lμm Regime”, International Electron Devices Meeting 1998 Technical Digest pp.785-788 (1998)

By the way, in the insulated gate field effect transistor obtained by such a manufacturing method, the upper end surfaces of the gate insulating film 630 and the first layer 631 are exposed in [Step-30] (see FIG. 20B). Is in a state. Therefore, in [Step-50], in order to form the contact plug forming openings 35A and 35B, the interlayer insulating layer 34 made of SiO ₂ is dry-etched (see FIG. 21B). The lower insulating layer 21 made of SiO ₂ and the stress liner layer 20 made of SiN are dry-etched (see FIG. 22A). Depending on the dry etching conditions, the top surface of the gate electrode 623 is formed. The exposed gate insulating film 630 or the gate insulating film 630 and the first layer 631 are etched. Furthermore, the first layer 631 is etched depending on the pretreatment conditions in [Step-60].

Further, in some cases, in order to form the stress liner layer again, following [Step-30] (see FIG. 20B), the lower insulating layer 21 made of SiO ₂ is removed using dilute hydrofluoric acid. In some cases, the first layer 631 made of hafnium silicide is etched by dilute hydrofluoric acid. In the wet etching using dilute hydrofluoric acid, the gate insulating film 630 made of hafnium oxide is not usually etched.

Alternatively, in the semiconductor element region (not shown), the layer structure of the interlayer insulating layer to be formed may require a laminated structure of a lower interlayer insulating layer made of SiN and an interlayer insulating layer made of SiO ₂ from the bottom. is there. In such a case, the structure of the insulating layer / interlayer insulating layer above the source / drain region 13 is as follows: the stress liner layer 20 made of SiN, the lower layer insulating layer 21 made of SiO _2, and the lower layer insulating layer made of SiN. , A four-layer structure of an upper interlayer insulating layer made of SiO ₂ . On the other hand, the structure of the interlayer insulating layer above the gate electrode 623 is a two-layer structure of a lower interlayer insulating layer made of SiN and an upper interlayer insulating layer made of SiO ₂ from the bottom. Therefore, in the same process as [Step-50] described above, the insulating layer / interlayer insulating layer above the gate electrode 623 and above the source / drain region 13 based on the photolithography technique and the dry etching technique. When the contact plug forming opening is formed in this portion, it is necessary to perform etching of a two-layer structure of the upper interlayer insulating layer made of SiO ₂ and the lower interlayer insulating layer made of SiN above the gate electrode 623. is there. Meanwhile, in the above the source / drain regions 13, the upper interlayer insulating layer made of SiO _2, the lower interlayer insulating layer made of SiN, 4-layer stress liner layer 20 made of the lower insulating layer 21, SiN made of SiO ₂ The composition must be etched. Therefore, there arises a problem that the etching conditions become very complicated and the etching selectivity cannot be taken sufficiently.

Therefore, after [Step-30] (see FIG. 20B), the lower insulating layer 21 made of SiO ₂ is removed using dilute hydrofluoric acid, and then an interlayer insulating layer made of SiN and SiO _{2 is} formed on the entire surface. The upper interlayer insulating layer made of SiO ₂ and the lower interlayer insulating layer made of SiN (source / drain region), both above the gate electrode 623 and above the source / drain region 13, are formed. In addition to the above, etching of a two-layer structure of the stress liner layer 20) made of SiN may be performed. As a result, problems such as very complicated etching conditions and insufficient etching selectivity can be avoided. However, since the lower insulating layer 21 made of SiO ₂ is removed using dilute hydrofluoric acid, the same problem as described above is caused such that the first layer 631 made of hafnium silicide is etched by dilute hydrofluoric acid. .

  As a result of the above, the first layer 631 and the gate insulating film 630 near the surface of the semiconductor substrate 11 become thin (see the region surrounded by a circle in FIG. 22B) or disappear. Such a problem is likely to occur. When the first layer 631 in the vicinity of the surface of the semiconductor substrate 11 becomes thin, the work function of the gate electrode in the n-channel insulated gate field effect transistor and the work function of the gate electrode in the p-channel insulated gate field effect transistor are reduced. The difference is eliminated or reduced. In such a state, when the contact plug 37A is formed in [Step-70], voids are generated in the contact plug 37A, and the electrical resistance value of the contact plug 37A is increased, or alternatively, the gate As a result of the reduction in the thickness of the insulating film 630, breakdown voltage deterioration is likely to occur. Furthermore, since the constituent material of the portion above the gate electrode 623 to be etched to form the contact plug forming openings 35A and 35B is different from the portion above the source / drain region 13, the contact plug forming portion is formed. There is also a problem that it is difficult to optimize the formation conditions of the openings 35A and 35B.

  Accordingly, an object of the present invention is to provide an insulating gate having a highly reliable gate electrode without forming a gate insulating film or a material constituting the gate electrode when a contact plug is formed above the gate electrode. A field effect transistor and a manufacturing method thereof are provided.

In order to achieve the above object, an insulated gate field effect transistor according to the first aspect of the present invention comprises:
(A) a source / drain region and a channel formation region;
(B) a gate electrode formed above the channel formation region, and
(C) a gate insulating film,
An insulated gate field effect transistor comprising:
The gate insulating film includes a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extending portion extending from the gate insulating film main body portion to the middle of the side surface portion of the gate electrode. Configured,
When relative to the channel forming region the surface of the gate electrode height H _Gate, and the height of the gate insulating film extending portion and H _Ins, and satisfies the H _Ins <H _Gate.

In the insulated gate field effect transistor according to the first aspect of the present invention, the gate electrode has a first layer made of the first metal material, and a second layer made of the second metal material different from the first metal material. The first layer is formed from the bottom surface of the gate electrode facing the channel formation region to the middle of the side surface of the gate electrode; the second layer occupies the remainder of the gate electrode When the height of the portion of the first layer formed halfway along the side surface of the gate electrode with respect to the surface of the channel formation region is defined as H _Mt-1 , H _Mt-1 <H _Gate is satisfied. It can be configured. Such a configuration is referred to as “an insulated gate field effect transistor according to the first-A aspect of the present invention” for convenience. In this case, it is preferable that H _{Ins ≈H Mt−1} . Here, the metal material includes metal compounds such as metals, alloys, and metal nitrides. The same applies to the following description.

  The insulated gate field effect transistor according to the first-A aspect of the present invention further includes a contact plug connected to the top surface of the gate electrode, and the bottom surface of the contact plug and the upper end of the gate insulating film extending portion. The second layer may exist between the two parts. Alternatively, the second layer is composed of two layers, an outer layer and an inner layer, and the outer layer of the second layer is formed on the side surface of the gate electrode from above the first layer. The layer may be configured to occupy the remaining portion of the gate electrode. In this case, the layer further includes a contact plug connected to the top surface of the gate electrode, and the bottom surface of the contact plug and the gate insulating film extending portion are provided. Between the upper end portion, at least one of the inner layer and the outer layer may be present.

Alternatively, in the insulated gate field effect transistor according to the first aspect of the present invention, the gate electrode is a first layer made of the first metal material, and a second layer made of the second metal material different from the first metal material. The first layer is composed of two layers and a third layer made of a third metal material different from the first metal material; the first layer extends from the bottom surface of the gate electrode facing the channel formation region to the side surface of the gate electrode. The second layer and the third layer occupy the remaining part of the gate electrode in a stacked state; the middle of the side surface of the gate electrode when the channel formation region surface is used as a reference H _Mt-1 the height of the portion of the first layer formed to, when the height of the interface between the second layer and the third layer and _{H Mt-2, H Mt-} 1 <H Gate, H mt- ₁ ≈H _Mt-2 can be satisfied. Such a configuration is referred to as “an insulated gate field effect transistor according to the first-B aspect of the present invention” for convenience. In this case, it is preferable that H _{Ins ≈H Mt−1} ≈H _Mt−2 .

  The insulated gate field effect transistor according to the first-B aspect of the present invention further includes a contact plug connected to the top surface of the gate electrode; the bottom surface of the contact plug and the upper end of the gate insulating film extending portion. A third layer may be present between the parts.

In the insulated gate field effect transistor according to the first aspect of the present invention including the preferred configuration and aspect described above,
0.1 ≦ H _Ins / H _Gate ≦ 0.95
And satisfy
It is preferable that (H _Gate −H _Ins ) ≧ 5 nm is satisfied.

In the insulated gate field effect transistor according to the first-A aspect or the first-B aspect of the present invention including the above-mentioned preferred configuration, the first layer is made of a metal material for defining the work function of the gate electrode. (Specifically, as the metal material constituting the first layer, a metal material having a preferable work function in relation to the channel formation region of the n-channel or p-channel insulated gate field effect transistor is appropriately selected. More specifically, the same applies to the following description.) More specifically, the first layer is a metal composed of the group consisting of hafnium, tantalum, titanium, molybdenum, ruthenium, nickel, platinum, and an alloy containing the metal. Or a metal compound (for example, a metal nitride or a metal silicide which is a compound of a metal and a semiconductor material), and the second layer includes: Tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), aluminum (Al) metal comprised from the group consisting of, desirably made of an alloy containing the metal. The third layer is preferably made of a metal composed of a group consisting of tungsten (W), copper (Cu), and aluminum (Al), and an alloy containing the metal. More specifically, as the material constituting the first layer, when the channel formation region is n-type, a metal composed of a group consisting of hafnium (Hf), tantalum (Ta), etc., the metal When the channel formation region is p-type, or an alloy containing metal, or a compound of the metal, it is made of titanium (Ti), molybdenum (Mo), ruthenium (Ru), nickel (Ni), platinum (Pt), or the like. Although the metal comprised from the group, the alloy containing this metal, or the compound of this metal can be selected, it is not limited to this. Alternatively, the first layer is made of a metal composed of the group consisting of hafnium, tantalum, titanium, tungsten, molybdenum, ruthenium, nickel, platinum, an alloy containing the metal, or a compound of the metal (for example, a metal nitride) It is desirable that the second layer be made of silicide (specifically, for example, tri-nickel silicide [Ni ₃ Si]).

Alternatively, in the insulated gate field effect transistor according to the first aspect of the present invention, the gate electrode is silicide (specifically, for example, in the case of an n-channel insulated gate field effect transistor, nickel disilicide [NiSi ₂ ], Nickel silicide [NiSi], and a p-channel insulated gate field effect transistor can be composed of tri-nickel silicide [Ni ₃ Si]). Such a configuration is referred to as “an insulated gate field effect transistor according to the 1-C aspect of the present invention” for convenience.

In order to achieve the above object, an insulated gate field effect transistor according to the second aspect of the present invention provides:
(A) a source / drain region and a channel formation region;
(B) a gate electrode formed above the channel formation region, and
(C) a gate insulating film,
An insulated gate field effect transistor comprising:
The gate insulating film is composed of a gate insulating film main body formed between the gate electrode and the channel formation region, and a gate insulating film extending portion extending from the gate insulating film main body to the top surface of the gate electrode. And
The gate electrode includes a first layer made of a first metal material, a second layer made of a second metal material different from the first metal material, and a third metal material different from the first metal material. Consisting of a third layer consisting of:
The first layer is formed in the middle of the side surface of the gate electrode from the bottom surface of the gate electrode facing the channel formation region,
The second layer and the third layer occupy the remainder of the gate electrode in the stacked state,
The height of the gate electrode with reference to the surface of the channel formation region is H _Gate , the height of the portion of the first layer formed partway along the side surface of the gate electrode is H _Mt−1 , the second layer and the second layer _Assuming that the height of the interface with the three layers is H _Mt-2 , H _Mt-1 <H _Gate , H _Mt-2 <H _Gate , H _Mt-1 ≈H _Mt-2 is satisfied.

  The insulated gate field effect transistor according to the second aspect of the present invention further includes a contact plug connected to the top surface of the gate electrode; the bottom surface of the contact plug and the upper end portion of the first layer. It can be set as the form which a 3rd layer exists in between.

  In the insulated gate field effect transistor according to the second aspect of the present invention including the above preferred embodiment, the first layer is preferably made of a metal material for defining the work function of the gate electrode, more specifically. The first layer is made of a metal composed of a group consisting of hafnium, tantalum, titanium, molybdenum, ruthenium, nickel, platinum, an alloy containing the metal, or a compound of the metal (for example, a metal nitride, The second layer is composed of a group consisting of tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), and aluminum (Al). It is desirable to be made of a metal or an alloy containing the metal. The third layer is preferably made of a metal composed of a group consisting of tungsten (W), copper (Cu), and aluminum (Al), and an alloy containing the metal. More specifically, as the material constituting the first layer, when the channel formation region is n-type, a metal composed of a group consisting of hafnium (Hf), tantalum (Ta), etc., the metal In the case where the channel formation region is p-type, an alloy containing metal or a compound of the metal is made of titanium (Ti), molybdenum (Mo), ruthenium (Ru), nickel (Ni), platinum (Pt), or the like. A metal composed of the group consisting of the above, an alloy containing the metal, or a compound of the metal can be selected, but is not limited thereto.

In the insulated gate field effect transistor according to the second aspect of the present invention including the preferred configuration and aspect described above,
0.1 ≦ H _Mt-1 / H _Gate ≦ 0.95
And satisfy
It is preferable that (H _Gate −H _Mt−1 ) ≧ 5 nm is satisfied.

In order to achieve the above object, a method of manufacturing an insulated gate field effect transistor according to the first aspect of the present invention includes:
(A) A source / drain region, a channel formation region, an insulating layer, and a substrate having an opening for forming a gate electrode above the channel formation region are prepared.
(B) forming a gate insulating film on the channel formation region exposed at the bottom of the gate electrode formation opening and on the sidewall of the gate electrode formation opening;
(C) The gate insulating film formed on the sidewall of the opening for forming the gate electrode is selectively removed, so that the main body of the gate insulating film left at the bottom of the opening for forming the gate electrode, and the gate insulation After obtaining the gate insulating film composed of the gate insulating film extending portion extending from the film main body portion to the middle of the side wall of the gate electrode forming opening,
(D) obtaining a gate electrode by embedding the inside of the opening for forming the gate electrode with a metal material;
Each step is provided.

  In the method for manufacturing an insulated gate field effect transistor according to the first aspect of the present invention, the selective removal of the gate insulating film formed on the side wall of the gate electrode formation opening in the step (c) After forming the layer, the resist layer is etched back to leave the resist layer under the gate electrode formation opening, and then the gate insulating film portion exposed at the upper portion of the sidewall of the gate electrode formation opening is removed. The resist layer may be removed.

In the method of manufacturing an insulated gate field effect transistor according to the first aspect of the present invention including the above-described preferred configuration, the height of the gate electrode when the channel formation region surface is used as a reference is H _Gate , and the gate insulating film When the height of the extending portion is H _Ins , it is preferable that H _Ins <H _Gate is satisfied.

  Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the first aspect of the present invention, the gate electrode includes a first layer made of the first metal material and a second layer different from the first metal material. In the step (b), the gate is formed on the channel formation region exposed at the bottom of the gate electrode formation opening and on the sidewall of the gate electrode formation opening in the step (b). An insulating film and a first layer are sequentially formed; in the step (c), the gate insulating film and the first layer formed on the side wall of the gate electrode forming opening are selectively removed; Gate insulating film main body left at bottom of electrode forming opening, and gate insulating film extending from gate insulating film main body to the middle of side wall of gate electrode forming opening Insulating film, and It is desirable to adopt a configuration for obtaining a first layer formed over the middle of the side surface portion of the gate electrode from the bottom portion of the gate electrode facing the Yaneru formation region. Such a configuration is referred to as “a manufacturing method of an insulated gate field effect transistor according to the first-A aspect of the present invention” for convenience.

  In the method for manufacturing an insulated gate field effect transistor according to the first-A aspect of the present invention, the selection of the gate insulating film and the first layer formed on the side wall of the gate electrode formation opening in the step (c) After the resist layer is formed on the entire surface, the resist layer is etched back to leave the resist layer under the gate electrode forming opening, and then exposed to the upper part of the sidewall of the gate electrode forming opening. It is preferable to comprise a step of removing the resist layer after removing the one layer portion and the gate insulating film portion.

  Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the first-A aspect of the present invention including the above preferable configuration, the remaining part of the opening for forming the gate electrode is a second portion in the step (d). It is preferable to obtain a gate electrode composed of a first layer and a second layer by embedding with a metal material. Such a configuration is referred to as “a manufacturing method of an insulated gate field effect transistor according to the first-A-1 aspect of the present invention” for convenience. In this case, following the step (d), an interlayer insulating layer is formed on the entire surface, and then an opening for forming a contact plug is formed in the portion of the interlayer insulating layer above the gate electrode. The method may further include a step of providing a contact plug in the opening, and the second layer may exist between the bottom surface of the contact plug and the upper end portion of the gate insulating film extension.

  Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the first-A aspect of the present invention including the above preferable configuration, the second layer is composed of two layers, an outer layer and an inner layer. The outer layer of the second layer is formed on the side surface of the gate electrode from above the first layer, and the inner layer of the second layer occupies the remaining part of the gate electrode. In the step (d), the gate electrode After the outer layer is formed over the first layer formed in the forming opening and on the sidewall of the gate electrode forming opening, the remaining portion can be embedded in the inner layer. Such a configuration is referred to as “a manufacturing method of an insulated gate field effect transistor according to the first-A-2 mode of the present invention” for convenience. In this case, following the step (d), an interlayer insulating layer is formed on the entire surface, and then an opening for forming a contact plug is formed in the portion of the interlayer insulating layer above the gate electrode. The method further includes a step of providing a contact plug in the opening, and at least one of the inner layer and the outer layer exists between the bottom surface of the contact plug and the upper end of the gate insulating film extension. be able to.

Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the first-A aspect of the present invention including the above preferable configuration, the metal in the remainder of the gate electrode forming opening in the step (d) For the embedding of the material, after forming a conductive material layer below the opening for forming the gate electrode, a metal material layer is formed on the entire surface, and then the conductive material layer and the metal material layer are chemically reacted, It is preferable to obtain a second layer made of the second metal material by a chemical reaction between the conductive material layer and the metal material layer. This structure is referred to as “a method for manufacturing an insulated gate field effect transistor according to the first-A-3 aspect of the present invention” for convenience), and the first layer is made of hafnium, tantalum, titanium, tungsten, molybdenum. , Lute A metal composed of a group consisting of aluminum, nickel, platinum, an alloy containing the metal, or a compound of the metal (for example, a metal nitride or a metal silicide that is a compound of a metal and a semiconductor material) The two layers are preferably made of silicide (specifically, for example, tri-nickel-silicide [Ni ₃ Si]).

In the manufacturing method of the insulated gate field effect transistor according to the first-A aspect of the present invention including the various preferable configurations and aspects described above, the gate electrode is formed on the basis of the surface of the channel formation region. _Assuming that the height is H _Gate , the height of the gate insulating film extension is H _Ins , and the height of the portion of the first layer formed partway along the side surface of the gate electrode is H _Mt−1 , H _Ins <H It is desirable to satisfy _Gate and H _{Ins ≈H Mt−1} .

Alternatively, in the method for manufacturing an insulated gate field effect transistor according to the first aspect of the present invention, the embedding of the metal material into the gate electrode formation opening in the step (d) is performed by using the gate electrode formation opening. Forming a conductive material layer at the bottom of the part, forming a metal material layer on the entire surface, then chemically reacting the conductive material layer and the metal material layer, and then removing the unreacted metal material layer Therefore, it is desirable to obtain the gate electrode by a chemical reaction between the conductive material layer and the metal material layer. Such a configuration is referred to as “a manufacturing method of an insulated gate field effect transistor according to the first-B aspect of the present invention” for convenience. In this case, the gate electrode is silicide (specifically, for example, in the case of an n-channel insulated gate field effect transistor, nickel disilicide [NiSi ₂ ], nickel silicide [NiSi], p-channel insulated gate) The field effect transistor is preferably made of tri-nickel-silicide [Ni ₃ Si].

Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the first aspect of the present invention,
The gate electrode includes a first layer made of a first metal material, a second layer made of a second metal material different from the first metal material, and a third metal material different from the first metal material. Consisting of a third layer consisting of:
In the step (b), the gate insulating film, the first layer, and the second layer are sequentially formed on the channel formation region exposed at the bottom of the gate electrode formation opening and on the sidewall of the gate electrode formation opening. Forming,
In the step (c), a part of the gate insulating film, the first layer, and the second layer formed on the side wall of the gate electrode formation opening is selectively removed, thereby forming the gate electrode formation opening. The gate insulating film main body portion left on the bottom, the gate insulating film extending from the gate insulating film main body portion to the middle of the side wall of the gate electrode forming opening, and the channel forming region Of the first layer formed in the middle of the side surface portion of the gate electrode from the bottom surface portion of the gate electrode opposed to the gate electrode, and the second layer filling the portion where the first layer in the gate electrode forming opening is formed It can be. Such a configuration is referred to as “a manufacturing method of an insulated gate field effect transistor according to the first-C aspect of the present invention” for convenience.

  In the method of manufacturing an insulated gate field effect transistor according to the 1-C aspect of the present invention, the gate insulating film formed on the side wall of the gate electrode formation opening in the step (c), The selective removal of the layer and the second layer is performed by forming a resist layer on the entire surface and then etching the gate electrode film portion, the first layer portion and the second layer on the side wall of the gate electrode formation opening by an etch back method. After removing the layer portion, the resist layer may be removed. Further, in the step (d), the remaining portion of the opening for forming the gate electrode is filled with a third metal material, whereby a gate electrode composed of the first layer, the second layer, and the third layer is obtained. In this case, further, following the step (d), after forming an interlayer insulating layer on the entire surface, an opening for forming a contact plug is formed in the portion of the interlayer insulating layer above the gate electrode, And a step of providing a contact plug in the contact plug formation opening; a third layer may be present between the bottom surface of the contact plug and the upper end of the gate insulating film extension.

In the method of manufacturing an insulated gate field effect transistor according to the 1-C aspect of the present invention including the preferable configuration and configuration described above, the height of the gate electrode with respect to the surface of the channel formation region H _Gate , the height of the gate insulating film extension H _Ins , the height of the first layer formed partway along the side surface of the gate electrode is H _Mt−1 , and the second and third layers When the interfacial height and _{H Mt-2, H Ins <} H Gate, it is preferable to satisfy the _{H Ins ≒ H Mt-1 ≒} H Mt-2.

In order to achieve the above object, a method of manufacturing an insulated gate field effect transistor according to the second aspect of the present invention includes:
(A) A source / drain region, a channel formation region, an insulating layer, and a substrate having an opening for forming a gate electrode above the channel formation region are prepared.
(B) forming a gate insulating film on the channel formation region exposed at the bottom of the gate electrode formation opening and on the sidewall of the gate electrode formation opening;
(C) A gate electrode is obtained by embedding a gate electrode forming opening with a metal material.
A method for producing an insulated gate field effect transistor comprising each step,
The gate electrode includes a first layer made of a first metal material, a second layer made of a second metal material different from the first metal material, and a third metal material different from the first metal material. Consisting of a third layer consisting of:
In the step (c), the first layer formed from the bottom surface of the gate electrode facing the channel formation region to the middle of the side surface of the gate electrode, and the first layer in the gate electrode formation opening are formed. After obtaining the second layer that fills the portion, the remaining portion of the gate electrode forming opening is filled with the third metal material to obtain a gate electrode composed of the first layer, the second layer, and the third layer. It is characterized by that.

  In the method for manufacturing an insulated gate field effect transistor according to the second aspect of the present invention, following the step (c), an interlayer insulating layer is formed on the entire surface, and then the portion of the interlayer insulating layer above the gate electrode. Forming a contact plug forming opening, and then providing a contact plug in the contact plug forming opening; a third layer is formed between the bottom surface of the contact plug and the upper end of the first layer. It can be an existing form.

In the method for manufacturing an insulated gate field effect transistor according to the second aspect of the present invention including the preferred embodiment described above, the height of the gate electrode when the channel formation region surface is used as a reference is H _Gate , The height of the gate insulating film extension is H _Ins , the height of the portion of the first layer formed partway along the side surface of the gate electrode is H _Mt-1 , and the height of the interface between the second layer and the third layer. the When _{H Mt-2, H Ins <} H Gate, to satisfy the _{H Ins ≒ H Mt-1 ≒} H Mt-2 preferably is.

  In the method of manufacturing an insulated gate field effect transistor according to the first-A aspect, the first-B aspect, the first-C aspect, or the second aspect of the present invention including the above-described preferable configuration, The layer is preferably made of a metal material for defining the work function of the gate electrode. Alternatively, in the method of manufacturing an insulated gate field effect transistor according to the 1st-A aspect, the 1st-C aspect, or the second aspect of the present invention including the above preferable configuration, The first layer is a metal composed of a group consisting of hafnium, tantalum, titanium, molybdenum, ruthenium, nickel, platinum, an alloy containing the metal, or a compound of the metal (for example, a metal nitride, a metal and a semiconductor) The second layer is a metal composed of a group consisting of tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), and aluminum (Al). It is desirable to be made of an alloy containing the metal. The third layer is preferably made of a metal composed of a group consisting of tungsten (W), copper (Cu), and aluminum (Al), and an alloy containing the metal. More specifically, as the material constituting the first layer, when the channel formation region is n-type, a metal composed of a group consisting of hafnium (Hf), tantalum (Ta), etc., the metal In the case where the channel formation region is p-type, an alloy containing metal or a compound of the metal is made of titanium (Ti), molybdenum (Mo), ruthenium (Ru), nickel (Ni), platinum (Pt), or the like. A metal composed of the group consisting of the above, an alloy containing the metal, or a compound of the metal can be selected, but is not limited thereto.

  Further, in the method for manufacturing an insulated gate field effect transistor according to the 1-A-1 aspect of the present invention, as a method of burying the remaining part of the opening for forming the gate electrode with the second metal material, In the method for manufacturing an insulated gate field effect transistor according to the 1st-A-2 aspect, as a method of burying the remaining part of the opening for forming the gate electrode with the inner layer, or as the 1st-C aspect or the 1st aspect of the present invention, In the method of manufacturing an insulated gate field effect transistor according to the second aspect, various chemical vapor deposition (CVD) methods; electron beam evaporation methods are used as a method of embedding the remainder of the gate electrode forming opening with the third metal material. Various physical vapor deposition methods (P) such as vapor deposition methods such as thermal filament deposition, sputtering, ion plating, and laser ablation Method D); plating method can be cited such as electrolytic plating or electroless plating method, or perform these methods alone, or alternatively, may be performed in combination. After that, it is desirable to perform a planarization process by a chemical / mechanical polishing method (CMP method), an etch back method, or the like.

  Here, in the manufacturing method of the insulated gate field effect transistor according to the first-A-3 aspect or the first-B aspect of the present invention described above, as a method for forming the conductive material layer, for example, a CVD method is used. And a combination of the PVD method and the etch back method, and as a method of forming the metal material layer on the entire surface, the CVD method and the PVD method can be mentioned, and the conductive material layer and the metal material layer can be chemically combined. A heat treatment can be given as an example of a reaction method. An example of a method for removing the unreacted metal material layer is a wet etching method.

In the insulated gate field effect transistor of the present invention including the various preferred configurations and embodiments described above, as described above, the interlayer insulating layer is formed on the entire surface and is located above the channel formation region. It is desirable that a contact plug connected to the top surface of the gate electrode is provided in this part. Further, the side surface portion of the gate electrode preferably faces the side wall, and the material constituting at least a part of the side wall is preferably different from the material constituting the interlayer insulating layer. Specifically, SiN can be exemplified as a material constituting the portion of the sidewall that is in contact with the side surface portion of the gate electrode. Examples of the interlayer insulating layer include a SiO ₂ material, a laminated structure of a SiN material and a SiO ₂ material. The top surface of the source / drain region is preferably composed of a silicide layer in order to reduce the contact resistance value. In addition, it is preferable to form a stress liner layer made of, for example, SiN on the source / drain region, and as a result, stress can be applied to the channel forming region, thereby improving the driving capability of the insulated gate field effect transistor. Can be achieved.

  Moreover, in the manufacturing method of the insulated gate field effect transistor of the present invention including the various preferable configurations and aspects described above, for example, as described above, for example, plasma CVD method, high density plasma CVD method, atmospheric pressure CVD After forming an interlayer insulating layer on the entire surface by various CVD methods such as the method, an opening for forming a contact plug is formed in the portion of the interlayer insulating layer located above the channel formation region based on, for example, photolithography technology and dry etching technology It is desirable to further include a step of obtaining a contact plug connected to the top surface of the gate electrode by embedding a conductive material in the contact plug forming opening based on, for example, a CVD method or a PVD method. . Further, the side wall of the gate electrode forming opening provided in the insulating layer is preferably made of a side wall, and the material constituting at least a part of the side wall is different from the material constituting the interlayer insulating layer. It is desirable that Specifically, SiN can be exemplified as a material constituting the portion of the sidewall that is in contact with the side surface portion of the gate electrode. It is desirable to form a silicide layer on the top surface of the source / drain region based on a well-known method in order to reduce the contact resistance value. Further, on the source / drain regions, it is preferable to form a stress liner layer made of, for example, SiN based on, for example, the CVD method. As a result, stress can be applied to the channel forming region. The driving ability of the transistor can be improved.

Here, after the contact plug formation opening is formed in the portion of the interlayer insulating layer located above the channel formation region, for example, based on the photolithography technique and the dry etching technique, the bottom of the contact plug formation opening is formed. In order to prevent the gate insulating film and the first layer (work function control layer) from being exposed, the height H _Ins of the gate insulating film extending portion and the height of the portion of the first layer formed partway along the side surface of the gate electrode It is important to determine the _length H _Mt-1 .

  The insulated gate field effect transistor according to the first aspect or the second aspect of the present invention including the various preferred configurations and aspects described above or the method for manufacturing the same (hereinafter, these are collectively referred to simply as the present invention). In some cases, a method of preparing a substrate including a source / drain region and a channel formation region, an insulating layer, and a gate electrode formation opening above the channel formation region, that is, producing such a substrate The method may be a known method. Specific examples of a method for removing the gate insulating film formed on the side wall of the gate electrode formation opening include a dry etching method and a wet etching method.

  In addition to a semiconductor substrate such as a silicon semiconductor substrate, a substrate having a semiconductor layer formed on the surface thereof (for example, a glass substrate, a quartz substrate, a surface) Examples thereof include a silicon semiconductor substrate, a plastic substrate, a plastic film, and the like on which an insulating layer is formed. The insulated gate field effect transistor is formed in, for example, a semiconductor substrate or a well region of a semiconductor layer. Between the insulated gate field effect transistor and the insulated gate field effect transistor, for example, an element isolation region composed of a trench structure, a LOCOS structure, or a combination of a trench structure and a LOCOS structure may be formed. Furthermore, a substrate having an SOI structure obtained by a SIMOX method or a substrate bonding method may be used. In this case, it is not necessary to form an element isolation region.

As a material constituting the gate insulating film, a relative dielectric constant k (= ε / ε ₀ ) in addition to a conventionally used SiO ₂ -based material, SiOF-based material, or SiN-based material (for example, SiN or SiON). ) Is generally a so-called high relative dielectric constant material of 4.0 or more. Examples of high dielectric constant materials include zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), HfSiON, aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), and lanthanum oxide (La ₂ O). A metal oxide film and a metal nitride film can be exemplified. The gate insulating film may be formed from one type of material or may be formed from a plurality of types of materials. The gate insulating film may be a single film (including a composite film made of a plurality of materials) or a laminated film. The gate insulating film of the n-channel type insulated gate field effect transistor and the gate insulating film of the p-channel type insulated gate field effect transistor can be made of the same material, or can be made of different materials. it can. The gate insulating film can be formed by a widely known method. In particular, ALD (Atomic Layer Deposition) method, metal organic chemical vapor deposition method (MOCVD method), sputtering method and the like can be exemplified as a method for forming the gate insulating film made of the above-mentioned high relative dielectric constant material. .

  As a method for forming the first layer (work function control layer), although depending on the material, various CVD methods including ALD method and MOCVD method, and PVD method can be exemplified. In the case where the second layer is made of silicide, n-channel type insulation is achieved by controlling the type and amount of impurities contained in the silicide, or by appropriately implanting aluminum ions into the silicide, for example. It is possible to optimize the work function values of the gate electrodes of the gate field effect transistor and the p-channel insulated gate field effect transistor.

As a material constituting the insulating layer or the interlayer insulating layer, in addition to the above-described SiO ₂ -based material and SiN-based material, an SiOF-based material, SiC, and an organic material having a dielectric constant k (= ε / ε ₀ ) of 3.5 or less Low dielectric constant insulating materials such as SOG, polyimide resin, fluorine resin (for example, fluorocarbon, amorphous tetrafluoroethylene, polyaryl ether, fluorinated aryl ether, fluorinated polyimide, parylene, benzocyclobutene, amorphous carbon, cyclohexane Perfluorocarbon polymer and fullerene fluoride), or the insulating layer and the interlayer insulating layer may be formed of a laminated structure of these materials. As a method for forming the insulating layer and the interlayer insulating layer, although depending on the material, a CVD method and a PVD method can be given. The insulating layer includes the above-described sidewall.

  Examples of the material constituting the contact plug provided in the interlayer insulating layer include refractory metal materials such as polycrystalline silicon doped with impurities and tungsten (W). The contact plug can be formed by forming a contact plug formation opening in the interlayer insulating layer by a dry etching method such as RIE, and then filling the contact plug formation opening with the above-described material by a known method. . Specifically, for example, the contact plug can be formed by burying tungsten in the contact plug formation opening by blanket tungsten CVD, and then removing the excess tungsten layer on the interlayer insulating layer. Note that it is preferable to bury tungsten in the contact plug forming opening by blanket-tungsten CVD after forming a Ti layer and a TiN layer as adhesion layers in the contact plug forming opening.

  In the present invention, the “channel formation region” means a region where a channel can be formed, and does not indicate only a region where a channel is actually formed. For example, a portion of a semiconductor layer or a semiconductor substrate that faces the gate electrode corresponds to a “channel formation region”. As a semiconductor device incorporating the insulated gate field effect transistor of the present invention, for example, a CMOS semiconductor device composed of NMOS and PMOS can be cited, and a BiCMOS semiconductor device including a bipolar transistor in addition to NMOS and PMOS can be cited. You can also.

  In the present invention, when the gate electrode is completed by a so-called damascene process, the top surface of the gate electrode is a gate insulating film or a first layer for defining the work function of the gate electrode (work function control layer). ) Is not exposed. Therefore, in order to form contact plugs to the gate electrode and the source / drain regions, the interlayer insulating layer and the insulating layer are dry-etched to provide contact plug forming openings, and pre-processing for contact plug formation is performed. Or when removing the lower insulating layer, it is possible to reliably prevent the occurrence of a phenomenon that the gate insulating film, the first layer, or the gate insulating film and the first layer are etched. . As a result, an insulated gate field effect transistor having high reliability can be provided, and for example, the work function of the gate electrode in an n-channel insulated gate field effect transistor can be reliably maintained at a desired value. . In addition, a highly reliable gate electrode can be formed without depending on the width of the gate electrode.

  In some cases, the material constituting the top surface of the gate electrode of the n-channel insulated gate field effect transistor is the same as the material constituting the top surface of the gate electrode of the p-channel insulated gate field effect transistor. Therefore, the contact plug forming opening can be reliably formed in the interlayer insulating layer under stable etching conditions.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to an insulated gate field effect transistor and a method of manufacturing the same according to the present invention, and more specifically, an insulated gate field effect transistor according to the first-A aspect of the present invention, and a first 1 The present invention relates to a method for manufacturing an insulated gate field effect transistor according to the A-1 aspect and the 1-A-2 aspect.

The insulated gate field effect transistor of Example 1 has a partial end view schematically shown in FIG.
(A) source / drain region 13 and channel forming region 12,
(B) a gate electrode 23 formed above the channel formation region 12, and
(C) the gate insulating film 30,
Is an insulated gate field effect transistor. In Example 1, the insulated gate field effect transistor was an n-channel insulated gate field effect transistor.

As shown in an enlarged schematic diagram of the gate electrode 23 and the like in FIG. 8B, the gate insulating film 30 made of hafnium oxide is formed between the gate electrode 23 and the channel forming region 12. The main body portion 30A and a gate insulating film extending portion 30B extending from the gate insulating film main body portion 30A to the middle of the side surface portion 23A of the gate electrode 23 are configured. Then, as shown in FIG. 8B, when the height of the gate electrode 23 with respect to the surface of the channel formation region 12 is H _Gate and the height of the gate insulating film extension 30B is H _Ins , Satisfies H _Ins <H _Gate .

In the insulated gate field effect transistor of Example 1, the gate electrode 23 is a first metal material (specifically, a metal material for defining the work function of the gate electrode 23, more specifically, hafnium. A first layer (work function control layer) 31 made of silicide [HfSi _x ]) and a second layer 32 made of a second metal material different from the first metal material. The first layer 31 is formed in a thin film shape from the bottom surface portion of the gate electrode 23 facing the channel formation region 12 to the middle of the side surface portion 23A of the gate electrode 23, and the second layer 32 is formed of the gate electrode 23. Account for the rest. Further, assuming that the height of the portion 31B of the first layer 31 formed partway along the side surface 23A of the gate electrode 23 with respect to the surface of the channel formation region 12 is H _Mt−1 , H _Mt−1. <Satisfy H _Gate H _{Ins ≈H Mt−1} . The portion of the first layer formed on the bottom surface of the gate electrode 23 is indicated by reference numeral 31A, and the portion of the first layer 31 formed in the middle of the side surface portion 23A of the gate electrode 23 is indicated by reference numeral 31B. . More specifically,
H _Gate ≒ 100nm
H _Ins ≒ 50nm
H _Mt-1 ≒ 50nm
It was. The same applies to Examples 2 to 3 described later. In the first embodiment, the second layer 32 is composed of two layers, a thin film outer layer 32A and an inner layer 32B. The outer layer 32A of the second layer 32 is the first layer. The inner layer 32 </ b> B of the second layer 32 occupies the remaining part of the gate electrode 23. The outer layer 32A is made of TiN, and the inner layer 32B is made of tungsten (W). Here, the outer layer 32A functions as a barrier layer and an adhesion improving layer, and also functions as a metal material layer (work function control layer) for defining the work function of the gate electrode in the PMOS. However, the formation of the outer layer 32A is not indispensable, and the second layer 32 can be composed of one layer.

  In the insulated gate field effect transistor of Example 1, the side surface portion 23A of the gate electrode 23 is in contact with the side wall. Here, the side wall includes an offset spacer 17 provided adjacent to the side surface portion 23 </ b> A of the gate electrode 23, a first side wall 18 and a second side wall 19 positioned outside the offset spacer 17. A silicide layer (specifically, a nickel / platinum / silicide layer) 13 </ b> A is formed on the surface of the source / drain region 13. Further, a stress liner layer 20 made of SiN is formed above the source / drain region 13, and a lower insulating layer 21 is formed on the stress liner layer 20. The lower insulating layer 21, the stress liner layer 20, and the sidewall constitute an insulating layer.

  Further, an interlayer insulating layer 34 is formed on the lower insulating layer 21 and the like, and a contact plug forming opening 35A is provided in a portion of the interlayer insulating layer 34 located above the channel forming region 12. A contact plug 37A made of tungsten and connected to the top surface of the gate electrode 23 is provided in the contact plug forming opening 35A. Then, at least one of the inner layer 32B and the outer layer 32A exists between the bottom surface of the contact plug 37A and the upper end portion of the gate insulating film extending portion 30B. When the second layer 32 is composed of one layer, the second layer 32 exists between the bottom surface of the contact plug 37A and the upper end portion of the gate insulating film extending portion 30B. On the other hand, a contact plug forming opening 35B is provided in a portion of the interlayer insulating layer 34 located above the source / drain region 13, and the contact plug forming opening 35B is made of tungsten, and the source / drain region is formed. Contact plugs 37 </ b> B connected to the silicide layers 13 </ b> A constituting 13 are provided. Reference numeral 11 is a silicon semiconductor substrate, and reference numeral 36 is a second barrier layer for forming contact plugs 37A and 37B.

  1A and 1B which are schematic partial end views of a silicon semiconductor substrate and the like, FIG. 2A and FIG. 2B, FIG. 3A and FIG. (A), (B), (A), (B) in FIG. 5, (A), (B) in FIG. 6, (A), (B) in FIG. 7, (A), (B in FIG. In the following, a method for manufacturing an insulated gate field effect transistor of Example 1 will be described.

[Step-100]
First, the base 10 provided with the channel forming region 12 and the source / drain region 13, the lower insulating layer 21 made of SiO ₂ , and the gate electrode forming opening 22 above the channel forming region 12 is prepared.

Specifically, after an element isolation region (not shown) is formed in the silicon semiconductor substrate 11, a dummy gate insulating film 14 is formed on the surface of the silicon semiconductor substrate 11, and then a dummy polysilicon layer 15 and SiN are formed. After sequentially forming the hard mask layer, a dummy gate electrode 15 ′ is formed based on the photolithography technique and the dry etching technique. The dummy gate electrode 15 ′ has a laminated structure of a dummy polysilicon layer 15 and a hard mask 16. Subsequently, after shallow ion implantation of impurities for forming the LDD structure, an offset spacer 17 made of SiN is formed on the side surface of the dummy gate electrode 15 ′, and SiO SiO for forming the first sidewall 18 is formed. _Two layers and an SiN layer for forming the second side wall 19 are sequentially formed, and the SiN layer and the SiO ₂ layer are etched back to thereby form the first side wall 18 positioned outside the offset spacer 17. And the 2nd side wall 19 can be obtained. Thereafter, deep ion implantation of impurities is performed to form the source / drain region 13. Next, a nickel / platinum layer is formed on the entire surface, and heat treatment is performed, whereby the upper portion of the source / drain region 13 is silicided to obtain the silicide layer 13A. Thereafter, the unreacted nickel / platinum layer is removed, and the heat treatment is performed again to stabilize the silicide layer 13A. As described above, the source / drain region 13 including the extension region and the silicide layer 13A (low resistance layer) can be obtained. A region sandwiched between the extension regions of the source / drain regions 13 becomes the channel forming region 12. Thereafter, a stress liner layer 20 made of SiN is formed on the entire surface. Thus, the state shown in FIG. 1A can be obtained.

Thereafter, a lower insulating layer 21 made of SiO ₂ is formed on the entire surface, and then a planarization process is performed based on the CMP method, whereby a part of the lower insulating layer 21 and the hard mask 16 (in some cases, dummy polysilicon is further added. Part of the layer 15 and part of the sidewall) are removed. Thus, the state shown in FIG. 1B can be obtained.

  Next, the exposed dummy gate electrode 15 'is removed by an etching method using radicals such as fluorine, and the dummy gate insulating film 14 is further removed by a wet etching method such as dilute hydrofluoric acid. In this way, the state shown in FIG. 2A can be obtained.

[Step-110]
Next, the gate insulating film 30 is formed on the channel formation region 12 exposed at the bottom of the gate electrode formation opening 22 and on the side wall of the gate electrode formation opening 22. By the way, in Example 1, the gate electrode 23 consists of the 1st layer (work function control layer) 31 which consists of a 1st metal material, and the 2nd metal material different from a 1st metal material. The second layer 32 is configured. Therefore, in the first embodiment, the gate insulating film 30 and the first electrode are formed on the channel forming region 12 exposed at the bottom of the gate electrode forming opening 22 and on the side wall of the gate electrode forming opening 22. The first layer 31 made of one metal material is sequentially formed.

Specifically, a gate insulating film 30 made of hafnium oxide and having a thickness of 3.0 nm is formed on the entire surface (see FIG. 2B). The gate insulating film 30 can be formed based on, for example, a CVD method using HfCl ₂ and NH ₃ as source gases, or can be formed based on a CVD method using organic Hf gas as a source gas. Alternatively, it can be formed by forming a hafnium nitride film based on a sputtering method using hafnium nitride as a target and then oxidizing the hafnium nitride film, or forming it based on an ALD method. be able to.

[Step-120]
Next, in Example 1, the first layer of hafnium silicide (HfSi _x ) and having a thickness of 15 nm is formed on the entire surface (specifically, on the gate insulating film 30) based on the sputtering method. 31 is formed (see FIG. 3A).

[Step-130]
Thereafter, the gate insulating film 30 formed on the side wall of the gate electrode forming opening 22 is selectively removed, so that the gate insulating film main body 30A left at the bottom of the gate electrode forming opening 22 and Then, the gate insulating film 30 composed of the gate insulating film extending portion 30B extending from the gate insulating film main body portion 30A to the middle of the side wall of the gate electrode forming opening 22 is obtained. Specifically, the selective removal of the gate insulating film 30 formed on the side wall of the gate electrode forming opening 22 is performed. After the resist layer 40 is formed on the entire surface, the resist layer 40 is etched back to form the gate electrode. The resist layer 40 is left below the opening 22 for use, and then the portion of the gate insulating film 30 exposed on the upper portion of the side wall of the opening 22 for forming the gate electrode is removed, and then the resist layer 40 is removed.

  As described above, the gate electrode 23 includes the first layer 31 and the second layer 32. Therefore, by selectively removing the gate insulating film 30 and the first layer 31 formed on the side wall of the gate electrode forming opening 22, the gate insulating film main body left at the bottom of the gate electrode forming opening 22 is removed. 30 A, the gate insulating film 30 constituted by the gate insulating film extending portion 30 B extending from the gate insulating film main body portion 30 A to the middle of the side wall of the gate electrode forming opening 22, and the channel forming region 12. A first layer 31 is obtained which is formed in the middle of the side surface portion 23 </ b> A of the gate electrode 23 from the bottom surface portion of the opposing gate electrode 23. Here, the portion of the first layer formed on the bottom surface portion of the gate electrode 23 is denoted by reference numeral 31A, and the portion of the first layer 31 formed in the middle of the side surface portion 23A of the gate electrode 23 is denoted by reference numeral 31B. Show.

  More specifically, after the resist layer 40 is formed on the entire surface, the resist layer 40 is etched back to leave the resist layer 40 below the gate electrode formation opening 22 (see FIG. 3B). For example, the etch back of the resist layer 40 may be performed under the following conditions. Next, the portion of the first layer 31 and the portion of the gate insulating film 30 exposed at the upper portion of the side wall of the gate electrode formation opening 22 are removed by a dry etching method based on the following conditions ((A) in FIG. 4). The resist layer 40 is removed based on the ashing method (see FIG. 4B).

[Etch back of resist layer 40]
Gas used: O ₂ / S ₂ Cl ₂ / N ₂ = 30 sccm / 10 sccm / 10 sccm

[Dry etching of the portion of the first layer 31 and the gate insulating film 30]
Gas used: Cl ₂ / BCl ₃ = 35 sccm / 10 sccm
Source power: 1000W
Bias power: 150W
Pressure: 1.3 Pa (10 millitorr)
Substrate temperature: 40 ° C

[Step-140]
Next, the gate electrode 23 is obtained by embedding the gate electrode forming opening 22 with a metal material. Specifically, the remaining portion of the gate electrode forming opening 22 is filled with a second metal material, whereby the gate electrode 23 composed of the first layer 31 and the second layer 32 is obtained.

More specifically, first, a thin film outer layer 32A made of TiN and functioning as a barrier layer is formed on the entire surface based on a sputtering method (see FIG. 5A). The outer layer 32A having a thickness of 10 nm can be formed based on a CVD method, a sputtering method, or an ALD method (using NH ₃ gas and TiCl ₄ gas alternately). Before this, if the first layer made of hafnium silicide (HfSi _x ) in the region where the PMOS is to be formed is removed, and the outer layer 32A made of TiN is formed directly on the region where the PMOS is to be formed. The outer layer 32A functions as a work function control layer in the PMOS, that is, a first layer.

  Thereafter, an inner layer 32B made of tungsten and having a thickness of 0.2 μm is formed on the entire surface based on the so-called blanket-tungsten CVD method, and then a planarization process is performed based on the CMP method. The inner layer 32B and the outer layer 32A on the spacer 17, the first sidewall 18, and the second sidewall 19 are removed (see FIG. 5B). Thus, the gate electrode 23 composed of the second layer 32 including the outer layer 32A and the inner layer 32B can be obtained. Here, the gate electrode 23 is formed above the channel formation region 12 with the gate insulating film 30 interposed therebetween, and includes a first layer 31 and a second layer 32 (an outer layer 32A and an inner layer 32B). ing. The top surface of the gate electrode 23 is only composed of the second layer 32 (the outer layer 32A and the inner layer 32B), and the first layer 31 and the gate insulating film 30 are not exposed. The distance from the top surface of the gate electrode 23 to the upper end portion of the gate insulating film extending portion 30B extending to the middle of the side wall of the gate electrode forming opening 22 is preferably 5 nm or more. Therefore, in [Step-130], when obtaining the gate insulating film 30 composed of the gate insulating film extending portion 30B extending from the gate insulating film main body portion 30A to the middle of the side wall of the gate electrode forming opening 22, Etching of the gate insulating film 30 so that the distance from the top surface of the gate electrode 23 to the upper end of the gate insulating film extending portion 30B extending to the middle of the side wall of the gate electrode forming opening 22 is 5 nm or more. I do.

[Step-150]
Next, an interlayer insulating layer 34 made of SiO ₂ is formed on the entire surface based on a CVD method such as a plasma CVD method, a high-density plasma CVD method, or an atmospheric pressure CVD method (see FIG. 6A).

[Step-160]
Thereafter, contact plug formation openings 35A and 35B are formed in the interlayer insulating layer 34 above the gate electrode 23 and above the source / drain region 13 based on the photolithography technique and the dry etching technique. 6B shows a state at the time when the formation of the contact plug forming opening 35A is completed and a state in the middle of forming the contact plug forming opening 35B, and FIG. The state at the time when the formation of the contact plug forming opening 35B is completed is illustrated. Here, an etching resist layer is actually formed, but the resist layer is not shown.

[Step-170]
Next, in order to form a contact plug, a pretreatment for removing a natural oxide film or the like is performed. Examples of the pretreatment include chemical treatment using dilute hydrofluoric acid, sputtering treatment using argon gas, and etching treatment using fluorine radicals.

[Step-180]
Thereafter, a second barrier layer 36 having a laminated structure of Ti (lower layer) / TiN (upper layer) is formed on the entire surface by sputtering (see FIG. 7B), and WF ₆ gas, H ₂ gas, After forming a tungsten layer on the entire surface based on a blanket tungsten CVD method (deposition temperature: 350 ° C.) using SiH ₄ gas, a planarization process based on the CMP method is performed, thereby forming an opening for forming a contact plug Contact plugs 37A and 37B can be obtained in 35A and 35B (see FIGS. 8A and 8B). Thereafter, an unillustrated wiring or the like is formed on the interlayer insulating layer 34 as necessary, and the insulated gate field effect transistor of Example 1 can be completed.

In Example 1, when the gate electrode is completed by a so-called damascene process, that is, in [Step-140] (see FIG. 5B), the gate insulating film 30 and the first layer 31 are formed. The end face is not exposed. Therefore, in [Step-160], in order to form the contact plug formation openings 35A and 35B, the interlayer insulating layer 34 made of SiO ₂ is dry-etched (see FIG. 6B), and subsequently. The lower insulating layer 21 made of SiO ₂ and the stress liner layer 20 made of SiN are dry-etched (see FIG. 7A), but the gate insulating film 30 and the first layer 31 are not exposed, Therefore, the phenomenon that the gate insulating film 30 and the first layer 31 are etched does not occur. Further, the first layer 31 is not etched by the pretreatment in [Step-170]. Therefore, the reliability of the obtained gate electrode 23 does not deteriorate. In [Step-180], when the contact plug 37A is formed, no void is generated in the contact plug 37A. Furthermore, the constituent material of the portion above the gate electrode 23 to be etched to form the contact plug forming openings 35A and 35B is different from that of the portion above the source / drain region 13, but the gate insulating film 30 is different. Since the upper end surface of the first layer 31 is not exposed, it is easy to optimize the formation conditions of the contact plug forming openings 35A and 35B.

  Example 2 is a modification of Example 1, and specifically Example 2 relates to a method of manufacturing an insulated gate field effect transistor according to the first-A-3 aspect of the present invention.

The second embodiment is the same as the first embodiment in that the first layer 31 is made of hafnium silicide (HfSi _x ), but the second layer 232 is made of nickel silicide. It is different. Further, the formation method of the second layer 232 is different from that of the first embodiment. Hereinafter, with reference to FIGS. 9A, 9 </ b> B, and 10, a manufacturing method of the insulated gate field effect transistor of Example 2 will be described.

[Step-200]
First, the same steps as [Step-100] to [Step-130] of Example 1 are performed.

[Step-210]
Thereafter, the metal material is embedded in the remaining portion of the gate electrode forming opening 22 based on the following method. That is, the conductive material layer 50 is formed below the gate electrode formation opening 22. Specifically, after a conductive material layer 50 made of amorphous silicon is formed on the entire surface based on the CVD method, the conductive material layer 50 is etched in the thickness direction by an etch back method, and a lower portion of the gate electrode formation opening 22 is formed. The conductive material layer 50 is left on (see FIG. 9A). Next, a metal material layer 51 made of nickel having a thickness of 20 nm is formed on the entire surface based on a sputtering method or a CVD method (see FIG. 9B). Thereafter, a heat treatment is performed at 580 ° C. for 60 seconds at normal pressure, whereby the conductive material layer 50 and the metal material layer 51 are chemically reacted to form a nickel silicide layer. Next, the unreacted metal material layer 51 is removed by immersing in a mixed solution in which HCl / H ₂ O ₂ / H ₂ O is mixed at a ratio of 1: 1: 2 for 15 minutes, and then heat treatment is performed again. To stabilize the nickel silicide layer. Thus, the second layer 232 made of the second metal material can be obtained by a chemical reaction between the conductive material layer 50 and the metal material layer 51 (see FIG. 10).

[Conditions for Forming Conductive Material Layer 50 Made of Amorphous Silicon]
Gas used: SiH ₄ / He / N ₂ = 100 sccm / 400 sccm / 200 sccm
Pressure: 70Pa
Substrate temperature: 490 ° C

[Step-220]
Subsequently, the insulated gate field effect transistor of Example 2 can be completed by performing the same processes as [Step-150] to [Step-180] of Example 1.

  The third embodiment is also a modification of the first embodiment. Specifically, the third embodiment includes the insulated gate field effect transistor according to the first-C aspect of the present invention and the first-B of the first embodiment. The present invention relates to a method of manufacturing an insulated gate field effect transistor according to an aspect.

  The third embodiment is different from the first embodiment in that the entire gate electrode 323 is made of nickel silicide 332. Further, the formation method of the gate electrode 323 is different from that of the first embodiment. Hereinafter, with reference to FIGS. 11A and 11B and FIGS. 12A and 12B, a method of manufacturing an insulated gate field effect transistor of Example 3 will be described.

[Step-300]
First, the same steps as [Step-100] to [Step-110] of the first embodiment are performed.

[Step-310]
Thereafter, the gate insulating film 30 formed on the side wall of the gate electrode forming opening 22 is selectively removed, so that the gate insulating film main body 30A left at the bottom of the gate electrode forming opening 22 and Then, the gate insulating film 30 composed of the gate insulating film extending portion 30B extending from the gate insulating film main body portion 30A to the middle of the side wall of the gate electrode forming opening 22 is obtained. Specifically, in the same manner as in [Step-130] of Example 1, after forming a resist layer on the entire surface, the resist layer is etched back to leave the resist layer under the gate electrode formation opening 22, Next, after removing the portion of the gate insulating film 30 exposed on the upper side wall of the gate electrode forming opening 22, the resist layer is removed. Thus, the state shown in FIG. 11A can be obtained.

[Step-320]
Next, the metal material is embedded in the gate electrode formation opening 22 by the following method, that is, after the conductive material layer 50 is formed below the gate electrode formation opening 22, the metal material layer 51 is formed on the entire surface. Next, after the conductive material layer 50 and the metal material layer 51 are chemically reacted, the unreacted metal material layer 51 is removed. Specifically, a step similar to [Step-210] of the second embodiment may be performed (see FIG. 11B, FIG. 12A, and FIG. 12B).

[Step-330]
Subsequently, the insulated gate field effect transistor of Example 3 can be completed by performing the same processes as [Step-150] to [Step-180] of Example 1.

  The fourth embodiment is also a modification of the first embodiment. Specifically, the fourth embodiment includes the insulated gate field effect transistor according to the first-B aspect of the present invention and the first-C of the first embodiment. The present invention relates to a method of manufacturing an insulated gate field effect transistor according to an aspect.

In the insulated gate field effect transistor of Example 4, a schematic partial end view is shown in FIG. 16A, and an enlarged schematic view of the gate electrode 423 and the like is shown in FIG. The gate electrode 423 includes a first layer 431 made of a first metal material, a second layer 432 made of a second metal material different from the first metal material, and a third layer different from the first metal material. The third layer 433 is made of a metal material. Specifically, the first layer (work function control layer) 431 is made of the first metal material (specifically, hafnium silicide [HfSi _x ]), as in the first embodiment. Similarly to the first embodiment, the second layer 432 includes two layers of a thin film outer layer 432A made of TiN and an inner layer 432B made of tungsten (W). Here, as in Example 1, the outer layer 432A functions as a barrier layer and an adhesion improving layer, and also as a metal material layer (work function control layer) for defining the work function of the gate electrode in the PMOS. It has the function of. However, the formation of the outer layer 432A is not essential, and the second layer 432 can be formed of one layer. Furthermore, the third layer 433 is also made of TiN, and is composed of two layers: an outer layer 433A that functions as a barrier layer and an adhesion improving layer, and an inner layer 433B made of tungsten (W).

The outer layer 432A of the second layer 432 is formed in a thin film shape from the bottom surface of the gate electrode 423 facing the channel forming region 12 to the middle of the side surface 423A of the gate electrode 423, as in the first embodiment. Yes. The second layer 432 and the third layer 433 occupy the remaining portion of the gate electrode 423 in the stacked state. Note that the height of the portion of the first layer 431 formed up to the middle of the side surface portion 423A of the gate electrode 423 with respect to the surface of the channel formation region 12 is H _Mt−1 , and the second layer 432 and the third layer 432 Assuming that the height of the interface with the layer 433 is H _Mt-2 , H _Mt-1 <H _Gate and H _Mt-1 ≈H _Mt-2 are satisfied. Furthermore, H _{Ins ≈H Mt−1} ≈H _Mt−2 . The portion of the first layer formed on the bottom surface of the gate electrode 423 is indicated by reference numeral 431A, and the portion of the first layer 431 formed in the middle of the side surface portion 423A of the gate electrode 423 is indicated by reference numeral 431B. . More specifically,
H _Gate ≒ 100nm
H _Ins ≒ 50nm
H _Mt-1 ≒ 50nm
H _Mt-2 ≒ 50nm
It was.

  Further, in the fourth embodiment, similarly to the first embodiment, a contact plug 37A connected to the top surface of the gate electrode 423 is further provided. The bottom surface of the contact plug 37A and the gate insulating film extending portion 430B are provided. A third layer 433 exists between the upper end portions.

  Hereinafter, with reference to FIGS. 13A and 13B, FIGS. 14A and 14B, FIGS. 15A and 15B, and FIG. 16A and FIG. A method for manufacturing the transistor will be described.

[Step-400]
First, the gate insulating film 430, the first layer 431, and the second layer 432 are formed on the channel formation region 12 exposed at the bottom of the gate electrode formation opening 22 and on the side wall of the gate electrode formation opening 22. Sequentially formed. Specifically, the same steps as [Step-100] to [Step-120] of the first embodiment are performed. Next, in the same manner as in [Step-140] of Example 1, first, an outer layer 432A in the second layer made of TiN having a thickness of 10 nm and functioning as a barrier layer is formed on the entire surface ((A in FIG. 13). )reference). Next, in the same manner as in [Step-140] in Example 1, an inner layer 432B in the second layer of tungsten having a thickness of 0.2 μm is formed on the entire surface based on the blanket tungsten CVD method (FIG. 13). (See (B)).

[Step-410]
Thereafter, a resist layer is formed on the entire surface, and then the portion of the gate insulating film 430, the portion of the first layer 431, and the portion of the second layer 432 on the sidewall of the gate electrode formation opening 22 are removed by an etch back method. Thereafter, the resist layer is removed. Specifically, a resist layer is formed on the entire surface, and the inner layer 432B and the outer layer 432A on the lower insulating layer 21 are removed based on an etch back method. Further, in the gate electrode forming opening 22, After selectively removing the inner layer 432B and the outer layer 432A in the second layer, and the first layer 431 and a part of the gate insulating film extending portion 430B, the resist layer is removed. Etch back using the RIE apparatus may be performed under the following conditions. Thus, the gate insulating film main body 430A left at the bottom of the gate electrode forming opening 22, and the gate insulating film extending portion extending from the gate insulating film main body 430A to the middle of the side wall of the gate electrode forming opening 22 A gate insulating film 430 composed of 430B, a first layer 431 formed in the middle of the side surface portion 423A of the gate electrode 423 from the bottom surface portion of the gate electrode 423 facing the channel formation region 12, and gate electrode formation A second layer 432 (an inner layer 432B and an outer layer 432A) that fills the portion in the opening 22 where the first layer 431 is formed can be obtained (see FIG. 14A).

[Etch-back condition of inner layer 432B in second layer]
Gas used: SF ₆ = 100 sccm
Pressure: 1.3 Pa (10 millitorr)
Power: Upper electrode / lower electrode = 800W / 20W
[Etch-back condition of outer layer 432A, first layer 431, and gate insulating film extension 430B in second layer]
Gas used: Cl ₂ / BCl ₃ / Ar = 70 sccm / 30 sccm / 100 sccm
Pressure: 0.8 Pa (6 mTorr)
Power: Upper electrode / lower electrode = 800W / 100W

[Step-420]
Thereafter, the remaining part of the gate electrode forming opening 22 is filled with a third metal material. Specifically, in the same manner as in [Step-140] in Example 1, an outer layer 433A made of TiN and functioning as a barrier layer is formed on the entire surface (see FIG. 14B). The outer layer 433A in the third layer having a thickness of 10 nm can be formed based on a CVD method, a sputtering method, or an ALD method (using NH ₃ gas and TiCl ₄ gas alternately).

  Next, in the same manner as in [Step-140] in Example 1, an inner layer 433B of a third layer having a thickness of 0.2 μm and made of tungsten is formed on the entire surface based on a blanket tungsten CVD method, and then CMP is performed. A planarization process based on the method is performed to remove the lower insulating layer 21, and the inner layer 433B and the outer layer 433A on the offset spacer 17, the first side wall 18, and the second side wall 19 (see FIG. 15). Thus, the third layer 433 including the outer layer 433A and the inner layer 433B, the second layer 432 including the outer layer 432A and the inner layer 432B, and the gate electrode 423 including the first layer 431 are formed. Obtainable. Here, the first layer 431 and the gate insulating film 430 are not exposed on the top surface of the gate electrode 423.

[Step-430]
Next, by performing the same steps as [Step-150] to [Step-180] of Example 1, the insulated gate field effect transistor of Example 4 can be completed (FIG. 16A and FIG. 16). (See (B)). Here, the third layer 433 exists between the bottom surface of the contact plug 37A and the upper end portion of the gate insulating film extending portion 430B.

  Example 5 relates to an insulated gate field effect transistor according to the second aspect of the present invention and a method for manufacturing the insulated gate field effect transistor according to the second aspect of the present invention.

The insulated gate field effect transistor of Example 5 shows a schematic partial end view in FIG. 19A, and an enlarged schematic view of the gate electrode 523 and the like as shown in FIG.
(A) source / drain region 13 and channel forming region 12,
(B) a gate electrode 523 formed above the channel formation region 12, and
(C) a gate insulating film 530,
Is an insulated gate field effect transistor.

  The gate insulating film 530 includes a gate insulating film body 530A formed between the gate electrode 523 and the channel formation region 12, and a gate extending from the gate insulating film body 530A to the top surface of the gate electrode 523. The gate electrode 523 includes a thin film-like first layer 531 made of a first metal material, and a second layer made of a second metal material different from the first metal material. 532 and a third layer 533 made of a third metal material different from the first metal material. The second layer 532 includes an outer layer 532A and an inner layer 532B, and the third layer 533 includes an outer layer 533A and an inner layer 533B. The above components in the insulated gate field effect transistor of the fifth embodiment can be substantially the same as those of the insulated gate field effect transistor of the fourth embodiment.

In the fifth embodiment, the first layer 531 is formed from the bottom surface of the gate electrode 523 facing the channel forming region 12 to the middle of the side surface 523A of the gate electrode 523. The three layers 533 occupy the remaining portion of the gate electrode 523 in the stacked state. Further, as shown in FIG. 19B, the height of the gate electrode 523 when the surface of the channel formation region 12 is used as a reference is H _Gate , and the second portion 523A formed halfway along the side surface portion 523A of the gate electrode 523 is formed. Assuming that the height of the portion of the first layer 531 is H _Mt-1 and the height of the interface between the second layer 532 and the third layer 533 is H _Mt-2 , H _Mt-1 <H _Gate , H _Mt-2 < H _Gate , H _Mt-1 ≈H _Mt-2 is satisfied. More specifically,
0.1 ≦ H _Mt-1 / H _Gate ≦ 0.95
And satisfy
(H _Gate −H _Mt−1 ) ≧ 5 nm is satisfied.

  Further, a contact plug 37A connected to the top surface of the gate electrode 523 is further provided, and a third layer 533 exists between the bottom surface of the contact plug 37A and the upper end portion of the first layer 531.

  Hereinafter, a method for manufacturing an insulated gate field effect transistor of Example 5 will be described with reference to FIGS. 17A, 17B, 18A, and 19B.

[Step-500]
First, the gate insulating film 530 is formed on the channel formation region 12 exposed at the bottom of the gate electrode formation opening 22 and on the sidewall of the gate electrode formation opening 22. Specifically, the same process as [Process-400] of Example 4 is performed. That is, the gate insulating film 530, the first layer 531 and the second layer 532 are formed on the channel formation region 12 exposed at the bottom of the gate electrode formation opening 22 and on the side wall of the gate electrode formation opening 22. Sequentially formed.

[Step-510]
Thereafter, the gate electrode 523 is obtained by filling the gate electrode forming opening 22 with a metal material. Specifically, after a resist layer is formed on the entire surface, the portion of the first layer 531 and the portion of the second layer 532 above the sidewall of the gate electrode formation opening 22 are removed by an etch back method, and then the resist layer Remove. More specifically, a resist layer is formed on the entire surface, the inner layer 532B and the outer layer 532A on the lower insulating layer 21 are removed based on the etch back method, and further, inside the opening 22 for forming the gate electrode. Then, after the inner layer 532B and the outer layer 532A in the second layer and a part of the first layer 531 are selectively removed, the resist layer is removed. Unlike the fourth embodiment, the gate insulating film 530 is not etched. It is possible to achieve a state in which the gate insulating film 530 is not etched by appropriately selecting etch back conditions, for example, gas used for etching, pressure, power applied to the upper and lower electrodes in the RIE apparatus, etching time, and the like. it can. Thus, the gate insulating film main body 530A left at the bottom of the gate electrode forming opening 22, and the gate insulating film extending portion extending from the gate insulating film main body 530A to the upper end of the side wall of the gate electrode forming opening 22. A gate insulating film 530 composed of 530B, a first layer 531 formed in the middle of the side surface 523A of the gate electrode 523 from the bottom surface of the gate electrode 523 facing the channel formation region 12, and gate electrode formation A second layer 532 (an inner layer 532B and an outer layer 532A) that fills the portion in the opening 22 where the first layer 531 is formed can be obtained (see FIG. 17A).

  Next, in the same manner as in [Step-420] in Example 4, the remaining part of the gate electrode forming opening 22 is filled with a third metal material. Thus, the gate electrode 523 including the third layer 533 including the outer layer 533A and the inner layer 533B, the second layer 532 including the outer layer 532A and the inner layer 532B, and the first layer 531 is formed. (See FIG. 17B and FIG. 18). Here, the first layer 531 is not exposed on the top surface of the gate electrode 523.

[Step-520]
Thereafter, the lower insulating layer 21 is removed based on a wet etching method using dilute hydrofluoric acid.

[Step-530]
Next, after a stress liner layer 20 ′ made of SiN is formed again on the entire surface, an interlayer insulating layer 34 ′ made of SiO _{2 is} further formed on the entire surface.

[Step-540]
Thereafter, the same steps as [Step-150] to [Step-180] of Example 1 are performed, whereby the insulated gate field effect transistor of Example 5 can be completed (FIG. 19A and FIG. 19). (See (B)). Here, the third layer 533 exists between the bottom surface of the contact plug 37 </ b> A and the upper end portion of the first layer 531.

In Example 5, the first layer 531 is not exposed on the top surface of the gate electrode 523 when [Step-510] is completed. Therefore, in [Step-520], when the lower insulating layer 21 is removed based on the wet etching method using dilute hydrofluoric acid, the first layer 531 is not damaged. In [Step-540], when the contact plug forming openings 35A and 35B are formed, the stress liner layer 20 ′ made of SiN and SiO ₂ are formed above the top surface of the gate electrode 523 from below. An interlayer insulating layer 34 made of is formed. Therefore, in [Step-540], in order to form the contact plug forming openings 35A and 35B, the interlayer insulating layer 34 made of SiO ₂ is dry-etched, and subsequently the stress liner layer 20 ′ made of SiN. At this time, the gate insulating film 530 is not damaged. Therefore, the reliability of the obtained gate electrode 523 is not lowered. In [Step-540], when the contact plug 37A is formed, no void is generated in the contact plug 37A. Further, the constituent material of the portion above the gate electrode 523 to be etched to form the contact plug forming openings 35A and 35B and the portion above the source / drain region 13 are different, but the first layer 531 is different. Therefore, it is easy to optimize the formation conditions of the contact plug forming openings 35A and 35B.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and configuration of the insulated gate field effect transistor described in the embodiment are examples, and can be appropriately changed. The manufacturing process of the insulated gate field effect transistor described in the embodiment is also an example, and can be appropriately changed. can do.

  In the first embodiment, the insulated gate field effect transistor is an n-channel insulated gate field effect transistor. However, when the p-channel insulated gate field effect transistor is used, for example, the first layer is made of ruthenium (Ru). May be configured. Alternatively, a method of adjusting the work function value by changing the constituent material of the gate insulating film instead of making the work function of the gate electrode a suitable value by changing the constituent material of the gate electrode has been proposed. (For example, JP-A-2006-24594) and such a method can also be applied to the present invention.

Further, in Example 2 or Example 3, instead of forming the resist layer 40 in the same process as [Process-130] in Example 1, the polysilicon layer 50 is formed in the gate electrode forming opening 22. Next, the first layer 31 and the gate insulating film 30 are etched (at this time, the polysilicon layer 50 functions as a kind of resist), and then a metal material layer 51 is formed and silicidized. You may employ | adopt the process of doing. Also in Examples 1 to 4, after forming the gate electrode, the lower insulating layer is removed based on the wet etching method using hydrofluoric acid, and then the stress liner layer made of SiN is formed again on the entire surface. After that, a process of forming an interlayer insulating layer made of SiO _{2 on} the entire surface may be employed.

1A and 1B are schematic partial end views of a semiconductor substrate and the like for explaining a method for manufacturing an insulated gate field effect transistor of Example 1. FIG. 2A and 2B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 1B. is there. 3A and 3B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 2B. is there. 4A and 4B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 3B. is there. 5A and 5B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 4B. is there. 6A and 6B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 5B. is there. FIGS. 7A and 7B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. 6B. is there. FIG. 8A is a schematic partial end view of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 1 following FIG. (B) is a schematic partial sectional view in which a gate electrode and the like are enlarged. FIGS. 9A and 9B are schematic partial end views of a semiconductor substrate and the like for explaining a method for manufacturing an insulated gate field effect transistor according to the second embodiment. FIG. 10 is a schematic partial end view of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 2 following FIG. 9B. 11A and 11B are schematic partial end views of a semiconductor substrate and the like for explaining the method for manufacturing the insulated gate field effect transistor of Example 3. FIG. FIGS. 12A and 12B are schematic partial end views of a semiconductor substrate and the like for explaining the method for manufacturing an insulated gate field effect transistor of Example 3 following FIG. 11B. is there. FIGS. 13A and 13B are schematic partial end views of a semiconductor substrate and the like for explaining the method for manufacturing an insulated gate field effect transistor of Example 4. FIGS. 14A and 14B are schematic partial end views of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 4 following FIG. 13B. is there. FIG. 15 is a schematic partial end view of a semiconductor substrate and the like for explaining the method for manufacturing an insulated gate field effect transistor of Example 4 following FIG. FIG. 16A is a schematic partial end view of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 4 following FIG. 15, and FIG. These are the typical partial cross sections which expanded the gate electrode etc. FIG. 17A and 17B are schematic partial end views of a semiconductor substrate and the like for explaining the method for manufacturing an insulated gate field effect transistor of Example 5. FIG. FIG. 18 is a schematic partial end view of a semiconductor substrate and the like for explaining the method for manufacturing an insulated gate field effect transistor of Example 5 following FIG. FIG. 19A is a schematic partial end view of a semiconductor substrate and the like for explaining the manufacturing method of the insulated gate field effect transistor of Example 5 following FIG. 18, and FIG. These are the typical partial cross sections which expanded the gate electrode etc. FIG. 20A and 20B are schematic partial end views of a semiconductor substrate and the like for explaining a conventional method for manufacturing an insulated gate field effect transistor. FIGS. 21A and 21B are schematic partial end views of a semiconductor substrate and the like for explaining a conventional method for manufacturing an insulated gate field effect transistor, following FIG. 20B. 22A and 22B are schematic partial end views of a semiconductor substrate and the like for explaining a conventional method for manufacturing an insulated gate field effect transistor, following FIG. 21B. 23A and 23B are schematic partial end views of a semiconductor substrate and the like for explaining a conventional method of manufacturing an insulated gate field effect transistor, following FIG. 22B.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Base | substrate, 11 ... Silicon semiconductor substrate, 12 ... Channel formation area | region, 13 ... Source / drain area | region, 13A ... Silicide layer, 14 ... Dummy gate insulating film, 15 ... Dummy polysilicon layer, 15 '... dummy gate electrode, 16 ... hard mask, 17 ... offset spacer, 18 ... first side wall, 19 ... second side wall, 20, 20 '... stress liner layer, 21 ... lower insulating layer, 22 ... opening for gate electrode formation, 23, 323, 423, 523 ... gate electrode, 23A, 423A, 523A ... gate electrode , 30, 430, 530... Gate insulating film, 30 A, 430 A, 530 A... Gate insulating film main body, 30 B, 430 B, 530 B. 31, 31A, 31B, 431, 431A, 431B, 531, 531A, 531B ... 1st layer, 32, 232, 432, 532 ... 2nd layer, 32A, 432A, 532A ... Two outer layers, 32B, 432B, 532B ... inner layer of second layer, 332 ... nickel silicide, 433,533 ... third layer, 433A, 533A ... outside of third layer Layer, 433B, 533B ... inner layer of the third layer, 34, 34 '... interlayer insulating layer, 35A, 35B ... contact plug forming opening, 36 ... second barrier layer, 37A 37B ... contact plug, 40 ... resist layer, 50 ... conductive material layer, 51 ... metal material layer

Claims (5)

(A) a source / drain region and a channel formation region;
(B) an insulating layer formed on the source / drain region and having an opening for forming a gate electrode above the channel formation region;
(C) a gate electrode formed by filling the opening for forming the gate electrode with a metal material;
(D) a gate insulating film, and
(E) a contact plug connected to the top surface of the gate electrode;
An insulated gate field effect transistor comprising:
The gate insulating film, the formed at the bottom of the gate electrode formation openings, the gate insulating film body portion formed between the gate electrode and the channel formation region, and wherein from said gate insulating film main body The gate electrode forming opening extends to the middle of the side wall and includes a gate insulating film extending portion extending to the middle of the side surface of the gate electrode.
The gate electrode is composed of a first layer and a second layer,
The first layer is formed in a thin film shape from the bottom surface of the gate electrode facing the channel formation region to the middle of the side surface of the gate electrode along the side surface of the gate electrode.
The second layer is composed of two layers, an outer layer and an inner layer,
The outer layer of the second layer is formed on the first layer formed in the opening for forming the gate electrode and on the side wall of the opening for forming the gate electrode, and on the side surface of the gate electrode. Is formed in a thin film shape along the portion to the top surface of the gate electrode, thereby covering the first layer and the gate insulating film extending portion,
The inner layer of the second layer is formed by embedding the remainder of the gate electrode formation opening, and occupies the remainder of the gate electrode,
Between the bottom surface of the contact plug and the upper end portion of the gate insulating film extending portion, at least one of the inner layer and the outer layer of the second layer exists,
The gate insulating film is made of hafnium oxide,
The first layer is made of hafnium silicide,
The outer layer of the second layer is made of titanium nitride,
2. The insulated gate field effect transistor according to claim 1, wherein an inner layer of the second layer is made of tungsten . When the height of the gate electrode with respect to the surface of the channel formation region is H _Gate and the height of the gate insulating film extension is H _Ins ,
0.1 ≦ H _Ins / H _Gate ≦ 0.95
And satisfy
The insulated gate field effect transistor according to claim 1, wherein (H _Gate −H _Ins ) ≧ 5 nm is satisfied. (A) A substrate including a source / drain region and a channel formation region, and an insulating layer formed on the source / drain region and having a gate electrode formation opening formed above the channel formation region is prepared. ,
(B) over said channel forming region exposed in the bottom portion of the gate electrode formation opening, and, on the sidewalls of the gate electrode formation openings, to form a gate insulating film, then,
(C) the selectively removing the gate insulating film formed on the side wall of the gate electrode formation openings, than Te, the gate insulating film main body left on the bottom of the gate electrode formation opening, and after obtaining a gate insulating film composed of the gate insulating film extending portion extending from the gate insulating film main body portion to the middle of the side walls of the gate electrode formation openings,
; (D) a gate electrode formation opening portion to form a gate electrode by filling a metal material, then,
(E) After forming an interlayer insulating layer on the entire surface, forming an opening for forming a contact plug in a portion of the interlayer insulating layer above the gate electrode, and then providing a contact plug in the opening for forming the contact plug.
In the method of manufacturing an insulated gate field effect transistor comprising each step ,
The gate electrode is composed of a first layer made of a first metal material and a second layer made of a second metal material different from the first metal material,
The second layer is composed of two layers, an outer layer and an inner layer,
The outer layer of the second layer is formed over the side surface of the gate electrode from above the first layer,
The inner layer of the second layer occupies the remainder of the gate electrode;
Between the bottom surface of the contact plug and the upper end portion of the gate insulating film extending portion, at least one of the inner layer and the outer layer of the second layer exists,
The gate insulating film is made of hafnium oxide,
The first layer is made of hafnium silicide,
The outer layer of the second layer is made of titanium nitride,
The inner layer of the second layer is made of tungsten,
In the step (b), the gate insulating film and the first thin film are formed on the channel formation region exposed at the bottom of the gate electrode formation opening and on the sidewall of the gate electrode formation opening. Forming layers sequentially,
In the step (c), the gate insulating film and the first layer formed on the side wall of the gate electrode formation opening are selectively removed, so that they remain at the bottom of the gate electrode formation opening. The gate insulating film main body and the gate extending from the gate insulating film main body to the middle of the side wall of the gate electrode forming opening and to the middle of the side surface of the gate electrode Formed from the bottom surface portion of the gate electrode facing the channel formation region to the middle of the side surface portion of the gate electrode along the side surface portion of the gate electrode. After obtaining the first thin film layer,
In the step (d), on the first layer formed in the opening for forming the gate electrode, on the side wall of the opening for forming the gate electrode, and along the side surface of the gate electrode. A method of manufacturing an insulated gate field effect transistor, wherein the thin film-shaped outer layer is formed up to a top surface of the gate electrode, and then the remaining portion is embedded with the inner layer . Wherein said gate insulating film and the first layer formed on the side wall of the gate electrode formation opening selective removal in the step (c), after forming on the entire surface resist layer, etching back the resist layer to leave the resist layer in the lower portion of the gate electrode formation opening, then after removing the portion and portions of the gate insulating film of the first layer exposed to the upper side wall of the gate electrode formation opening 4. The method of manufacturing an insulated gate field effect transistor according to claim 3 , further comprising a step of removing the resist layer. Wherein when a reference channel formation region surface, the height H _Gate of the gate electrode, height H _Ins of the gate insulating film extending portion, the formed up to the middle of the side surface portion of the gate electrode first _{4. The} method of manufacturing an insulated gate field effect transistor according to claim 3 , wherein H _Ins <H _Gate and H _{Ins ≈H Mt-1} are satisfied, where H _Mt-1 is the height of the portion of one layer. .

Images