JP4360433B2 - Ferroelectric memory device and electronic device - Google Patents

Description

  The present invention relates to a ferroelectric memory device, and more particularly to a readout circuit of a ferroelectric memory device.

  For reading from a ferroelectric memory device (FeRAM: Ferroelectric Random Access Memory), a method using a latch-type sense amplifier circuit is generally used (for example, see Patent Document 1 below).

  However, in this case, the voltage applied to the plate line is divided into the ferroelectric capacitor capacitance (Cs) and the bit line capacitance (Cbl). Accordingly, a sufficient potential is not applied to the ferroelectric capacitor due to the bit line capacitance (Cbl). In addition, since the difference between the bit line voltages is amplified and read by the sense amplifier, the bit line voltage decreases and the sense margin decreases as the bit line capacitance (Cbl) increases.

Therefore, a read circuit that can virtually fix the bit line to the ground potential has been studied (for example, see Patent Document 2 below).
JP 2000-187990 A JP 2002-133857 A

  However, even when the circuit described in the above-mentioned Patent Document 2 is used, as will be described in detail later, (1) when the ferroelectric capacitor capacitance of the memory cell deviates greatly from the initial setting, (2) the memory cell When the ratio between the ferroelectric capacitor capacity and the tank capacity is significantly changed, the read margin is slightly reduced.

  Further, (3) it is important to improve the read margin while improving erroneous determination. In particular, when reading data from a ferroelectric memory cell, “0” data, which has a small amount of charge, is transferred to the bit line earlier, and the potential of “0” data and the potential of “1” data are temporarily reversed. is there. In such a reverse state, if the potential difference between the “0” data and the “1” data is increased, erroneous determination is likely to occur.

  Therefore, an object of the present invention is to improve the read margin of a ferroelectric memory device. It is another object of the present invention to improve read characteristics of a ferroelectric memory device.

  (1) A ferroelectric memory device according to the present invention includes a first p-channel MISFET connected between a first node and a third node, the gate electrode of which is connected to a second node, and the second node. A first p-channel MISFET whose gate electrode is connected to the first node, and a first charge transfer connected between the first bit line and the third node. A MISFET, a second charge transfer MISFET connected between a second bit line and the fourth node, and a first gate line of the first bit line and the first charge transfer MISFET; Between the first control circuit that controls the potential applied to the first gate electrode according to the potential of the first bit line, and between the second bit line and the second gate electrode of the second charge transfer MISFET. Connected to A second control circuit for controlling a potential applied to the second gate electrode according to a potential of the second bit line, a first capacitor connected to the first node, and a second capacitor connected to the second node. A second capacitor, a first negative potential generating circuit connected to the first bit line, and a second negative potential generating circuit connected to the second bit line.

  According to such a configuration, the first and second p-channel type MISFETs can suppress an increase in the potential of one of the first and second nodes, so that a large potential difference between them can be secured and the read margin can be improved. Can do. Further, by hitting the first and second bit lines to a negative potential by the first and second negative potential generating circuits, the operations of the first and second p-channel MISFETs in the initial stage of reading can be limited, and erroneous determination can be improved.

  Preferably, each of the first and second charge transfer MISFETs is a p-channel type MISFET.

  Preferably, the first control circuit is a first inverter connected between a first bit line and a gate electrode of the first charge transfer MISFET, and the input portion and the first bit line are third. A first inverter connected via a capacitor, and having an output portion connected to the gate electrode of the first charge transfer MISFET via a fourth capacitor; and the second control circuit includes a second bit line and the first inverter A second inverter connected between the gate electrode of the second charge transfer MISFET, the input part of which is connected to the second bit line via a fifth capacitor, the output part of which is connected to the second charge transfer A gate electrode of the MISFET has a second inverter connected via a sixth capacitor. According to such a configuration, the potentials of the first and second bit lines can be fed back to the gate electrodes of the first and second charge transfer MISFETs.

  Preferably, the first negative potential generation circuit includes a seventh capacitor connected between the first bit line and the first signal line, and the second negative potential generation circuit includes the second bit. And an eighth capacitor connected between the first signal line and the first signal line. According to this configuration, it is possible to easily generate a negative potential with an easy configuration.

  For example, the seventh and eighth capacitors are ferroelectric capacitors. As described above, a ferroelectric capacitor may be used as the capacitor.

  Preferably, a ferroelectric memory is connected to each of the first bit line or the second bit line, and the seventh and eighth capacitors have substantially the same capacity as a ferroelectric capacitor constituting the ferroelectric memory. It is. With such a configuration, when the charge for “0” data is canceled and the bit line rises to a positive potential, the reversal of the potential of the “0” data and the potential of the “1” data is corrected.

  For example, a first n-channel type MISFET connected between the output part of the first inverter and a ground potential; a second n-channel type MISFET connected between the output part of the second inverter and the ground potential; Have

  According to such a configuration, the potential of one of the first and second nodes can be raised by the first and second n-channel MISFETs.

  For example, a third n-channel MISFET connected between the output of the first inverter and the first n-channel MISFET and having a gate electrode connected to the input of the first inverter, and the output of the second inverter And a fourth n-channel type MISFET having a gate electrode connected to the input portion of the second inverter.

  According to such a configuration, the third and fourth n-channel MISFETs can raise the potential of one of the first and second nodes while reflecting the potential difference between the first and second bit lines.

  Preferably, the first and second n-channel MISFETs are controlled to be turned on after a certain period after the first and second negative potential generating circuits start operating. According to such a configuration, the first and second negative potential generating circuits can limit the operation of the first and second p-channel MISFETs in the initial stage of reading, and further, the potential of the “0” data during a certain period. And the potential inversion of the “1” data can be corrected, and the potential of one of the first and second nodes can be raised based on the corrected appropriate potential difference. Therefore, it is possible to improve the read margin while preventing erroneous determination.

  For example, a third charge transfer MISFET connected in parallel with the first charge transfer MISFET and a gate electrode connected to a second signal line, and connected in parallel with the second charge transfer MISFET, and a gate electrode connected to the second charge transfer MISFET. And a fourth charge transfer MISFET connected to the signal line.

  According to this configuration, the potential of one of the first and second nodes can be raised by the third and fourth charge transfer MISFETs.

  For example, it is connected between the third node and the ground potential, and is connected between the third p-channel MISFET whose gate electrode is connected to the second signal line, the fourth node, and the ground potential. And a fourth p-channel MISFET whose gate electrode is connected to the second signal line. The third node is a connection node between the first charge transfer MISFET and the first p-channel MISFET. The fourth node is a connection node between the second charge transfer MISFET and the second p-channel MISFET.

  According to such a configuration, the potential of one of the first and second nodes can be raised by the third and fourth p-channel MISFETs.

  For example, a fifth p-channel MISFET connected between the input portion of the first inverter and the power supply potential and having a gate electrode connected to the second signal line, and between the input portion of the second inverter and the power supply potential. And a sixth p-channel type MISFET whose gate electrode is connected to the second signal line.

  According to such a configuration, the potential of one of the first and second nodes can be raised by the fifth and sixth p-channel MISFETs.

  Preferably, the potential of the second signal line is controlled to change after a certain period after the operation of the first and second negative potential generating circuits starts.

  According to such a configuration, the operations of the first and second p-channel MISFETs in the initial stage of reading can be restricted, and further, the inversion of the potential of the “0” data and the potential of the “1” data can be corrected during a certain period. The potential of one of the first and second nodes can be raised based on the corrected appropriate potential difference. Therefore, it is possible to improve the read margin while preventing erroneous determination.

  For example, a ferroelectric memory is connected to each of the first bit line and the second bit line. With this configuration, the present invention can be applied to so-called 2T2C ferroelectric memory cells.

  For example, a ferroelectric memory is connected to the first bit line, and a reference potential is applied to the second bit line. With this configuration, the present invention can be applied to so-called 1T1C ferroelectric memory cells.

  (2) An electronic apparatus according to the present invention includes the ferroelectric memory device. According to such a configuration, the characteristics of the electronic device can be improved. Here, the electronic device refers to a general device having a certain function provided with the ferroelectric memory device according to the present invention, and the configuration thereof is not particularly limited. For example, the electronic device includes the ferroelectric memory device. Computer devices in general, mobile phones, PHS, PDAs, electronic notebooks, IC cards, and other devices that require storage devices are included.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a ferroelectric memory device. As shown in the figure, the ferroelectric memory device 100 includes a memory cell array 110 and peripheral circuit units (120, 130, 140, etc.). The memory cell array 110 is composed of a plurality of memory cells arranged in an array, and each memory cell is arranged at the intersection of the word line WL and the bit lines BL-L and BL-R. Here, a 2T2C cell will be described as an example. Therefore, one data is stored by two transistors and two ferroelectric capacitors respectively connected to the bit lines BL-L and BL-R. Further, the word line control unit 120 and the plate line control unit 130 configuring the peripheral circuit control voltages of the plurality of word lines WL and the plurality of plate lines PL. By these controls, data stored in the memory cell MC is read to the plurality of bit lines BL, and data supplied from the outside is written to the memory cell MC via the bit line BL. Such reading and writing are performed by the bit line control unit 140.

  FIG. 2 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of the present embodiment.

  As shown, the bit lines BL-L and BL-R are connected to the first node Vmn-L via p-channel MISFETs (Charge Transfer MISFETs: Metal Insulator Semiconductor Field Effect Transistors) T2-L and T2-R, respectively. And connected to the second node Vmn-R.

  On the other hand, tank capacitors C5-L and C5-R are connected between the first node Vmn-L and the second node Vmn-R and the ground potential (reference potential, GND, Vss), respectively. Further, negative potential generating circuits 17-L and 17-R are connected to the first node Vmn-L and the second node Vmn-R via switching transistors VswmL and VswmR, respectively. Although the ferroelectric capacitors are used here as the tank capacitors C5-L and C5-R, paraelectric capacitors may be used. However, if a ferroelectric capacitor is used, a large capacity can be obtained with a small area.

With the above configuration, even if a potential is transferred from the memory cell to the bit lines BL-L and BL-R, the negative charges accumulated in the first and second tank capacitors are transferred to the p-channel type MISFETs T2-L and T2-R. By transferring via the bit line, the bit line can be virtually fixed to the ground potential. Therefore, most of the read voltage applied to the plate line can be applied to the ferroelectric capacitor of the memory cell, and the read margin can be improved. In addition, the reading speed can be improved. Further, since the influence of the bit line capacity can be reduced, the above-mentioned good characteristics can be maintained even if the bit line length is increased by increasing the capacity of the memory cell.
Hereinafter, the circuit of FIG. 2 will be described in more detail.

  The gate electrodes (nodes Vthg-L and Vthg-R) of the p-channel type MISFETs T2-L and T2-R are respectively connected to threshold potential (Vth) generation circuits 15-L and 15-R via switching transistors VswL and VswR, respectively. Is connected.

  Further, inverter amplifier circuits 13-L and 13-R are connected between the bit lines BL-L and BL-R and the gate electrodes of the p-channel type MISFETs T2-L and T2-R, respectively. The inverter amplifier circuits 13-L, 13-R are configured by inverters INVL, INVR, capacitors C1-L, C1-R, C2-L, C2-R and resistors RL, RR.

  Specifically, the bit line BL-L and the input part of the inverter INVL are connected via a capacitor C1-L, and the gate electrode of the p-channel MISFET T2-L and the output part of the inverter INVL have a capacitor C2-L. Connected through. Moreover, the input part and output part of inverter INVL are connected via resistance RL.

  Similarly, the input part of the bit line BL-R and the inverter INVR is connected via the capacitor C1-R, and the gate electrode of the p-channel type MISFET T2-R and the output part of the inverter INVR are connected via the capacitor C2-R. It is connected. Further, the input part and the output part of the inverter INVR are connected via a resistor RR.

  The inverter amplifier circuits 13-L and 13-R use paraelectric capacitors as the capacitors C1-L, C1-R, C2-L, and C2-R, but may also use ferroelectric capacitors. Good. The inverter amplifier circuits 13-L and 13-R play a role of more firmly fixing the bit line to the ground potential by feeding back the bit line potential to the gate electrode of the p-channel type MISFET.

  Further, positive potential conversion circuits (L / S) 19-L and 19-R are connected to the first node Vmn-L and the second node Vmn-R, and their outputs (signals) Vsf-L and Vsf- Reading is performed by determining the potential difference of R by the latch circuit 20.

  In this embodiment, p-channel MISFETs P1-L and P1-R are respectively provided between the p-channel MISFETs T2-L and T2-R and the first and second nodes Vmn-L and Vmn-R. It is connected. The gate electrode of the p-channel type MISFET P1-L is connected to the second node Vmn-R, and the gate electrode of the p-channel type MISFET P1-R is connected to the first node Vmn-L. The cross-connected p-channel type MISFETs P1-L and P1-R are referred to as a circuit 30. As will be described later, this circuit 30 can be said to be an electric charge countermeasure circuit.

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. 3 and 4 show timing charts (potential simulation) at the time of reading from the ferroelectric memory device.

  As shown in FIG. 3A, the control signal Vthgen of the threshold potential generation circuits 15-L and 15-R is set to the H level (high potential level), and the threshold potential generation circuits 15-L and 15-R are connected to the p-channel type. The threshold potentials of MISFETs T2-L and T2-R are output. At this time, the common control signal Vsw of the switching transistors VswL and VswR is at the H level, and the switching transistors VswL and VswR are in the on state (see FIG. 3B). Therefore, the threshold potential is supplied to the gates of the p-channel type MISFETs T2-L and T2-R. Next, the potential of the word line WL is set to the H level (see WL in FIG. 4).

  Further, the control signal Vsw is set to L level (low potential level), and the switching transistors VswL and VswR are turned off. Thereby, the nodes Vthg-L and Vthg-R are in a floating state.

  Next, the control signal Vmngen of the negative potential generation circuits 17-L and 17-R is set to the H level, and negative potentials are output from the negative potential generation circuits 17-L and 17-R. At this time, the common control signal Vswm of the switching transistors VswmR and VswmL is at the H level, and the switching transistors VswmR and VswmL are in the on (conductive) state (see FIG. 3D). Therefore, the first node Vmn-L and the second node Vmn-R are negative potentials. In other words, negative charges are charged in the tank capacitors C5-L and C5-R.

  Next, the control signal Vswm is set to L level, and the switching transistors VswmR and VswmL are turned off. As a result, the first node Vmn-L and the second node Vmn-R are in a floating state.

  Next, the plate line PL is set to the H level (see PL in FIG. 4). As a result, the charge of the memory cell is read out. In other words, the charge of the memory cell is transferred to the bit lines BL-L and BL-R.

  Due to the charge transfer, the potentials of the bit lines BL-L and BL-R rise. By amplifying this potential increase in the opposite phase by the inverter amplifiers 13-L and 13-R, the potentials of the nodes Vthg-L and Vthg-R are decreased. The amount of potential change (decrease width) depends on the amount of potential change (increase amount) of the bit line. That is, it depends on the difference in charge amount between “0” data and “1” data in the memory cell.

  Here, when the potentials of the nodes Vthg-L and Vthg-R are lowered, the p-channel MISFETs T2-L and T2-R are turned on. Therefore, charges are transferred from the bit lines BL-L and BL-R to the tank capacitors C5-L and C5-R charged to a negative potential. That is, the potentials of the first node Vmn-L and the second node Vmn-R rise. When all the charges of the memory cells are transferred to the tank capacitors C5-L and C5-R, the potentials of the bit lines BL-L and BL-R are lowered, the potentials of the nodes Vthg-L and Vthg-R are raised, and p Channel type MISFETs T2-L and T2-R are turned off. Therefore, the potential increase at the first node Vmn-L and the second node Vmn-R stops. At this time, the potential fluctuations of the nodes Vthg-L and Vthg-R differ depending on the charge amounts of the “0” data and “1” data of the memory cell, and correspondingly, the first node Vmn-L and the second node Vmn. The increase range of the potential of -R is different. That is, a potential difference is generated between the first node Vmn-L and the second node Vmn-R due to the difference in charge amount between the “0” data and the “1” data.

  Here, in the present embodiment, as described above, the p-channel MISFETs P1-L and P1-R (30) that are cross-connected are provided in the sense amplifier circuit, so that the following operation is performed.

  That is, the higher one of the first node Vmn-L and the second node Vmn-R first reaches the threshold potential (Vth) of the p-channel MISFETs P1-L and P1-R, and the other side The p-channel type MISFET is turned off. In FIG. 4, since the second node Vmn-R has already reached the threshold potential (here, -0.7 V), the p-channel MISFET P1-L is turned off. As a result, the rise in the potential of the first node Vmn-L stops (see Vmn-R and Vmn-L in FIG. 4).

  In this manner, in this embodiment, since the increase in the potential of one of the first node Vmn-L and the second node Vmn-R can be suppressed regardless of the potentials of the nodes Vthg-L and Vthg-R, A large potential difference can be secured. Therefore, the read margin can be improved.

  Hereinafter, the effects of the present embodiment will be described in more detail with reference to the comparison circuit (FIG. 5).

  FIG. 5 is a configuration diagram of the sense amplifier circuit when the cross-connected p-channel type MISFETs P1-L and P1-R are not used. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. In the circuit shown in FIG. 5, p-channel type MISFETs T2-L and T2-R are directly connected to the first node Vmn-L and the second node Vmn-R, respectively.

  In such a circuit, (1) when the ferroelectric capacitor capacity of the memory cell deviates greatly from the initial setting, (2) when the ratio between the ferroelectric capacitor capacity of the memory cell and the tank capacity changes significantly, the read margin Decreases.

  For example, FIG. 6 shows a simulation result in the case where the ferroelectric capacitor capacity (“0” data charge amount) of the memory cell is large. In this case, it can be said that the ferroelectric capacitor capacity of the memory cell is relatively larger than the tank capacity.

  In this case, as shown in FIG. 6, the first node Vmn-L corresponding to “0” data rises greatly. On the other hand, since the second node Vmn-R corresponding to the “1” data rises only to a predetermined potential (in this case, 0.7 V), the potential difference between the first node Vmn-L and the second node Vmn-R is small. turn into. Accordingly, correspondingly, the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R is also reduced. In the positive potential conversion, a conversion loss usually occurs, so that the potential difference is further reduced.

  On the other hand, in the present embodiment, as described above, an increase in one potential of the first node Vmn-L and the second node Vmn-R (Vmn-L in FIG. 4) can be suppressed. A large potential difference can be secured. In other words, the potential difference between the first node Vmn-L and the second node Vmn-R can be equal to or greater than Vth. Therefore, the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R can be increased. That is, since the potentials of the first node Vmn-L and the second node Vmn-R are negative potentials, it is necessary to convert them to positive potentials and latch the difference. Accordingly, the latch circuit 20 is turned on after a predetermined time when the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R becomes large, and the read signal is output as a digital signal (H or L). To do.

  Thus, the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R can be increased. Further, since a potential difference of at least Vth is secured, the potential difference between the outputs Vsf-L and Vsf-R can be increased regardless of the setting (conversion loss) of the positive potential conversion circuit.

  As described in detail above, according to the present embodiment, the read margin can be improved. Further, the reading out characteristics can be improved. 4 and 6 also show changes in potentials of the nodes Vthg-L and Vthg-R.

(Embodiment 2)
In the first embodiment, the countermeasure when the ferroelectric capacitor capacity (the amount of charge of “0” data) of the memory cell is large has been described. In the present embodiment, the ferroelectric capacitor capacity (“1”) is described. A countermeasure when the “data charge amount” is small will be described. In this case, it can be said that the ferroelectric capacitor capacity of the memory cell is relatively small compared to the tank capacity. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 7 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of the present embodiment. A circuit 40 is incorporated in the circuit shown in FIG.

  That is, the p-channel MISFET P3- is connected to the third node Vc-L and the fourth node Vc-R, which are connection nodes between the p-channel MISFETs T2-L and T2-R and the p-channel MISFETs P1-L and P1-R. L and P3-R are connected.

  Specifically, a p-channel MISFET P3-L is connected between the third node Vc-L and the ground potential, and a p-channel MISFET P3-R is connected between the fourth node Vc-R and the ground potential. It is connected. The gate electrodes of the p-channel type MISFETs P3-L and P3-R are connected to the signal line Vupb via the capacitor C7. The back gates of the p-channel type MISFETs P3-L and P3-R are connected to the ground potential. By connecting in this way, leakage current to the substrate can be reduced. Note that signal lines and signals may be denoted by the same reference numerals. Although a paraelectric capacitor is used here as the capacitor C7, a ferroelectric capacitor may be used.

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. 8 and 9 are timing charts at the time of reading from the ferroelectric memory device. The detailed description of the same operation as that of the first embodiment is omitted, and in particular, the operation related to the circuit 40 will be described in detail. Further, (A) to (D) of FIG. 8 have the same waveforms as (A) to (D) of FIG.

  As described with reference to FIG. 3 and the like in the first embodiment, the control signal Vthgen is set to the H level (see FIGS. 3A and 8A), and the p-channel type MISFETs T2-L and T2-R are set. , Supply a threshold potential. Next, the potential of the word line WL is set to the H level (see WL in FIG. 9). Further, the control signal Vsw is set to the L level (see FIGS. 3B and 8B), and the nodes Vthg-L and Vthg-R are set in a floating state. Next, the control signal Vmngen is set to the H level (see FIGS. 3C and 8C), and negative charges are charged in the tank capacitors C5-L and C5-R. Next, the control signal Vswm is set to the L level (see FIGS. 3D and 8D), and the first node Vmn-L and the second node Vmn-R are set in a floating state.

  Next, the plate line PL is set to the H level (see PL in FIG. 9). As a result, as described in the first embodiment, the charge of the memory cell is transferred to the bit lines BL-L and BL-R. Furthermore, the potentials of the first node Vmn-L and the second node Vmn-R rise.

  Here, in this embodiment, as described above, since the p-channel type MISFETs P3-L and P3-R (40) are provided, the following operation is performed.

  That is, as shown in FIG. 8E, the control signal Vup is set to the H level for a certain period (for example, after the period t1 from the rise of the plate line PL). That is, Vupb, which is an inverted signal of Vup, becomes L level. Therefore, a signal is transmitted through the capacitor C7, and the p-channel MISFETs P3-L and P3-R are turned on. Therefore, the third node Vc-L and the fourth node Vc-R which are negative potentials are connected to the ground potential, and the first node Vmn-L and the second node Vmn-R which are negative potentials rise.

  Thereafter, as described in detail in the first embodiment, the higher one of the first node Vmn-L and the second node Vmn-R has the higher p-channel type MISFETs P1-L, P1. The threshold potential of −R is reached and the other p-channel MISFET is turned off. In FIG. 9, the potential of the second node Vmn-R is first raised to the threshold potential (here, -0.7 V), and the p-channel MISFET P1-L is turned off. As a result, the rise in the potential of the first node Vmn-L stops (see Vmn-R and Vmn-L in FIG. 9).

  As described above, in this embodiment, since the ferroelectric capacitor capacity of the memory cell is small, the potential of the first and second nodes Vmn-L and Vmn-R is increased in the charge transfer from the memory cell. Even if the number is small, it is possible to ensure a large potential difference. Therefore, the read margin can be improved.

  Hereinafter, the effects of the present embodiment will be described in more detail with reference to the above-described comparison circuit (FIG. 5).

  FIG. 10 shows a simulation result in the case where the ferroelectric capacitor capacity (charge amount of “1” data) of the memory cell is small in the comparison circuit shown in FIG.

  In this case, as shown in FIG. 10, the transfer (extraction) of the potential from the memory cell ends early, and the potential increase of the second node Vmn-R corresponding to the “1” data stops. Therefore, the potential difference between the first node Vmn-L and the second node Vmn-R is reduced, and the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R is also corresponding to this. It gets smaller. In the positive potential conversion, a conversion loss usually occurs, so that the potential difference is further reduced.

  On the other hand, in this embodiment, as described above, the circuit 30 sets the potentials of the first node Vmn-L and the second node Vmn-R by the p-channel type MISFETs P3-L and P3-R (40). It can be raised to an operating potential. The potential difference between the first node Vmn-L and the second node Vmn-R can be made equal to or greater than Vth.

  Therefore, the potential difference between the outputs Vsf-L and Vsf-R of the positive potential conversion circuits 19-L and 19-R can be increased. Further, since a potential difference of at least Vth is secured, the potential difference between the outputs Vsf-L and Vsf-R can be increased regardless of the settings (conversion loss) of the positive potential conversion circuits 19-L and 19-R. . As a result, the read margin can be improved. Reading characteristics can be improved. 9 and 10 also show changes in potentials of the nodes Vthg-L and Vthg-R (the same applies to FIG. 11).

  Of course, since the circuit 30 is provided in the present embodiment, even when the ferroelectric capacitor capacity (the amount of charge of “0” data) of the memory cell described in detail in the first embodiment is large. Can respond.

  FIG. 11 shows a simulation result when the ferroelectric capacitor capacitance (charge amount of “0” data) of the memory cell is large in the circuit of FIG. In this case, the circuit 30 operates before the timing at which the control signal Vup becomes H level, and a potential difference between the first node Vmn-L and the second node Vmn-R can be ensured. The operation of the circuit 30 is as described in the first embodiment. Therefore, the result of FIG. 11 is the same as that of FIG.

  Thus, according to the present embodiment, it is possible to cope with the case where the ferroelectric capacitor capacity of the memory cell is increased or decreased.

  Further, the tank capacities C5-L and C5-R can be constituted by gate capacities, for example. The gate capacitance is a capacitance composed of a substrate, an insulating film on the substrate, and a conductive film thereover, and this conductive film can be formed of the same material (process) as the gate electrode of the MISFET.

  That is, when tank capacitors are formed of a material different from the ferroelectric capacitors constituting the memory cells, it is difficult to control the capacitance ratio to a predetermined capacity in the usage state because the piezoelectric characteristics and temperature characteristics of these capacitors are different. It is. However, according to the present embodiment, even if these capacitance ratios change, the circuits 30 and 40 can compensate for them as described above. Therefore, the tank capacity can be constituted by the gate electrode. If the tank capacity is constituted by a gate capacity, process variations can be reduced as compared with a ferroelectric capacity. Of course, the tank capacitance may be configured using a conductive film (for example, wiring) other than the gate electrode.

(Embodiment 3)
In this embodiment, another configuration example of the small charge countermeasure circuit (40) will be described. In addition, the same code | symbol is attached | subjected to the same location as Embodiment 1, 2, and the detailed description is abbreviate | omitted.

  FIG. 12 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of the present embodiment. Circuits 40A-L and 40A-R are incorporated in the circuit shown in FIG.

  That is, the n-channel type MISFET N1-L is connected between the output part of the inverter INVL and the ground potential, and the n-channel type MISFET N1-R is connected between the output part of the inverter INVR and the ground potential. The gate electrodes of these n-channel type MISFETs N1-L and N1-R are connected to the signal line Vup.

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. Operations of various signals and the like are the same as those in the second embodiment (FIGS. 8 and 9). Therefore, here, the operation of the circuits 40A-L and 40A-R after the change of the control signal Vup to the H level will be described.

  As shown in FIG. 8E, when the control signal Vup becomes H level after a certain period from the start of the read operation (for example, after t1 from the rise of the plate line PL), the n-channel type MISFETs N1-L, N1- R is turned on. Therefore, the potentials at the output portions of the inverters INBL and INBR are lowered, and the potentials at the nodes Vthg-L and Vthg-R are lowered accordingly. Therefore, the p-channel MISFETs T2-L and T2-R are turned on, and the bit lines BL-L and BL-R are connected to the first and second nodes Vmn-L and Vmn-R which are negative potential nodes. As a result, the potentials of the first and second nodes Vmn-L and Vmn-R rise. That is, when transfer (extraction) of charges from the memory cell is completed and the potentials of the nodes Vthg-L and Vthg-R are not changed, the p-channel type MISFETs T2-L and T2-R are turned off. However, here, the p-channel MISFETs T2-L and T2-R are forcibly turned on by the n-channel MISFETs N1-L and N1-R, and the potentials of the first and second nodes Vmn-L and Vmn-R are set. Raise.

  Thereafter, as described in the second embodiment, the higher one of the first node Vmn-L and the second node Vmn-R has the p-channel type MISFETs P1-L, P1-R first. And the other side p-channel MISFET is turned off. In FIG. 9, the potential of the second node Vmn-R is first raised to the threshold potential (here, -0.7 V), and the p-channel MISFET P1-L is turned off. As a result, the rise in the potential of the first node Vmn-L stops (see Vmn-R and Vmn-L in FIG. 9).

  As described above, in the present embodiment, as in the second embodiment, even when the ferroelectric capacitor capacitance of the memory cell is small, the potential difference between the first and second nodes Vmn-L and Vmn-R. Can be secured greatly. Therefore, the read margin can be improved. Of course, since the circuit 30 is also provided in this embodiment, it is possible to cope with the case where the ferroelectric capacitor capacity of the memory cell described in detail in Embodiment 1 is large.

(Embodiment 4)
In the present embodiment, still another configuration example of the small charge countermeasure circuit (40) will be described. In addition, the same code | symbol is attached | subjected to the same location as Embodiment 1, 2, 3, and the detailed description is abbreviate | omitted.

  FIG. 13 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of this embodiment. Circuits 40B-L and 40B-R are incorporated in the circuit shown in FIG.

  That is, a p-channel type MISFET P2-L is connected between the input portion of the inverter INVL and the power supply potential (drive potential, Vcc, Vdd), and the p-channel type MISFET P2-R is connected between the input portion of the inverter INVR and the power supply potential. Is connected. The gate electrodes of these p-channel type MISFETs P2-L and P2-R are connected to the signal line Vupb.

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. Operations of various signals and the like are the same as those in the second embodiment (FIGS. 8 and 9). Therefore, here, the operation of the circuits 40B-L and 40B-R after the change of the control signal Vupb to the L level will be described.

  As shown in FIG. 8E, when the control signal Vup becomes H level after a certain period from the start of the read operation (for example, after t1 from the rise of the plate line PL), Vupb which is an inverted signal of Vup is L The p-channel type MISFETs P2-L and P2-R are turned on. Therefore, the potentials at the input portions of the inverters INBL and INBR are increased, and the potentials at the output portions of the inverters INBL and INBR are decreased. Correspondingly, the potentials of the nodes Vthg-L and Vthg-R are lowered. Therefore, the p-channel MISFETs T2-L and T2-R are turned on, and the bit lines BL-L and BL-R are connected to the first and second nodes Vmn-L and Vmn-R which are negative potential nodes. As a result, the potentials of the first and second nodes Vmn-L and Vmn-R rise. That is, when the transfer (extraction) of charges from the memory cell is completed and the potentials of the nodes Vthg-L and Vthg-R no longer change, the p-channel MISFETs T2-L and T2-R are turned off. However, here, the p-channel type MISFETs P2-L and P2-R are forced to turn on the p-channel type MISFETs T2-L and T2-R, and the potentials of the first and second nodes Vmn-L and Vmn-R are set. Raise.

  Thereafter, as described in the second embodiment, the higher one of the first node Vmn-L and the second node Vmn-R has the p-channel type MISFETs P1-L, P1-R first. And the other side p-channel MISFET is turned off. In FIG. 9, the potential of the second node Vmn-R is first raised to the threshold potential (here, -0.7 V), and the p-channel MISFET P1-L is turned off. As a result, the rise in the potential of the first node Vmn-L stops (see Vmn-R and Vmn-L in FIG. 9).

  As described above, in the present embodiment, as in the second embodiment, even when the ferroelectric capacitor capacitance of the memory cell is small, the potential difference between the first and second nodes Vmn-L and Vmn-R. Can be secured greatly. Therefore, the read margin can be improved. Of course, since the circuit 30 is also provided in this embodiment, it is possible to cope with the case where the ferroelectric capacitor capacity of the memory cell described in detail in Embodiment 1 is large.

  Next, further effects of the small charge countermeasure circuits (40, 40A-L / R, 40B-L / R) described in the second to fourth embodiments will be described.

  In the small charge countermeasure circuit 40 of the second embodiment, the first and second nodes Vmn-L and Vmn-R can be reliably pulled up by the control signal Vupb. Further, since it is controlled separately from the bit lines BL-L and BL-R, it is difficult to give noise to the bit lines BL-L and BL-R.

  In the small charge countermeasure circuits 40A-L / R and 40B-L / R of the third and fourth embodiments, it is not necessary to form the capacitor C7 for controlling the MISFET with a positive potential, and the circuit area is reduced. be able to.

  In addition, in the small charge countermeasure circuit 40B-L / R of the fourth embodiment, since the potential on the input side of the inverters INVL and INVR is controlled, the input / output potentials of the inverters INVL and INVR can be fixed at the H level and the L level. Through current can be reduced.

  In the above embodiment, a 2T2C ferroelectric memory has been described as an example. However, in the present invention, 1T1C (for example, open bit type 1T1C) ferroelectric in which a reference potential is applied to one bit line is described. It is also applicable to body memory.

(Embodiment 5)
FIG. 14 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of the present embodiment. In the circuit shown in FIG. 2, negative potential generation circuits 50-L, 50-R and pull-up circuits (charge-reduction countermeasure circuits) 41A-L, 41A-R are incorporated. In the following description, components having the same functions as those in the first to fourth embodiments are given the same or related reference numerals, and repeated description thereof is omitted. In the following description, signal lines and signals (potentials) may be denoted by the same reference numerals.

  That is, the negative potential generation circuits 50-L and 50-R have capacitors C8-R and C8-L, respectively, and the capacitor C8-R is connected between the bit line BL-R and the signal line Vblm. The capacitor C8-L is connected between the bit line BL-L and the signal line Vblm. Here, ferroelectric capacitors are used as the capacitors C8-R and C8-L, but paraelectric capacitors may be used.

  The pull-up circuits 41A-L and 41A-R each have two n-channel MISFETs (N2-L and N1-L, N2-R and N1-R). That is, n-channel MISFETs N2-L and N1-L are connected in series between the output part of the inverter INVL and the ground potential (reference potential, GND, Vss). The gate electrode of the n-channel MISFET N2-L The gate electrode of the n-channel MISFET N1-L is connected to the signal line Vup. Also, n-channel type MISFETs N2-R and N1-R are connected in series between the output part of the inverter INVL and the ground potential, and the gate electrode of the n-channel type MISFET N2-R is connected to the input part of the inverter INVR. The gate electrode of the n-channel type MISFET N1-R is connected to the signal line Vup.

  Other configurations are the same as those of the first embodiment (FIG. 2). Briefly, the bit lines BL-L and BL-R are connected to the first node Vmn-L and the second node via the two p-channel type MISFETs T2-L and P1-L, T2-R and P1-R, respectively. It is connected to the node Vmn-R. A connection node between the p-channel type MISFET T2-L and P1-L is Vc-L, and a connection node between the p-channel type MISFET T2-R and P1-R2 is Vc-R.

  On the other hand, tank capacitors C5-L and C5-R are connected between the first node Vmn-L and the second node Vmn-R and the ground potential, respectively.

  Further, negative potential generating circuits 17-L and 17-R are connected to the first node Vmn-L and the second node Vmn-R via switching transistors VswmL and VswmR, respectively.

  Further, positive potential conversion circuits (L / S) 19-L and 19-R are connected to the first node Vmn-L and the second node Vmn-R, and their outputs (signals) Vsf-L and Vsf- Reading is performed by determining the potential difference of R by the latch circuit 20.

  Further, the gate electrodes (nodes Vthg-L, Vthg-R) of the p-channel type MISFETs T2-L, T2-R are respectively connected to threshold potential (Vth) generation circuits 15-L, 15 through switching transistors VswL, VswR. -R is connected.

  In addition, inverter amplifier circuits (control circuit, feedback circuit) 13-L and 13-R are respectively provided between the bit lines BL-L and BL-R and the gate electrodes of the p-channel type MISFETs T2-L and T2-R. It is connected. The inverter amplifier circuits 13-L, 13-R are configured by inverters INVL, INVR, capacitors C1-L, C1-R, C2-L, C2-R and resistors RL, RR. These resistors RL and RR may be switching transistors.

  Specifically, the bit line BL-L and the input part of the inverter INVL are connected via a capacitor C1-L, and the gate electrode of the p-channel MISFET T2-L and the output part of the inverter INVL have a capacitor C2-L. Connected through. Moreover, the input part and output part of inverter INVL are connected via resistance RL.

  Similarly, the input part of the bit line BL-R and the inverter INVR is connected via the capacitor C1-R, and the gate electrode of the p-channel type MISFET T2-R and the output part of the inverter INVR are connected via the capacitor C2-R. It is connected. Further, the input part and the output part of the inverter INVR are connected via a resistor RR.

  The gate electrode of the p-channel type MISFET P1-L is connected to the second node Vmn-R, and the gate electrode of the p-channel type MISFET P1-R is connected to the first node Vmn-L. The cross-connected p-channel type MISFETs P1-L and P1-R are referred to as a circuit 30 (large charge countermeasure circuit).

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. 15 and 16 show timing charts at the time of reading in the ferroelectric memory device of the present embodiment. The horizontal axis represents time [ns], and the vertical axis represents potential [V].

  As shown in FIG. 15A, the control signal Vthgen of the threshold potential generating circuits 15-L and 15-R is set to the H level (high potential level), and the threshold potential generating circuits 15-L and 15-R are connected to the p-channel type. The threshold potentials of MISFETs T2-L and T2-R are output. At this time, the common control signal Vsw of the switching transistors VswL and VswR is at the H level, and the switching transistors VswL and VswR are in the on (conductive) state (see FIG. 15B). Therefore, the threshold potential is supplied to the gate electrodes of the p-channel type MISFETs T2-L and T2-R.

  Next, the control signal Vsw is set to L level (low potential level), and the switching transistors VswL and VswR are turned off (see FIG. 15B). Thereby, the nodes Vthg-L and Vthg-R are in a floating state.

  Next, the potential of the word line WL is set to the H level (see WL in FIG. 16). Further, the control signal Vmngen of the negative potential generation circuits 17-L and 17-R is set to the H level, and negative potentials are output from the negative potential generation circuits 17-L and 17-R (see FIG. 15C). At this time, the common control signal Vswm of the switching transistors VswmR and VswmL is at the H level, and the switching transistors VswmR and VswmL are in the on state (see FIG. 15D). Therefore, the first node Vmn-L and the second node Vmn-R are negative potentials. In other words, negative charges are charged in the tank capacitors C5-L and C5-R.

  Next, the signal Vblm is changed from the H level to the L level (see FIG. 15E), and the potentials of the bit lines BL-L and BL-R are lowered. That is, the potential of the bit lines BL-L and BL-R is tapped from the ground potential to the negative potential. For example, it can be confirmed that the potentials of the bit lines BL-L and BL-R slightly decrease from around 0 V to a negative potential around 15 ns in FIG. Note that the fall of the signal Vblm (change from the H level to the L level) may be performed before and after the rise (reading start) of the plate line PL, and is not limited to the timing.

  Corresponding to the potential change of the bit lines BL-L and BL-R, the potentials of the nodes Vthg-L and Vthg-R rise. That is, in response to the potentials of the bit lines BL-L and BL-R being lowered, the potentials at the input portions of the inverters INVL and INVR are lowered and the potentials at the output portion are raised. Accordingly, the potentials of the nodes Vthg-L and Vthg-R are increased.

  Next, the control signal Vswm is set to L level, and the switching transistors VswmR and VswmL are turned off (see FIG. 15D). As a result, the first node Vmn-L and the second node Vmn-R are in a floating state.

  Next, the plate line PL is set to the H level (see PL in FIG. 16). As a result, the charge of the memory cell is read out. In other words, the charge of the memory cell is transferred to the bit lines BL-L and BL-R.

  Due to the charge transfer, the potentials of the bit lines BL-L and BL-R rise. By amplifying this potential increase in the opposite phase by the inverter amplifiers 13-L and 13-R, the potentials of the nodes Vthg-L and Vthg-R are decreased. The amount of potential change (decrease width) depends on the amount of potential change (increase amount) of the bit line. That is, it depends on the difference in charge amount between “0” data and “1” data in the memory cell.

  Here, when the potentials of the nodes Vthg-L and Vthg-R are lowered, the p-channel MISFETs T2-L and T2-R are turned on. Therefore, charges are transferred from the bit lines BL-L and BL-R to the tank capacitors C5-L and C5-R charged to a negative potential. That is, the potentials of the first node Vmn-L and the second node Vmn-R rise. When all the charges of the memory cells are transferred to the tank capacitors C5-L and C5-R, the potentials of the bit lines BL-L and BL-R are lowered and the potentials of the nodes Vthg-L and Vthg-R are raised. Then, the p-channel type MISFETs T2-L and T2-R are turned off. Therefore, the potential increase at the first node Vmn-L and the second node Vmn-R stops. At this time, the potentials of the nodes Vthg-L and Vthg-R vary depending on the charge amounts of the “0” data and “1” data in the memory cell. Correspondingly, the first node Vmn-L and the second node The increasing range of the potential of Vmn-R is different. That is, a potential difference is generated between the first node Vmn-L and the second node Vmn-R due to the difference in charge amount between the “0” data and the “1” data.

[Effect of large charge countermeasure circuit]
In this embodiment, as described in detail in the first embodiment, the sense amplifier circuit includes p-channel MISFETs P1-L and P1-R (30) that are cross-connected. The following operations are performed.

  That is, the higher one of the first node Vmn-L and the second node Vmn-R first reaches the threshold potential (Vth) of the p-channel MISFETs P1-L and P1-R, and the other side The p-channel type MISFET is turned off. In FIG. 16, since the second node Vmn-R has already reached the threshold potential (here, -0.7 V), the p-channel MISFET P1-L is turned off. As a result, the rise in the potential of the first node Vmn-L stops (see Vmn-R and Vmn-L in FIG. 16).

  As described above, since a rise in the potential of one of the first node Vmn-L and the second node Vmn-R can be suppressed regardless of the potentials of the nodes Vthg-L and Vthg-R, a large potential difference between them can be secured. Can do. Therefore, the read margin can be improved.

[First effect of pull-up circuit]
Next, as shown in FIG. 15F, the control signal Vup is set to the H level after a certain period (for example, after a period t2 from the fall of the signal Vblm). Therefore, the n-channel type MISFETs N1-L and N1-R are turned on. Here, a voltage of about 1/2 Vcc is applied to the gate electrode of the n-channel MISFET N2-L or N2-R from the beginning. This is because the input / output parts of the inverters (INVL, INVR) are connected by the resistor RR. Therefore, the n-channel MISFETs N2-L and N2-R are slightly on from the beginning, and correspond to the rise in the potentials of the bit lines BL-L and BL-R (the potentials of the input portions of the inverters INVL and INVR). The degree of ON (ON current) increases.

  Since the n-channel MISFETs N1-L and N1-R are turned on when the control signal Vup rises, the potentials of the nodes Vthg-L and Vthg-R are lowered. The degree of this potential drop varies depending on the difference in potential between BL-L and BL-R. Therefore, the p-channel type MISFETs T2-L and T2-R are turned on, and the potentials of the first and second nodes Vmn-L and Vmn-R can be raised.

  Thereafter, as described above, the higher one of the first node Vmn-L and the second node Vmn-R first reaches the threshold potential of the p-channel type MISFETs P1-L and P1-R. The p channel MISFET on the other side is turned off.

  Thus, the pull-up circuits 41A-R and 41A-L can raise the potentials of the first node Vmn-L and the second node Vmn-R to the potential at which the circuit 30 operates (the second to second embodiments). 4).

  Further, in the present embodiment, the on-states (on currents) of the n-channel type MISFETs N2-L and N2-R differ according to the potentials of the bit lines BL-L and BL-R. Therefore, the potentials of the nodes Vthg-L and Vthg-R can be lowered while reflecting the potential difference between the bit lines BL-L and BL-R (refer to the vicinity of 27 to 30 ns in FIG. 16). That is, the potentials of the first node Vmn-L and the second node Vmn-R can be raised while reflecting the potential difference between the bit lines BL-L and BL-R. Therefore, the reading margin can be further improved.

  Thereafter, outputs (signals) Vsf-L and Vsf-R of positive potential conversion circuits (L / S) 19-L and 19-R connected to the first node Vmn-L and the second node Vmn-R, respectively. Is read by the latch circuit 20.

[Effect of negative potential generator]
Further, in the present embodiment, since the negative potential generation circuits 50-L and 50-R are incorporated, it is possible to improve reading accuracy (reduce erroneous determination).

  For example, when reading data from a memory cell, the amount of charge read out from “1” data is larger for “0” data and “1” data. However, when a specific deterioration occurs in the ferroelectric characteristics or when there is a difference in the area of the ferroelectric capacitance due to manufacturing variations, the potential on the “0” data side temporarily changes to the “1” data side. It may be higher than the potential. Such a case is called a case where the charge output order is reversed.

  FIG. 17 is a timing chart when the output order of charges is reversed in the comparison circuit (FIG. 5). As shown in the figure, the potential of the bit line BL-L (broken line) is larger than the potential of the bit line BL-R (for example, see the vicinity of 20 ns). Accordingly, Vthg-L <Vthg-R and Vmn-L> Vmn-R. However, finally, the potential of the bit line BL-R becomes larger than the potential of the bit line BL-L, and Vmn-L <Vmn-R.

  FIG. 18 is a timing chart when the charge output order is reversed in the circuit shown in FIG. As shown in the drawing, the potential of the bit line BL-L (broken line) is larger than the potential of the bit line BL-R (for example, see the vicinity of 20n). Along with this, Vthg−L <Vthg−R, and reading (erroneous determination) corresponding to Vmn−L> Vmn−R is performed.

  FIG. 19 is a timing chart when the output order of charges is reversed in the circuit of this embodiment (FIG. 14). As shown in the figure, although the potential of the bit line BL-L (broken line) is initially higher than the potential of the bit line BL-R (for example, refer to the vicinity of 20n), the node Vmn is corrected after correcting these relations. The rise of -L and Vmn-R starts, and finally, determination based on Vmn-L <Vmn-R is made. That is, erroneous determination is improved. Furthermore, the potential difference between the nodes Vmn-L and Vmn-R is larger than in the case of FIG. That is, the read margin is improved.

  The improvement of the erroneous determination is an effect of the negative potential generation circuits 50-L and 50-R. That is, the negative potential generating circuits 50-L and 50-R cause the bit lines B-L and BL-R to hit the negative potential, thereby increasing the potentials of the nodes Vthg-L and Vthg-R. The operation of the first and second p-channel MISFETs can be limited. That is, the timing when the p-channel type MISFETs T2-L and T2-R are turned on can be delayed. In other words, the operation of the first and second p-channel MISFETs in the initial stage of reading can be masked.

  Therefore, even if the output order of charges is temporarily reversed, these relationships are corrected before the p-channel MISFETs T2-L and T2-R are turned on.

  Therefore, after the potential on the “1” data side becomes higher than the potential on the “0” data side, the p-channel type MISFETs T2-L and T2-R are turned on, and the potential increases at the nodes Vmn-L and Vmn-R are started. (See the vicinity of 30 ns in FIG. 19).

  Furthermore, the potentials of the nodes Vthg-L and Vthg-R can be forcibly lowered by raising the signal Vup after the potential on the “1” data side becomes higher than the potential on the “0” data side. Therefore, the potential of the first or second node Vmn-L, Vmn-R can be raised to the potential at which the circuit 30 operates more quickly.

  Further, it is preferable that the capacitors C8-L and C8-R of the negative potential generating circuits 50-L and 50-R have substantially the same capacitance as the ferroelectric capacitors constituting the ferroelectric memory. “Substantially the same capacity” refers to, for example, forming the same material with the same dimensions in design. With this configuration, when the charge for “0” data is canceled and the bit line rises to a positive potential, the reversal of the potential of the “0” data and the potential of the “1” data is corrected. Become.

  In the circuit shown in FIG. 12 as well, for example, by adjusting the tank capacities C5-L and C5-R, the potential difference between the nodes Vthg-L and Vthg-R does not occur at the initial stage of reading. The effect described in Embodiment 3 can be enjoyed while preventing the determination.

[Second effect of pull-up circuit]
Furthermore, in this embodiment, since the bit lines BL-L and BL-R are beaten to a negative potential, it is desirable to use the pull-up circuits 41A-L and 41A-R together.

  In other words, in this embodiment, there are cases where charges read to the nodes Vmn-R and Vmn-L via the bit lines BL-L and BL-R are reduced. For example, when the ferroelectric capacitor of the memory cell and the capacitors C8-L and C8-R constituting the negative potential generating circuit have different degrees of deterioration, the bit line is struck too negatively.

  FIG. 20 is a timing chart when the potential of the bit line is overstruck to a negative potential in the circuit shown in FIG. 14 excluding the pull-up circuit. That is, in FIG. 20, the change to the negative potential of the bit lines BL-L and BL-R is larger than that in FIG. In such a case, as shown in the figure, the potential increase of the node Vmn-R corresponding to the “1” data is small, and the potential difference between the nodes Vmn-L and Vmn-R is also small. Accordingly, the read margin is reduced.

  FIG. 21 is a timing chart in the case where the bit line potential is overstruck to a negative potential in the circuit of this embodiment (FIG. 14). Also in this case, as described above in the section “Effect of the pull-up circuit”, the potentials of the first node Vmn-L and the second node Vmn-R are set by the pull-up circuits 41A-R and 41A-L. Thus, the read margin can be improved.

(Embodiment 6)
FIG. 22 is a circuit diagram showing a configuration of the sense amplifier circuit (read circuit) of the present embodiment. A pull-up circuit 41B is incorporated in place of the pull-up circuits 41A-L and 41A-R in FIG. 14 (fifth embodiment).

  That is, p-channel MISFETs P4-L and P4-R are connected between the bit lines BL-L and BL-R and the p-channel MISFETs P1-L and P1-R, respectively (P4-L, P4-R). ) Is connected to the signal line Vupb via the capacitor C9. In other words, p-channel MISFETs P4-L and P4-R are connected in parallel with the p-channel MISFETs T2-L and T2-R, respectively. Other configurations are the same as those of the fifth embodiment (FIG. 14). Although a paraelectric capacitor is used here as the capacitor C9, a ferroelectric capacitor may be used.

  Next, a read operation of the ferroelectric memory device having the sense amplifier circuit will be described. Operations of various signals and the like are the same as those in the fifth embodiment (FIGS. 15 and 16). Therefore, here, the operation of the circuit 41B after the change of the control signal Vup to the H level (change of the control signal Vupb to the L level) will be described.

  That is, when the control signal Vup is set to the H level after a certain period (for example, after the period t2 from the fall of the signal Vblm), the control signal Vupb is set to the L level, and the p-channel type MISFETs P4-L and P4-R are turned on. Become. Therefore, the potentials of the first node Vmn-L and the second node Vmn-R, which are negative potentials, can be raised. Thereafter, the higher-potential node Vmn-R first reaches the threshold potential (Vth) of the p-channel MISFETs P1-L and P1-R, and turns off the other p-channel MISFET.

  Thus, also in this embodiment, the same effect as in the fifth embodiment is obtained. That is, since the increase in the potential of one of the first node Vmn-L and the second node Vmn-R can be suppressed by the large charge countermeasure circuit 30, it is possible to ensure a large potential difference between them. Therefore, the read margin can be improved.

  Further, the pull-up circuit 41B can raise the potentials of the first node Vmn-L and the second node Vmn-R to the potential at which the circuit 30 operates. Furthermore, the potentials of the first node Vmn-L and the second node Vmn-R can be raised while reflecting the potential difference between the bit lines BL-L and BL-R. Therefore, the reading margin can be further improved. Further, even when the bit line potential is excessively negative, the pull-up circuit can raise the potentials of the first node Vmn-L and the second node Vmn-R to the potential at which the circuit 30 operates.

(Embodiment 7)
Instead of the pull-up circuits 41A-L and 41A-R of the fifth embodiment (FIG. 14), the pull-up circuits (40, 40A, 40B) of the second to fourth embodiments (FIGS. 7, 12, and 13) are used. May be applied.

  23 to 25 are circuit diagrams showing configurations of the sense amplifier circuit (read circuit) of the present embodiment.

<Application example 1>
As shown in FIG. 23, the pull-up circuit (40) of the second embodiment (FIG. 7) may be incorporated in place of the pull-up circuits 41A-L and 41A-R of the fifth embodiment (FIG. 14).

  That is, the p-channel MISFET P3- is connected to the third node Vc-L and the fourth node Vc-R, which are connection nodes between the p-channel MISFETs T2-L and T2-R and the p-channel MISFETs P1-L and P1-R. L and P3-R are connected.

  Specifically, a p-channel MISFET P3-L is connected between the third node Vc-L and the ground potential, and a p-channel MISFET P3-R is connected between the fourth node Vc-R and the ground potential. It is connected. The gate electrodes of the p-channel type MISFETs P3-L and P3-R are connected to the signal line Vupb via the capacitor C7. The back gates of the p-channel type MISFETs P3-L and P3-R are connected to the ground potential. By connecting in this way, leakage current to the substrate can be reduced. Although a paraelectric capacitor is used here as the capacitor C7, a ferroelectric capacitor may be used.

<Application example 2>
As shown in FIG. 24, instead of the pull-up circuits 41A-L and 41A-R of the fifth embodiment (FIG. 14), the pull-up circuits (40A-L and 40A-R) of the third embodiment (FIG. 12) are used. ) May be incorporated.

  That is, the n-channel type MISFET N1-L is connected between the output part of the inverter INVL and the ground potential, and the n-channel type MISFET N1-R is connected between the output part of the inverter INVR and the ground potential. The gate electrodes of these n-channel type MISFETs N1-L and N1-R are connected to the signal line Vup.

<Application example 3>
As shown in FIG. 25, instead of the pull-up circuits 41A-L and 41A-R of the fifth embodiment (FIG. 14), the pull-up circuits (40B-L and 40B-R of the third embodiment (FIG. 13) are replaced. ) May be incorporated.

  That is, a p-channel type MISFET P2-L is connected between the input portion of the inverter INVL and the power supply potential (drive potential, Vcc, Vdd), and the p-channel type MISFET P2-R is connected between the input portion of the inverter INVR and the power supply potential. Is connected. The gate electrodes of these p-channel type MISFETs P2-L and P2-R are connected to the signal line Vupb.

  Also in the circuits of Application Examples 1 to 3 (FIGS. 23 to 24), the pull-up circuit causes the potentials of the first node Vmn-L and the second node Vmn-R, which are negative potentials, to be the potential at which the circuit 30 operates. (See Embodiments 2 to 4).

  Further, even when the bit line potential is excessively negative, the pull-up circuit can raise the potentials of the first node Vmn-L and the second node Vmn-R to the potential at which the circuit 30 operates.

  Although the so-called 2T2C ferroelectric memory device has been described in the fifth to seventh embodiments, the present invention may be applied to a 1T1C ferroelectric memory device.

  Further, the pull-up circuit (41A, 41B) described in the fifth and sixth embodiments may be applied to the circuit of the first embodiment (FIG. 2). Further, the negative potential generation circuit 50 described in the fifth embodiment may be applied to the circuit of the first embodiment (FIG. 2).

  As described above, the examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements. It is not limited to the description.

It is a block diagram which shows the structure of a ferroelectric memory device. FIG. 3 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to the first embodiment. It is a figure which shows the timing chart at the time of reading of a ferroelectric memory device. It is a figure which shows the timing chart at the time of reading of a ferroelectric memory device. FIG. 3 is a configuration diagram of a sense amplifier circuit when cross-connected p-channel MISFETs P1-L and P1-R are not used. FIG. 6 is a diagram showing a simulation result when the ferroelectric capacitor capacity of the memory cell is large in the comparison circuit shown in FIG. 5. FIG. 6 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a second embodiment. It is a figure which shows the timing chart at the time of reading of a ferroelectric memory device. It is a figure which shows the timing chart at the time of reading of a ferroelectric memory device. FIG. 6 is a diagram showing a simulation result when the ferroelectric capacitor capacity of the memory cell is small in the comparison circuit shown in FIG. 5. FIG. 8 is a diagram showing a simulation result when the ferroelectric capacitor capacity of the memory cell is large in the circuit of FIG. 7. FIG. 6 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a third embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a fifth embodiment. 10 is a timing chart at the time of reading in the ferroelectric memory device according to the fifth embodiment. 10 is a timing chart at the time of reading in the ferroelectric memory device according to the fifth embodiment. 6 is a timing chart when the output order of charges is reversed in the comparison circuit shown in FIG. 5. 13 is a timing chart when the output order of charges is reversed in the circuit shown in FIG. 12. 15 is a timing chart when the output order of charges is reversed in the circuit shown in FIG. 15 is a timing chart in the case where the pull-up circuit is removed from the circuit shown in FIG. 15 is a timing chart in the case where the bit line potential is overstruck to a negative potential in the circuit shown in FIG. FIG. 10 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a sixth embodiment. FIG. 20 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a seventh embodiment. FIG. 20 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a seventh embodiment. FIG. 20 is a circuit diagram illustrating a configuration of a sense amplifier circuit (read circuit) according to a seventh embodiment.

Explanation of symbols

  13-L, 13-R ... inverter amplifier circuit, 15-L, 15-R ... threshold potential (Vth) generation circuit, 17-L, 17-R ... negative potential generation circuit, 19-L, 19-R ... positive Potential conversion circuit, 20 ... latch circuit, 30 ... large charge countermeasure circuit, 40 ... small charge countermeasure circuit, 40A-L, 40A-R ... small charge countermeasure circuit, 40B-L, 40B-R ... small charge countermeasure circuit, 41A -L, 41A-R ... Pull-up circuit, 50-L, 50-R ... Negative potential generation circuit, 100 ... Ferroelectric memory device, 110 ... Memory cell array, 120 ... Word line control unit, 130 ... Plate line control unit 140, bit line control unit, BL-L, BL-R, bit line, C1-L, C1-R, C2-L, C2-R, ... capacity, C5-L, C5-R ... tank capacity, C7 ... Capacity, C8-L, C8-R ... Capacity, C9 ... Capacity INVL, INVR: inverter, N1-L, N1-R, N2-L, N2-R ... n-channel type MISFET, P1-L, P1-R ... p-channel type MISFET, P2-L, P2-R ... p-channel MISFET, P3-L, P3-R ... p-channel MISFET, P4-L, P4-R ... p-channel MISFET, PL ... plate line, RL, RR ... resistor, T2-L, T2-R ... p-channel Type MISFET, t1, t2 ... period, Vc-L, Vc-R ... node, Vmn-L, Vmn-R ... node, Vmngen ... control signal, Vsf-L, Vsf-R ... output (signal), VswL, VswR ... Switching transistor, VswmL, VswmR ... Switching transistor, Vsw, Vswm ... Control signal, Vthg-L, Vthg-R ... Node, thgen ... control signal, Vup, Vupb ... signal, Vblm ... signal, WL ... word line

Claims (16)

A first p-channel type MISFET connected between the first node and the third node, the gate electrode of which is connected to the second node;
A second p-channel MISFET connected between the second node and the fourth node, the gate electrode of which is connected to the first node;
A first charge transfer MISFET connected between a first bit line and the third node;
A second charge transfer MISFET connected between a second bit line and the fourth node;
The first bit line is connected between the first bit line and the first gate electrode of the first charge transfer MISFET, and controls the potential applied to the first gate electrode in accordance with the potential of the first bit line. A control circuit;
The second bit line is connected between the second bit line and the second gate electrode of the second charge transfer MISFET, and controls a potential applied to the second gate electrode in accordance with the potential of the second bit line. A control circuit;
A first capacitor connected to the first node;
A second capacitor connected to the second node;
A first negative potential generating circuit connected to the first bit line;
A second negative potential generating circuit connected to the second bit line;
A ferroelectric memory device comprising:   2. The ferroelectric memory device according to claim 1, wherein each of the first and second charge transfer MISFETs is a p-channel type MISFET. The first control circuit is a first inverter connected between a first bit line and a gate electrode of the first charge transfer MISFET, and the input portion and the first bit line are connected via a third capacitor. A first inverter having an output portion connected to a gate electrode of the first charge transfer MISFET through a fourth capacitor;
The second control circuit is a second inverter connected between a second bit line and a gate electrode of the second charge transfer MISFET, and the input portion and the second bit line are connected via a fifth capacitor. 3. The ferroelectric memory device according to claim 1, further comprising: a second inverter connected to the output portion of the second charge transfer MISFET via a sixth capacitor. The first negative potential generating circuit has a seventh capacitor connected between the first bit line and the first signal line,
4. The second negative potential generating circuit has an eighth capacitor connected between the second bit line and the first signal line. The ferroelectric memory device according to item.   5. The ferroelectric memory device according to claim 4, wherein the seventh and eighth capacitors are ferroelectric capacitors. A ferroelectric memory is connected to each of the first bit line or the second bit line,
6. The ferroelectric memory device according to claim 5, wherein the seventh and eighth capacitors are substantially the same as a ferroelectric capacitor constituting the ferroelectric memory. A first n-channel MISFET connected between the output of the first inverter and a ground potential;
A second n-channel MISFET connected between the output of the second inverter and a ground potential;
4. The ferroelectric memory device according to claim 3, further comprising: A third n-channel MISFET connected between the output of the first inverter and the first n-channel MISFET and having a gate electrode connected to the input of the first inverter;
A fourth n-channel MISFET connected between the output of the second inverter and the second n-channel MISFET and having a gate electrode connected to the input of the second inverter;
8. The ferroelectric memory device according to claim 7, further comprising:   9. The first and second n-channel type MISFETs are controlled to be turned on after a certain period after the first and second negative potential generating circuits start operating. The ferroelectric memory device as described. A third charge transfer MISFET connected in parallel with the first charge transfer MISFET and having a gate electrode connected to the second signal line;
A fourth charge transfer MISFET connected in parallel with the second charge transfer MISFET and having a gate electrode connected to the second signal line;
7. The ferroelectric memory device according to claim 1, further comprising: A third p-channel MISFET connected between the third node and a ground potential and having a gate electrode connected to the second signal line;
A fourth p-channel MISFET connected between the fourth node and a ground potential and having a gate electrode connected to the second signal line;
7. The ferroelectric memory device according to claim 1, further comprising: A fifth p-channel MISFET connected between the input portion of the first inverter and the power supply potential and having a gate electrode connected to the second signal line;
A sixth p-channel MISFET connected between the input portion of the second inverter and a power supply potential and having a gate electrode connected to the second signal line;
4. The ferroelectric memory device according to claim 3, further comprising:   13. The potential of the second signal line is controlled to change after a certain period after the operation of the first and second negative potential generating circuits starts. The ferroelectric memory device as described.   14. The ferroelectric memory device according to claim 1, wherein a ferroelectric memory is connected to each of the first bit line and the second bit line.   14. The ferroelectric memory according to claim 1, wherein a ferroelectric memory is connected to the first bit line, and a reference potential is applied to the second bit line. Body storage device.   An electronic apparatus comprising the ferroelectric memory device according to claim 1.

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