JP4228755B2 - Solid-state image sensor and driving method of solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a driving method of the solid-state imaging device, and in particular, converts a signal charge read from each pixel of a pixel unit into an electric signal by a charge detection unit provided at a subsequent stage of a vertical transfer unit, and the charge detection unit The present invention relates to a so-called horizontal scan type solid-state imaging device and a driving method of the solid-state imaging device.
[0002]
[Prior art]
Conventionally, a charge detector is provided for each vertical CCD in order to suppress noise generated in a CCD (Charge Coupled Device) type solid-state imaging device, particularly thermal noise generated in a MOS transistor of an output amplifier, and to improve the SN ratio. A horizontal scanning type solid-state imaging device having a configuration described above has been proposed (for example, see Patent Document 1).
[0003]
Further, in order to be suitable for increasing the number of pixels, and to enable low power consumption and high-speed driving, charge detection means for converting the signal charge output from the vertical CCD into an electric signal is provided for each vertical CCD. A horizontal scan type solid-state imaging device that sequentially scans and reads signals output from a plurality of charge detection means has also been proposed (see, for example, Patent Document 2).
[0004]
[Patent Document 1]
JP-A-6-97414
[Patent Document 2]
JP 2002-135656 A
[0005]
In each of the conventional techniques described in Patent Documents 1 and 2, the signals of the odd-numbered pixel column and the even-numbered pixel column are output in a time division manner. The reason is usually that color coding is repeated for two consecutive pixels in the horizontal direction. For example, if the color of two horizontal pixels is a combination of G (green) and R (red), G, R, G, R, G , R,..., And B (blue) and G are combined into B, G, B, G, B, G,..., And pixel signals of different colors in the odd and even pixel columns are mixed. This is in order not to match.
[0006]
By the way, in recent years, camcorders with a still image function obtain moving image signals compliant with the NTSC system or the PAL system from an image sensor that supports still images of 2 million pixels or more. Specifically, when a solid-state imaging device is used for both moving images and still images, pixel signals are added during moving images or thinning processing is performed to lower the spatial sampling frequency, such as the NTSC method or the PAL method. Broadcast signal.
[0007]
For example, in the NTSC system, the format is horizontal 720 × vertical 480. On the other hand, the digital still camera has a format of horizontal 1600 × vertical 1200 or the like, which has much more pixels than the NTSC system. Therefore, with respect to a digital still camera format signal, a moving image signal compliant with the NTSC method or the PAL method can be obtained by adding or thinning out pixel signals during moving images.
[0008]
[Problems to be solved by the invention]
As described above, when a moving image signal compliant with the NTSC system or the PAL system is obtained from a multi-pixel image sensor having 2 million pixels or more, the horizontal scan type solid-state image sensor according to each of the conventional techniques described above as the image sensor If each pixel signal is read out independently by time division, the drive frequency of the image sensor becomes abnormally high, and the number of continuous shots per second decreases for still image applications. .
[0009]
By the way, when the solid-state imaging device is used for both moving images and still images, horizontal two-pixel addition for adding pixel signals between two pixels in the horizontal direction during moving images is an existing technology in the field of imaging devices having a horizontal CCD structure. Technology. In this horizontal CCD structure image pickup device, when independent reading at the time of still image and mixed (addition) reading at the time of moving image can be used in combination, the odd pixel row and the timing of transferring signal charges from the vertical CCD to the horizontal CCD at the time of mixing. A time lag occurs in even-numbered pixel columns. This timing shift is not a problem in an image sensor having a horizontal CCD structure because the transfer efficiency from the vertical CCD to the horizontal CCD is good.
[0010]
However, in the above-described horizontal scanning solid-state imaging device according to each of the prior arts, if the independent readout at the time of still image and the mixed readout at the time of moving image can be used together, the subsequent stage of the charge detection unit provided for each vertical CCD When a CDS (Correlated Double Sampling) circuit is installed in the CDS circuit, the output timing from the vertical CCD is shifted in time between the odd pixel column and the even pixel column, so that the capacitor in the CDS circuit is charged. Since there is a difference between the odd-numbered pixel column and the even-numbered pixel column in the discharge time, there is no problem when the charge is 100% efficient. However, when the charge is not 100% efficient, the output timing deviation from the vertical CCD is different between the vertical pixel columns. Sensitivity difference (gain difference) or non-linear difference (linearity difference).
[0011]
As color coding of an image sensor for a digital still camera, a horizontal 2 × vertical 2 Bayer array shown in FIG. 8A is generally used. In an imaging device having a Bayer color coding, if downsampling is performed by adding two horizontal pixels, the color centroids are not evenly spaced, as is apparent from FIG. 8B. In other words, the sampling points are equal. Since there is no interval, there is a problem that the resolution in the oblique direction is lowered and a false color signal is generated.
[0012]
The present invention has been made in view of the above problems, and the object of the present invention is to effectively perform spatial downsampling during moving images and reduce the drive frequency when adopting a horizontal scanning method. An object of the present invention is to provide a solid-state imaging device and a method for driving the solid-state imaging device.
[0013]
[Means for Solving the Problems]
The solid-state imaging device according to the present invention includes a pixel unit having pixels that are two-dimensionally arranged and having color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction, and each vertical pixel column of the pixel unit. A charge transfer unit that transfers signal charges read from each pixel in the vertical direction, and one for each vertical pixel column corresponding to the plurality of pixels, and a signal from the charge transfer unit A charge detecting means for converting the voltage of the charge and a scanning means for sequentially reading signals output from the charge detecting means are provided.
[0014]
In the solid-state imaging device having the above configuration, since the color coding of the pixel portion is coding that becomes the same color pixel over a plurality of pixels that are continuous in the horizontal direction, each signal charge of the same color pixel does not need to be read out in a time-division independent manner. The signal charges of the same color can be added by one charge detection means for each vertical pixel column corresponding to a plurality of pixels. Since it is not necessary to perform readout in a time-division independent manner, spatial downsampling during moving images can be effectively performed, and the drive frequency of the image sensor can be reduced. Further, since it is sufficient to provide one charge detection means for each vertical pixel column corresponding to a plurality of pixels, the number of charge detection means can be greatly reduced.
[0015]
The solid-state imaging device driving method according to the present invention drives a solid-state imaging device including a pixel unit in which pixels are arranged in a two-dimensional shape and has a color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction. A transfer step of transferring a signal charge read from each pixel of the pixel unit in a vertical direction for each vertical pixel column; and a signal charge transferred in the transfer step corresponding to the plurality of pixels. It includes a conversion step for converting the voltage by one charge detection means for each vertical pixel column, and a scanning step for sequentially reading the signal voltages converted in the conversion step.
[0016]
In such a solid-state imaging device driving method, by adding a single charge detection means for each vertical pixel column corresponding to a plurality of pixels, under color coding that is the same color pixel over a plurality of pixels continuous in the horizontal direction. The signal charges of the same color can be added without reading out the signal charges of the same color pixels independently in a time division manner. Since it is not necessary to perform readout in a time-division independent manner, spatial downsampling during moving images can be effectively performed, and the drive frequency of the image sensor can be reduced.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, for example, a case where the present invention is applied to a solid-state imaging device adopting an interline transfer method will be described as an example. However, the present invention is not limited to this, and other transfer methods such as a frame transfer transfer method are adopted. The present invention can also be applied to a solid-state image sensor.
[0018]
FIG. 1 is a block diagram showing an outline of a configuration example of a solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device according to the present embodiment is, for example, a CCD type solid-state imaging device, and a signal charge photoelectrically converted by a pixel is transferred in a vertical direction by a vertical CCD (vertical transfer unit), and a charge provided at a subsequent stage of the vertical CCD. A horizontal scanning method is employed in which each signal voltage obtained by voltage conversion in the detection unit is sequentially read out by horizontal scanning.
[0019]
In FIG. 1, a vertical output unit 30, a signal processing unit 40, a horizontal output unit 50, and a post-stage signal processing unit 60 are mounted on a semiconductor substrate 10 together with a pixel unit 20. However, the post-stage signal processing unit 60 can be provided outside the semiconductor substrate 10. The pixel unit 20 includes photoelectric conversion elements (pixels) 21 including photodiodes and the like that are two-dimensionally arranged in a matrix on the semiconductor substrate 10, and vertical CCDs 22 that are arranged for each vertical pixel column with respect to the pixel array. It has composition which has.
[0020]
A color filter and an on-chip lens (both not shown) are provided on the incident surface side of the pixel unit 20. The solid-state imaging device according to the present embodiment is characterized by color coding of the color filter. Specifically, a color filter having color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction is used. As an example, as shown in FIG. 2, R, R, G, G, R, R, G, G,... In one row, G, G, B, B, G, G, B, B in the next row. ,..., And the like, color coding is possible by repeating four horizontal pixels of the same horizontal pixel and repeating two vertical pixels.
[0021]
In the pixel unit 20, the photoelectric conversion element 21 photoelectrically converts the received light over the exposure period, and accumulates signal charges generated by the photoelectric conversion. The vertical CCD 22 transfers signal charges read from each of the photoelectric conversion elements 21 in the vertical direction by being driven by, for example, six-phase clock pulses Vφ1 to Vφ6, and sequentially supplies them to the vertical output unit 30.
[0022]
The vertical output unit 30 includes an output gate unit 31 provided in units of two vertical CCDs 22 corresponding to a color coding of a plurality of adjacent pixels, for example, four horizontal continuous pixels of the same color pixel, and this output gate unit. The signal charge supplied through 31 is detected, and a charge detection unit, for example, an FD (floating diffusion) unit 32, which converts the detected signal charge into a signal voltage is configured.
[0023]
FIG. 3 is a plan pattern diagram showing an outline of a configuration example of the output gate unit 31. Here, the case of horizontal two-pixel addition is shown as an example.
[0024]
As apparent from FIG. 3, the first storage gate (STG) unit 311 and the first hold gate (HLD) are provided only in every other vertical pixel column, that is, odd (ODD) pixel column (or even (EVEN) pixel column). ) Portion 312 is provided. Further, a second storage gate portion 313 and a second hold gate portion 314 are provided after the first hold gate portion 312 in common for each vertical pixel column. The first and second storage gate pulses φSTG1 and φSTG2 are applied to the gate electrodes of the first and second storage gate portions 311 and 313, respectively, and the gate electrodes of the first and second hold gate portions 312 and 314 are applied to the gate electrodes, respectively. First and second hold gate pulses φHLD1 and φHLD2 are applied, respectively.
[0025]
The first storage gate unit 311 and the first hold gate unit 312 perform the transfer operation on the signal charges of the odd pixel columns and add the signal charges of the adjacent two horizontal pixels in the FD unit 32 to When transferring the signal charges in parallel with the signal charges and independently reading out the signal charges of the odd-numbered pixel column and even-numbered pixel column, the timing of shifting the signal charge of the odd-numbered pixel column and the signal charge of the even-numbered pixel column in time It has a function of time-division reading to transfer with. Specifically, out of the signal charges of one line transferred from the vertical CCD 22 at the same timing, the signal charges of the odd pixel columns are accumulated and held in the first storage gate unit 311 and the first hold gate unit 312. In the meantime, the signal charges of the even pixel columns are transferred and output. Thereafter, the accumulation / hold state by the first storage gate portion 311 and the first hold gate portion 312 is released, and the signal charges of the odd pixel columns are transferred and output.
[0026]
When the second storage gate unit 313 and the second hold gate unit 314 independently read out the signal charges of the odd pixel column and the even pixel column, the signal charges of the odd pixel column and the even pixel column of the odd pixel column read out in time division When the signal charges are always transferred to the FD unit 32 at a constant timing, and the signal charges of two adjacent horizontal pixels are added by the FD unit 32, the first storage gate unit 311 and the first hold gate unit 312 The signal charges of the odd-numbered pixel column and the even-numbered pixel column that have been read in a time-division manner by the action are synchronized and have a function as a synchronization means for transferring to the FD unit 32 at the same timing.
[0027]
Here, the operation for synchronization at the time of horizontal two-pixel addition in the output gate unit 31 having the above configuration will be described with reference to the timing chart of FIG. FIG. 4 shows the timing relationship between the first and second storage gate pulses φSTG1 and φSTG2 and the first and second hold gate pulses φHLD1 and φHLD2.
[0028]
First, when the first storage gate pulse φSTG1 becomes a high level (hereinafter referred to as “H” level) (time t11), the potential of the first storage gate unit 311 becomes deep, so that the final transfer of the vertical CCD 22 is performed. Of the signal charges transferred from the stage, only the signal charges of the odd pixel columns are stored in the first storage gate unit 311. At this time, the first hold gate pulse φHLD1 is at a low level (hereinafter referred to as “L” level), and the potential of the first hold gate portion 312 is in a shallow state. The first hold gate 312 holds the first storage gate 311.
[0029]
Further, the signal charges in the even pixel columns are output as they are. At this time, since the second storage gate pulse φSTG2 is at the “L” level and the potential of the second storage gate portion 313 is shallow, the signal charges of the even pixel columns are held immediately before the second storage gate portion 313. The Time division readout is realized by the action of the first storage gate portion 311 and the first hold gate portion 312.
[0030]
Next, when the first hold gate pulse φHLD1 becomes “H” level (time t12), the potential of the first hold gate unit 312 becomes deep, and the hold state for the signal charges in the odd pixel columns is released. The signal charge accumulated in the storage gate portion 311 starts to move to the first hold gate portion 312. Next, when the second storage gate pulse φSTG2 becomes “H” level (time t13), the potential of the second storage gate unit 313 becomes deep, and thus the signal charges of the odd pixel columns accumulated in the first storage gate unit 311 are reduced. It extends to the second storage gate part 313.
[0031]
In addition, the signal charges of the even-numbered pixel columns that have been held immediately before the second storage gate portion 313 are accumulated in the second storage gate portion 313. At this time, since the second hold gate pulse φHLD2 is at the “L” level and the potential of the second hold gate unit 314 is shallow, each signal charge in the odd pixel column and the even pixel column is related to the second hold gate. The second storage gate unit 313 holds the unit 314.
[0032]
Subsequently, the first storage gate pulse φSTG1 becomes “L” level (time t14). All signal charges of the first storage gate portion 311 are pushed out to the first hold gate portion 312 and the second storage gate portion 313. After that, when the second hold gate pulse φHLD2 becomes “H” level (time t15), the potential of the second hold gate unit 314 becomes deep, so that the odd and even pixel columns accumulated in the second storage gate unit 313 are accumulated. Are started to be output to the FD unit 32 all at once.
[0033]
Then, the first hold gate pulse φHLD1 becomes “L” level (time t16), then the second storage gate pulse φSTG2 becomes “L” level (time t17), and finally the second hold gate pulse φHLD2 becomes “ At the L ″ level (time t18), the transfer of the signal charges of the odd pixel column and even pixel column to the FD unit 32 is all completed. That is, the second storage gate unit 313 and the second hold gate unit 314 have the same timing for the signal charges of the odd-numbered pixel column and the even-numbered pixel column that are time-division read by the first storage gate unit 311 and the first hold gate unit 312. Then, the data is transferred to the FD unit 32.
[0034]
In this configuration example, the second storage gate portion 313 and the second hold gate portion 314 are provided at the subsequent stage of the first hold gate portion 312. However, the second storage gate portion 313 is omitted and the second hold gate portion 313 is omitted. The timing at which the signal charges are transferred to the FD unit 32 can also be synchronized by holding the signal charges of the odd-numbered pixel column and the even-numbered pixel column in the unit 314.
[0035]
Next, the FD unit 32 of the vertical output unit 30 will be described. The FD unit 32 is provided in a one-to-one relationship with the output gate unit 31, that is, one for each of the two adjacent vertical CCDs 22, and the signal charges of the odd pixel column and the even pixel column are output to the output gate unit 31. When the signals are transferred with a time difference by 31, they are processed in a time-sharing manner, converted into a signal voltage having a voltage value corresponding to the amount of charge of each signal charge, and output, synchronized by the output gate unit 31 and transferred. In this case, the signal charges of the odd pixel column and the even pixel column are added (mixed), converted into a signal voltage having a voltage value corresponding to the charge amount of the added signal charge, and output.
[0036]
Referring again to FIG. 1, the signal processing unit 40 has a one-to-one relationship with the FD unit 32, that is, one for each of the two adjacent vertical CCDs 22, and is included in the signal voltage output from the FD unit 32. Is configured to have at least a noise removing means for removing a noise component contained in the CDS circuit 41, for example. The CDS circuit 41 has a sample-and-hold capacitor, and reduces noise by utilizing the correlation between the noise included in the feedthrough of the output signal waveform from the FD unit 32 and the noise included in the signal. Is. As the CDS circuit 41, a circuit having a known circuit configuration can be used.
[0037]
Here, as the capacitance of the capacitor is increased, the effect of noise removal can be improved. However, when the CDS circuit 41 is arranged correspondingly, the area of the capacitor becomes a problem. On the other hand, the solid-state imaging device according to the present embodiment employs a configuration in which one CDS circuit 41 is provided for each of, for example, two vertical CCDs 22 adjacent to each other. Arrangement space can be secured in the direction. As a result, the CDS circuit 41 can be arranged over two vertical pixel columns, so that the pattern layout in the vertical direction can be particularly reduced. In addition, since the capacitance of the capacitor can be designed to be large enough for the arrangement space, the noise removal effect of the CDS circuit 41 can be improved.
[0038]
Here, the CDS circuit 41 is arranged in a one-to-one relationship with the FD unit 32. However, the present invention is not limited to this, and one CDS circuit 41 is provided for each of the FD units 32. It is also possible to provide each output signal of the plurality of FD units 32 to the CDS circuit 41 in a time-sharing manner using a switch means or the like. According to this, the number of capacitors can be further reduced, and a wider arrangement space can be secured in the horizontal direction, so that the pattern layout in the vertical direction can be further reduced.
[0039]
The horizontal output unit 50 includes a horizontal scanning circuit 51 and a horizontal output circuit 52. The horizontal scanning circuit 51 is constituted by a shift register or the like, and sequentially outputs horizontal scanning pulses at a predetermined cycle. The horizontal output circuit 52 sequentially selects and outputs the signal voltage for one line supplied through the signal processing unit 40 in synchronization with the horizontal scanning pulses sequentially output from the horizontal scanning circuit 51.
[0040]
The post-stage signal processing unit 60 has an output amplifier 61, a sample hold (S / H) circuit 62, a memory (storage means) 63, and an arithmetic circuit 64. The output amplifier 61 amplifies the signal voltages sequentially output from the horizontal output circuit 52. The sample hold circuit 62 samples and holds the signal voltage output from the output amplifier 61 in synchronization with the sample hold pulse φSH. The memory 63 stores the signal voltage sampled and held by the sample hold circuit 62 as a memory voltage. The memory 63 stores the memory voltage corresponding to each of the FD units 32.
[0041]
Here, the sample hold pulse φSH is given to the sample hold circuit 62 only during a period in which signal charges are not read out from the pixel portion 20 (hereinafter referred to as “charge non-read out period”), and at the time of horizontal scanning by the horizontal scanning circuit 52. It is a synchronized pulse signal. Thus, in the charge non-reading period, the signal voltage sequentially output through the horizontal output circuit 51 and the output amplifier 61 under the scanning by the horizontal scanning circuit 52 from the FD section 32 through the CDS circuit 41 is sampled by the sample hold circuit 62. It is held and stored in the memory 63.
[0042]
Therefore, the memory voltage stored in the memory 63 does not depend on the amount of signal charges photoelectrically converted by each photoelectric conversion element 21 of the pixel unit 20, and varies in the characteristics of each FD unit 32 (particularly in gain variation). ) And includes only an output error due to the characteristic variation of each FD section 32. Incidentally, in the charge non-reading period, since the clock pulses Vφ1 to Vφ6 are not applied to the vertical CCD 22, readout of signal charges from the photoelectric conversion element 21 and charge transfer by the vertical CCD 22 are not executed. It can be controlled not to read out signal charges from the unit 20.
[0043]
The arithmetic circuit 64 passes through the CDS circuit 41 from the FD section 32 and then scans by the horizontal scanning circuit 52 in the period for reading signal charges from the pixel section 20 (hereinafter referred to as “charge reading period”). The signal voltage sequentially output through the output amplifier 61 and the memory voltage stored in the memory 63 are processed. Here, as a matter of course, the signal voltage output from the output amplifier 61 during the charge readout period depends on the charge amount of the signal charge photoelectrically converted by each photoelectric conversion element 21 of the pixel unit 20, and the FD unit 32. This includes output error components due to individual characteristic variations.
[0044]
The arithmetic circuit 64 corrects the level of the signal voltage (particularly the black level) by performing arithmetic processing, for example, subtraction processing, on the signal voltage output from the output amplifier 61 and the memory voltage read from the memory 63 during the charge readout period. I do. By this correction processing, an output error component due to characteristic variation of each FD unit 32 can be removed from signal components based on signal charges read from the pixel unit 20. The signal voltage after this correction processing is output to the outside of the semiconductor substrate 10 as a CCD imaging signal Vout.
[0045]
As described above, the signal voltage output from each of the FD units 32 when the signal charge is not read from the pixel unit 20 is stored in the memory 63, and each of the FD units 32 is read when the signal charge is read from the pixel unit 20. By calculating the signal voltage output from the signal 63 and the corresponding signal voltage stored in advance in the memory 63, streak noise is generated from the signal components based on the signal charge read from the pixel unit 20. It is possible to remove an output error component due to characteristic variation of each FD unit 32 that becomes a factor. As a result, it is possible to prevent the occurrence of streak-like noise without performing adjustment for adjusting the reference level for each FD section 32.
[0046]
In the horizontal scan type solid-state imaging device according to the present embodiment described above, the pixel unit 20 has a multi-pixel configuration of, for example, horizontal 1600 × vertical 1200, and supports still images for a camcorder with a still image function, for example. Used as an imaging device. In the horizontal scan type solid-state imaging device, in the still image mode, the signal charge of each pixel of horizontal 1600 × vertical 1200 is read independently for each pixel (still image independent reading).
[0047]
However, in the horizontal scanning type solid-state imaging device according to the present embodiment, one FD unit 32 and one CDS circuit 41 are provided for two adjacent vertical CCDs 22. Therefore, in the output gate unit 31 shown in FIG. 3, time-division reading is performed by the first storage gate unit 311 and the first hold gate unit 312. The operation of time division reading by the first storage gate unit 311 and the first hold gate unit 312 is as described above.
[0048]
That is, out of the signal charges for one line transferred by the vertical CCD 22, the signal charges of the odd-numbered pixel columns are accumulated in the first storage gate unit 311, and only the signal charges of the even-numbered pixel columns are output. Thereafter, by releasing the hold state by the first hold gate unit 312, the signal charges of the odd pixel columns stored in the first storage gate unit 311 are transferred and output. The signal charges of the odd-numbered pixel column and the even-numbered pixel column thus time-division read in this way are always alternately supplied to the common FD unit 32 at a constant timing by the second storage gate unit 313 and the second hold gate unit 314. Transferred.
[0049]
Then, the signal is alternately converted into a signal voltage by the FD unit 32, and further, noise removal processing is alternately performed by the CDS circuit 41 and output to the horizontal output circuit 52. The horizontal output circuit 52 first outputs the pixel signals of the even pixel columns in order by scanning by the horizontal scanning circuit 51, and then outputs the pixel signals of the odd pixel columns in order. The pixel signals of the even-numbered pixel column and the odd-numbered pixel column that are output separately are subjected to processing of rearranging corresponding to the pixel arrangement of the pixel unit 20 in an external signal processing circuit.
[0050]
On the other hand, in the moving image mode in which a moving image signal compliant with the NTSC method or the PAL method is obtained from this still image-capable image sensor, processing for lowering the spatial sampling frequency is performed by performing signal charge addition and thinning processing in the horizontal direction and the vertical direction. Done. As an example, it is assumed that pixel information of horizontal 1600 × vertical 1200 is down-sampled to 1/2 in the horizontal direction and 1/3 in the vertical direction by performing addition processing.
[0051]
Here, the NTSC format is horizontal 720 × vertical 480, and the PAL format is horizontal 720 × vertical 575. Therefore, even if the information of the horizontal 1600 pixels is down-sampled to ½, there is a horizontal 800 information amount, and the NTSC / PAL horizontal 720 can be covered. Also, even if the information of vertical 1200 pixels is down-sampled to 1/3, there is a vertical 400 information amount, and since it has a higher spatial frequency than the PAL single field 287.5 (= 575/2) line, Sufficient resolution can be obtained.
[0052]
In this way, the horizontal 800 and vertical 400 information amounts obtained by downsampling are converted into horizontal 720 and vertical 287.5 (in the case of PAL) information amounts in an external digital signal processing system. Signal processing is performed digitally.
[0053]
Below, an example of the operation | movement at the time of downsampling of a horizontal direction and a vertical direction is demonstrated. In the horizontal direction, 1/2 down-sampling is performed, and in the vertical direction, 1/3 down-sampling is performed.
[0054]
First, horizontal half-sampling will be described. In this case, in the output gate unit 31 shown in FIG. 3, among the signal charges for one line transferred from the vertical CCD 22, the first storage gate unit 311 and the first hold gate unit 312 for the signal charges of the odd pixel columns. By passing through the transfer operation according to, the second storage gate unit 313 and the second hold gate are reached, although the second storage gate unit 313 arrives at the second storage gate unit 313 later than the signal charge of the even-numbered pixel column by the time required for the transfer operation. By synchronizing with the unit 314, the signal charges of the odd pixel column and the even pixel column are transferred to the FD unit 32 at the same timing.
[0055]
As described above, the signal charges of the two horizontal pixels read out simultaneously are added (mixed) in the FD unit 32 and down-sampled to ½. The added signal charges of the two horizontal pixels are converted into a signal voltage by the FD unit 32, and further, noise removal processing is performed by the CDS circuit 41 and output to the horizontal output circuit 52. The horizontal output circuit 52 sequentially outputs pixel signals for one line down-sampled to ½ by scanning by the horizontal scanning circuit 51.
[0056]
Here, the color filter (not shown) arranged in the pixel unit 20 has color coding of repeating two pixels in the horizontal two-pixel continuous same color pixel and repeating two pixels in the vertical direction (see FIG. 2). Under this color coding, by arranging one FD section 32 for two horizontal pixels and performing horizontal two-pixel addition in the FD section 32, as shown in FIG. Can be equally spaced. As a result, it is possible to eliminate problems such as a decrease in oblique resolution and generation of false color signals.
[0057]
Next, vertical 1/3 downsampling will be described. This vertical 1/3 downsampling is executed in, for example, the vertical CCD 22 driven by 6 phases (Vφ1 to Vφ6). That is, in the vertical two-pixel repetitive color coding, the same color is arranged every other line (one row) for the same vertical pixel column, so that three lines of signal charges are added every other line, so-called interlaced three lines. By the addition, 1/3 down-sampling with the color centroids at equal intervals is performed.
[0058]
The specific operation of vertical 1/3 downsampling will be described below. In the vertical CCD 22, a pair of transfer electrodes is arranged for each pixel of the pixel unit 20, and six phases of clock pulses Vφ1 to Vφ6 are provided in two phases, that is, Vφ1 and Vφ2, Vφ3 and Vφ4, and Vφ5. And Vφ6 are assigned. In general, since the transfer electrodes to which the clock pulses Vφ1, Vφ3, and Vφ5 are applied also serve as readout gate electrodes that read signal charges from the pixels, the clock pulses Vφ1, Vφ3, and Vφ5 are high, medium, and low. The high level pulse becomes the readout pulse.
[0059]
Here, for example, as shown in FIG. 6A, clock pulses Vφ1, Vφ3, and Vφ5 are assigned to four-pixel repetition and vertical two-pixel repetition color coding of two consecutive pixels of the same color in the horizontal direction. The vertical 1/3 downsampling will be specifically described with reference to the timing chart of FIG.
[0060]
In the following description, regarding the clock pulses Vφ1, Vφ3, and Vφ5, the high level is referred to as a read pulse standing, and the middle level and the low level are referred to as “H” level and “L” level, respectively. . For clock pulses Vφ2, Vφ4, and Vφ6, the levels corresponding to the middle level and low level of clock pulses Vφ1, Vφ3, and Vφ5 are referred to as “H” level and “L” level, respectively.
[0061]
First, when the first-phase clock pulse Vφ1 is at “L” level and the fourth-phase to sixth-phase clock pulses Vφ4-Vφ6 are at “H” level, a read pulse is generated at the third-phase clock pulse Vφ3. At the same time, when the second-phase clock pulse Vφ2 becomes “L” level (time t21), the signal charges of the pixels on the line to which the clock pulse Vφ3 is applied (in FIG. 6A, the second, fifth, and eighth lines). The signal charge of each pixel is read out to the vertical CCD 22.
[0062]
Here, in order to simplify the description, in FIG. 6A, the signal charges of the three pixels of the pixel G51 on the fifth line in the first column, the pixel G31 on the third line, and the pixel G11 on the first line are shown. The case of adding 3 lines interlaced will be described as an example.
[0063]
At the same time as the readout pulse of the third-phase clock pulse Vφ3 disappears, the first-phase clock pulse Vφ1 becomes “H” level (time t22), and thereafter the third-phase clock pulse Vφ3 becomes “L” level ( Time t23) Second phase clock pulse Vφ2 is at “H” level (time t24), Fourth phase clock pulse Vφ4 is at “L” level (time t25), Third phase clock pulse Vφ3 is at “H” level (Time t26) The fifth-phase clock pulse Vφ5 is sequentially shifted to the “L” level (time t27), and the fourth-phase clock pulse Vφ4 is sequentially shifted to the “H” level (time t28). The signal charge of the pixel G51 is transferred up to the third line, and is accumulated under the transfer electrode pair to which the first and second phase clock pulses Vφ1 and Vφ2 at the “H” level are applied.
[0064]
Next, at the same time when the readout pulse is generated in the first-phase clock pulse Vφ1, and the sixth-phase clock pulse Vφ6 becomes “L” level (time t29), the signal charge of the pixel G31 in the third line is read out to the vertical CCD 22. It is. As a result, the signal charges of the pixel G51 on the fifth line and the pixel G31 on the third line are skipped and two lines are added.
[0065]
Thereafter, simultaneously with the disappearance of the read-out pulse of the first-phase clock pulse Vφ1, the fifth-phase clock pulse Vφ5 becomes “H” level (time t30), and thereafter the first-phase clock pulse Vφ1 becomes “L”. Level (time t31), sixth phase clock pulse Vφ6 is at “H” level (time t32), second phase clock pulse Vφ2 is at “L” level (time t33), and first phase clock pulse Vφ1 is “H”. The “level” (time t34), the third phase clock pulse Vφ3 transitions to the “L” level (time t35), and the second phase clock pulse Vφ2 sequentially transitions to the “H” level (time t36). The added signal charges of the pixels G51 and G31 on the third line are transferred to the first line, and the fifth and sixth phase clock pulses Vφ5 and Vφ6 at the “H” level are applied. Stored under the transfer electrode pair.
[0066]
Next, when a readout pulse is generated at the fifth phase clock pulse Vφ5 and the fourth phase clock pulse Vφ4 becomes “L” level (time t37), the signal charge of the pixel G11 in the first line is read out to the vertical CCD 22. It is. As a result, the added signal charges of the pixels G51 and G31 of the fifth line and the third line are further added to the signal charges of the pixel G11 of the first line. As a result, as shown in FIG. Each signal charge of the pixel G51 of the eye, the pixel G31 of the third line, and the pixel G11 of the first line is skipped and three lines are added.
[0067]
As described above, under the vertical 2-pixel repetitive color coding, the vertical CCD 22 is driven, for example, in six phases (Vφ1 to Vφ6), and by performing interlaced three-line addition for adding signal charges for three lines every other line. Thus, 1/3 downsampling with the color centroids at equal intervals can be realized.
[0068]
As described above, in the horizontal scan type solid-state imaging device, the color coding of the pixel unit 20 is coding that is the same color pixel over a plurality of pixels continuous in the horizontal direction, and each vertical pixel column corresponding to the plurality of pixels. On the other hand, by arranging the FD sections 32 one by one so that the same color addition can be performed, spatial downsampling at the time of moving images can be effectively performed, and the drive frequency of the image sensor can be reduced. Further, since the number of the FD portions 32 can be reduced to half or more, the pattern layout after the FD portion 32 can be made rough.
[0069]
Further, in the solid-state imaging device configured as described above, which can use both independent readout at the time of still image and mixed readout at the time of moving image, the signal charge of the odd pixel column is transferred to the first storage gate unit 311 at the time of mixed reading in the moving image mode. As a result of the transfer operation by the first hold gate unit 312, the second storage gate unit 313 arrives at the second storage gate unit 313 later than the signal charges of the even pixel columns. Since the signal charges of the odd-numbered pixel column and the even-numbered pixel column can be transferred to the FD unit 32 at the same timing by synchronizing with the two hold gate unit 314, the odd-numbered pixel column and the even-numbered pixel column Time gap can be eliminated.
[0070]
Here, consider a case where the signal charges of the odd pixel columns are transferred to the FD unit 32 later than the signal charges of the even pixel columns by the time required for the transfer operation by the first storage gate unit 311 and the first hold gate unit 312. . The FD unit 32 sequentially converts the signal charge into a signal voltage when the signal charge is transferred and supplies the signal voltage to the CDS circuit 41. Therefore, in the CDS circuit 41, charging of the capacitor is started when the signal voltage is supplied. However, when the charging of the capacitor is not 100% efficient, a signal based on the signal charge of the even-numbered pixel column supplied first. The voltage can be charged 100%, but the signal voltage based on the signal charges of the odd pixel columns supplied with a delay cannot be charged 100%. Accordingly, the charge ratios of the signal voltages to the capacitors in the odd-numbered pixel column and the even-numbered pixel column are different from each other, resulting in a sensitivity difference (gain difference) or non-linear difference (linearity difference) between the vertical pixel columns.
[0071]
On the other hand, in the solid-state imaging device according to the present embodiment, the signal charges of the odd-numbered pixel column and the even-numbered pixel column are synchronized by the second storage gate unit 313 and the second hold gate unit 314 to the FD unit 32 at the same timing. As a result of the transfer, even when the charging of the capacitor in the CDS circuit 41 is not 100% efficient, charging of the capacitors of the signal voltages of the odd pixel column and the even pixel column is started at the same timing, Since the charge ratio to the capacitor is the same, there is no difference in sensitivity or non-linear difference between the vertical pixel columns.
[0072]
In the above embodiment, in the color-type solid-state imaging device having color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction, the charge detection means is provided for each vertical pixel column corresponding to the plurality of pixels. By providing one by one, spatial downsampling during moving images is effectively performed and the drive frequency of the image sensor is reduced. However, even in a monochrome solid-state image sensor, each vertical pixel column corresponding to a plurality of pixels By providing one charge detection means for each, the same effect can be obtained.
[0073]
In the above embodiment, the case of horizontal 2-pixel addition and interlaced 3-line addition has been described as an example, but the same applies to the case where down-sampling is performed by adding 3 horizontal pixels or more and adding 4 lines or more. Is possible.
[0074]
【The invention's effect】
As described above, according to the solid-state imaging device according to the present invention, the color coding of the pixel unit is coding that becomes the same color pixel over a plurality of pixels that are continuous in the horizontal direction. Even if it is not divided and read out independently, the signal charge of the same color can be added by one charge detection means for each vertical pixel column corresponding to a plurality of pixels, so that spatial downsampling at the time of moving images is effectively performed and the image sensor is driven. The frequency can be reduced and the number of charge detection means can be greatly reduced because it is sufficient to provide one charge detection means for each vertical pixel column corresponding to a plurality of pixels.
[0075]
According to the driving method of the solid-state imaging device according to the present invention, one charge detection unit is used for each vertical pixel column corresponding to a plurality of pixels under color coding that is the same color pixel over a plurality of pixels continuous in the horizontal direction. By adding, signal charges of the same color can be added without having to read out each signal charge of the same color pixel independently in a time-sharing manner, thus effectively performing spatial downsampling during moving images and reducing the drive frequency of the image sensor. Can be planned.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an outline of a configuration example of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating color coding of repeating four horizontal pixels and repeating two vertical pixels of the same two-color horizontal pixels.
FIG. 3 is a plan pattern diagram showing an outline of a configuration example of an output gate portion.
FIG. 4 is a timing chart for explaining the operation of the output gate unit;
FIG. 5 is an explanatory diagram of horizontal two-pixel addition in color coding in which four horizontal pixels of the same color are continuously repeated and four vertical pixels are repeated.
FIG. 6 is an explanatory diagram of interlaced three-line addition in color coding of repeating four pixels of two horizontal continuous pixels of the same color and repeating two vertical pixels.
FIG. 7 is a timing chart for explaining the operation of interlaced 3-line addition.
FIG. 8 is an explanatory diagram of a problem of the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 20 ... Pixel part, 21 ... Photoelectric conversion element (pixel), 22 ... Vertical CCD, 30 ... Vertical output part, 31 ... Output gate part, 32 ... FD (floating diffusion) part, 40 ... Signal processing part , 41 ... CDS circuit, 50 ... horizontal output unit, 51 ... horizontal output circuit, 52 ... horizontal scanning circuit, 60 ... post signal processing unit, 61 ... output amplifier, 62 ... sample hold circuit, 63 ... memory, 64 ... arithmetic circuit

Claims (11)

A pixel section having pixels that are arranged in a two-dimensional shape and having color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction;
A charge transfer unit that is provided for each vertical pixel column of the pixel unit and transfers signal charges read from the pixels in the vertical direction;
Charge detection means provided for each vertical pixel column corresponding to the plurality of pixels, and for voltage-converting signal charges from the charge transfer unit;
A solid-state imaging device comprising: scanning means for sequentially reading signals output from the charge detection means. The plurality of pixels are two pixels;
2. The solid-state image pickup device according to claim 1, wherein one charge detection unit is provided for each of two vertical pixel columns corresponding to the two pixels. The solid-state imaging device according to claim 1, further comprising a signal processing unit that performs signal processing on a signal output from the charge detection unit. 4. The solid-state imaging device according to claim 3, wherein the signal processing unit includes a noise removing unit that removes noise included in a signal output from the charge detecting unit. 5. The solid-state imaging device according to claim 4, wherein the noise removing unit is a correlated double sampling circuit including a capacitor that is charged and discharged according to a signal output from the charge detecting unit. 6. The solid-state imaging device according to claim 5, wherein one correlated double sampling circuit is provided for each of a plurality of charge detection means. For each vertical pixel column corresponding to the plurality of pixels, signal charge transfer from the charge transfer unit to the charge detection unit is performed at the same timing for each vertical pixel column corresponding to the plurality of pixels. The solid-state imaging device according to claim 1. Storage means for storing a signal output from each of the charge detection means when the signal charge is not read from the pixel portion;
An arithmetic means for arithmetically processing a signal output from each of the charge detection means and a corresponding signal stored in the storage means when reading out the signal charge from the pixel portion. Item 10. A solid-state imaging device according to Item 1. A method for driving a solid-state imaging device including a pixel unit having pixels that are arranged in a two-dimensional shape and have a color coding that is the same color pixel over a plurality of pixels that are continuous in the horizontal direction,
A transfer step of transferring the signal charge read from each pixel of the pixel unit in the vertical direction for each vertical pixel column;
A conversion step of converting the signal charge transferred in the transfer step by one charge detection means for each vertical pixel column corresponding to the plurality of pixels;
And a scanning step of sequentially reading out the signal voltages converted in the conversion step. 10. The method of driving a solid-state imaging device according to claim 9, wherein, in the transfer step, the signal charges are transferred to the one charge detection unit at the same timing for each vertical pixel column corresponding to the plurality of pixels. A storage step of storing a signal output from each of the charge detection means when the signal charge is not read from the pixel unit;
The solid state according to claim 9, further comprising a calculation step of calculating a signal output from the one charge detection unit and a signal stored in the storage step when reading the signal charge from the pixel unit. Driving method of image sensor.

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