JP4223002B2 - Silicon-germanium heterojunction bipolar transistor - Google Patents

Description

  The present invention relates to a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT).

  It is well known to form HBTs using a wafer with at least one silicon germanium (SiGe) layer on a silicon substrate. On such a substrate, mechanical strain is generated in the composite film by germanium atoms due to the difference in lattice constant between the SiGe film and the silicon substrate. In the plane of the silicon substrate, a SiGe lattice having a large lattice constant is pressed onto the silicon substrate having a small lattice constant. In the plane perpendicular to the silicon substrate, the lattice constant of the SiGe layer is larger than the lattice constant of the silicon substrate, so that it is under tensile stress. Due to this strain and the Ge atoms themselves, a band gap deviation is formed between the SiGe film and the natural Si substrate existing therebelow. This bandgap bias creates a unique field of SiGe HBTs that improve transistor speed because a gradient field is formed in the base, increasing the diffusion of carriers across the base. SiGe HBTs are used as transistors for small signal amplifiers (i.e., switching at about 5 volts or less) and achieve the switching speed (greater than 1 GHz) required for current wireless communication devices.

One of the difficulties we have encountered when using SiGe HBTs for small signal amplifiers is that the common emitter output characteristics for such amplifiers (ie, collector current versus collector-emitter voltage) are generally poor early voltages. (Early voltage). “Early voltage” (V _A ) is a characteristic of the slope of these output characteristics, and is represented by a voltage obtained by extrapolating the curve to IC = 0A. As the curve becomes horizontal, the voltage at IC = 0 extrapolation increases, so the Early voltage becomes “higher”. FIG. 1 is a diagram showing the early voltage of a SiGe HBT not using the present invention. Individual curves show output characteristics when various base voltages are applied. The higher the curve is, the higher the applied base voltage. Note that the slope of the curve becomes more vertical as the applied base current increases.

According to the inventors' discovery, V _A is a key indicator of the current gain cutoff frequency (f _T ) of SiGe HBTs. V _A is lower NPN device was found to be of a low f _T. Devices with low current gain cut-off frequencies can only achieve suboptimal switching speeds.

  Therefore, there is a need in the art for a SiGe HBT with an increased early voltage and thus an increased current gain cutoff frequency.

  Therefore, an object of the present invention is to increase the current gain cutoff frequency of SiGe HBT.

  In a first aspect, the present invention is a SiGe HBT with a SiGe layer having a plurality of misfit dislocations therein that has a thickness and Ge concentration that exceeds the SiGe stability limit and does not form many charge trapping sites.

  In another aspect, the invention comprises a SiGe layer having a thickness of at least about 70 nm and a Ge concentration of at least 10% on a plurality of isolation structures, comprising a base / collector junction above the isolation structure, A SiGe HBT with a plurality of misfit dislocations that does not extend much beyond the base / collector junction.

  In yet another aspect, the present invention comprises a SiGe layer having a cutoff frequency of at least about 19 GHz and a plurality of isolation regions adjacent to the collector region and a base region formed on the collector region. The misalignment dislocations in the bipolar transistor for small signal amplifiers formed adjacent to the plurality of isolation regions and extending into the collector region without substantially extending into the base region It is.

  In yet another aspect, the present invention includes a step of forming a plurality of isolation regions on a silicon substrate and a step of forming a SiGe layer on the substrate and the isolation region, wherein the thickness of the SiGe layer is SiGe stable. Thicker than the limit, the Ge content of the SiGe layer is greater than the SiGe stability limit, and doping the SiGe layer and the substrate with a first dopant to form a collector region, the collector comprising A method of forming a bipolar transistor, wherein the region includes a plurality of misfit dislocations that do not extend substantially beyond the collector region to other parts of the bipolar transistor.

  According to the discovery of the present inventors, the Early voltage (and hence the cut-off frequency) can be significantly increased by increasing the thickness of the SiGe layer. Although it is known in the prior art to increase the thickness of SiGe for other purposes, thicker SiGe layers are generally avoided because of the fear of forming misfit dislocations. As detailed below, according to the inventors' discovery, misalignment dislocations do not adversely affect the performance or yield of the resulting SiGe HBT, if properly managed.

  The use of SiGe increases the charge mobility. This is because mechanical strain is introduced due to lattice mismatch unique to the Si—Ge compound. However, it is the established theory in the art that if Ge is present in excess, or if the SiGe layer is too thick, the resulting crystal dislocations reduce both performance and yield. The reduction in performance may be due to dislocations that relieve the mechanical stress responsible for the band gap deviation caused by SiGe. Yield reduction may be due to defects that disturb the crystallinity of the substrate. In fact, this general understanding has become so widespread that it is commonly referred to as the "Mathews-Blakesley stability limit" or "Stiffler limit", due to the researcher who originally reported these interactions. (Stiffler et al., Journal of Applied Physics, Vol. 71, No. 10, pp. 4820-4825; Matthews and Braxley, “Defects in Epitaxial Multilayers”, Journal of Crystal Growth. 27, 118-125 (1974) (Stiffler et al., Journal of Applied Physics, Vol. 71, No. 10, pp. 4820-4825; Mathews and Blakeslee, "Defects in Epitaxial Multilayers," Journal of Crystal Growth 27 pp. 118-125 (1974))). For ease of future reference, these results will be referred to as “SiGe stability limits”. The various SiGe stability limits reported by Matthews-Braxley and Stiffler are plotted in FIG. FIG. 4 shows the reported optimal relationship between SiGe thickness and Ge concentration. Much research has focused on various methodologies beyond the SiGe stability limit by eliminating such misfit dislocations. See U.S. Pat. No. 5,256,550 to Laderman et al. In this US patent, a low temperature epitaxial technique is used to deposit the first SiGe layer, then form a Si cap layer, and then subject to appropriate thermal cycling to form a thick SiGe layer without misfit dislocations. Has been. In this structure, it is necessary to cover with a Si layer in order to continue the strain of the SiGe layer without forming misfit dislocations. A paper by K. Schonenberg et al. Entitled “Stability of SiGe strained layers in trench-isolated silicon islands of small area” (Electro Chemical Society Proceedings, Vol. 96-4, Process Physics in Semiconductor Technology) And the 4th International Symposium on Modeling, Los Angeles, California, May 5-10, 1996, pp. 296-308 (A paper by K. Schonenberg et al. Entitled "The Stability of SiGe Strained Layers on Small Area Trench Isolated Silicon Islands "Electrochemical Society Proceedings, Vol. 96-4, Proceedings of the 4th International Symposium on Process Physics and Modeling in Semiconductor Technology, Los Angeles, CA May 5-10 1996, pp. 296-308)) According to reports, the size of the SiGe region defined by the isolation is reduced and the shallow trench isolation is corrected. Reducing stress, defect density is small to be observed. This area dependence is attributed to Vescan, "Selective epitaxial growth of strained SiGe / Si for optoelectronic devices" (Material Science and Engineering B, Solid State Mana Reals for Advanced Technology, Vol. 51, Vol. 51). 1-3, pp. 166-69 (1998)) (Vescan, "Selective Epitaxial Growth of Strained SiGe / Si for Optoelectronic Devices," Materials Science and Engineering B, Solid-State Materials for Advanced Technology, Vol. 51, No 1-3, pp. 166-69 (1998)).

  Another reason to avoid misfit dislocations in the active region of the bipolar transistor is to prevent charge trapping sites from forming. The presence of a large number of these charge trapping sites shortens the minority carrier lifetime. In a typical bipolar transistor, this results in a reduced current gain. This is undesirable for small signal applications. However, in power amplification applications, a reduction in current gain is acceptable. Thus, US Pat. No. 5,097,308 discloses a dislocation that forms a trap that increases minority carrier recombination in a bipolar power rectifier at 9-20 μm from the SiGe-Si interface to shorten the minority carrier lifetime. Intentional introduction is taught. Shortening the lifetime of minority carriers is desirable in bipolar rectifier elements in order to increase the switching speed. The switching speed of the bipolar transistor is determined by the speed with which the charge in the base is removed. One process for removing charge is recombination. This causes electrons and holes to recombine at the charge trapping site and turn off the transistor. However, for small-signal amplification applications of standard SiGe bipolar transistors, the reduction in current gain associated with a shortened minority carrier lifetime is undesirable (in fact, would normally be avoided, and as noted above, As a result, slowing the switching speed would not be compatible with the goal of increasing the current gain cutoff frequency).

  According to the discovery of the present inventors, when the SiGe layer is formed with the thickness / concentration combination larger than the SiGe stability curve, the early voltage is remarkably improved, so that the cutoff frequency is increased. In addition, misfit dislocations that significantly release the mechanical stress that forms the band gap deviation due to SiGe are not formed. And the crystallinity of the substrate is not disturbed so much. FIG. 4 shows the SiGe thickness and concentration used to provide the data reported here. For comparison, the Ge concentration was fixed at 10% and the thickness was increased. Note that the first two data points are below the SiGe stability curve. These devices provided the early voltage results shown in FIG. The thickness of the SiGe of the present invention starts from about 70 nm.

  As shown in FIG. 5, the SiGe HBT according to the present invention is formed on a single crystal silicon substrate 10 having a shallow trench isolation region (STI) 12 therein. The SiGe layer 14 is epitaxially grown on the substrate 10 using an existing method. The thickness t is at least 40 nm and the Ge concentration is at least about 10%. After appropriate doping to form the collector region 14C, the SiGe layer is doped in situ during growth to form the base region 14B (not magnified in the horizontal direction at a constant ratio). It should be noted that as a practical matter, boron exiting the base during the thermal cycles of the various processes diffuses in the SiGe layer, ie, from depth X to depth Y in the SiGe layer 14. there's a possibility that. Thus, the resulting base / collector junction location can be JA or JB. Next, an emitter electrode (not shown) is formed using a known method to complete the formation of the HBT. Next, the HBT according to the present invention is connected to another HBT on the substrate to form an integrated circuit. FIG. 2 is a diagram showing collector current versus collector-emitter voltage of a SiGe HBT according to the present invention. Note that the early voltage is significantly improved (the plot is much more horizontal for all applied base voltages, ie the collector current is constant with increasing collector-emitter voltage). .

FIG. 3 shows collector currents of (a) NPN having the early voltage shown in FIG. 1 (indicated by a solid line) and (b) NPN having the early voltage shown in FIG. 2 (indicated by a dashed line). It is the figure which plotted density versus cutoff frequency. Note that the cutoff frequency of the transistor with improved Early voltage according to the present invention is higher. The peak of Ft is about 19 GHz. It should also be noted that the higher cut-off frequency occurs over a wider range of collector current.

  One aspect of the present invention is that the early voltage and the cut-off frequency are thus increased without the cost of dislocations (due to charge trapping) or performance degradation (due to crystal dislocations).

First, consider trapping charges. First, it should be noted that an increase in the cutoff frequency shown in FIG. 5 is observed. Even if a significant amount of charge trapping is introduced by misfit dislocations, the resulting carrier recombination reduces the cutoff frequency and does not increase it. FIGS. 6 and 7 show NPN Gummel plots (IC, IB vs. VCE) having the Early voltages shown in FIGS. 1 and 2, respectively. Note that the IB and IC curves in this Gummel plot have an ideal slope (n┤1 [n is a measure of ideality] or 60 mV / decade [room temperature]). This indicates that a significant amount of charge trapping was not introduced by misfit dislocations formed as part of the thicker SiGe layer. One consequence of avoiding increased charge trapping is that these higher cutoff frequencies are achieved without a corresponding decrease in device breakdown voltage (BV _CEO ), as shown in FIGS. It is to be done. In other words, the cutoff frequency Ft of a device having a predetermined breakdown voltage BV _CEO increases as the SiGe thickness is increased. This is particularly important for device designs that require devices with high breakdown voltages (eg, power amplifiers and read heads).

  Next, consider the yield. FIG. 8 is a plot of the normalized yield of SiGe HBTs according to the present invention versus various thicknesses of SiGe. The illustrated first region (thickness 30 nm [300 angstroms], Ge concentration 10%) is located almost at the upper limit of the SiGe stability curve (see FIG. 3). It should be noted that the yield does not change much even if the thickness exceeds the SiGe stability curve with a Ge concentration of 10%. This indicates that the crystallinity of the substrate is not significantly disturbed by misfit dislocations in the SiGe layer according to the present invention. This is because, if the crystallinity of the substrate is disturbed by the misfit dislocation, the yield will decrease as the thickness of the SiGe layer increases.

  FIG. 9 is a plot of Ge concentration percentage versus 70 nm thick SiGe layer depth for three embodiments of the present invention. In the first embodiment shown by curve A, the Ge concentration in the SiGe layer according to the present invention is about 10% over the thickness direction of the 40 nm thick SiGe film. This embodiment resulted in a plot of collector current versus collector-emitter voltage of the present invention, shown by the solid line in FIG. In the second embodiment shown by curve B, the Ge concentration in the SiGe layer according to the present invention is about 10% over the thickness direction of the 70 nm thick film. The yield data shown in FIG. 8 was obtained from the first embodiment and the second embodiment. In the third embodiment shown by curve C, the Ge concentration in the SiGe layer according to the invention is at the upper surface of the SiGe layer and the first third of its thickness (about 23 nm for a 70 nm thick SiGe film). After that, the Ge percentage drops substantially linearly from 25% to 10% over the second third of the SiGe film thickness, after which the concentration is the film thickness The balance is 10%. When the content at the lower surface is reduced to 10%, the results expressed in misfit dislocations, yield, and performance should be the same as those observed in the first two embodiments of the present invention.

  In a fourth embodiment of the invention (not shown in FIG. 9), the SiGe layer is 150 nm thick and its Ge concentration is about 10% over this thickness. According to the inventors' discovery, misfit dislocations exhibited the general properties reported here even at this thickness and Ge content. According to our belief based on these results, the SiGe layer can be thicker than 150 nm and still exhibit the properties reported here.

  The results reported here show that there is no underlying reason for the need to limit the concentration and thickness of SiGe due to concerns about dislocation formation.

  Thus, it will be apparent that the only natural limitation on the percentage of Ge concentration is the introduction of excess or understress in the underlying Si layer. According to the inventors' belief, concentrations less than about 5% do not have enough stress to be introduced and the charge mobility is not improved by a reasonable amount, and at concentrations above about 35% the Early voltage is reduced. Yield is reduced due to the introduction of unacceptable stress in thickness situations (approx. 70 nm or more) that appear to optimize, or the formation of hillocks on the top surface of the SiGe layer.

  According to the inventors' discovery, misfit dislocations in the SiGe layer according to the present invention are mostly present at the ends 12A and 12B of the STI region shown in FIG. This dislocation showed a tendency to run in the horizontal direction along the SiGe / Si interface indicated by the broken line 10A. Notably, in fact, no extension was observed in the base / collector junction JA or JB, and no extension in the emitter region was observed. Also, as described above, the ideal Gümmel plot shows that the resulting dislocations do not form much charge trapping sites.

  Therefore, according to the discovery of the present inventors, contrary to the teaching in the art, the SiGe layer having misfit dislocations can improve the performance without deteriorating the yield. Also, according to the discovery of the present inventors, the existence of a large number of misfit dislocations is not a limiting factor in performance or yield, contrary to the teaching in the art. On the contrary, the important point is that dislocations do not generate much charge trapping, and the number of dislocations extending across the base / collector junction is not very high.

  Although the invention has been described with reference to a specific set of embodiments, the invention should not be construed as limited thereto. The embodiments described above can be modified within the spirit and scope of the present invention described in the claims. For example, specific Ge concentrations, concentration gradients, and SiGe thicknesses are shown, but other concentrations, gradients, and / or thicknesses are used as long as the same general results reported here are obtained be able to. ("A and / or B" represents A and B, A, or B.)

  The present invention can be applied to an electric circuit and an electric device, particularly an electric circuit and an electric device used in a communication system.

FIG. 3 is a plot of experimental SiGe HBT IC vs. VCE. FIG. 3 is a plot of SiGe HBT IC vs. VCE according to the present invention. FIG. 3 is a plot of collector current density versus cutoff frequency for two NPNs having the Early voltage shown in FIGS. 1 and 2, respectively. FIG. 6 is a plot of SiGe concentration versus thickness showing various data points including those of the present invention overlaid on the SiGe stability curves reported in prior art papers. 2 is a cross-sectional view of a SiGe HBT constructed in accordance with the teaching of the first embodiment of the present invention. FIG. FIG. 3 shows two NPN Gümmel plots (IC, IB vs. VCE) with the Early voltages shown in FIGS. 1 and 2, respectively. FIG. 3 shows two NPN Gümmel plots (IC, IB vs. VCE) with the Early voltages shown in FIGS. 1 and 2, respectively. FIG. 5 is a plot of normalized yield data for SiGe HBTs with thicknesses indicated by the data points in FIG. 4. FIG. 6 shows three embodiments of Ge concentration versus layer thickness of a SiGe layer according to the present invention.

Explanation of symbols

10 single crystal silicon substrate 12 STI region 14 SiGe layer

Claims (13)

A silicon substrate;
A plurality of isolation regions formed in the silicon substrate at the surface of the silicon substrate;
Wherein formed on the silicon substrate and the surface of said plurality of isolation regions, SiGe stable than the limit has a thickness rod and Ge concentration, base region formed in the collector region is formed on the surface side and the collector region the provided, a plurality of misfit dislocations is formed adjacent to the plurality of isolation regions, said in the base region extends into said collector region without extending substantially heterojunction type which includes a SiGe layer bipolar transistor data. The transistor of claim 1, wherein the cutoff frequency is at least 19 GHz . The transistor of claim 1 , wherein the Ge concentration of the SiGe layer is at least 10%. Is 7 0 nm to as thickness Saga least the SiGe layer, the transistor according to claim 3. Is 1 50 nm to as thickness Saga least the SiGe layer, the transistor according to claim 3. 4. The transistor of claim 3 , wherein the Ge concentration of the SiGe layer varies within the SiGe layer . The transistor according to claim 6 , wherein the value of Ge concentration of the SiGe layer is higher on its upper surface and lower on its lower surface. The Ge concentration,
Takes a first value on top of the SiGe layer ,
Taking a second value smaller than the first value at the bottom of the SiGe layer ,
Takes a value that varies from the first value to the second value in the middle of the SiGe layer ;
The transistor according to claim 7 . Value greater than the is 2 5%, smaller than the is 1 0%, the transistor according to claim 8. The Ge concentration is 25% Te 1 Odor upper third of the thickness of the SiGe layer, the transistor according to claim 8. 11. The transistor of claim 10 , wherein the Ge concentration decreases linearly from 25% to 10% in the middle third of the thickness of the SiGe layer . The Ge concentration of 1 0% Te 1 Odor bottom third of the thickness of the SiGe layer, the transistor according to claim 1 1. Forming a plurality of isolation area to divorce the surface of the substrate,
And forming a SiGe layer on the separation area and contact the base plate, the thickness of the SiGe layer is thicker than the SiGe stability limit, Ge content of the SiGe layer is greater than SiGe stability limit The forming step;
And forming a base region in the SiGe layer contact and the collector region in the SiGe layer is doped with the base plate in de Panto and the collector region, a plurality of misfit dislocations within the plurality of isolation regions Forming in the collector region adjacent to and not substantially extending into the base region; and
The including a method of manufacturing a heterojunction bipolar transistor.

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