JP4212140B2 - Gate array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a gate array which is a semiconductor integrated circuit.
[0002]
[Prior art]
  In recent years, LSIs (Large Scale Integrated Circuits) have been increased in speed and integration due to advances in microfabrication technology and the like. Accordingly, in order to put LSIs that operate at high speed into practical use, low power consumption of LSIs has become one of the important technologies.
[0003]
  That is, when the LSI is operated at high speed, power consumption increases. Therefore, in order to stably operate the LSI, it is necessary to adopt a ceramic package, install heat radiating fins, and the like, resulting in an increase in cost. In addition, low power consumption is an important technology from the viewpoint of battery usage time in small and light portable devices that have been recently developed.
[0004]
  Conventionally, as one of the above-mentioned LSIs, a gate array in which basic cells each composed of two NMOS (N-type metal oxide semiconductor) transistors and two PMOS (P-type metal oxide semiconductor) transistors are regularly arranged. Is commonly used. FIG. 11 shows an example of the gate array.
[0005]
  In FIG. 11, 1 is a gate array, 2 is an input / output interface unit, and 3 is a gate array unit in which the basic cells composed of MOS transistors are spread. FIG. 12 is a layout pattern diagram of the basic cell, and FIG. 13 is an equivalent circuit diagram of the basic cell.
[0006]
  12 and 13, NG 1 is the gate of the first NMOS transistor 4, and NG 2 is the gate of the second NMOS transistor 5. ND1, ND2, and ND3 are the sources or drains of the first and second NMOS transistors 4 and 5, respectively. Here, the source or drain ND 2 is a common node of the first NMOS transistor 4 and the second NMOS transistor 5.
[0007]
  Similarly, PG 1 is the gate of the first PMOS transistor 6, and PG 2 is the gate of the second PMOS transistor 7. PD1, PD2 and PD3 are the sources or drains of the first and second PMOS transistors 6 and 7, respectively. Here, the source or drain PD2 is a common node of the first PMOS transistor 6 and the second PMOS transistor 7.
[0008]
  The well PW connected to the back gate, which is a semiconductor region in which a channel is formed when the first and second NMOS transistors 4 and 5 are turned on, is connected to GND and connected to the back gates of the first and second PMOS transistors 6 and 7. The well NW is connected to the power supply VDD.
[0009]
[Problems to be solved by the invention]
  By the way, in order to reduce the operating power of the gate array, a great effect can be obtained by reducing the operating voltage (VDD). However, when the operating voltage is lowered, the driving currents of the MOS transistors 4 to 7 are reduced, the delay time of the circuit realized on the gate array is increased, and the operating speed is lowered. Therefore, it is conceivable to reduce the threshold voltage Vth of the MOS transistors 4 to 7 so that the drive current of the MOS transistors 4 to 7 does not become so small even at a low voltage. However, when the threshold voltage Vth is lowered, the leakage current of the MOS transistors 4 to 7 increases, and the power consumption increases due to the leakage current even when the circuit is in the standby mode. Therefore, there is a problem that the power consumption does not become so low even though the operating voltage is lowered.
[0010]
  In the basic cell shown in FIGS. 12 and 13, the source or drain ND2 is a common node of the first and second NMOS transistors 4 and 5. The source or drain PD2 is a common node for the first and second PMOS transistors 6 and 7. Therefore, when an inverter circuit is configured using the basic cell, as shown in FIG. 14, the second NMOS transistor 5 and the second PMOS transistor 7 are not used at all, and the circuit cannot be efficiently formed on the gate array. There is also a problem.
[0011]
  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a gate array that can solve the above-described problems, can operate at high speed with low power consumption, and can efficiently form a circuit without waste.
[0012]
[Means for Solving the Problems]
  In order to achieve the above object, the invention according to claim 1
  A gate array in which basic cells including MOS transistors having gates, sources and drains that are electrically independent from each other are arranged,
  The gate, source and drain are electrically independent for each transistor.And
  The semiconductor region in which the channel is formed when the MOS transistor is turned on is electrically independent for each MOS transistor,
  In the gate array comprising voltage setting means for setting the voltage of the semiconductor region independently of the voltage of the source,
  A semiconductor region in which a channel is formed at the time of on is electrically connected to the gate of the corresponding MOS transistor.Have
It is characterized by that.
[0013]
  According to the above configuration, a MOS transistor having a gate, a source, and a drain which are electrically independent from each other and for each transistor can be a component of a circuit formed on the gate array alone. Therefore, the MOS transistor is used without waste when a circuit is formed on the gate array..
[0014]
  furtherThe voltage of the semiconductor region in which the channel is formed when turned on is set independently of the source voltage for each MOS transistor. In this manner, the voltage of the semiconductor region can be set to a voltage other than the power supply voltage (VDD) and the ground voltage (GND) that are often used as the control voltage of the conventional gate array. Therefore, the threshold voltage of each MOS transistor belonging to the circuit formed on the gate array can be lowered during the operation of the circuit and raised during standby. That is, a reduction in the operating speed of the MOS transistor when the operating voltage of the circuit is lowered to reduce power consumption is prevented. Further, the leakage current of each MOS transistor during standby is suppressed.
[0015]
  Further, the same voltage as that of the gate is applied to a semiconductor region where a channel is formed when each MOS transistor is turned on. Thus, each MOS transistor is controlled so that the threshold voltage decreases when the MOS transistor is on, while the threshold voltage increases when it is off. As a result, even if the circuit formed on the gate array is in operation, if there is an off-state MOS transistor in the current path from the power source VDD to GND, the off-state MOS transistor causes a through current to flow. It is suppressed.
[0016]
  Also,Claim 2The invention according to
  Claim 1In the gate array of the invention according to
  The voltage setting means can control the voltage of the semiconductor region individually for each MOS transistor.
It is characterized by that.
[0017]
  According to the above configuration, the threshold voltage is controlled for each individual MOS transistor configuring the basic cell. Thus, the threshold voltage of each MOS transistor is individually set to a desired value according to the operating voltage or the like..
[0018]
  MaTheClaim 3The invention according to
  Having gate and sourceA gate array in which basic cells including MOS transistors are arranged,
  A semiconductor region in which a channel is formed when the MOS transistor is turned on is electrically independent for each of the plurality of MOS transistors,
  Each of the semiconductor regions that are electrically independent for each of the plurality of MOS transistors is electrically connected to the gate of each of the MOS transistors belonging to each semiconductor region,
  The voltage of the semiconductor region isEach of the above MOS transistorsVoltage setting means for setting independently of the source voltage is provided.
It is characterized by that.
[0019]
  According to the above configuration, the voltage of the semiconductor region is set independently of the voltage of the source for each of the plurality of MOS transistors sharing the semiconductor region in which a channel is formed when turned on. Thus, the threshold voltage of each MOS transistor is set to a desired value for each of the plurality of MOS transistors. In this case, it is not necessary to form a separation band for separating the MOS transistors between the plurality of MOS transistors, and the area of the gate array is reduced accordingly.
[0020]
  Further, the same voltage as that of the gate of each MOS transistor belonging to each semiconductor region is applied to each of the semiconductor regions which are electrically independent for each of the plurality of MOS transistors. Thus, each MOS transistor is controlled so that the threshold voltage decreases when the MOS transistor is on, while the threshold voltage increases when it is off. As a result, even if the circuit formed on the gate array is in operation, if there is an off-state MOS transistor in the current path from the power source VDD to GND, the off-state MOS transistor causes a through current to flow. It is suppressed.
[0021]
  Also,Claim 4Inventions related toThe gate arrayIs
  Gates that are electrically independent of each other , Comprising a plurality of MOS transistors having a source and a drain;
  In the MOS transistorSemiconductor region where channel is formed when onIs electrically connected to the gate of the corresponding MOS transistor,
  The plurality of MOS transistors are
  Each of the semiconductor regions in which a channel is formed at the time of the on-stateEach MOS transistor is electrically independentA first MOS transistor,
  A second MOS transistor in which a semiconductor region in which a channel is formed at the time of ON is electrically independent for each of the plurality of MOS transistors;
Including
  In the first MOS transistorThe voltage of the semiconductor region, Of the first MOS transistorSet independently of the source voltageFirstVoltage setting meansWhen,
  Second voltage setting means for setting the voltage of the semiconductor region in the second MOS transistor independently of the voltage of the source of the second MOS transistor;
It is characterized by having.
[0022]
  According to the above configuration,The MOS transistor includes the first MOS transistor capable of controlling a threshold voltage for each one and the second MOS transistor having a small area per element by performing element isolation for each plurality. InThe semiconductor region in which the channel is formed when onThe first MOS transistor is electrically connected to the gate of the corresponding MOS transistor.MOS transistor1st area whereWhen,SecondMOS transistorA second region, and a third region including the first voltage setting unit and the second voltage setting unit,By configuring a gate array that mixes, the controllability and area efficiency are good, andTo suppress the through current during operation.Possible gate arrayCan be realizedThe
[0023]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is an equivalent circuit diagram showing a basic cell constituting the gate array of the first embodiment. FIG. 2 shows a layout pattern of the basic cell 11.
[0024]
  The basic cell 11 includes a PMOS transistor 12 and an NMOS transistor 13. Note that PS is the source or drain of the PMOS transistor 12, PG is the gate, PD is the drain or source, and NW is a well connected to the back gate. Similarly, NS is the source or drain of the NMOS transistor 13, NG is the gate, ND is the drain or source, and PW is a well connected to the back gate. The source (drain) PS, gate PG, drain (source) PD, and well PW of the PMOS transistor 12, respectively, and the source (drain) NS, gate NG, drain (source) NS, and well PW of the NMOS transistor 13, respectively. Are electrically independent as separate nodes. The individual MOS transistors 12 and 13 are separated from adjacent MOS transistors by trenches T as shown in FIG.
[0025]
  FIG. 3 shows a configuration in which a gate array unit 16 formed by regularly arranging basic cells having the layout pattern shown in FIG. 2 is arranged at the center of a rectangular substrate 17 and an input / output interface unit 18 is arranged at the periphery. The gate array 15 is provided.
[0026]
  FIG. 4 is an equivalent circuit diagram of a two-input NAND circuit in which two basic cells 11 shown in FIGS. 1 and 2 are used and two NMOS transistors and two PMOS transistors are combined. FIG. 5 shows the layout pattern of FIG. The individual MOS transistors 12, 13, 12 ′, 13 ′ are isolated from each other by the trench T.
[0027]
  The two-input NAND circuit shown in FIGS. 4 and 5 includes a basic cell 11 as shown in FIG. 2 and a basic cell 11 ′ having a layout pattern in which the source side and the drain side of the basic cell 11 are inverted. have. A first metal wiring 19 is connected to the gate terminal PA of the first PMOS transistor 12 and the gate terminal NA of the first NMOS transistor 13 constituting the basic cell 11. On the other hand, the second metal wiring 20 is connected to the gate terminal PB ′ of the second PMOS transistor 12 ′ and the gate terminal NB ′ of the second NMOS transistor 13 ′ constituting the basic cell 11 ′.
[0028]
  The source NS ′ of the second NMOS transistor 13 ′ is connected to GND. The source NS of the first NMOS transistor 13 and the drain ND ′ of the second NMOS transistor 13 ′ are connected. Further, the drain PD of the first PMOS transistor 12, the drain PD ′ of the second PMOS transistor 12 ′, and the drain ND of the first NMOS transistor 13 are connected. The source PS of the first PMOS transistor 12 and the source PS ′ of the second PMOS transistor 12 ′ are connected to the power supply VDD. The well PW of the first NMOS transistor 13 and the well PW ′ of the second NMOS transistor 13 ′ are connected to the control power supply VPW. The well NW of the first PMOS transistor 12 and the well NW ′ of the second PMOS transistor 12 ′ are connected to the control power supply VNW. Here, when the control voltage VPW = 0V and the control voltage VNW = VDD, the threshold voltage Vthp of the first and second PMOS transistors 12, 12 ′ is −0.3V, and the first and second NMOS transistors 13, 13 It is assumed that the threshold voltage Vthn of 'is 0.3V.
[0029]
  Next, the operation of the 2-input NAND circuit having the above configuration will be described. When the level of the input signal A input to the first metal wiring 19 connected to the gate terminal PA of the first PMOS transistor 12 and the gate terminal NA of the first NMOS transistor 13 becomes “H (power supply voltage VDD level)”, The first PMOS transistor 12 is turned off, while the first NMOS transistor 13 is turned on. Further, when the level of the input signal B input to the second metal wiring 20 connected to the gate terminal PB ′ of the second PMOS transistor 12 ′ and the gate terminal NB ′ of the second NMOS transistor 13 ′ becomes “H”, The 2PMOS transistor 12 ′ is turned off, while the second NMOS transistor 13 ′ is turned on. Thus, when the first and second NMOS transistors 13 and 13 ′ are turned on, the output signal Y of the GND level (level “L”) is derived to the drain ND of the first NMOS transistor 13.
[0030]
  Further, when the level of the input signal A becomes “L (GND level)”, the first NMOS transistor 13 is turned off while the first PMOS transistor 12 is turned on. As a result, the output signal Y of the VDD level (level “H”) is derived to the drain PD of the first PMOS transistor 12. Similarly, when the level of the input signal B is “L”, the output signal Y of level “H” is derived to the drain PD ′ of the second PMOS transistor 12 ′. Further, when the levels of both input signals A and B are “L”, both PMOS transistors 12 and 12 ′ are turned on, and an output signal Y of level “H” is derived to both drains PD and PD ′. .
[0031]
  Here, when the NAND circuit is operating at the power supply voltage VDD = 1V, if the control voltage VPW = about 0.5V and the control voltage VNW = about 0.5V, the first and second PMOS transistors 12, The threshold voltage Vthp of 12 ′ is reduced to about −0.1V. Similarly, the threshold voltage Vthn of the first and second NMOS transistors 13 and 13 ′ is reduced to about 0.1V. As a result, the drive current becomes larger than when the threshold voltage Vthp is −0.3 V and the threshold voltage Vthn is 0.3 V, and higher speed operation is possible. That is, it is possible to prevent a decrease in operating speed when the power supply voltage VDD is reduced from about 3 V to about 1 V to reduce power consumption.
[0032]
  When the NAND circuit is stopped, the threshold voltage Vthp of the first and second PMOS transistors 12 and 12 ′ is −0 by setting the control voltage VPW = 0V and setting the control voltage source VNW = VDD. The threshold voltage Vthn of the first and second NMOS transistors 13 and 13 ′ becomes 0.3V. Therefore, the leakage current when the NAND circuit is stopped can be suppressed to be smaller than that in the case of the operation in which the threshold voltages Vthp = −0.1V and Vthn = 0.1V. In order to further suppress the leakage current during the stop, the threshold voltage Vthp is reduced to about -0.5V by setting the control power supply VPW = -0.5V and the control power supply VNW = (VDD + 0.5V). The voltage Vthn can be increased to about 0.5 V, and the leakage current during stop can be further suppressed.
[0033]
  As described above, in the gate array in the present embodiment, the gate G, source (drain) S, drain (source) D and well W are electrically isolated from each other and separated from other MOS transistors by the trench T. The basic cell 11 is composed of two P-type and N-type MOS transistors 12 and 13. The well NW connected to the back gate of the PMOS transistor 12 of each basic cell 11 is connected to the control power supply VNW, while the well PW connected to the back gate of the NMOS transistor 13 is connected to the control power supply VPW.
[0034]
  Therefore, the threshold voltage Vthp of the PMOS transistor 12 and the threshold voltage Vthn of the NMOS transistor 13 can be controlled by controlling the voltage of the control power supply VNW and the voltage of the control power supply VPW to control the well potential of the back gate. That is, in the present embodiment, by setting the threshold voltages Vthp and Vthn during operation of the circuit formed of the basic cells 11 to be lower than the threshold voltages Vthp and Vthn during standby (when stopped), Each MOS transistor during low voltage operation can be operated at higher speed. Therefore, if the operating frequency is constant, the operating voltage can be lowered to reduce power consumption. Further, by setting the threshold voltages Vthp and Vthn at the time of standby (when the circuit is stopped) to a voltage that can sufficiently suppress the leakage current, the leakage current of the MOS transistors 12 and 13 at the time of standby is suppressed. be able to.
[0035]
  That is, according to the present embodiment, the threshold voltage Vth can be controlled for each MOS transistor in the gate array chip, and the power consumption of the entire gate array can be further reduced. Further, the basic cell 11 in the present embodiment is formed by one PMOS transistor 12 and one NMOS transistor 13. Therefore, when an inverter circuit is formed using the basic cell 11, an unused MOS transistor does not occur in the basic cell 11, and the circuit can be formed efficiently without waste.
[0036]
  In the above embodiment, the source (drain) S, the gate G, the drain (source) S, and the well W in both the PMOS transistor 12 and the NMOS transistor 13 constituting the basic cell 11 are set to separate nodes. As electrically independent. However, the above-described effect can be obtained even if each of the source (drain) S, gate G, drain (source) S, and well W of only one of the MOS transistors is electrically independent as separate nodes. Further, the voltages of the well NW of the PMOS transistor 12 and the well PW of the NMOS transistor 13 constituting the basic cell 11 are set to the voltage during operation of the circuit (two-input NAND circuit) to which the basic cell 11 belongs and the voltage during standby (stop). The two voltages are switched to a predetermined voltage. However, the present invention is not limited to this, and the voltage can be controlled to two arbitrary levels according to switching of the power supply voltage VDD or the like.
[0037]
  Next, a second embodiment of the gate array of the present invention will be described. FIG. 6 is an equivalent circuit diagram showing a basic cell in the gate array of the present embodiment. FIG. 7 shows a layout pattern of the basic cell 21.
[0038]
  In the present embodiment, the gate array is composed of a plurality of basic cells 21. The basic cell 21 includes a P-type MOS transistor circuit and an N-type MOS transistor circuit. The P-type MOS transistor circuit includes a first PMOS transistor 22 and a second PMOS transistor 23 having a layout pattern in which the source side and the drain side of the first PMOS transistor 22 are inverted, and a trench T is formed around the first PMOS transistor 22. Are isolated from adjacent MOS transistors. Similarly, the N-type MOS transistor circuit includes a first NMOS transistor 24 and a second NMOS transistor 25 having a layout pattern in which the source side and the drain side of the first NMOS transistor 24 are inverted, and a trench T around the periphery. To separate the adjacent MOS transistors.
[0039]
  A well NW communicates with the back gates of the first and second PMOS transistors 22 and 23. Similarly, the well PW communicates with the back gates of the first and second NMOS transistors 24 and 25. PD1, PD2 and PD3 are the drains or sources of the first and second PMOS transistors 22 and 23, and PD2 of them is a common node. PG 1 is the gate of the first PMOS transistor 22, and PG 2 is the gate of the second PMOS transistor 23. Further, ND1, ND2, and ND3 are drains or sources of the first and second NMOS transistors 24 and 25, and ND2 of them is a common node. NG 1 is the gate of the first NMOS transistor 24, and NG 2 is the gate of the second NMOS transistor 25.
[0040]
  In the first embodiment described above, the well potential (back gate potential) can be controlled for each MOS transistor as shown in FIG. 1 and FIG. The well potential (back gate potential) can be controlled for each MOS transistor. That is, the threshold voltage Vthp or the threshold voltage Vthn can be controlled for each of the first and second PMOS transistors 22 and 23 and the first and second NMOS transistors 24 and 25.
[0041]
  Therefore, according to the present embodiment, the threshold voltage Vth cannot be finely controlled for each MOS transistor as in the first embodiment. However, in this embodiment, since it is not necessary to isolate the elements by the trench T for each MOS transistor, the basic cells 21 are regularly arranged on the substrate to form a gate array as shown in FIG. In this case, there is an advantage that the area of the gate array can be reduced because it is not necessary to perform element isolation for each MOS transistor.
[0042]
  In the basic cell 21 in the second embodiment, the well NW and drain (source) PD2 of the two PMOS transistors 22 and 23 are shared, and the well PW and drain (source) of the two NMOS transistors 24 and 25 are shared. ND2 is shared. However, the number of MOS transistors that share the well W and drain (source) D in the present invention is not limited to “2”, and may be determined as appropriate according to the circuit configuration realized on the gate array. .
[0043]
  By the way, when the above-mentioned basic cells are regularly arranged on the substrate to form the gate array as described above, the threshold voltage Vth for each MOS transistor is provided in the gate array section 26 as shown in FIG. 1 and FIG. 2 in which the basic cell 11 shown in FIG. 1 and FIG. 2 is arranged, and element isolation is performed for every two MOS transistors, so that the area per MOS transistor is small in FIG. 6 and FIG. The second area 26b in which the basic cell 21 shown is arranged and the third area 27 in which a memory, a CPU (central processing unit) and the like are arranged are mixed. Thus, a gate array with good controllability and area efficiency can be realized by arranging a plurality of types of basic cells having different numbers of MOS transistors having a back gate communicating with one well. Reference numeral 28 denotes a substrate, and 29 denotes an input / output interface unit.
[0044]
  However, in the basic cells 11 and 21 in the gate array as shown in FIG. 8, as described above, the threshold voltage Vth of the MOS transistor is divided into two stages when the circuit to which the MOS transistor belongs is in operation and in the standby state. To switch to. When the circuit is in operation, the threshold voltage Vth of the MOS transistor is reduced. Therefore, the threshold voltage Vth of the MOS transistor in the off state in the circuit is also small, and there is a disadvantage that a through current flowing from the power supply VDD to the GND via each MOS transistor becomes large.
[0045]
  FIG. 9 is an equivalent circuit diagram of a 2-input NAND circuit according to the third embodiment in which the above-described drawbacks are improved. FIG. 10 shows the layout pattern of FIG. As in the case of the 2-input NAND circuit shown in FIGS. 4 and 5, the 2-input NAND circuit according to the present embodiment uses two basic cells 11 shown in FIGS. Two PMOS transistors are configured as one set.
[0046]
  However, the configuration of the 2-input NAND circuit in the present embodiment is the same as that of the 2-input NAND circuit shown in FIGS. 4 and 5, and the back gates of the first and second PMOS transistors 31, 31 ′ are wells NW, NW, respectively. Are connected to the gates PG and PG 'of the same PMOS transistors 31 and 31' through 'and the back gates of the first and second NMOS transistors 32 and 32' through the wells PW and PW ', respectively. It is different in that it is connected to the gates NG and NG ′ of the same NMOS transistors 32 and 32 ′, and the other points are the same. As a result, as described below, operation is possible even with a power supply voltage VDD as low as about 0.5 V, and leakage current and through current are suppressed.
[0047]
  That is, the level of the input signal A input to the first metal wiring 33 connected to the gate terminal PA of the first PMOS transistor 31 and the gate terminal NA of the first NMOS transistor 32 is “H (power supply voltage VDD level)”. Then, the level of the gate voltage of the first NMOS transistor 32 becomes “H” and the transistor is turned on. In this case, the level of the well PW connected to the back gate is also the power supply voltage VDD level, and the threshold voltage Vthn of the first NMOS transistor 32 is lower than that when the level of the well PW is the GND level. Therefore, the first NMOS transistor 32 can operate at high speed even when the power supply voltage VDD is 0.5V.
[0048]
  Similarly, when the level of the input signal B input to the second metal wiring 34 connected to the gate terminal PB ′ of the second PMOS transistor 31 ′ and the gate terminal NB ′ of the second NMOS transistor 32 ′ becomes “H”. The gate voltage level of the second NMOS transistor 32 ′ becomes “H” and is turned on. In this case, the level of the well PW ′ connected to the back gate is also the power supply voltage VDD level, and the threshold voltage Vthn ′ of the second NMOS transistor 32 ′ is lower than that when the level of the well PW ′ is the GND level. Therefore, the second NMOS transistor 32 ′ can operate at high speed even when the power supply voltage VDD is 0.5V. Thus, when the first and second NMOS transistors 32 and 32 ′ are turned on, the GND level output signal Y is derived to the drain ND of the first NMOS transistor 32.
[0049]
  On the other hand, since the levels of the input signals A and B are “H”, the gate voltages of the first and second PMOS transistors 31 and 31 ′ become “H” and turn off. In this case, the levels of the wells NW and NW ′ connected to the back gates of the first and second PMOS transistors 31 and 31 ′ are the same power supply voltage VDD level as the gate voltage. Therefore, the threshold voltages Vthp and Vthp ′ are not lower than when the levels of the wells NW and NW ′ are the GND level. Therefore, the leakage currents of the first and second PMOS transistors 31 and 31 ′ in the off state and the through current flowing from the power supply VDD to the GND through each MOS transistor are suppressed.
[0050]
  Next, when the level of the input signal A is “L (GND level)”, the first NMOS transistor 32 is turned off and the level of the well PW becomes the same GND level as the level of the gate NG. Therefore, the threshold voltage Vhtn of the first NMOS transistor 32 does not become lower than when the level of the well PW is the power supply voltage VDD level. On the other hand, the first PMOS transistor 31 is turned on, and the VDD level output signal Y is derived from the drain PD. In this case, the level of the well NW becomes the same GND level as the level of the gate PG, and the threshold voltage Vthp of the first PMOS transistor 31 is lower than that when the level of the well NW is the power supply voltage VDD level. Therefore, the first PMOS transistor 31 can operate at high speed even when the power supply voltage VDD is 0.5V.
[0051]
  At this time, since the threshold voltage Vthn of the first NMOS transistor 32 is high as described above, the leakage current of the first NMOS transistor 32 in the off state and the through current flowing from the power supply VDD to the GND through each MOS transistor are generated. It can be suppressed.
[0052]
  Even when the level of the input signal B is “L” and when the levels of both the input signals A and B are “L”, the operation is the same as in the first embodiment, and the VDD level is low. An output signal Y is derived. Even in this case, for the same reason described above, the leakage current of the NMOS transistor in the off state and the through current flowing from the power supply VDD to the GND through each MOS transistor can be suppressed.
[0053]
  As described above, the gate array in the present embodiment is configured using the basic cells 11 shown in FIGS. 1 and 2 as in the case of the first embodiment. The back gates of the PMOS transistor 31 and the NMOS transistor 32 of each basic cell 11 are connected to the gates PG and NG of the same MOS transistors 31 and 32 via the wells PW and NW, respectively. Therefore, the threshold voltage Vthp of the PMOS transistor 31 is lower than when the well potential is the power supply voltage VDD when turned on, but not lower than when the well potential is GND when turned off. The threshold voltage Vthn of the NMOS transistor 32 is lower than when the well potential is GND when turned on, but not lower than when the well potential is the power supply voltage VDD when turned off.
[0054]
  Therefore, even when a circuit formed using the basic cell 11 is in operation, the leakage voltage and the through current can be suppressed by increasing the threshold voltage Vth of the MOS transistor in the off state as much as possible. Furthermore, the threshold voltage Vth of the MOS transistor in the on state can be made as low as possible so that even a power supply voltage VDD as low as 0.5 V can be operated at high speed. That is, according to the present embodiment, a gate array with lower power consumption can be realized.
[0055]
  That is, as shown in FIGS. 1 and 2, the threshold voltage Vth can be controlled for each MOS transistor using the MOS transistor in the present embodiment in which the back gate is connected to the gate through the well. A first basic cell is formed. Further, by using the MOS transistor in the present embodiment in which the back gate is connected to the gate through the well, element isolation is performed for each of the plurality of MOS transistors, thereby reducing the area per MOS transistor. A second basic cell as shown in FIG. 7 is formed. FIG. 8 shows a mixture of the first area in which the first basic cells are arranged, the second area in which the second basic cells are arranged, and the third area in which a memory, a CPU, and the like are arranged. By forming such a gate array, it is possible to realize a gate array that has good controllability and area efficiency and can suppress the through current during operation.
[0056]
  In each of the above embodiments, each MOS transistor is formed on a well and a back gate is connected to the well. However, the present invention is not limited to this, and can be applied even when each MOS transistor is formed on a semiconductor substrate. However, in that case, the semiconductor region in which the channel is formed when each MOS transistor is turned on needs to be electrically independent from the semiconductor region in which the channel of the other MOS transistor is formed.
[0057]
  The configuration of the basic cell is not limited to the configuration of the basic cell (equivalent circuit, layout pattern) in each of the above embodiments.
[0058]
【The invention's effect】
  As apparent from the above, the gate array of the invention according to claim 1 is formed by arranging basic cells including MOS transistors having gates, sources and drains that are electrically independent from each other, and the gates, sources and drains are arranged. Are electrically independent for each transistor, the MOS transistor can be a component of a circuit formed on the gate array alone. Accordingly, when forming a circuit on the gate array, each MOS transistor can be used without waste, and the circuit can be formed efficiently.
[0059]
  furtherThe semiconductor region in which the channel is formed when the MOS transistor is turned on is electrically independent for each MOS transistor, and the voltage of the semiconductor region is set independently of the source voltage by the voltage setting means. For each MOS transistor, the voltage of the semiconductor region can be set to a voltage other than the power supply voltage VDD or GND, which has been conventionally used as a control voltage for the gate array. Therefore, the threshold voltage of each MOS transistor is set low during operation of the circuit to which the MOS transistor belongs, and set high during standby (stop), and the MOS transistor operates at high speed when the operating voltage is lowered to reduce power consumption. In addition, it is possible to reduce power consumption by suppressing leakage current during standby.
[0060]
  Further, since the semiconductor region in which the channel is formed when the transistor is turned on is electrically connected to the gate of the corresponding MOS transistor, the semiconductor region in which the channel is formed when the MOS transistor is turned on includes the gate. The same voltage can be applied. Therefore, the threshold voltage of each MOS transistor can be controlled to be low when on and high when off. That is, according to the present invention, even if the circuit formed on the gate array is in operation, if there is an off-state MOS transistor in the current path from the power supply VDD to GND, the through current can be suppressed. Further reduction in power consumption can be achieved.
[0061]
  Also,Claim 2The voltage setting means in the gate array according to the invention can control the voltage of the semiconductor region in which the channel is formed individually for each MOS transistor, so that the threshold voltage of each MOS transistor can be individually controlled. Can be set to a desired value according to the operating voltage.
[0062]
  MaTheClaim 3The gate array of the invention according to the invention is formed by arranging basic cells including MOS transistors, and a semiconductor region in which a channel is formed when the MOS transistor is turned on is electrically independent for each of the plurality of MOS transistors. The voltage of the semiconductor region is set by voltage setting means.Each of the above MOS transistorsSince the voltage is set independently of the source voltage, the threshold voltage of each MOS transistor can be set to a desired value in units of a plurality of MOS transistors. Therefore, the MOS transistor can be operated at a high speed when the operating voltage is lowered to reduce the power consumption, and the leakage current during standby can be suppressed. Further, since it is not necessary to form a separation band for separating the MOS transistors between the plurality of MOS transistors, the area of the gate array can be reduced accordingly.
[0063]
  Furthermore, since each of the semiconductor regions electrically independent for each of the plurality of MOS transistors is electrically connected to the gate of each of the MOS transistors belonging to each semiconductor region, the semiconductor The same voltage as that of the gate is applied to each of the regions. Therefore, each MOS transistor can be controlled such that the threshold voltage decreases when the MOS transistor is on, while the threshold voltage increases when it is off. As a result, even if the circuit formed on the gate array is in operation, if there is an off-state MOS transistor in the current path from the power source VDD to GND, the through-state current is reduced by the off-state MOS transistor. Can be suppressed.
[0064]
  The gate array of the invention according to claim 4 isGates that are electrically independent of each other , Multiple with source and drainSemiconductor region in which channel is formed when MOS transistor is turned onIs electrically connected to the gate of the corresponding MOS transistor, and the plurality of MOS transistors have the semiconductor region in each of the above-described semiconductor regions.Each MOS transistor is electrically independentA first MOS transistor, and a second MOS transistor in which the semiconductor region is electrically independent for each of the plurality of MOS transistors. , SecondBy voltage setting meansThe first , In the second MOS transistorThe voltage of the semiconductor regionThe first , Of the second MOS transistorSince it is set independently from the source voltage,A first region in which the first MOS transistors capable of controlling the threshold voltage are arranged for each one. AreaWhen,By performing element isolation for each of the plurality, the second area is small.MOS transistorA second region, and a third region including the first voltage setting unit and the second voltage setting unit,MixedBy configuring a gate array, Good controllability and area efficiency,And it can suppress the through current during operation.A gate array that canRealizeCan.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram showing one embodiment of a basic cell constituting a gate array of the present invention.
FIG. 2 is a diagram showing a layout pattern of the basic cell shown in FIG. 1;
3 is a diagram showing a gate array using the basic cell shown in FIGS. 1 and 2. FIG.
4 is an equivalent circuit diagram of a two-input NAND circuit formed using the basic cell shown in FIGS. 1 and 2. FIG.
FIG. 5 is a diagram showing a layout pattern of the 2-input NAND circuit shown in FIG. 4;
FIG. 6 is an equivalent circuit diagram of a basic cell different from FIG.
7 is a diagram showing a layout pattern of the basic cell shown in FIG. 6. FIG.
8 is a diagram showing a gate array using the basic cell shown in FIGS. 1 and 2 and the basic cell shown in FIGS. 6 and 7. FIG.
FIG. 9 is an equivalent circuit diagram of a two-input NAND circuit different from FIGS. 4 and 5 formed using the basic cell shown in FIGS. 1 and 2;
10 is a diagram showing a layout pattern of the 2-input NAND circuit shown in FIG. 9; FIG.
FIG. 11 is a diagram showing a gate array on which a conventional basic cell is mounted.
12 is a diagram showing a layout pattern of basic cells mounted on the gate array of FIG. 11. FIG.
13 is an equivalent circuit diagram of the basic cell shown in FIG.
14 is a diagram showing a layout pattern of an inverter circuit realized on the basic cell shown in FIGS. 12 and 13. FIG.
[Explanation of symbols]
11, 11 ', 21 ... basic cells,
12,12 ', 22,23,31,31' ... PMOS transistor,
13,13 ', 24,25,32,32' ... NMOS transistor,
15 ... Gate array, 16, 26 ... Gate array part,
19, 20, 33, 34 ... metal wiring,
PG, NG, PG1, NG1, PG ', NG' ... Gate,
PS, PD, NS, ND, PS ', PD', NS ', ND'
                    , PD1 to PD3, ND1 to ND3 ... source or drain,
NW, PW, NW ', PW' ... well, T ... trench.

Claims (4)

A gate array in which basic cells including metal oxide semiconductor transistors having gates, sources and drains that are electrically independent from each other are arranged,
The gate, source and drain are electrically independent for each transistor ,
The semiconductor region in which a channel is formed when the metal oxide semiconductor transistor is turned on is electrically independent for each metal oxide semiconductor transistor,
In the gate array comprising voltage setting means for setting the voltage of the semiconductor region independently of the voltage of the source,
A gate array , wherein a semiconductor region in which a channel is formed at the time of ON is electrically connected to the gate of the corresponding metal oxide semiconductor transistor . The gate array of claim 1,
The gate array according to claim 1, wherein the voltage setting means is capable of controlling the voltage of the semiconductor region individually for each metal oxide semiconductor transistor. A gate array in which basic cells including a metal oxide semiconductor transistor having a gate and a source are arranged ,
A semiconductor region in which a channel is formed when the metal oxide semiconductor transistor is turned on is electrically independent for each of the plurality of metal oxide semiconductor transistors,
Electrically Independent husband of the semiconductor region s in each of the plurality of metal oxide semiconductor transistors, which is the gate electrically connected to each of the metal oxide semiconductor transistors belonging to each of the semiconductor regions ,
A gate array comprising voltage setting means for setting a voltage of the semiconductor region independently of a voltage of the source of each of the metal oxide semiconductor transistors . Comprising a plurality of metal oxide semiconductor transistors having gates , sources and drains which are electrically independent from each other ;
A semiconductor region in which a channel is formed when the metal oxide semiconductor transistor is turned on is electrically connected to the gate of the corresponding metal oxide semiconductor transistor ,
The plurality of metal oxide semiconductor transistors are
A first metal oxide semiconductor transistor in which a semiconductor region in which a channel is formed at the time of ON is electrically independent for each of the metal oxide semiconductor transistors;
A second metal oxide semiconductor transistor in which a semiconductor region in which a channel is formed at the time of on is electrically independent for each of the plurality of metal oxide semiconductor transistors;
Including
First voltage setting means for setting a voltage of the semiconductor region in the first metal oxide semiconductor transistor independently of a voltage of the source of the first metal oxide semiconductor transistor;
Second voltage setting means for setting a voltage of the semiconductor region in the second metal oxide semiconductor transistor independently of a voltage of the source of the second metal oxide semiconductor transistor;
Gate array, comprising the.

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