JP4205717B2 - Optical sensor circuit and image sensor - Google Patents

Description

  The present invention relates to an optical sensor circuit and an image sensor, and in particular, has a linear output characteristic and a logarithmic output characteristic corresponding to the illuminance of incident light, and realizes a MOS type image sensor having a wide dynamic range with increased transfer charge and sensitivity. The present invention relates to an optical sensor circuit suitable for the image sensor, and an image sensor manufactured using the optical sensor circuit as one pixel.

  The types of photosensor circuits forming each pixel of the MOS type image sensor include a photosensor circuit having linear output characteristics with respect to a change in illuminance (intensity) of incident light, and a logarithm with respect to a change in illuminance of incident light. And an optical sensor circuit having output characteristics. In the following, these optical sensor circuits will be outlined, and their characteristics will be evaluated in terms of SN ratio, dynamic range, afterimage, sensitivity at low illumination, and the like.

  FIG. 16 shows a circuit example of an optical sensor circuit having a linear output characteristic. The optical sensor circuit 101 includes a photodiode PD as an optical sensor element that detects incident light (optical signal) L1 and converts it into an electrical signal. The photodiode PD has a capacitor C1 that is a parasitic capacitance (including a floating capacitance of the wiring). The optical sensor circuit 101 further includes a MOS transistor Q1 for charging and discharging the charge of the capacitor C1, a MOS transistor Q2 for amplifying the terminal voltage of the capacitor C1, and the amplified terminal voltage (Vout). A MOS transistor Q3 that selectively outputs a pixel signal is provided. A resistor R is connected to the drain terminal of the MOS transistor Q3.

  Necessary voltages V1 and V2 are applied by the voltage controller 102 to the gate terminal G1 and the drain terminal D1 of the MOS transistor Q1. Similarly, required voltages V3 and V4 are applied to the gate terminal G3 of the MOS transistor Q3 and the outer terminal T1 of the resistor R by the voltage controller 102 or the like (pixel selection circuit or the like). Timing of generating the required voltages V1 to V4 output by the voltage controller 102 is instructed by the timing signal generator 103.

  The operation of the photosensor circuit 101 will be described. With the drain voltage V2 of the MOS transistor Q1 maintained at the high level, the gate voltage V1 of the MOS transistor Q1 is set to the high level at the initialization timing. As a result, the charge remaining in the capacitor C1 of the photodiode PD is discharged to the drain of the MOS transistor Q1. Thereafter, the gate voltage V1 is switched to the low level (0 V), and the MOS transistor Q1 is turned off. Thereafter, charge is further accumulated in the capacitor C1 of the photodiode PD. A terminal voltage is applied to the gate of the MOS transistor Q2 in the capacitor C1 generated by the charge accumulation. When the MOS transistor Q3 is turned on after a certain exposure time at the photodiode PD has elapsed, an optical signal is output as a voltage Vout from the drain of the MOS transistor Q3.

  In the photosensor circuit 101, the photocurrent flowing through the photodiode PD is governed by the discharge current of the charge charged in the capacitor C1 of the photodiode PD. Therefore, the output voltage Vout, which is the sensor output of the optical sensor circuit 101, exhibits a linear output characteristic proportional to the discharge current. Since the optical sensor circuit 101 can control the sensor output based on the exposure time, it becomes a storage type image sensor. However, according to the circuit configuration of the optical sensor circuit 101, the output voltage Vout to be output is proportional to the intensity of the incident light L1, so that it is saturated when strong light is incident and the dynamic range cannot be widened. is doing.

  An optical sensor circuit having a circuit configuration similar to the optical sensor circuit 101 is shown in FIG.

  Next, FIG. 17 shows a circuit example of an optical sensor circuit having logarithmic output characteristics. In FIG. 17, elements that are substantially the same as those described in FIG. 16 are given the same reference numerals, and redundant detailed description of these elements is omitted. In the photosensor circuit 201, a MOS transistor Q21 is used instead of the MOS transistor Q1 in the photosensor circuit 101. In the MOS transistor Q21, the gate is electrically connected to the drain. Other circuit configurations such as the photodiode PD, the capacitor C1, the MOS transistor Q2, the MOS transistor Q3, and the resistor R are the same as those described in FIG. In this optical sensor circuit 201, the MOS transistor Q21 converts the sensor current of the photodiode PD into a sensor voltage having a logarithmic characteristic in a weak inversion state.

  In the optical sensor circuit 201, the gate of the MOS transistor Q21 is connected to the drain thereof, the drain voltage and the gate voltage are set to the same constant drain voltage V2, the MOS transistor Q3 is turned on, and the light is output as the output voltage Vout. The signal is detected. A high level gate voltage is supplied from the voltage controller 102 to the gate terminal G3 of the MOS transistor Q3.

  Since the optical sensor circuit 201 uses logarithmic output characteristics, it can take a wide dynamic range. However, since the photocurrent flows through the channel of the MOS transistor Q21, the exposure time cannot be increased and the S / N ratio cannot be improved as in the accumulation type image sensor. Therefore, the sensitivity of low illuminance is inferior to that of the storage type image sensor using the photosensor circuit 101. Further, if the current flowing through the MOS transistor Q21 is small, the impedance of the channel becomes high, and there is a problem that an afterimage is likely to occur.

An optical sensor circuit having logarithmic output characteristics is described in Patent Document 1.
JP 2000-329616 A

  As described above, according to the optical sensor circuit exhibiting linear output characteristics, since the detection signal is proportional to the incident light intensity, it is saturated when a strong light is incident, and a wide dynamic range cannot be obtained. Further, according to the optical sensor circuit exhibiting logarithmic output characteristics, the sensitivity of low illuminance is inferior, and when the current flowing through the MOS transistor Q21 is small, the channel impedance of the transistor becomes high and an afterimage is likely to occur.

  In view of the above problems, an object of the present invention is an optical sensor circuit having linear output characteristics with respect to incident light with low illuminance and logarithmic output characteristics with respect to incident light with high illuminance, and having a linear output range. Can be set arbitrarily, the variation of each optical sensor circuit can be suppressed, the S / N ratio is high at low illumination, etc., and the signal charge is increased by the capacitor for charge integration during sample and hold to increase the sensitivity. It is an object of the present invention to provide a photosensor circuit that can be used, and an image sensor using the photosensor circuit.

  In order to achieve the above object, an optical sensor circuit and an image sensor according to the present invention are configured as follows.

  A first optical sensor circuit (corresponding to claim 1) converts a light signal into a current signal, and converts a current signal output from the photoelectric conversion element into a voltage signal having a logarithmic characteristic in a weak inversion state. A first MOS transistor (Q1), a first capacitance element (C1) connected to a voltage detection terminal of the photoelectric conversion element, a second capacitance element (C2) holding a voltage signal, A second MOS transistor (Q4) for controlling charge movement between the first capacitance element and the second capacitance element, and gate voltages and drain voltages of the first MOS type transistor Q1 and the second MOS type transistor Q4. And control means for supplying. This control means performs voltage control as follows. First, the drain voltage of the first MOS transistor Q1 is set to a high voltage value (VdH) for a first predetermined time, and the gate voltage of the first MOS transistor Q1 and the gate voltage of the second MOS transistor Q4 are respectively set to the second voltage. A high voltage value (Vg1H, Vg2H) is set for a predetermined time, and charging or discharging of the second capacitance element to be integrated as an optical signal is controlled and set to a constant potential. Thereafter, the second MOS transistor Q4 is turned off to open the second capacitance element, the drain voltage of the first MOS transistor Q1 is set to a low voltage (VdL), and the first MOS transistor Q1 The gate voltage is set to an intermediate potential (Vg1M), thereby discharging the charge of the first capacitance element. Thereafter, the drain voltage of the first MOS transistor Q1 is set to a high voltage (VdH), and then the gate voltage of the first MOS transistor Q1 is set to a low voltage (Vg1L) when a third predetermined time has elapsed. VdH and Vg1M are set so as to satisfy the relationship of “Vg1M−VdH <Vth1 and Vg1M−VdL> Vth1, where Vth1 is the threshold voltage of the first MOS transistor Q1”. Thereafter, the gate voltage of the second MOS transistor Q4 is set to a predetermined voltage (Vg2M) for a fourth predetermined time after a certain exposure time has elapsed, and “Vg1M <Vg2M <Vg1M + Vth2, where Vth2 is the first voltage Vg2M”. It is set so as to satisfy the relationship of “threshold voltage of 2MOS transistor Q4”, whereby the charge of the first capacitance element is transferred to the second capacitance element. Thereafter, the second MOS transistor Q4 is turned off to open the second capacitance element, and the terminal voltage of the second capacitance element is used as a sensor output signal.

  In the second photosensor circuit (corresponding to claim 2), in the above configuration, it is preferable that the control unit has a gate intermediate potential (Vg1M) and a low set potential (Vg1L) of the first MOS transistor (Q1). It is characterized by switching to an arbitrary voltage.

  The third photosensor circuit (corresponding to claim 3) preferably has a third MOS type transistor (Q2) for amplifying the terminal voltage of the second MOS type transistor (Q4) in the above configuration. It is attached.

  In the above configuration, the fourth photosensor circuit (corresponding to claim 4) is preferably a fourth MOS transistor (Q3) for selectively outputting a voltage signal output from the third MOS transistor (Q2). ).

  An image sensor according to the present invention (corresponding to claim 5) is characterized in that an imaging region is formed using one of the first to fourth photosensor circuits described above as one pixel.

The present invention has the following effects.
First, according to the present invention, when the photoelectric conversion element is irradiated with incident light, the charge is stored in the first capacitance element according to the intensity of the incident light based on the operation of the MOS transistor Q1, and then the charge is charged. An optical sensor circuit that transfers charges from the first capacitance element to the second capacitance element based on the operation of the transfer MOS transistor Q4. The charge storage potential of the second capacitance element is set to the first level during charge transfer. Since it is set to be higher than the potential of one capacitance element, the charge accumulated in the first capacitance element can be efficiently transferred to the second capacitance element, and the charge accumulated in the first capacitance element can be transferred. It can be used effectively, and the signal charge can be increased by the capacitor for charge integration during sample and hold, and the sensor sensitivity of the optical sensor circuit can be increased.
Secondly, according to the present invention, the change point between the linear output characteristic region and the logarithmic output characteristic region can be controlled by the optical sensor circuit having the linear output characteristic and the logarithmic output characteristic according to the illuminance of the incident light. The variation of the potential of the changing point for each optical sensor circuit can be stably eliminated, the S / N ratio is high at low illuminance and the like, the sensitivity is wide, the dynamic lens is wide, and the afterimage can be reduced.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  A first embodiment of an optical sensor circuit according to the present invention will be described with reference to FIGS. FIG. 1 shows a circuit configuration of an optical sensor circuit according to the first embodiment. 1 to 12, elements that are substantially the same as the elements shown in FIGS. 16 and 17 used in the description of the “Background Art” section are given the same reference numerals.

  FIG. 1 shows an optical sensor circuit according to a first embodiment of the present invention. The optical sensor circuit 10 includes a photodiode PD that is an optical sensor element that detects the light L1 and converts it into an electrical signal, and a capacitor C1 that is a parasitic capacitance (including stray capacitance such as wiring) of the photodiode PD. . The capacitor C1 is connected in parallel between the anode and cathode of the photodiode PD, and is connected to the voltage detection terminal (cathode) of the photodiode PD. The photodiode PD is an example of an optical sensor element, and the optical sensor element is not limited to this.

  The photodiode PD is provided with a conversion MOS transistor Q1 for converting the sensor current into a sensor voltage having a logarithmic characteristic in a weak inversion state. The MOS transistor Q1 has a drain 11d, a source 11s, and a gate 11g. The cathode of the photodiode PD is connected to the source 11s of the MOS transistor Q1. On the other hand, the anode of the photodiode PD is connected to the ground terminal. A drain voltage Vd is supplied from the voltage controller 13 to the drain terminal 12d of the MOS transistor Q1, and a gate voltage Vg1 is supplied from the voltage controller 13 to the gate terminal 12g.

  The optical sensor circuit 10 further includes a capacitor C2 for accumulating charges and a MOS transistor Q4 for moving charges. The MOS transistor Q4 is a charge transfer MOS transistor for selectively transferring charges from the capacitor C1 to the capacitor C2 between the capacitors C1 and C2. The charge transfer MOS transistor Q4 is also called a “shutter transistor”.

  When the MOS transistor Q4 is turned on, the photosensor circuit 10 samples and holds the light signal as a voltage signal in response to the incident light L1. The sample and hold function of the optical sensor circuit 10 is called a “shutter function”.

  In the MOS transistor Q4, its source 16s is connected to the cathode of the photodiode PD, and its drain 16d is an output terminal 17 for outputting a sensor signal. The gate voltage Vg2 is supplied from the voltage controller 13 to the gate terminal 18g of the gate 16g of the MOS transistor Q4.

  The timings for supplying the voltages Vd, Vg1, and Vg2 supplied by the voltage controller 13 are instructed by the timing signal generator 14, and the level of each voltage at each time point is determined in advance. The respective voltage waveform diagrams of the voltages Vd, Vg1, and Vg2 supplied by the voltage controller 13 and the like are shown in the timing chart of FIG. Based on the voltage controller 13 and the timing signal generator 14, a control means 15 having an initial setting function and a voltage control function is configured.

  The operating states of the MOS transistors Q1 and Q2 are controlled and set according to the voltage levels of the voltages Vd, Vg1 and Vg2 supplied from the voltage controller 13. Thereby, the operation of the optical sensor circuit 10 is controlled, and the shutter function is realized.

  The operation of the optical sensor circuit 10 will be described below.

  First, the basic operation will be described. When the light L1 is incident on the photodiode PD, a sensor current flows in the photodiode PD according to the illuminance (or intensity) of the light L1. This sensor current is stored in the capacitor C1 as a terminal voltage (VC1) of the capacitor C1 after the electric charge is stored in the capacitor C1 and converted into a sensor voltage. The MOS transistor Q1 converts the sensor current of the photodiode PD into a sensor voltage (VC1) having a logarithmic characteristic in a weak inversion state. Next, the MOS transistor Q4 is turned on at a predetermined timing and the capacitor C1 and the capacitor C2 are electrically connected. The charge stored in the capacitor C1 moves to the capacitor C2, and is stored in the capacitor C2. It is held as the terminal voltage of C2. The output voltage Vout from the output terminal 17 of the photosensor circuit 10 is taken out as the terminal voltage of the capacitor C2.

  Next, the operation of the optical sensor circuit 10 in relation to the voltages Vd, Vg1, and Vg2 supplied by the voltage controller 13 will be described with reference to FIGS.

  The timing chart of FIG. 2 shows voltage levels and generation timings of respective parts of the circuit for performing initial voltage setting and charge transfer. 3 to 5 are potential diagrams. FIG. 3 is a potential diagram for initialization setting, FIG. 4 is a potential diagram for exposure, and FIG. 5 is a potential diagram for charge transfer. In each potential diagram, the potential (Vd) of the drain 11d of the MOS transistor Q1, the potential (Vg1) of the gate 11g of the MOS transistor Q1, the potential of the capacitor C1, the potential (Vg2) of the gate 16g of the MOS transistor Q4, the capacitor Each state of the potential of C2 is shown.

  In FIG. 2, the drain voltage Vd of the MOS transistor Q1 is set to a high voltage value (VdH) from t1 to t2, and the gate voltage Vg1 of the MOS transistor Q1 and the gate voltage Vg2 of the MOS transistor Q4 are respectively set to high voltages. Set to the value (Vg1H, Vg2H). As a result, the drain 11d, the capacitor C1, and the capacitor C2 of the MOS transistor Q1 become conductive, and the charging or discharging of the capacitor C2 for integration as an optical signal is controlled and set to a desired constant potential.

  The above state is shown in FIG. In FIG. 3A, the vertical axis indicates the potential, and the horizontal axis indicates the drain 11d (Vd) of the MOS transistor Q1 in the optical sensor circuit 10, the gate 11g (Vg1) of the MOS transistor Q1, the capacitor C1, and the MOS A gate 16g (Vg2) and a capacitor C2 of the type transistor Q4 are shown. The potential on the vertical axis is set so that the potential increases as it goes downward. This also applies to (B) to (D) in FIG. 3, (A) and (B) in FIG. 4, and (A) to (C) in FIG. In FIG. 3A, the drain voltage Vd and the gate voltages Vg1 and Vg2 are in a high state (high potential level), and the capacitors C1 and C2 are electrically connected at the same level. Is in a state. Based on the state shown in FIG. 3A, the capacitor C2 is reset.

  Next, at time t2, the gate voltage Vg2 is set to a low voltage (Vg2L), the MOS transistor Q4 is turned off, and the capacitor C2 is opened. Here, the “open state” of the capacitor C2 means a state in which the electrical connection relationship with the capacitor C1 is disconnected. That is, the sample hold (S / H) is reset (ST1).

  After that, the capacitor C2 is in an open state, and at time t3, the drain voltage Vd of the MOS transistor Q1 is set to a low voltage (VdL) and the gate voltage Vg1 of the MOS transistor Q1 is set to an intermediate potential (Vg1M : Medium potential level). The state where the drain voltage Vd is VdL continues until time t4, and the state where the gate voltage Vg1 is Vg1M continues until time t5. When the drain voltage Vd is set to a low voltage (VdL) between t3 and t4, the charge stored in the capacitor C1 is discharged, and the photodiode PD is reset (state ST2). The capacitor C1 is also reset when the electric charge is discharged.

  The above state is shown in FIG. In FIG. 3B, the level of the drain voltage Vd is in a low potential state, the potential of the gate voltage Vg1 is in an intermediate potential (Medium potential level), and the potential of the gate voltage Vg2 is low. It is in a potential (low potential level) state. At this time, the capacitor C1 and the capacitor C2 are electrically disconnected. Based on the state shown in FIG. 3B, the capacitor C1 is reset.

  Thereafter, at time t4, the drain voltage Vd of the MOS transistor Q1 is set to a high voltage (VdH).

  The above state is shown in FIG. In FIG. 3C, the level of the drain voltage Vd is in a high potential side state, the potential of the gate voltage Vg1 is in an intermediate potential state (Medium potential level), and the potential of the gate voltage Vg2 is low. It is in a potential (low potential level) state. At this time, the capacitor C1 and the capacitor C2 are electrically disconnected, and the potential difference (state ST11) is set so that the potential of the capacitor C1 is higher than the potential of the capacitor C2.

  Thereafter, when a predetermined time (t5-t4) has passed, the gate voltage Vg1 of the MOS transistor Q1 is set to a low voltage (Vg1L) at time t5.

  In the above, VdH and Vg1M are set so as to satisfy the relationship of “Vg1M−VdH <Vth1 and Vg1M−VdL> Vth1, where“ Vth1 ”is the threshold voltage of the MOS transistor Q1”. Yes. In other words, the intermediate gate voltage value Vg1M of the MOS transistor Q1 is set so as not to exceed the voltage value obtained by adding the threshold voltage of the MOS transistor Q1 to the drain voltage VdH of the MOS transistor Q1. .

  FIG. 3D shows a state in the middle of changing the gate voltage Vg1 of the MOS transistor Q1 to a low voltage (Vg1L). An arrow AR1 indicates the direction of change of the gate voltage Vg1. Others are the same as the state of (C) of FIG. By changing the gate voltage Vg1 as indicated by the arrow AR1, linear-logarithmic characteristics based on the MOS transistor Q1 are realized.

  Thus, the initial setting (initialization) of the optical sensor circuit 10 is completed.

  Then, based on said state, fixed exposure time (t4-t6) passes and exposure is performed (state ST3). During the exposure time (t4 to t6), the sensor current flowing through the photodiode PD is stored as a charge in the capacitor C1.

  After the exposure time has elapsed, the gate voltage Vg2 of the MOS transistor Q4 is set to an intermediate voltage (Vg2M) for a predetermined time (t6 to t7).

  In the above, Vg1M and Vg2M are set so as to satisfy the magnitude relationship of “Vg1M <Vg2M <Vg1M + Vth2, where“ Vth2 ”is the threshold voltage of the MOS transistor Q4”.

  By the voltage control described above, the charge stored in the capacitor C1 based on the exposure is transferred to the capacitor C2 at time intervals t6 to t7, and the charge is stored in the capacitor C2 (state ST4).

  Thereafter, the gate voltage Vg is set to a low voltage (Vg2L), the MOS transistor Q4 is turned off, the capacitor C2 is opened, and the terminal voltage of the capacitor C2 is taken out as a sensor output signal.

  The above series of operations is periodically repeated at a predetermined timing.

  Next, with reference to FIG. 6 to FIG. 8 and the like, operations in the optical sensor circuit 10 after the time point t4, that is, after the start of exposure will be described.

  FIG. 6 shows the relationship between the intermediate gate voltage value Vg1M and threshold voltage Vth1 of the MOS transistor Q1 and the terminal voltage VC1 of the photodiode PD.

  As shown in the left block 21 of FIG. 6, immediately after the time point t4, the terminal voltage VC1 of the photodiode PD is equal to the threshold voltage of the MOS transistor Q1 with respect to the intermediate gate voltage value Vg1M of the MOS transistor Q1. The voltage rises rapidly at a speed of nanosecond order or less so that the voltage becomes lower by a potential difference corresponding to Vth1.

  Thereafter, as time further elapses, the terminal voltage VC1 of the photodiode PD increases as shown in the right block 22 of FIG. 6, and the intermediate gate voltage value Vg1M of the MOS transistor Q1 and the terminal of the photodiode PD are increased. The voltage difference with the voltage VC1 is smaller than the threshold voltage Vth1 of the MOS transistor Q1. The terminal voltage VC1 of the photodiode PD rises because the channel impedance of the MOS transistor Q1 becomes high and a subthreshold current flows.

  As described above, the intermediate gate voltage value Vg1M of the MOS transistor Q1 is switched to the lower gate voltage value Vg1L at time t5 when the subthreshold current flows and has transient characteristics.

  The interval between time t4 and time t5 is preferably set to a time on the order of about microseconds. By setting the time interval in this way, the terminal voltage VC1 of the photodiode PD reaches the state in which the subthreshold current is flowing.

  The purpose of setting the difference between the intermediate gate voltage value Vg1M and the high drain voltage VdH to be smaller than the threshold voltage Vth1 of the MOS transistor Q1 is that the photodiode is in a state where such a subthreshold current flows. This is for setting the terminal voltage VC1 of the PD. Furthermore, the purpose of setting the gate voltage Vg1M of the MOS transistor Q1 to the low voltage Vg1L at the time t5 is to set the potential difference (W) shown below to be large.

W = VC1- (Vg1L-Vth)
Here, VC1: terminal voltage of the photodiode PD
Vg1L: gate voltage of the MOS transistor Q1
Vth1: threshold voltage of MOS transistor Q1

  That is, this is because the terminal voltage (VC1) of the photodiode PD is set higher than a voltage lower than the gate voltage (Vg1L) by the threshold voltage (Vth1).

  As described above, by setting the potential difference W to be high, the gate of the MOS transistor Q1 can be turned off. As a result, at the time of exposure at low illuminance, the parasitic capacitance of the photodiode has a photoelectric conversion charge. Accumulation is performed, and the terminal potential (VC1) of the photodiode PD varies linearly. Such a range in which the potential varies linearly is referred to as a “linear output region”. This state is shown in FIG. In FIG. 4A, an arrow AR2 indicates an increase in the charge stored in the capacitor C1. The amount of charge stored in the capacitor C1 does not exceed the gate potential Vg1L. At the time of exposure, at high illuminance, the gate of the MOS transistor Q1 is turned on and operates at the sub-threshold value. The photoelectrically converted charge flows through the MOS transistor Q1, and the terminal potential of the photodiode PD is logarithmic. Output characteristics are shown. Such a range in which the potential varies logarithmically is referred to as a “logarithmic output region”. This state is shown in FIG. In FIG. 4B, an arrow AR3 indicates a state where the amount of charge stored in the capacitor C1 exceeds the gate potential Vg1L and overflows to the drain side.

  In the above, the linear output region can be increased by increasing the potential difference W. The reason for this will be described in detail below with reference to FIG.

  FIG. 7 shows the relationship between the gate voltage Vg1 of the MOS transistor Q1 and the threshold voltage Vth1, and the relationship between the terminal voltage VC1 of the photodiode PD. By reducing the gate voltage Vg1, the relationship between the gate voltage Vg1 and the threshold voltage Vth1 can be changed while maintaining the terminal voltage VC1 of the photodiode PD. That is, the above-described W shown as a specific range in FIG. 7, that is, the potential difference W can be changed.

  In FIG. 7, the change from the potential relationship shown on the left side in the drawing to the potential relationship shown on the right side in the drawing in which the gate voltage Vg1 is lowered by ΔVg from the intermediate gate voltage value Vg1M to a low gate voltage value Vg1L. Show. As a result, the range W (High) (= VC1− (Vg1M−Vth1)) based on the potential relationship on the left side changes to the range W (Low) (= VC1− (Vg1L−Vth1)) based on the potential relationship on the right side. . Here, there is a relationship of VgL = Vg1M−ΔVg with respect to the gate voltage Vg1. As a result, a relationship of W (Low)> W (High) is obtained. Thus, the range (potential difference) W can be increased by changing the gate voltage Vg1 by ΔVg from the intermediate gate voltage value Vg1M to the low gate voltage value Vg1L.

  FIG. 8 shows the relationship between the low gate voltage value Vg1L of the MOS transistor Q1 and the threshold voltage Vth1, the terminal voltage VC1 of the photodiode PD, the range of linear output characteristics, and the like. In FIG. 8, a range 23 indicates a linear output region, and a range 24 indicates a logarithmic output region. A boundary point 25 between the linear output region 23 and the logarithmic output region 24 is a change point.

  As shown in FIG. 8, since the terminal voltage VC1 of the photodiode PD can be set to the potential of an arbitrary linear output region 23, an image sensor (imaging region) composed of a plurality of pixels like a two-dimensional MOS image sensor. When applied to the above, it is effective for suppressing variations in the output of the optical sensor circuit caused by variations in the threshold voltage of each pixel of the MOS transistor.

  Furthermore, with reference to FIGS. 9-11, the aspect which suppresses the dispersion | variation in the output between the two photosensor circuits (pixel) A and B as an example is demonstrated here.

  As shown in FIG. 9, after the operation at time t4, in each of the optical sensor circuits A and B, the terminal voltage VC1 of the photodiode PD described above is relative to the set gate voltage of the MOS transistor Q1. The voltage rapidly rises to a voltage lower by a potential difference corresponding to the threshold voltage Vth1 of the MOS transistor Q1 at a speed of nanosecond order or less. At this time, since the threshold voltage Vth1 of the MOS transistor Q1 varies between the photosensor circuits A and B, the terminal voltage VC1 differs between the photosensor circuits A and B. That is, as indicated by the blocks 26 and 27 in FIG. 6, the terminal voltage of the optical sensor circuit A is VC1A, and the terminal voltage of the optical sensor circuit B is VC1B.

  Thereafter, as time further elapses, the state is as shown in FIG. That is, in each of the optical sensor circuits A and B in the same blocks 26 and 27 in FIG. 10, as the terminal voltage potential (VC1A, VC1B) of the photodiode PD increases, the high gate voltage value Vg1M of the MOS transistor Q1 increases. The potential difference from the terminal voltage of the photodiode PD is equal to or less than the threshold voltage (Vth1A, Vth1B) of the MOS transistor Q1. Since the channel impedance of the MOS transistor Q1 becomes high, a sub-threshold current is caused to flow, whereby the potential (VC1A, VC1B) of the terminal voltage of the photodiode PD rises.

  In this way, when the gate voltage value Vg1M of the MOS transistor Q1 is switched and set to a low gate voltage value Vg1L in a state where the subthreshold current flows and has a transient characteristic, the result is as shown in FIG. That is, in the two photosensor circuits A and B, the potential difference ΔW (= W (Low) −W (High)) between W (Low) and W (High) described above is an intermediate gate voltage of the MOS transistor Q1. Since it is set by the difference (ΔVg) between the value Vg1M and the low gate voltage value VgL, the potential difference does not depend on the variation of the threshold voltage of the MOS transistor Q1 constituting each of the photosensor circuits A and B. Therefore, in the different optical sensor circuits A and B, the potential differences ΔW (= W (Low) −W (High)) are the same.

  As described above, since the potential difference ΔW can be arbitrarily set, the range and logarithm indicating the linear output characteristic region with respect to the terminal voltage VC1 of the photodiode PD that is the sensor detection potential in the dark state of each photosensor circuit (pixel). The potential of the terminal, which is the changing point between the ranges indicating the output characteristic area, can be arbitrarily set, and both ranges can be arbitrarily controlled, thereby varying the output variation between the photosensor circuits (pixels). Can be eliminated.

  After the initial setting and exposure described above, after the elapse of a predetermined time, the charge is transferred from the capacitor C1 to the capacitor C2 as described above. This state is shown in (A) to (C) of FIG. Based on the relationship of “Vg1M <Vg2M <Vg1M + Vth2”, the gate voltage Vg2 is changed to an intermediate value (Vg1M) as indicated by an arrow AR3. At this time, the transfer gate of the MOS transistor Q4 cannot be completely opened. By doing so, the electric charge stored in the capacitor C1 is transferred to the capacitor C2 as indicated by an arrow AR4. Finally, as shown in FIG. 5C, the potential of the gate voltage Vg2 becomes low (arrow AR5) and becomes a low voltage value (Vg2L).

  Since the potential difference between the potential of the capacitor C1 and the potential of the capacitor C2 is set as shown in the state ST11 ((C) in FIG. 3), the charge is effectively transferred from the capacitor C1 to the capacitor C2. Charge accumulation at C2 can be enhanced, and the charge stored in the capacitor C1 can be effectively utilized. Thereby, the detection sensitivity of the optical sensor circuit 10 can be increased.

  FIG. 12 shows a characteristic pattern of sensor output characteristics obtained by the optical sensor circuit 10. The horizontal axis of FIG. 12 is a logarithmic scale (log). It is possible to arbitrarily switch an intermediate gate voltage value Vg1M of the gate voltage Vg1 of the MOS transistor Q1, and to output a sensor signal in an optimum state corresponding to the photographing conditions. When the difference ΔVg between the gate voltage value Vg1M and the lower gate voltage value Vg1L is changed from “small” to “large”, the sensor output characteristic changes as indicated by an arrow 32.

  Next, modified examples of the optical sensor circuit according to the present invention are shown in FIGS. FIG. 13 shows an optical sensor circuit according to the second embodiment of the present invention, and FIG. 14 shows an optical sensor circuit according to the third embodiment of the present invention.

  The photosensor circuit 20 according to the second embodiment shown in FIG. 13 is provided with a MOS transistor Q2 for amplifying the sensor output voltage with respect to the circuit elements of the photosensor circuit 10 according to the first embodiment. Yes. Elements that are substantially the same as those described in the previous embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

  The MOS transistor Q2 is an amplifying MOS transistor for amplifying the sensor voltage output as the terminal voltage of the capacitor C2.

  In the optical sensor circuit 20, the output terminal of the capacitor C2 or the drain 16d of the MOS transistor Q4 is applied to the gate 41g of the MOS transistor Q2. A drain voltage Vref is supplied from a voltage controller or the like to the drain terminal 42d of the MOS transistor Q2 via a resistor R, and the source 41s is connected to the ground terminal. The sensor output voltage Vout is extracted from the drain 41d of the MOS transistor Q2 in an amplified state.

  In the photosensor circuit 30 according to the third embodiment shown in FIG. 14, a MOS transistor Q3 is attached to the circuit elements of the photosensor circuit 20 according to the second embodiment. In FIG. 14, elements that are substantially the same as those described in the second embodiment are denoted by the same reference numerals.

  The MOS transistor Q3 is an output selection MOS transistor for selectively outputting the voltage signal output from the amplification MOS transistor Q2.

  In this photosensor circuit 30, the drain 41d of the MOS transistor Q2 and the source 51s of the MOS transistor Q3 are connected. A gate voltage Vg3 is supplied to the gate terminal 52g of the MOS transistor Q3. A resistor R is connected to the drain 51d of the MOS transistor Q3, and a voltage Vref is supplied to the other terminal 52d of the resistor R. The sensor output voltage Vout is taken out from the drain 51d of the MOS transistor Q3.

 The voltage waveforms of the gate voltage Vg3 and the voltage Vref are shown in (D) and (E) of FIG. The gate voltage Vg3 is generated between t8 and t9, and the voltage Vref is applied in a constant voltage state at a required level. When the gate voltage Vg3 is turned on, the photosensor circuit is selected and the sensor voltage is output.

  In the optical sensor circuits 20 and 30 configured as described above, as shown in FIG. 14, by giving necessary control signals for driving the respective units, as in the optical sensor circuit 10 of the first embodiment, An electric signal corresponding to the incident light L1 is obtained.

  FIG. 15 shows a configuration example of an image sensor having a rectangular imaging region 71 in which the photosensor circuit 30 shown in FIG. 14 is arranged as a pixel (S) in a two-dimensional matrix as an example. In FIG. 15, block 13 is the voltage controller described above, block 72 is a pixel selection circuit provided in common to each pixel S, and block 73 is a signal selection circuit for sequentially outputting pixel signals of each pixel S. . Voltages Vd, Vg1, and Vg2 are supplied from the voltage controller 13, a voltage Vg3 is supplied from the pixel selection circuit 72, and a voltage Vref is supplied to the terminal 52d.

  In the above description of each embodiment, the MOS type transistor is described as an n-channel type, but it is needless to say that a p-channel type MOS transistor can be used instead.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective configurations are as follows. It is only an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

  The present invention is used as an optical sensor circuit (or pixel) that forms a one-dimensional or two-dimensional image sensor of a MOS image sensor that is an imaging device.

1 is an electric circuit diagram of a first embodiment of an optical sensor circuit according to the present invention. It is a timing waveform diagram which shows the signal state of each part of the optical sensor circuit which concerns on 1st Embodiment (and 3rd Embodiment). It is a potential diagram of each part of the optical sensor circuit at the time of initialization setting. It is a potential diagram of each part of the optical sensor circuit at the time of exposure. It is a potential diagram of each part of the photosensor circuit during charge transfer. It is a figure explaining the relationship between Vg1M, Vth1, and VC1 of the MOS transistor Q1 of the optical sensor circuit according to the first embodiment. It is a figure explaining the relationship between Vg1M, Vth1, and VC1 of the MOS transistor Q1 of the optical sensor circuit according to the first embodiment. It is a figure explaining the relationship between Vg1L, Vth1, VC1, and the linear output range of MOS type transistor Q1 of the optical sensor circuit which concerns on 1st Embodiment. It is a figure explaining the relationship between Vg1M, Vth1, and VC1 of the MOS transistor Q1 of the photosensor circuits A and B according to the first embodiment. It is a figure explaining the relationship between Vg1M, Vth1, and VC1 of the MOS transistor Q1 of the photosensor circuits A and B according to the first embodiment. It is a figure explaining the relationship (after reducing gate voltage (DELTA) Vg) of Vg1M, Vth1, and VC1 of MOS type transistor Q1 of optical sensor circuits A and B concerning a 1st embodiment. It is a graph which shows the change characteristic of the sensor output of the photosensor circuit concerning a 1st embodiment. It is an electric circuit diagram of a second embodiment of the photosensor circuit according to the present invention. It is an electric circuit diagram of 3rd Embodiment of the optical sensor circuit based on this invention. It is an electric circuit diagram which shows the image sensor comprised using the optical sensor circuit which concerns on 3rd Embodiment of this invention. It is an electric circuit diagram of the conventional photosensor circuit which has a linear output characteristic. It is an electrical circuit diagram of a conventional photosensor circuit having logarithmic output characteristics.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Photosensor circuit 13 Voltage controller 14 Timing signal generation part 15 Control means 20 Photosensor circuit 30 Photosensor circuit PD Photodiode C1 Capacitor C2 Capacitor Q1 Conversion MOS type transistor Q2 Amplification MOS type transistor Q3 Output selection MOS type transistor Q4 MOS transistor for charge transfer

Claims (5)

A photoelectric conversion element that converts an optical signal into a current signal;
A first MOS transistor for converting the current signal output from the photoelectric conversion element into a voltage signal having a logarithmic characteristic in a weak inversion state;
A first capacitance element connected to a voltage detection terminal of the photoelectric conversion element;
A second capacitive element for holding the voltage signal;
A second MOS transistor for controlling charge movement between the first capacitive element and the second capacitive element;
Control means for supplying a gate voltage and a drain voltage of the first MOS transistor and the second MOS transistor;
The control means includes
The drain voltage of the first MOS transistor is set to a high voltage value (VdH) for a first predetermined time, and the gate voltage of the first MOS transistor and the gate voltage of the second MOS transistor are respectively set for a second predetermined time. Set to a high voltage value (Vg1H, Vg2H), set a constant potential by controlling charging or discharging of the second capacitance element for integration as an optical signal, and then
The second MOS transistor is turned off to open the second capacitance element, the drain voltage of the first MOS transistor is set to a low voltage (VdL), and the gate of the first MOS transistor is set. Setting the voltage to an intermediate potential (Vg1M), thereby discharging the charge of the first capacitive element;
The drain voltage of the first MOS transistor is set to a high voltage (VdH), and then the gate voltage of the first MOS transistor is set to a low voltage (Vg1L) when a third predetermined time has elapsed, and VdH and Vg1M are set so as to satisfy the relationship of “Vg1M−VdH <Vth1 and Vg1M−VdL> Vth1, where Vth1 is the threshold voltage of the first MOS transistor”.
After a certain exposure time has elapsed, the gate voltage of the second MOS transistor is set to a predetermined voltage (Vg2M) for a fourth predetermined time, and Vg1M <Vg2M <Vg1M + Vth2, where Vth2 is the second MOS Is set so as to satisfy the relationship of “threshold voltage of the transistor”, thereby transferring the charge of the first capacitance element to the second capacitance element,
The second MOS transistor is turned off to open the second capacitance element, and the terminal voltage of the second capacitance element is used as a sensor output signal.
An optical sensor circuit characterized by performing voltage control as described above.   2. The optical sensor circuit according to claim 1, wherein the control means switches the gate intermediate potential (Vg1M) and the low set potential (Vg1L) of the first MOS transistor to an arbitrary voltage.   3. The optical sensor circuit according to claim 1, further comprising a third MOS transistor for amplifying a terminal voltage of the second MOS transistor.   4. The optical sensor circuit according to claim 3, further comprising a fourth MOS type transistor for selectively outputting a voltage signal output from the third MOS type transistor.   5. An image sensor, wherein an imaging region is formed using the photosensor circuit according to claim 1 as one pixel.

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