JP4261514B2 - Burst head detection circuit - Google Patents

Description

  The present invention relates to a station side device of an optical transmission system, and more particularly to a burst head detection circuit for detecting the head of a burst signal from a home side device.

  2. Description of the Related Art Conventionally, as an optical transmission system that enables high-speed data transmission, a passive optical network (hereinafter referred to as PON) system that time-multiplexes a data signal packet for each subscriber is known. FIG. 6 shows the configuration of this PON system. In the PON system, a plurality of home side devices (ONUs) 102-1 to 102-n are connected to one station side device (OLT) 101 via a passive device such as an optical coupler 103. Reference numeral 104 denotes an optical fiber.

  Upstream burst signals (packet data) from the respective home-side devices 102-1 to 102-n are time-multiplexed and reach the station-side device 101. At this time, the transmission distance to the station-side device 101 is the home-side device. Therefore, the optical power when reaching the station-side device 101 is different for each home-side device. FIG. 7 shows burst signals from the respective home-side devices 102-1 to 102-n that reach the station-side device 101. In FIG. 7, 105-1 to 105-n are added to the burst signals from the home side devices 102-1 to 102-n, and 106-1 to 106-n are added to the heads of the burst signals 105-1 to 105-n. It is a preamble.

  FIG. 8 shows a configuration of a conventional receiving circuit of the station side device 101. Reference numeral 100 denotes a light receiving element such as a photodiode that converts the received optical signal into a current and outputs the current. Reference numeral 200 denotes a preamplifier that converts the current output from the light receiving element 100 into a differential voltage by the amplifier 201 and the feedback resistors 202 and 203. A circuit 300 is a limiter amplifier circuit that compensates an offset of an output signal output from the preamplifier circuit 200 by an amplifier 301 and an offset compensation circuit (hereinafter referred to as an AOC circuit) 302. Subsequent to the limiter amplifier circuit 300, a circuit such as a discriminator (not shown) that performs burst signal discrimination and reproduction is provided. Such a station-side device 101 is disclosed in Non-Patent Document 1, for example.

  The preamplifier circuit 200 converts the current output from the light receiving element 100 into a voltage by a transimpedance gain proportional to the values of the feedback resistors 202 and 203 and outputs the voltage. However, when the input current from the light receiving element 100 increases, the amplitude of the output voltage is saturated and waveform distortion occurs. Therefore, in the preamplifier circuit 200, in order to achieve both high sensitivity and high dynamic range characteristics, when the input current increases, the values of the feedback resistors 202 and 203 are decreased to reduce the transimpedance gain, thereby increasing the large current. An output voltage with little distortion is also obtained at the time of input.

  FIG. 9 shows input / output characteristics when the values (RF1, RF2,..., RFn) of the feedback resistors 202 and 203 of the preamplifier circuit 200 are switched. Since the ratio of the output amplitude of the preamplifier circuit 200 to the input current from the light receiving element 100 is the conversion gain, the gain is higher as the slope of the characteristic in FIG. 9 is larger, and is lower as the slope is gentler. As described above, since the gain is proportional to the values of the feedback resistors 202 and 203, a high resistance is used to obtain a high gain, and a low resistance is used to obtain a low gain. In FIG. 9, RF1> RF2>...> RFn.

Saruwatari, Sugawara, Ibe, “Optical receiver for burst signal of 156 Mbps”, IEICE General Conference, Proceedings, 1997, B-10-128

  As described above, in the conventional preamplifier circuit 200, in order to achieve both high sensitivity and a wide dynamic range characteristic, it waits at the maximum gain until the burst signal is received from the home side device, and after receiving the burst signal, The gain is set according to the amplitude of the burst signal. However, since the preamplifier circuit 200 waits at the maximum gain until the burst signal is received, if noise is superimposed in the non-signal period between the burst signals, the noise is amplified at the maximum gain. Therefore, the limiter amplifier circuit There is a possibility that the waveform of the signal output to the discriminator or the like at the rear stage of 300 is disturbed and the circuit at the rear stage malfunctions.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a burst head detection circuit that can detect the head of a burst signal and remove noise in a non-signal period between burst signals. And

The present invention relates to a burst head detection circuit for detecting a head of the burst signal in a receiving circuit for receiving a burst signal, and a high-pass filter that receives the burst signal and a filter output signal that has passed through the high-pass filter. And a hysteresis comparator for detecting a change in the filter output signal exceeding a predetermined threshold.
In the configuration example of the burst head detection circuit according to the present invention, the high-pass filter includes offset adding means for adding an offset to the filter output signal.
Further, in one configuration example of the burst head detection circuit of the present invention, until the head of the burst signal is detected by the hysteresis comparator, the burst signal output to the subsequent circuit is cut off, and the burst signal A switch is provided for outputting the burst signal to a subsequent circuit when the head is detected.
Further, one configuration example of the burst head detection circuit of the present invention further includes a set-reset flip-flop circuit that generates the control signal for the switch from the output signal of the hysteresis comparator.
In the configuration example of the burst head detection circuit according to the present invention, the high-pass filter acquires the burst signal from an output of an amplifier that amplifies the burst signal.
The burst head detection circuit according to an embodiment of the present invention further includes an AOC circuit that compensates for the offset of the burst signal, and resets the AOC circuit at the head of the burst signal based on the output signal of the hysteresis comparator. And an AOC stabilization reset circuit.

  According to the present invention, the burst signal is input to the high-pass filter, and the output signal of the high-pass filter is input to the hysteresis comparator, so that it is affected by the noise superimposed on the no-signal period of the burst signal and the extinction ratio. Therefore, it is possible to accurately detect the head of the burst signal. As a result, according to the present invention, noise in the no-signal period of the burst signal can be easily removed, and malfunction of a circuit such as a subsequent classifier can be prevented.

  Further, in the present invention, by providing an offset adding means for adding an offset to the filter output signal, it is possible to prevent the hysteresis comparator from malfunctioning due to noise during a non-signal period.

  In the present invention, the burst signal output to the subsequent circuit is blocked until the head of the burst signal is detected by the hysteresis comparator, and when the head of the burst signal is detected, the burst signal is transferred to the subsequent circuit. By providing an output switch, noise during a no-signal period can be removed.

  In the present invention, the high-pass filter can easily detect the head of the burst signal by acquiring the burst signal from the output of the amplifier that amplifies the burst signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a limiter amplifier circuit according to an embodiment of the present invention. The limiter amplifier circuit of the present embodiment includes a differential amplifier 1, an AOC circuit 2, a high-pass filter (HPF) 3, a hysteresis comparator (HysComp) 4, a set-reset flip-flop circuit (SR-FF) 5, The switch 6 includes a delay circuit 7, an exclusive OR circuit (EX-OR) 8, and an OR circuit 9. The delay circuit 7 and the EX-OR 8 and OR 9 constitute an AOC stabilization reset circuit.

  Hereinafter, the operation of the limiter amplifier circuit of the present embodiment will be described. FIG. 2 shows signals of respective parts of the limiter amplifier circuit of FIG. The vertical axes in FIGS. 2A to 2I are all voltages, and the horizontal axis is time. 2A is a signal waveform diagram showing the positive phase input signal VIP and the negative phase input signal VIN input to the differential amplifier 1, and FIG. 2B is a positive phase output signal AOP output from the differential amplifier 1. 2C is a signal waveform diagram showing the negative phase output signal AON, FIG. 2C is a signal waveform diagram showing the positive phase output signal HOP and the negative phase output signal HON output from the HPF 3, and FIG. 2D is input from the outside. 2E is a signal waveform diagram showing the output signal HSO of HysComp4, FIG. 2F is a signal waveform diagram showing the output signal FFO of SR-FF5, and FIG. 2 (G) is a signal waveform diagram showing the output signal DO of the delay circuit 7, FIG. 2 (H) is a signal waveform diagram showing the output signal EXO of the EX-OR 8, and FIG. Positive-phase output output to a circuit (not shown) It is a signal waveform diagram showing a No. VOP and the negative phase output signal VON. NP is noise superimposed on the no-signal period of the positive phase input signal VIP, and NN is noise superimposed on the no-signal period of the negative phase input signal VIN.

First, the positive phase input signal VIP output from a preamplifier circuit (not shown) is input to the positive phase input terminal of the differential amplifier 1, and the negative phase input signal VIN output from the preamplifier circuit is input to the negative phase input terminal. Entered.
The differential amplifier 1 amplifies the difference between the positive phase input signal VIP and the negative phase input signal VIN, and outputs the amplification result as a positive phase output signal AOP and a negative phase output signal AON.

  At this time, the AOC circuit 2 detects and holds the maximum value of the positive-phase input signal VIP and the maximum value of the negative-phase input signal VIN, generates an offset compensation signal from these maximum values, and generates the offset compensation signal. By adding to the output of the differential amplifier 1, the offset between the positive phase input signal VIP and the negative phase input signal VIN is removed. The AOC circuit 2 is described in Non-Patent Document 1 described above. In the positive phase input signal VIP and the negative phase input signal VIN shown in FIG. 2A, an offset ΔV1 occurs with respect to the level V1 of the positive phase input and the negative phase input when the differential amplifier 1 is not input. It can be seen that the offset is removed in the normal phase output signal AOP and the reverse phase output signal AON shown in FIG. V2 in FIG. 2B is the level of the positive phase output signal AOP and the negative phase output signal AON when the differential amplifier 1 is not input.

  Next, the HPF 3 removes low frequency components from the normal phase output signal AOP and the negative phase output signal AON output from the differential amplifier 1 and passes only high frequency components necessary for signal transmission. The normal phase output signal HOP and the negative phase output signal HON that have passed through the HPF 3 are as shown in FIG. Here, an offset is added to the positive phase output signal HOP and the negative phase output signal HON that have passed through the HPF 3 with respect to the level V3 of the positive phase input and the negative phase input when HysComp4 is not input. FIG. 3 is a circuit diagram showing one configuration example of the HPF 3, and FIG. 4 is an enlarged signal waveform diagram of FIG.

  The HPF 3 includes capacitors C1 and C2 and resistors R1, R2, R3, and R4 that are offset adding means. When the values of the resistors R1, R2, and R3 are Ra and the value of the resistor R4 is Rb, Rb <Ra. The reason for setting the resistance value in this way will be described later. A general HPF can be constituted by a capacitor C1 with respect to a positive phase input, and can be constituted with a capacitor C2 with respect to a negative phase input. In contrast, in the present embodiment, the above-described offset is added by adding resistors R1, R2, R3, and R4. The reason for adding this offset will be described below.

  As is well known, HysComp4 has improved noise resistance by providing a hysteresis width to the threshold voltage. FIG. 5 shows input / output characteristics of HysComp4. VrefH and VrefL are threshold voltages, and HSW is a hysteresis width. In FIG. 5, the voltage of the positive phase output signal HOP output from the HPF 3 is used as the input voltage. HysComp4 outputs an L level when the input voltage becomes higher than the threshold voltage VrefH, and outputs an H level when the input voltage becomes lower than the threshold voltage VrefL. Note that the input / output characteristics of the negative phase output signal HON are opposite to those in FIG. 5, and HysComp4 outputs an H level when the negative phase output signal HON becomes higher than the threshold voltage VrefH, and the negative phase output signal HON. Is lower than the threshold voltage VrefL, the L level is output.

  HysComp4 is reset when an H-level system reset signal S-Reset as shown in FIG. 2D is input from the outside, and outputs an L level as shown in FIG. The system reset signal S-Reset is a reset signal input from an external circuit (not shown) during a no-signal period between burst signals. HysComp4 reset by the system reset signal S-Reset is an H level signal as shown in FIG. 2 (e) when the positive phase output signal HOP becomes lower than the threshold voltage VrefL at time t1 in FIGS. When HSO is output and the positive phase output signal HOP becomes higher than the threshold voltage VrefH at time t2, the output signal HSO is set to L level.

  In the present embodiment, by providing resistors R1 and R2, offset ΔV2 is added to the positive phase output signal HOP, and by providing resistors R3 and R4, offset ΔV3 is added to the negative phase output signal HON. Thereby, in the present embodiment, the noise NP superimposed on the positive phase output signal HOP is lower than the threshold voltage VrefL, or the noise NN superimposed on the negative phase output signal HON is the threshold voltage VrefH. It is possible to prevent the output signal HSO of HysComp4 from being erroneously set to the H level due to the noises NP and NN.

Furthermore, in this embodiment, when the values of the resistors R1, R2, and R3 are Ra and the value of the resistor R4 is Rb, Rb <Ra is set so that ΔV2 <ΔV3. By setting such an offset, the possibility that the noise NP superimposed on the positive phase output signal HOP becomes lower than the threshold voltage VrefL is further reduced.
With the above configuration, in the present embodiment, the leading 1-bit falling edge of the burst signal can be accurately detected by HysComp4.

  Next, the SR-FF 5 outputs the H-level output signal FFO as shown in FIG. 2F when the H-level system reset signal S-Reset is input to the set input terminal S. When HysComp4 outputs the H level output signal HSO as described above, this signal HSO is input to the reset input terminal R, so that the SR-FF5 is reset and the output signal FFO is set to the L level.

  When the output signal FFO of the SR-FF 5 is at the H level, the switch 6 masks its output and blocks signal output from the differential amplifier 1 to the subsequent circuit. Further, when the output signal FFO of the SR-FF 5 is at the L level, the switch 6 cancels the mask and outputs the normal phase output signal AOP and the negative phase output signal AON output from the differential amplifier 1 as shown in FIG. ) And output as a normal phase output signal VOP and a negative phase output signal VON.

  On the other hand, the delay circuit 7 delays the output signal FFO of the SR-FF 5 by Δt and outputs it as an output signal DO shown in FIG. The EX-OR 8 takes an exclusive OR of the output signal FFO of the SR-FF 5 and the output signal DO of the delay circuit 7 and outputs the result as an output signal EXO shown in FIG. The output signal EXO of this EX-OR8 is input to the AOC circuit 2 as the reset signal Reset through the OR9, and the AOC circuit 2 is reset.

  In the AOC circuit 2, there is a hold circuit that detects and holds the maximum value of the positive-phase input signal VIP and the maximum value of the negative-phase input signal VIN, and a capacitor is used for this hold circuit. If it is always operated, there is a possibility that the AOC circuit 2 malfunctions by detecting the level of noise or the like in the non-signal period. Therefore, in the present embodiment, the AOC circuit 2 is stably operated by discharging the capacitor of the hold circuit at the leading edge of the first bit of the burst signal by the reset signal Reset.

  As described above, in this embodiment, the burst signal is passed through the HPF 3 and the output signal of the HPF 3 is input to the HysComp 4, so that the influence of noise and extinction ratio superimposed on the no-signal period of the burst signal can be reduced. Without falling, it is possible to accurately detect the falling edge of the first bit of the burst signal. In this embodiment, the burst signal output to the subsequent circuit is cut off by the switch 6 until the leading edge of the burst signal is detected from the input of the system reset signal S-Reset. When the leading edge of the first bit is detected, the mask is released and the burst signal is output to the subsequent circuit, so noise during the no-signal period can be removed and the subsequent stage can be identified. Malfunction of a circuit such as a container can be prevented.

Furthermore, in this embodiment, since the burst signal is acquired from the output of the differential amplifier 1 that is easy to detect the signal and is input to the HPF 3, the falling edge of the first bit of the burst signal is easily detected. be able to.
In this embodiment, EX-OR8 is used, but an AND circuit (AND) may be used instead of EX-OR8.

  The present invention can be applied to, for example, a station side device of an optical transmission system.

It is a circuit diagram which shows the structure of the limiter amplifier circuit used as embodiment of this invention. FIG. 2 is a signal waveform diagram showing signals at various parts of the limiter amplifier circuit of FIG. 1. FIG. 2 is a circuit diagram showing one configuration example of a high-pass filter in the limiter amplifier circuit of FIG. 1. FIG. 3 is an enlarged signal waveform diagram of FIG. It is a figure which shows the input-output characteristic of the hysteresis comparator in the limiter amplifier circuit of FIG. It is a block diagram which shows the structure of a PON system. It is a figure which shows the burst signal from each home side apparatus which arrives at a station side apparatus. It is a block diagram which shows the structure of the conventional receiving circuit of the station side apparatus in a PON system. It is a figure which shows the input-output characteristic of the preamplifier circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Differential amplifier, 2 ... AOC circuit, 3 ... High pass filter, 4 ... Hysteresis comparator, 5 ... Set-reset flip-flop circuit, 6 ... Switch, 7 ... Delay circuit, 8 ... Exclusive OR circuit, 9 ... Logical sum Circuit, C1, C2 ... capacitor, R1, R2, R3, R4 ... resistance.

Claims (6)

In a receiving circuit for receiving a burst signal, a burst head detecting circuit for detecting a head of the burst signal,
A high-pass filter that receives the burst signal;
A burst head detection circuit comprising: a hysteresis comparator that receives a filter output signal that has passed through the high-pass filter and detects a change in the filter output signal that exceeds a predetermined threshold value. The burst head detection circuit according to claim 1,
The burst start detection circuit according to claim 1, wherein the high-pass filter includes offset adding means for adding an offset to the filter output signal. The burst head detection circuit according to claim 1,
Further, output of the burst signal to a subsequent circuit is cut off until the head of the burst signal is detected by the hysteresis comparator, and when the head of the burst signal is detected, the burst signal is A burst head detection circuit comprising a switch for outputting to a burst. In the burst head detection circuit according to claim 3,
The burst head detection circuit further comprises a set-reset flip-flop circuit for generating a control signal for the switch from the output signal of the hysteresis comparator. The burst head detection circuit according to claim 1,
The burst head detection circuit, wherein the high-pass filter acquires the burst signal from an output of an amplifier that amplifies the burst signal. The burst head detection circuit according to claim 1,
An AOC circuit for compensating for the offset of the burst signal;
A burst head detection circuit comprising: an AOC stabilization reset circuit that resets the AOC circuit at the head of the burst signal based on an output signal of the hysteresis comparator.

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