JP4127420B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and relates to a technique that is effective when used in a one-chip microcomputer or the like provided with a timing generation circuit that forms a timing signal corresponding to an edge of a clock signal.
[0002]
[Prior art]
In a memory or a digital integrated circuit, a basic clock signal is delayed, and an internal circuit forms a timing signal necessary for operation. An inverter circuit is used as a delay circuit formed in the semiconductor integrated circuit device.
[0003]
[Problems to be solved by the invention]
In the delay circuit using the inverter circuit, the delay time changes corresponding to the fluctuation of the power supply voltage. That is, the power supply voltage of a digital circuit using a semiconductor integrated circuit device generally allows a voltage fluctuation of about ± 10%, and the delay time also fluctuates in response to such a voltage fluctuation. In the timing generation circuit, the timing design is performed in consideration of the worst case in consideration of the fluctuation of the power supply voltage, so that there is a problem that high-speed operation is hindered.
[0004]
An object of the present invention is to provide a semiconductor integrated circuit device including a timing generation circuit that realizes stable operation with low power consumption. Another object of the present invention is to provide a semiconductor integrated circuit device including a timing generation circuit that achieves stable operation while simplifying the circuit. Still another object of the present invention is to provide a semiconductor integrated circuit device provided with a level conversion circuit with a logic function. Still another object of the present invention is to provide a semiconductor integrated circuit device including a timing generation circuit that realizes operation verification with a simple configuration while realizing stable operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0005]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a delay circuit that is operated with a constant voltage made independent of the power supply voltage supplied from the external terminal is combined and a timing signal of a level corresponding to the power supply voltage is generated to control the internal circuit. The timing signal is formed by a level conversion circuit with a logic function that receives the delay signal.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied. Each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
[0007]
The single-chip microcomputer of this embodiment includes a central processing unit CPU, a clock generation circuit CPG, a data transfer controller (data transfer device) DTC, an interrupt controller INT, a read-only memory ROM in which programs are stored, a temporary storage RAM, random access memory RAM used for storage, FEEROM (Flash Electrical Eraseable & Programmable Read Only Memory) used for storage of non-volatile data, timer (ITU), serial communication interface The SCI, A / D (analog / digital) converter, and first to ninth input / output ports IOP1 to IOP9 are functional blocks or functional modules.
[0008]
Each functional block or functional module described above is connected to each other by an internal bus. The internal bus includes a control bus for transmitting a read signal and a write signal in addition to an address bus and a data bus, and may further include a bus size signal (WORD) or a system clock. The functional blocks or functional modules are read / written by the central processing unit CPU or the data transfer controller DTC via the internal bus. Although not particularly limited, the bus width of the internal bus is composed of 16 bits.
[0009]
In the single-chip microcomputer of this embodiment, the ground potential Vss, the power supply voltage Vcc, the analog ground potential AVss, the analog power supply voltage AVcc, the analog reference voltage Vref, and the reset RES as other dedicated control terminals are not particularly limited. , Standby STBY, mode control MD0, MD1, clock input EXTAL, XTAL, etc. are provided.
[0010]
Each input / output port is also used as an input / output terminal of an address bus, data bus, bus control signal or timer, serial communication interface SCI, and A / D converter. That is, the timer, the serial communication interface SCI, and the A / D converter each have input / output signals, and are input / output from / to the outside through a terminal also used as an input / output port.
[0011]
The timer compare match signal, overflow signal, and underflow signal are provided to the A / D converter as a start signal (A / D conversion start trigger). The interrupt signal is output from the A / D converter, timer, and serial communication interface SCI, and the interrupt controller INT receives the interrupt signal and gives an interrupt request signal to the central processing unit CPU based on the designation of a predetermined register or the like. Or whether to give a start request signal to the data transfer controller DTC. Such switching is performed by a predetermined bit of the interrupt controller.
[0012]
As described in “H8 / 3003 Hardware Manual” issued by Hitachi, Ltd. or Japanese Patent Application No. 4-137554, the data transfer device DTC can be used for a plurality of units of data by one activation. The so-called block transfer mode can be transferred. These have a source address register, a destination address register, a block size counter, a block size holding register, and a block transfer counter, and can perform data transfer in units of blocks.
[0013]
FIG. 2 is a schematic block diagram showing an embodiment of the FEEPROM. The X address signal XA is supplied to an X address buffer (X Add Latch) 4 and the address signal fetched here is latched. The Y address signal YA is supplied to a Y address buffer (X Add Counter) 5. Although not particularly limited, the Y address buffer 5 includes a counter and can read stored information for a maximum of one word line in synchronization with a clock signal. A control signal input circuit (Control Signal Input) 6 determines operation modes such as writing, reading, and batch erasing specified by the clock signal CKM and the control signal, and generates a timing signal necessary for the determination.
[0014]
The X address signal taken into the X address buffer 4 is supplied to an X decoder (X Decoder) 2 where it is decoded to select one word line of the memory array 1. Although not particularly limited, the X decoder 2 includes a main word line (SiD) connected to the gate of the selection MOSFET and a word line (connected to the control gate of the storage transistor) in each of the write operation, the erase operation, and the read operation. Word line) and a source selection line (SiS) selection signal corresponding to the main word line (SiD) are formed. Since the potentials of these selection signals vary depending on each mode, an output circuit that outputs a voltage selection / non-selection level corresponding to the operation mode is provided. A voltage necessary for these operation modes is formed by an internal voltage generation circuit (Internal Voltage) 8.
[0015]
In the memory array, a memory transistor in which a control gate and a floating gate are stacked is provided at an intersection between a word line and a data line. A data line to which the drain of the storage transistor is connected is connected to a main data line (Global Bit Line) through the selection MOSFET. Although not particularly limited, the data line is connected to the drains of a plurality of storage transistors via the selection MOSFET. Similarly, the sources of the storage transistors constituting these one block are connected to a common source line (Common Source Line) via a selection MOSFET.
[0016]
The main data line selected by the column switch is connected to the input of the sense amplifier. As will be described later, the sense amplifier uses the high level / low level read to the main data line to which the selected memory cell is connected as the reference voltage based on the precharge potential of the unselected main data line to which the memory cell is not connected. Sense. A latch circuit is provided at the output of the sense amplifier, and the sense output is held in the latch circuit.
[0017]
The column switch (Y Gate) 5 connects the two main data lines to the input / output terminals of the sense amplifier by a selection signal formed by decoding the address signal formed by the Y address buffer 5. A Y decoder that forms the selection signal is included in the column switch 5. The Y address buffer 5 can take a designated address signal as a head value, generate an address signal synchronized with the clock signal CLM by a counter, and perform a continuous read operation. The data terminal D is used for inputting and outputting data consisting of a plurality of bits. The signal is decoded by the control logic circuit included in the control signal input circuit 6, and the timing signal and potential setting necessary for the operation are performed by the control logic circuit. The control signal input circuit 6 includes a timing generation circuit using a delay circuit as will be described later.
[0018]
FIG. 3 is a block diagram for explaining the read operation of the FEEPROM. In FIG. 2A, a pair of data lines D and / D, word lines WL1 and WL2, memory cells MC1 and MC2, and sense amplifiers are shown as representatives. Therefore, the data line, source line selection MOSFET, main data line, column switch, and the like shown in FIG. 2 are omitted.
[0019]
The memory cell MC1 and the like have a large threshold voltage with respect to the selection level of the word line by performing writing and erasing by injecting or discharging the charge of the floating gate, and a small threshold voltage. Have to have. For example, when the read signal is obtained from the memory cell MC1 to the data line D by setting the word line WL1 to the selection level, the data line / D paired with the read signal is also selected by the column switch. Then, the read current source corresponding to the selected data line D is activated by the signal R1, and the read current is injected. As a result, if the threshold voltage of the memory cell MC1 is smaller than the selected level of the word line WL1, the data line D is kept at the precharge voltage regardless of the supply of the read current. Changes to a low level.
[0020]
On the other hand, if the threshold voltage of the memory cell MC1 is larger than the selection level of the word line WL1, and it is in an off state, the read current is supplied to change to a high level with respect to the precharge voltage. At this time, the read current source is deactivated by the signal R2 to the data line / D, and the data line / D is maintained at the precharge potential. As a result, the high level / low level of the selected data line D changes with reference to the precharge voltage of the data line / D, and two singles that are activated by the sense amplifier active signal (CT2). Amplified by an end differential amplifier circuit.
[0021]
The data lines D and / D are provided with precharge MOSFETs Q1 and Q2, and the data lines D and / D are precharged to the power supply voltage VCC side by a precharge signal (CT1). The data lines D and / D are provided with discharge MOSFETs Q3 and Q4, and the data lines D and / D are discharged to the circuit ground potential by a discharge signal (CT3).
[0022]
As shown in FIG. 5B, the discharge signal CT3 changes from the high level to the low level, the MOSFETs Q3 and Q4 are turned off and the precharge operation ends, and the precharge signal CT1 changes from the low level to the high level. The level is changed to turn on the MOSFETs Q1 and Q2. As a result, the data lines D and / D change from a discharge level such as a circuit ground potential to a precharge level corresponding to the power supply voltage VCC.
[0023]
The precharge signal CT1 changes from the high level to the low level, the precharge operation is completed, and the sense amplifier active signal CT2 changes from the low level to the high level to activate the sense amplifier. At the same time, since the current flows through the selected data line D, a potential difference corresponding to the stored information of the memory cell MC1 as described above is generated on the data lines D and / D, and this is sensed. The amplifier amplifies.
[0024]
In the amplification operation of the sense amplifier, if the operation period of the sense amplifier is lengthened so that the current Id continues to flow, a 2 × Id direct current continues to flow during this period to increase power consumption. Therefore, in this embodiment, the operation period of the sense amplifier is a period during which the sense amplifier active signal CT2 is at a high level so that the operation is terminated when an amplified signal necessary for the operation of the output side latch circuit LCH is obtained. To control. After the sense amplifier active signal CT2 is set to the low level, the decharge signal CT3 is set to the high level to discharge the data lines D and / D to a low level such as the ground potential of the circuit. The latch circuit LCH performs a latch operation in response to the timing signal CT4, and captures and holds the output of the sense amplifier at the timing when the latch circuit LCH is set to the high level.
[0025]
The erase operation of the memory cell MC1 and the like is performed in units of blocks divided by the selection MOSFET, and a high voltage of about 10 V is applied to the word lines WL1 and WL2 and the like in the block to form the memory cell MC1 and the like. A negative voltage such as −9 V is applied to the P-type well potential and the source. As a result, a tunnel current is passed from the P-type well to the floating gate to inject charges and raise the threshold voltage. At this time, the memory cell is turned on by 10 V of the word line WL1, and the selection MOSFET is turned off to prevent the negative voltage of the source from being transmitted to the main bit line, and the block to be erased. The negative voltage is applied only to the memory cells. This eliminates unwanted stress on the memory cells of the non-erased block.
[0026]
In the write operation, a negative voltage such as −9V is applied to the word line WL1, and the potential of the unselected word line is set to 0V. A voltage of 6 V is applied to the data line to which the memory cell to be written is connected, and the threshold voltage is lowered by discharging the charge accumulated in the floating gate to the drain by the tunnel current. The unselected data line is opened or grounded so that the tunnel current is not generated.
[0027]
FIG. 4 is a block diagram showing an embodiment of the timing generation circuit according to the present invention. The timing generation circuit shown in FIG. 3 includes a first timing generation circuit and a second timing generation circuit, and the second timing generation circuit allows the precharge signal CT1 and the sense amplifier active signal CT2 shown in FIG. And a discharge signal CT3.
[0028]
In this embodiment, in order to prevent the timing signals CT1 to CT3 from being affected by the above-described fluctuations in the power supply voltage, in other words, necessary operations while achieving high speed operation and low power consumption. In order to ensure a margin, the delay circuits DL1 to DL3 constituting the first timing generation circuit have ± 10% of the operating voltage centered on the power supply voltage VCC supplied from the external terminal, for example, 3.3V or 3V. The power supply voltage VCC is operated by an internal clamp voltage that is stepped down to, for example, about 2.5 V so that the delay time is not affected by fluctuations of 2.7 V to 3.6 V that allow for a fluctuation range of 2.7 V to 3.6 V. On the other hand, the power supply for the precharge circuit and the sense amplifier uses an external power supply voltage in consideration of its supply capability.
[0029]
The control circuit CONT determines the operation mode based on the control signal. If the operation mode is determined to be the read mode, the control circuit CONT opens the gate and transmits the clock signal CKM to the inputs of the delay circuits DL1 to DL3 formed in series. Although not particularly limited, the gate is also operated by the internal clamp voltage. The inputs N1 of the delay circuits DL1 to DL3 and the delay signals N2 to N4 are transmitted to level conversion circuits LOGC1 & LVC to LOGC3 & LVC having a logical function constituting the second timing generation circuit. The level conversion circuits LOGC1 & LVC to LOGC3 & LVC having these logic functions receive the delay signals N1 to N4 having signal levels corresponding to the constant voltage, and correspond to the precharge operation, the sense amplifier operation and the discharge operation, and The timing signals CT1 to CT3 are formed by converting into signal levels corresponding to the precharge circuit, sense amplifier and discharge circuit operating with the power supply voltage VCC.
[0030]
Although not particularly limited, the delay circuits DL1 to DL3 include a control terminal c, and the delay time is switched by a control signal supplied from the control circuit CONT to the control terminal c. Although not particularly limited, the operation mode is a test mode for verifying the operation margin of the internal circuit, and the timing margin of each of the timing signals CT1 to CT3 is set to a stricter condition by supplying the control signal. It is used for verifying operation margins of the charge circuit, sense amplifier and discharge circuit.
[0031]
FIG. 5 is a waveform diagram for explaining the operation of the timing generation circuit. FIG. 4A shows a case where the clock signal CKM is set to a high frequency such as 60 MHz, and FIG. 5B shows a case where the clock signal CKM is set to a relatively low frequency such as 30 MHz. Yes.
[0032]
Memory cell access is instructed by the low level of the memory select signal / MS, and the word line WL is selected in response to the high level of the clock signal CKM. With the rising edge of the clock signal CKM as a reference, the timing generation circuit starts the precharge operation by changing the timing signal CT1 from the low level to the high level after 3 ns. At the same time, the timing signal CT3 is set to a low level to end the discharge operation. Therefore, the data lines D and / D are precharged so as to rise at the same level from the circuit ground potential toward the power supply voltage VCC.
[0033]
After 5 ns with the rising edge of the clock signal CKM as a reference, the timing signal CT4 is set to low level to release the latch operation. As a result, the latch operation of the latch circuit is released and the amplified signal can be taken from the sense amplifier. The timing signal CT1 is changed to a low level after 6 ns with reference to the rising edge of the clock signal CKM, and the precharge operation is terminated. Although not shown, the supply of the read current is started to the selected data line before and after the end of the precharge operation.
[0034]
The timing signal CT2 is set to the high level after 7 ns with the rising edge of the clock signal CKM as a reference, and the sense amplifier is activated. At this timing, the sense amplifier starts its operation and amplifies the level difference between the data lines D and / D as described above. The timing signals CT3 and CT4 are set to high level after 14 ns with respect to the rising edge of the clock signal CKM, and the discharge operation and the latch operation are started. Then, after 15 ns with respect to the rising edge of the clock signal CKM, the timing signal CT2 is set to the low level to stop the operation of the sense amplifier, and the current 2 × Id is stopped from flowing there.
[0035]
In the above series of operations, even if the frequency of the clock signal CKM is slowed down to 30 MHz, which is 1/2, as shown in FIG. 5B, the same time is set with reference to the rising edge of the clock signal CKM. Thus, each circuit performs the same operation as described above. Thus, for example, when timing control is performed such that the sense amplifier is activated by the clock signal CKM, it is consumed by the sense amplifier in the above example corresponding to the operating frequency of the clock signal CKM. The current increases twice. On the other hand, when each operation timing is controlled at a fixed time in synchronization with the edge of the clock signal CKM as described above, only a necessary period can be consumed without depending on the frequency of the clock signal CKM. It will be a thing.
[0036]
In addition, in this embodiment, since the delay circuit for performing the timing setting is operated with a constant voltage obtained by stepping down the power supply voltage VCC, it is not affected by fluctuations in the power supply voltage or the power supply voltage of the system in which it is mounted. Therefore, it is possible to control the operation at the optimal timing corresponding to the read signal amount of the memory cell and the sensitivity of the sense amplifier as described above, and it is not necessary to set an extra time margin in consideration of the voltage fluctuation. The frequency can be increased. In other words, a high-speed read operation is enabled.
[0037]
FIG. 6 shows a configuration diagram of an embodiment of a level conversion circuit with logic function LOG1 & LVC included in the timing generation circuit. This circuit forms a timing signal that responds only to the rising edge of the clock signal CKM. A specific circuit is shown in FIG. FIG. 5B shows timing waveforms for explaining the operation. The input signal N1 and its inverted signal N1N are the first signal, and the delayed signal N2 delayed by the delay circuit DL1 and its inverted signal N2N are the second signal. These two signals are combined to form an output signal OUT having a pulse width corresponding to the rising edge of the first signal and corresponding to the delay time of the delay circuit DL1.
[0038]
In order to realize the logic function as described above, the input signal N1 and its inverted delay signal N2N are supplied to a NAND gate circuit. That is, the input signal N1 is supplied to the gates of the P-channel MOSFET Q10 and the N-channel MOSFET Q15, and the inverted delay signal N2N is supplied to the gates of the P-channel MOSFET Q12 and the N-channel MOSFET Q14. The N-channel MOSFETs Q14 and Q15 are connected in series, and the P-channel MOSFETs Q10 and Q12 are connected in a substantially parallel configuration to form a NAND gate.
[0039]
In this embodiment, in order to add a level conversion function, a P-channel MOSFET Q11 is inserted in series between the P-channel MOSFET Q10 that receives the input signal N1 and the output node A. The inverted input signal N1N is supplied to the gate of the N-channel MOSFET Q16 whose source is connected to the ground potential, and is supplied to the gate of the P-channel MOSFET Q13 provided between the drain and the power supply voltage VCC. A signal at the output node A of the NAND gate circuit is supplied. The signal at the output node B of the MOSFETs Q13 and Q16 is supplied to the gate of the P-channel MOSFET Q11. As a result, the level conversion operation is performed by making the two circuits into a latch form.
[0040]
When the input signal N1 becomes high level, the N-channel MOSFET Q15 is turned on, and the N-channel MOSFET Q16 is turned off by the low level of the inverted signal N1N. At this time, since the inverted delay signal N1DN is at a high level, the N-channel MOSFET Q14 is in an on state, so that the output node A changes to a low level corresponding to the on state of the MOSFET Q15.
[0041]
As the output node A changes to the low level, the P-channel MOSFET Q13 is turned on, and the output node B is raised to the high level up to the voltage VCC. Therefore, the P-channel type MOSFET Q11 is cut off. As a result, since the input signal N1 is a constant voltage equal to or lower than the power supply voltage VCC, even if the P-channel type MOSFET Q10 is turned on weekly, a direct current does not flow through the paths of the MOSFETs Q10, Q11 and Q14 and Q15. A low level such as the ground potential of the circuit can be formed.
[0042]
When the inverted delay signal N1DN changes to the low level with a delay, the N-channel MOSFET Q14 is turned off and the P-channel MOSFET Q12 is turned on. As a result, the node A changes from a low level to a high level corresponding to the voltage VCC. In response to the output node A changing to a high level such as the power supply voltage VCC, the P-channel MOSFET Q13 is cut off. Therefore, the output node B maintains the high level in a high impedance (floating) state. Therefore, the off state of the P-channel MOSFET Q11 is maintained.
[0043]
Thereafter, when the input signal N1 changes to a low level and the inverted signal N1N changes to a high level, the N-channel MOSFET Q16 is turned on and the output node B is set to a low level. As a result, the P-channel MOSFET Q11 is turned on to operate as a two-input NAND gate circuit. However, the inverted input signal N1DN goes high with a delay from the low level of the input signal N1. Therefore, the output node A is maintained at a high level like the power supply voltage VCC by the P channel type MOSFETs Q10 and Q11. The signal at the node A is inverted through a MOSFET inverter circuit that also operates at the power supply voltage VCC, and is output as an output signal OUT (CT1).
[0044]
With this configuration, a timing signal having a pulse width corresponding to the delay time can be formed. Moreover, even if the input signal N1, its delay signal N2, etc. have a small amplitude corresponding to the internal clamp voltage, an output signal whose level is converted to the power supply voltage VCC as described above can be formed. That is, the variation in delay time and the number of circuit elements can be reduced as compared with the case where a similar circuit function is realized by combining the NAND gate circuit and the level conversion circuit as described above.
[0045]
FIG. 7 shows a configuration diagram of an embodiment of a level conversion circuit with logic function LOG2 & LVC included in the timing generation circuit. In this circuit, a pulse signal having a constant pulse width is formed like the sense amplifier active signal. A specific circuit is shown in FIG. FIG. 5B shows timing waveforms for explaining the operation. The input signal N2 and its inverted delay signal N2DN are the first signal, and the delay signal N3 delayed by the delay time set by the delay circuit and its inverted delay signal N3DN are the second signal. The inverted delay signals N2DN and N3DN are delay signals formed from the middle of the inverter circuit provided in the delay circuit or the next-stage delay circuit. These four signals are combined to form an output signal OUT having a pulse width corresponding to the phase difference between the first signal and the second signal, that is, the delay time of the delay circuit.
[0046]
In order to realize the logic function as described above, the input signal N2 and its inverted delay signal N2DN are supplied to a NAND gate circuit. That is, the input signal N2 is supplied to the gates of the P-channel MOSFET Q21 and the N-channel MOSFET Q27, and the inverted delay signal N2DN is supplied to the gates of the P-channel MOSFET Q20 and the N-channel MOSFET Q26. The N-channel MOSFETs Q26 and Q27 are connected in series, and the P-channel MOSFETs Q20 and Q21 are connected in parallel to form a NAND gate configuration.
[0047]
Similarly, the delay signal N3 and its inverted delay signal N3DN are also supplied to the NAND gate circuit. That is, the delay signal N3 is supplied to the gates of the P-channel MOSFET Q24 and the N-channel MOSFET Q30, and the inverted delay signal N3DN is supplied to the gates of the P-channel MOSFET Q23 and the N-channel MOSFET Q29. The N-channel MOSFETs Q29 and Q30 are connected in series, and the P-channel MOSFETs Q23 and Q24 are connected in parallel to form a NAND gate configuration.
[0048]
In order to provide a level conversion function, the P-channel MOSFETs Q22 and Q25 are provided in the P-channel MOSFET and the output nodes A and B in the two NAND gate circuits, and the ground potential of the output node and the circuit is N-channel MOSFETs Q28 and Q31 are provided. The gates of the P-channel MOSFET Q22 and N-channel MOSFET Q28, and the P-channel MOSFET Q25 and N-channel MOSFET Q31 are shared, and the signals of the other output nodes B and A are supplied to each other. An N-channel MOSFET Q32 for initial setting is provided between the output node B and the circuit ground potential, and the output node B is reset to the circuit ground potential by the signal i3 generated when the power is turned on. .
[0049]
As described above, in the initial state where the output node A is at the high level and the output node B is at the low level, the P-channel MOSFET Q22 on the output node A side is turned on, and the P-channel MOSFET Q25 on the output node B side is turned off. Is done. That is, the output node A is set to a high level like the power supply voltage VCC by the P-channel MOSFET Q20 which is turned on by the low level of the input signal N2DN, and the P-channel MOSFET Q25 is turned off.
[0050]
When the input signal N2 becomes high level, the N-channel MOSFET 15 is turned on, and a current path is formed by the N-channel MOSFET Q26 turned on by the high level of the inverted signal N2DN, and the output node A is set to high level. To low level. At this time, the output node A changes to the high level through the P channel MOSFET Q24 which is turned on by the low level of the delay signal N3 due to the change of the output node A to the low level and the P channel MOSFET Q25 being turned on. That is, the output node A and the output node B are switched to high level and low level at high speed by the positive feedback loop in the latch circuit as described above. The inversion delay signal N2DN becomes low level after a delay, and the N-channel MOSFET Q26 is turned off and the P-channel MOSFET Q20 is turned on. However, the output nodes A and B do not change.
[0051]
When the input signal N3 becomes high level after a delay time, the N-channel MOSFET 30 is turned on, and a current path is formed by the N-channel MOSFET Q29 that is turned on by the high level of the inverted signal N3DN. Node B is changed from high level to low level. At this time, the P node MOSFET Q22 is turned on by the change of the output node B to the low level, and the output node A is changed to the high level through the P channel MOSFET Q20 which is turned on by the low level of the signal N2DN. That is, the output node A and the output node B are switched between a high level and a low level at high speed by a positive feedback loop in the latch circuit as described above. The inversion delay signal N3DN becomes low level with a delay, and the N-channel MOSFET Q29 is turned off and the P-channel MOSFET Q23 is turned on. However, the output nodes A and B are not changed.
[0052]
As described above, the inverted delayed signals N2DN and N3DN are switched by the latch circuit at a high speed by changing the signals N2 and N3 to the high level, and the input signals N2, N2DN are switched by the switching operation of the latch circuit. In addition, a steady DC current is prevented from flowing between the P-channel MOSFET and the N-channel MOSFET that are turned on in a weekly manner due to the high levels of N3 and N3DN.
[0053]
FIG. 8 shows a circuit diagram of an embodiment of the delay circuit. FIG. 2A shows a unit circuit having a fixed delay time, in which CMOS inverter circuits N3 and N4 are connected in cascade, and a capacitor C1 for adjusting the delay amount is provided therebetween. (B) shows a unit circuit having a variable delay time. In the figure, a MOSFET Q that is switch-controlled by a control signal c is provided between the CMOS inverter circuits N5 and N6 similar to the above, and the capacitor C2 similar to the above is selectively connected. That is, when the switch MOSFETQ is turned on and the capacitor C2 is connected, a larger delay amount can be obtained than when the switch MOSFETQ is turned off.
[0054]
The delay circuits DL1 to DL3 are configured by combining FIGS. 8A and 8B. Then, when the test mode is set by the control circuit CONT in FIG. 4, the control signal c is generated, and the switch MOSFET in FIG. The read operation is performed with strict operating conditions such as shortening the delay time to be set or shortening the delay time to set the time difference between the timing signals CT1 and CT2. By performing the test under such severe conditions, the operation is guaranteed in the actual memory operation.
[0055]
The effects obtained from the above embodiment are as follows.
(1) By combining a delay circuit that is operated with a constant voltage made independent of the power supply voltage supplied from the external terminal and generating a timing signal at a level corresponding to the power supply voltage to control the internal circuit, There is an effect that a stable operation with power consumption can be realized.
[0056]
(2) A memory array including a plurality of memory cells in which memory cells are arranged in matrix at intersections of a plurality of word lines and a plurality of data lines, a precharge circuit for precharging the data lines, and the data lines The timing signal controls the operation period of the precharge circuit and the sense amplifier based on the rising or falling edge of a predetermined clock signal. As a result, it is possible to obtain the effects of low power consumption that does not depend on the operating frequency, high speed operation that does not depend on the power supply voltage, and a stable operating margin.
[0057]
(3) By setting the frequency of the clock signal in accordance with the application, it is possible to achieve an effect of realizing low power consumption in the sense amplifier while expanding the application.
[0058]
(4) The delay circuit has a function of switching a delay time according to a control signal, and this function can be used for verification of circuit operation, so that a highly reliable operation can be ensured. Returned.
[0059]
(5) The precharge supply power supply and the sense amplifier power supply use an external supply power supply having a high current supply capability, so that an effect of ensuring a more reliable operation can be obtained.
[0060]
(6) A first input signal is supplied to the gate, and a first P-channel MOSFET and a first N-channel provided between the first output node and the power supply voltage and between the output node and the ground potential of the circuit, respectively. And a second N-channel MOSFET provided between the second output node and the ground potential of the circuit, the power supply voltage and the first Between the output node and between the first output node and the circuit ground potential, the first P-channel MOSFET and the first N-channel MOSFET are connected to the CMOS logic configuration, and the gate is connected to the second logic node. A second P-channel MOSFET and a second N-channel MOSFET to which an input signal is supplied, the first output node, and the first P-channel M A third P-channel MOSFET, which is inserted in series with the OSFET and whose gate is connected to the second output node, and is provided between the second output node and the power supply voltage. A fourth P-channel type MOSFET connected to the first output node, wherein the first and second input signals have a small signal level with respect to the power supply voltage from the first output node to the second output signal. It is possible to obtain a circuit that forms an output signal of a level corresponding to the power supply voltage in synchronization with the change timing of one input signal from one level to the other level, and further, the level conversion circuit has a logic function. As a result, it is possible to reduce the circuit scale and to generate a highly accurate timing signal.
[0061]
(7) a first CMOS logic circuit that receives the first input signal and its inverted delay signal, a second CMOS logic circuit that receives the second input signal and its inverted delay signal, and the first and second First and second MOSFETs of the first conductivity type provided in parallel to the first conductivity type logic MOSFET in the serial form of each CMOS logic circuit, and each of the first and second CMOS logic circuits First and second MOSFETs of the second conductivity type provided in parallel with the second conductivity type logic MOSFET in parallel configuration, the first conductivity type first and second MOSFETs and the second conductivity of the first conductivity type are provided. The gates of the first MOSFET and the second MOSFET of the type are connected in common and cross-connected to the output of the other CMOS logic circuit, respectively, and the first and second input signals and the respective inverted delay signals are A level conversion circuit with a logic function that has a low signal level with respect to the power supply voltage and generates an output signal having a level corresponding to the power supply voltage and corresponding to a time difference between the first and second input signals. Further, by providing the level conversion circuit with a logic function, the circuit scale can be reduced and a highly accurate timing signal can be generated.
[0062]
(8) By controlling the operation of the memory circuit that operates with the power supply voltage as described in (2) above using the timing signal generated by the level conversion circuit with logic function of (6) and (7) above, The effect that a high-speed and stable operation can be realized is obtained.
[0063]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the internal circuit to which the timing signal formed by the timing generation circuit is supplied has an operation sequence executed by a memory circuit such as an EPROM, a mask ROM, a static RAM, or a timing signal in addition to the flash EEPROM as described above. It can be widely used as various digital circuits. In the level conversion circuit with logic function, the internal circuit is operated at a step-down voltage for low power consumption, and the input / output signal is a signal corresponding to the power supply voltage level in order to achieve compatibility with an external device. It can be widely used in various semiconductor integrated circuit devices.
[0064]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, low power consumption is achieved by combining a delay circuit that is operated with a constant voltage that is made independent of the power supply voltage supplied from the external terminal, and generating a timing signal at a level corresponding to the power supply voltage to control the internal circuit. Stable operation with power can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.
FIG. 2 is a schematic block diagram showing an embodiment of the FEEPROM of FIG.
3 is a configuration diagram for explaining a read operation of the FEEPROM in FIG. 2; FIG.
FIG. 4 is a block diagram showing an embodiment of a timing generation circuit according to the present invention.
5 is a waveform diagram for explaining the operation of the timing generation circuit of FIG. 4; FIG.
6 is a block diagram showing an embodiment of a level conversion circuit with logic function LOG1 & LVC included in the timing generation circuit of FIG. 4;
7 is a block diagram showing an embodiment of a level conversion circuit with logic function LOG2 & LVC included in the timing generation circuit of FIG. 4; FIG.
FIG. 8 is a circuit diagram showing an embodiment of the delay circuit of FIG. 4;
[Explanation of symbols]
CPU ... Central processing unit, CPG ... Clock generation circuit, DTC ... Data transfer device, RAM ... Random access memory, ROM ... Read-only memory, FEEPROM ... Flash electrical erasable & programmable read-only memory , IOP1 to IOP9 ... I / O port, INT ... Interrupt controller, SCI ... Serial communication interface,
DESCRIPTION OF SYMBOLS 1 ... Memory array, 2 ... X decoder, 3 ... Column switch (sense & latch), 4 ... X address buffer, 5 ... Y address buffer, 6 ... Control signal input circuit, 7 ... Input / output buffer, 8 ... Internal voltage generation circuit.
MC1, MC2... Memory cells, Q1 to Q32... MOSFET, N1 to N6... CMOS inverter circuit, C1, C1.

Claims (11)

A first timing generation circuit that is operated at a constant voltage independent of a power supply voltage supplied from an external terminal and generates a plurality of first timing signals;
A second timing generation circuit that combines a plurality of first timing signals formed by the first timing generation circuit and generates a second timing signal at a level corresponding to the power supply voltage;
An internal circuit whose operation is controlled by the second timing signal formed by the second timing generation circuit,
The internal circuit is
A memory array comprising a plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data lines;
A precharge circuit for precharging the data line;
A semiconductor integrated circuit device comprising: a sense amplifier for amplifying a read signal read out to the data line.   2. The semiconductor integrated circuit device according to claim 1, wherein the first timing generation circuit comprises a plurality of delay element arrays.   2. The semiconductor integrated circuit according to claim 1, wherein the second timing signal controls an operation period of the precharge circuit and the sense amplifier with reference to a rising or falling edge of a predetermined clock signal. apparatus.   4. The semiconductor integrated circuit device according to claim 3, wherein the frequency of the clock signal is set in accordance with the application.   2. The semiconductor integrated circuit device according to claim 1, wherein the first timing signal has a function of switching a delay amount by a control signal, and the function is used for verifying a circuit operation.   4. The semiconductor integrated circuit device according to claim 1, wherein the power supply for the precharge circuit is the power supply voltage.   4. The semiconductor integrated circuit device according to claim 1, wherein the power supply of the sense amplifier is the power supply voltage. The second timing generation circuit includes:
A first input timing signal is supplied to the gate, and a first P-channel MOSFET and a first N-channel MOSFET provided between the first output node and the power supply voltage and between the output node and the circuit ground potential, respectively. When,
An inverted signal of the first input timing signal is supplied to the gate, and a second N-channel MOSFET provided between the second output node and the ground potential of the circuit;
The first P-channel MOSFET and the first N-channel MOSFET are connected to the CMOS logic configuration between the power supply voltage and the first output node and between the first output node and the ground potential of the circuit. A second P-channel MOSFET and a second N-channel MOSFET having a gate supplied with a second input timing signal;
A third P-channel MOSFET inserted in series between the first output node and the first P-channel MOSFET and having a gate connected to the second output node;
A fourth P-channel MOSFET provided between the second output node and the power supply voltage and having a gate connected to the first output node;
Said first and second input timing signal is a small signal level corresponding to the constant voltage, the logic function with the level conversion circuit for forming an output signal of the level corresponding to the power supply voltage from said first output node The semiconductor integrated circuit device according to claim 1, further comprising: The second timing generation circuit includes:
A first CMOS logic circuit that receives the first input timing signal and its inverted delay signal;
A second CMOS logic circuit receiving a second input timing signal and its inverted delay signal;
A first conductivity type first and second MOSFET provided in parallel with a first conductivity type logic MOSFET in series with the first and second CMOS logic circuits;
A second conductivity type first and second MOSFET provided in parallel with the second conductivity type logic MOSFET in parallel configuration of the first and second CMOS logic circuits;
The gates of the first and second MOSFETs of the first conductivity type, the first MOSFET and the second MOSFET of the second conductivity type are connected in common, and are mutually connected to the output of the other CMOS logic circuit,
Said first and second input timing signal and the respective inverted delayed signal, the is a small signal level corresponding to the constant voltage, the level corresponding to the power supply voltage from the output terminal of the first or 2CMOS logic circuit output 2. The semiconductor integrated circuit device according to claim 1, further comprising a level conversion circuit with a logic function for forming a signal. A first input signal is supplied to the gate, and a first P-channel MOSFET and a first N-channel MOSFET provided between the first output node and the power supply voltage and between the output node and the circuit ground potential, ,
An inverted signal of the first input signal is supplied to the gate, and a third N-channel MOSFET provided between the second output node and the ground potential of the circuit;
The first P-channel MOSFET and the first N-channel MOSFET are connected to the CMOS logic configuration between the power supply voltage and the first output node and between the first output node and the ground potential of the circuit. A second P-channel MOSFET and a second N-channel MOSFET, each having a gate supplied with a second input signal,
A third P-channel MOSFET inserted in series between the first output node and the first P-channel MOSFET and having a gate connected to the second output node;
A fourth P-channel MOSFET provided between the second output node and the power supply voltage and having a gate connected to the first output node;
Said first and second input signal is a small signal level with respect to the supply voltage, has a logic function with the level conversion circuit for forming an output signal of the level corresponding to the power supply voltage from said first output node A semiconductor integrated circuit device. A first CMOS logic circuit having a first input terminal and a second input terminal;
A second CMOS logic circuit having a third input terminal and a fourth input terminal;
The first CMOS logic circuit is
A first conductivity type first MOSFET and a second conductivity type first MOSFET having a gate connected to the first input terminal;
A first conductivity type second MOSFET having a gate connected to the second input terminal and a second conductivity type second MOSFET;
The first conductivity type first and second MOSFETs are connected in parallel,
The first and second MOSFETs of the second conductivity type are connected in series,
The second CMOS logic circuit is:
A first conductivity type third MOSFET and a second conductivity type third MOSFET having a gate connected to the third input terminal;
A first conductivity type fourth MOSFET and a second conductivity type fourth MOSFET having a gate connected to the fourth input terminal;
The first conductivity type third and fourth MOSFETs are connected in parallel,
The second conductivity type third and fourth MOSFETs are connected in series,
A first conductivity type fifth MOSFET provided between first and second MOSFETs of the first conductivity type in parallel form of the first CMOS logic circuit and an output terminal of the first CMOS logic circuit;
A first conductivity type sixth MOSFET provided between first and second MOSFETs of the first conductivity type in parallel form of the second CMOS logic circuit and an output terminal of the second CMOS logic circuit;
A second conductivity type fifth MOSFET provided in parallel with the first and second MOSFETs of the second conductivity type formed in series with the first CMOS logic circuit;
A second conductivity type sixth MOSFET provided in parallel with the second and third conductivity type third and fourth MOSFETs arranged in series with the second CMOS logic circuit;
The gates of the first conductivity type fifth MOSFET and the second conductivity type fifth MOSFET are connected in common,
The gates of the first conductivity type sixth MOSFET and the second conductivity type sixth MOSFET are connected in common,
The gates of the first conductive type fifth MOSFET and the second conductive type fifth MOSFET, the first conductive type sixth MOSFET and the second conductive type sixth MOSFET which are connected in common are connected to each other. And the output terminal of the second CMOS logic circuit,
A first input signal is supplied to a first input terminal of the first CMOS logic circuit, an inverted delay signal of the first input signal is supplied to a second input terminal,
A second input signal is supplied to a first input terminal of the second CMOS logic circuit, an inverted delay signal of the second input signal is supplied to a second input terminal,
Said first and second input signals and the respective inverted delay signal is small signal level with respect to the supply voltage, the first or 2CMOS logic circuit output signal from the output terminal of the level corresponding to the power supply voltage A semiconductor integrated circuit device comprising a level conversion circuit with logic function for forming

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