JP4192793B2 - Semiconductor integrated circuit and power-on reset circuit - Google Patents

Description

The present invention is a power-on reset circuit which outputs an initial reset signal to the semiconductor integrated circuit inside the sequential logic circuit detects a rise of the supply voltage, and a semiconductor integrated circuit incorporating such a power-on reset circuit.

  In a semiconductor integrated circuit, when a power supply voltage rises, it is desirable to reset the sequential logic circuit to a desired state in order to prevent malfunction of the circuit. Conventionally, in order to reset the sequential logic circuit, a power-on reset circuit that detects the rise of the power supply voltage and outputs an initial reset signal has been used.

FIG. 5 shows a configuration of a conventional power-on reset circuit. As shown in FIG. 5, the power-on reset circuit, between the power supply potential V _DD and the power supply potential V _SS, resistor R and the capacitance C are connected in series. An input terminal of the inverter is connected to a connection point between the resistance element R and the capacitance C.

  When the power is turned on to the power-on reset circuit, the capacitance C is charged through the resistance element R, so that the potential at the connection point between the resistance element R and the capacitance C gradually increases. The charging time of the capacitance C is determined by the product (time constant) of the resistance value of the resistance element R and the capacitance value of the capacitance C.

  Immediately after the power is turned on, since the potential at the connection point between the resistance element R and the capacitance C is lower than the threshold voltage of the inverter, a high level signal is output from the output terminal of the inverter. Thereafter, when the capacitance C is charged and the potential at the connection point between the resistance element R and the capacitance C becomes higher than the threshold voltage of the inverter, a low level signal is output from the output terminal of the inverter.

  However, in the power-on reset circuit shown in FIG. 5, in order to lengthen the initial reset period, it is necessary to increase the resistance value of the resistance element R or the capacitance value of the capacitance C to increase the time constant. There is a problem that the area increases. Furthermore, in order to manufacture the resistance element R and the capacitance C, a manufacturing process other than the MOS transistor manufacturing process is required. On the other hand, when the resistance element R and the capacitance C are external parts in order to facilitate the manufacturing process, there is a problem that the usability of the semiconductor integrated circuit is deteriorated.

  As a related technique, Patent Document 1 below discloses a power-on reset system that can minimize an increase in LSI chip area and ensure a sufficiently long reset period. According to Patent Document 1, since a period from the set of flip-flops connected to the timer to the reset is used as a system reset period, a long reset period can be secured and the timer measurement time is changed. Thus, the reset period can be arbitrarily selected. However, since this power-on reset system requires a resistive element and a capacitance, the substrate area increases and the manufacturing process of the semiconductor integrated circuit becomes complicated.

  Patent Document 2 below discloses a power-on reset circuit that prevents chattering generated at an output terminal and realizes stable circuit operation. According to Patent Document 2, chattering can be prevented from occurring by connecting a diode between the input terminal and the output terminal of the buffer gate circuit. However, this power-on reset system also requires a resistance element and capacitance, which increases the substrate area and complicates the manufacturing process of the semiconductor integrated circuit.

Further, Patent Document 3 below discloses a power-on reset circuit that is free from static power consumption and hardly affected by inappropriate stimulation. According to Patent Document 3, since the power-on reset circuit is configured only by MOS transistors, a manufacturing process of a resistance element and a capacitance is not required. However, in Patent Document 3, if the voltages between the gate and the source of the transistors M3, M4, and M2 are V _GS1 , V _GS2 , and V _GS3 , respectively, the relationship between these and the power supply voltage V _DD is expressed by the following equation: .
V _DD = V _GS1 + V _GS2 + V _GS3

In order for the power-on reset circuit to operate normally, each of the gate-source voltages V _GS1 , V _GS2 , V _GS3 must be equal to or higher than the threshold voltage V _TH . Since the threshold voltage V _TH of a general transistor is about 0.6 V ± 0.2 V in consideration of variation, the power supply voltage V _DD is 2.4 V in order for the power-on reset circuit to operate reliably. It is necessary to be above. Therefore, this power-on reset circuit cannot be used when a low voltage power supply of about 1.8 V is used.
Japanese Patent Laid-Open No. 5-291915 (pages 1, 4 and FIG. 1) JP-A-5-299993 (pages 1, 2 and 1) JP-A-5-303449 (first page, FIG. 1)

Therefore, in view of the above points, the present invention provides a power-on reset circuit that can operate under a low-voltage power supply of about 1.8 V without using a resistance element and a capacitance , and such a power-on reset circuit . An object is to provide a built-in semiconductor integrated circuit.

In order to solve the above-described problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that activates an initial reset signal for a predetermined period in response to rising of a power supply voltage, and is configured by at least one transistor, A potential holding means for holding the potential of the first node so as to have a predetermined ratio with respect to the voltage, and a first current by flowing a current to the first node when the power supply voltage reaches a predetermined value. A level changing means for changing the potential of the node; a level determining means for comparing one power supply potential with the potential of the first node; and determining the level of the initial reset signal based on the comparison result; Control means for controlling the operation of the potential changing means in accordance with the determined level of the initial reset signal.

  Here, the potential holding means may be configured by a capacitance ratio of a plurality of groups of transistors connected to be equivalent to a reverse-biased diode. In addition, the potential changing means forms a first transistor through which a current flows when the power supply voltage reaches a predetermined value, and a current mirror circuit with the first transistor, thereby passing a current through the first node. These transistors may be included. Further, the control means may stop the operation of the current mirror circuit when the initial reset signal is deactivated.

Further, the level determining means changes the initial reset signal activated to the low level to the high level when the difference between the one power supply potential and the potential of the first node reaches a predetermined value. You may make it cancel reset mode.
Alternatively, the level determining means compares one power supply potential with the potential of the first node, determines the potential of the second node based on the comparison result, and inverts the potential of the second node. The initial reset signal may be generated by determining the potential of the third node and inverting the potential of the third node. In that case, the semiconductor integrated circuit includes at least one transistor, and has at least one second potential holding unit that holds the potential of the second node so as to have a predetermined ratio to the power supply voltage. A third potential holding unit that is configured by a transistor and holds the potential of the third node so as to have a predetermined ratio with respect to the power supply voltage may be further provided.

Furthermore, a power-on reset circuit according to the present invention is a power-on reset circuit that activates an initial reset signal for a predetermined period in response to a rise of a power supply voltage, and includes a first node. The result of comparing the potential holding means for holding the potential, the potential changing means for changing the potential of the first node when the power supply voltage reaches a predetermined value, and the potential of the first node and the potential of the first node And a control means for controlling the operation of the potential changing means based on the level.

  According to the present invention, the initial reset signal is based on the result of changing the potential of the first node held by the potential holding means by the potential changing means and comparing one power supply potential with the potential of the first node. Therefore, a power-on reset circuit that can operate under a low-voltage power supply of about 1.8 V can be realized without using a resistance element and a capacitance.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 shows a configuration of a power-on reset circuit built in a semiconductor integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, this power-on reset circuit includes P-channel MOS transistors QP1 to QP5 and N-channel MOS transistors QN1 to QN8, and is output from an output terminal (node) ND within a certain period from the rise of the power supply potential. Outputs an initial reset signal of negative logic (low level).

The source of the transistor QP1 is connected to the power supply potential _{V DD,} the gate of the transistor QP1 is connected to the power supply potential _{V SS.} The drain of the transistor QN1 is connected to the drain of the transistor QP1, the source of the transistor QN1 is connected to the power supply potential _{V SS.}

The drain of the transistor QN5 is connected to the drains of the transistors QP1 and QN1, and the gate of the transistor QN5 is connected to the node NC. The drain of the transistor QN6 is connected to the source of transistor QN5, the source of the transistor QN6 is connected to the power supply potential _{V SS,} the gate of the transistor QN6 is connected to the node ND.

The source of the transistor QN7 is connected to the power supply potential _{V SS,} the gate of transistor QN1 and QN7 is connected to the source of transistor QN5, the drain of the transistor QN6. When transistor QN5 is on and transistor QN6 is off, transistor QN1 and transistor QN7 form a current mirror circuit.

  The drain and gate of the transistor QN8 are connected to the node NA, and the source of the transistor QN8 is connected to the drain of the transistor QN7. Transistor QN8 is connected in saturation and is equivalent to a diode, and is forward biased.

The source of the transistor QP2 is connected to the power supply potential V _DD , the drain of the transistor QP2 is connected to the node NB, and the gate of the transistor QP2 is connected to the node NA. The drain of the transistor QN2 is connected to the node NB, the source of the transistor QN2 is connected to the power supply potential _{V SS,} the gate of transistor QN2 is connected to the node NC. Further, the source of the transistor QP5 is connected to the power supply potential V _DD , the drain of the transistor QP5 is connected to the node NB, and the gate of the transistor QP5 is connected to the node NC.

The source of the transistor QP3 is connected to the power supply potential V _DD , the drain of the transistor QP3 is connected to the node NC, and the gate of the transistor QP3 is connected to the node NB. The drain of the transistor QN3 is connected to the node NC, the source of the transistor QN3 is connected to the power supply potential _{V SS,} the gate of the transistor QN3 is connected to the node NB. Transistors QP3 and PN3 constitute an inverter.

The source of the transistor QP4 is connected to the power supply potential V _DD , the drain of the transistor QP4 is connected to the output terminal ND, and the gate of the transistor QP4 is connected to the node NC. The drain of the transistor QN4 is connected to the output terminal ND, the source of the transistor QN4 is connected to the power supply potential _{V SS,} the gate of the transistor QN4 is connected to the node NC. Transistors QP4 and QN4 constitute an inverter.

  In FIG. 1, nodes with the same symbol (NC and NC, ND and ND) are connected to each other. The nodes NA to NC are connected to the circuits shown in FIGS. 2A to 2C, respectively. As shown in FIG. 2, the power-on reset circuit further includes P channel MOS transistors QP11 to QP13 and N channel MOS transistors QN11 to QN13.

As shown in FIG. 2 (A), the transistor to the node NA is the source of the transistor QP11 which drain and gate are connected to the power supply potential V _DD, a drain and a gate connected to the power supply potential V _SS QN11 Is connected to the source. Here, each of the transistors QP11 and QN11 is equivalent to a circuit in which a diode is reverse-biased, and functions as a capacitance. In the present embodiment, the capacitance of the transistor QP11 is set larger than the capacitance of the transistor QN11 by increasing the ratio of the gate width / gate length of the QP11 or by connecting a plurality of P-channel MOS transistors in parallel. ing. The transistor QN11 may be omitted and a parasitic capacitance may be used.

Further, as shown in FIG. 2 (B), the node NB, and the source of the transistor QP12 which drain and gate are connected to the power supply potential V _DD, a drain and a gate connected to the power supply potential V _SS The source of the transistor QN12 is connected. Here, each of the transistors QP12 and QN12 is equivalent to a circuit in which a diode is reverse-biased, and functions as a capacitance. In the present embodiment, by increasing the gate width / gate length ratio of QN12 or by connecting a plurality of N-channel MOS transistors in parallel, the capacitance of transistor QN12 is larger than the capacitance of transistor QP12. Is set. The transistor QP12 may be omitted and a parasitic capacitance may be used.

Furthermore, as shown in (C) of FIG. 2, the node NC, and the source of the transistor QP13 which drain and gate are connected to the power supply potential V _DD, a drain and a gate connected to the power supply potential V _SS The source of the transistor QN13 is connected. Here, each of the transistors QP13 and QN13 is equivalent to a circuit in which a diode is reverse-biased, and functions as a capacitance. In the present embodiment, the capacitance of the transistor QP13 is set to a value larger than the capacitance of the transistor QN13 by increasing the gate width / gate length ratio of the QP13 or by connecting a plurality of P-channel MOS transistors in parallel. is doing. The transistor QN13 may be omitted and a parasitic capacitance may be used.

Next, the characteristics of the MOS transistor will be described. The MOS transistor performs a saturation operation when the relationship among the drain-source voltage V _DS , the gate-source voltage V _GS, and the threshold voltage V _TH is V _DS ≧ V _GS −V _TH. And when V _DS <V _GS −V _TH , the desaturation operation is performed.

一方、ＭＯＳトランジスタが非飽和動作を行う場合には、トランジスタのドレイン電流Ｉ_Ｄは、次式（２）で表される。

ここで、βはトランジスタの利得係数を表している。 When the MOS transistor performs a saturation operation, the drain current _{ID of the} transistor is expressed by the following equation (1).

On the other hand, when the MOS transistor performs a non-saturated operation, the drain current _{ID of the} transistor is expressed by the following equation (2).

Here, β represents the gain coefficient of the transistor.

一方、ＰチャネルＭＯＳトランジスタの利得係数β_Ｐは、次式（４）で表される。

ここで、μ_Ｎは電子易動度、μ_Ｐは正孔易動度、Ｃ_ＮはＮチャネルトランジスタの単位面積当たりのゲート絶縁膜の容量、Ｃ_ＰはＰチャネルトランジスタの単位面積当たりのゲート絶縁膜の容量、Ｗはトランジスタのチャネル幅、Ｌはトランジスタのチャネル長を表している。 The gain coefficient β _N of the N channel MOS transistor is expressed by the following equation (3).

On the other hand, the gain coefficient β _P of the P-channel MOS transistor is expressed by the following equation (4).

Here, μ _N is the electron mobility, μ _P is the hole mobility, C _N is the capacitance of the gate insulating film per unit area of the N-channel transistor, and C _P is the gate insulation per unit area of the P-channel transistor. The capacitance of the film, W is the channel width of the transistor, and L is the channel length of the transistor.

Next, the operation of the power-on reset circuit will be described. First, an operation in a period in which the power supply potential V _DD rises from 0 V to the threshold voltage V _{TH of the} transistor will be described. In the following description, since the power supply potential _VSS is 0 V, the power supply potential V _DD corresponds to the power supply voltage.

During the period when the power supply potential V _DD rises to the threshold voltage V _TH of the transistor, the transistors QP1 to QP5 and QN1 to QN8 do not perform their original operations and do not have current supply capability, so that the transistors QP11 to QP13 function as capacitances. The potentials of the respective nodes are determined by the charges that QN11 to QN13 accumulate as the power supply potential V _DD increases.

Here, the capacitance of the transistor QP11 and _{C P11,} and the capacitance of the transistors QN11 and _{C N11,} the potential _{V A} of the node NA, represented by the following formula (5).
V _A = {C _P11 / (C _P11 + C _N11 )} × V _DD (5)
In this embodiment, since C _P11 = 32C _N11 , V _A = 32/33 × V _DD , and the initial state of the potential _VA of the node NA can be set to the power supply potential V _DD side. Similarly, it is possible to set the initial state of the potential V _B at the node NB to the power supply potential V _SS side, it is possible to set the initial state of the potential V _C at the node NC to the power supply potential V _DD side.

Next, an operation in a period in which the power supply potential V _DD rises from the threshold voltage V _TH to the set potential will be described. When power supply potential V _DD exceeds the operable potential, transistors QP1 to QP5 and QN1 to QN7 start their original operations. That is, since the gate-source voltage V _GSP1 of the transistor QP1 becomes larger than the threshold voltage V _{THP1 of} the transistor QP1, the transistor QP1 is turned on. Thus, the transistor QP1 is started drain current _{I 1} flows to the drain of the transistor QN1 and _QN5, the voltage of V _{DD -V DSP 1} is applied. V _DSP1 is the drain-source voltage of the transistor QP1.

Although the transistor QP1 initially performs a non-saturation operation, the transistor QP1 operates in a state close to saturation (V _DSP1 ≈V _GSP1 −V _THP1 ). Therefore, the drain current I _D1 flowing through the transistor QP1 is expressed by the following equation (6). Become.
I _D1 = β _P1 (V _DD −V _THP1 ) ² (6)
Here, β _P1 represents the gain coefficient of the transistor QP1.

Since the potential V _{B of the} node NB is set to the power supply potential V _SS side and the potential V _{C of the} node NC is set to the power supply potential V _DD side, the output terminal ND receives a low level (power supply potential V _SS ) Initial reset signal is output. That is, the power-on reset circuit outputs a low-level initial reset signal from the output terminal ND after the power supply potential rises. Further, since the gate potential of the transistor QN6 connected to the output terminal ND is also at the power supply potential V _SS, the transistor QN6 is turned off.

ここで、β_Ｎ１はトランジスタＱＮ１の利得係数、β_Ｎ７はトランジスタＱＮ７の利得係数、Ｖ_ＯＳはトランジスタＱＮ１とＱＮ７との間で発生するオフセット誤差を表している。 On the other hand, since the potential V _{C of the} node NC to which the gate of the transistor QN5 is connected is set on the power supply potential V _DD side, the transistor QN5 is turned on and the transistors QN1 and QN7 operate as a current mirror circuit. As a result, the drain current _ID2 flows through the transistor QN7, and the charge accumulated in the transistor QP11 connected to the node NA is released. A drain current _ID2 flowing through the transistor QN7 is expressed by the following equation (7).

Here, β _N1 represents a gain coefficient of the transistor QN1, β _N7 represents a gain coefficient of the transistor QN7, and V _OS represents an offset error generated between the transistors QN1 and QN7.

The offset error V _OS is expressed by the following equation (8).
V _OS = V _THN7 −V _THN1 (8)
Here, V _THN7 represents the threshold voltage of the transistor QN7, and V _THN1 represents the threshold voltage of the transistor QN1.

When the drain current _ID2 flows, the charge accumulated in the transistor QP11 decreases, and a voltage drop at the node NA occurs. As a result, the difference between the potential _{V A} and the power supply potential _{V DD} of the node NA, i.e., to increase the gate-source voltage _{V GSP2} the transistor QP2 is, the gate-source voltage _{V GSP2} is transistor QP2 threshold voltage _{V thp2} Becomes larger than that, the transistor QP2 starts to turn on.

Note that since the node NC set on the power supply potential V _DD side is connected to the gate of the transistor QN2, the transistor QN2 is turned on. Therefore, the potential at the connection point between the drains of QN2 of the transistor QP2 (node NB) is determined by the relationship between the gate-source voltage _{V GSN2} gate-source voltage _{V GSP2} the transistor QN2 transistor QP2 .

ここで、β_Ｐ２、Ｖ_ＧＳＰ２、Ｖ_ＴＨＰ２は、トランジスタＱＰ２の利得係数、ゲート・ソース間電圧、しきい電圧をそれぞれ表し、β_Ｎ２、Ｖ_ＧＳＮ２、Ｖ_ＴＨＮ２、Ｖ_ＳＩＦＴは、トランジスタＱＮ２の利得係数、ゲート・ソース間電圧、しきい電圧、しきい電圧の経年変化による増加分をそれぞれ表している。 The potential of the node NB is initially set on the power supply potential _VSS side. However, when the voltage drop at the node NA increases and the absolute value of the gate-source voltage V _GSP2 of the transistor QP2 increases to satisfy the relationship of the following equation (9), the transistor QP2 turns on and the potential of the node NB Rises to near the power supply potential V _DD .

_{Here, β P2, V GSP2, V} THP2 the gain factor of the transistor QP2, represents the gate-source voltage, a threshold voltage, _{respectively, β N2, V GSN2, V} THN2, V SIFT is the gain coefficient of the transistor QN2 , Gate-source voltage, threshold voltage, and threshold voltage increase over time.

Accordingly, when the voltage drop at the node NA becomes large and the relationship of Expression (9) is satisfied, the power-on reset circuit outputs a high level (power supply potential V _DD ) signal from the output terminal ND. As a result, the reset mode is released. In order to prevent the charge from flowing back to the transistor QP11, a transistor QN8 that is connected in saturation and equivalent to a diode is used.

Next, an operation in a period in which the power supply potential V _DD rises to the set potential and is stable will be described. After the potential of the node NB is raised to the power supply potential V _DD near the node NC is fixed to the power supply potential V _SS, a high level signal from the output terminal ND continues to be outputted.

Therefore, since the transistor QN5 is turned off and the transistor QN6 is turned on, the transistors QN1 and QN7 do not function as a current mirror circuit, the drain currents I _D1 and I _D2 are stopped, and no power is consumed.

As a result, the node NA enters a high impedance state, and therefore, the potential of the node NA may fluctuate due to noise or the like, and the next stage may malfunction. In order to prevent such a malfunction, in the present embodiment, the potential of the node NB is fixed to the power supply potential V _DD using the transistor QP5 in which the node NC is connected to the gate. Further, by making the on-resistance of the transistor QP5 smaller than the on-resistance of the transistor QN2, the potential after the node NB does not change even if the potential of the node NA changes.

Next, an operation in a period during which the power supply potential V _DD falls from the set potential to 0 V will be described. In the period in which the power supply potential V _DD falls from the set potential to the threshold voltage V _TH , the potential of each node is fixed, so that no malfunction occurs. Further, during the period when the power supply potential V _DD falls from the threshold voltage V _TH to 0 V, the sequential logic circuit connected to the output terminal ND of the power-on reset circuit does not perform the original operation, so that no malfunction is caused. .

  However, if the power is turned on again before the charges accumulated in the transistors QP11 to QP13 and QN11 to QN13 are completely discharged, the charges accumulated in the transistors QP11 to QP13 and QN11 to QN13 malfunction. May cause. Therefore, in the present embodiment, the transistors QP11 to QP13 and QN11 to QN13 are saturatedly connected to form a circuit equivalent to a diode, so that charges are removed when a forward bias is applied to the nodes NA to NC to prevent malfunction. is doing.

FIG. 3 is a diagram showing the potential of each node when the power supply potential V _DD rises sharply. When power supply potential V _DD rises, transistors QP11-QP13 and QN11-QN13 start to accumulate electric charges. Here, as shown in FIG. 3, when the power supply potential V _DD rises steeply, the amount of charge stored in the transistor also suddenly increases. Therefore, the nodes NA and NC are synchronized with the rise of the power supply potential V _DD . The potential also rises sharply.

Next, since the drain current _ID2 flows due to the operation of the current mirror circuit, the charge accumulated in the transistor QP11 is released at the node NA, and the potential _{VA of the} node NA decreases. After that, when the difference between the potential _{VA of the} node NA and the power supply potential V _DD widens and the relationship of Expression (9) is satisfied, the potential of the node NB transitions to the high potential side, and the potential of the node NC decreases to the low potential. And the potential of the node ND changes to the high potential side.

  Since the current mirror circuit stops operating due to the transition of the potential of the node ND to the high potential side, the discharge of the charge accumulated in the transistor QP11 is stopped at the node NA, and the potential of the node NA is stabilized.

FIG. 4 is a diagram showing the potential of each node when the power supply potential V _DD rises slowly. When power supply potential V _DD rises, transistors QP11-QP13 and QN11-QN13 start to accumulate electric charges. Here, as shown in FIG. 4, when the power supply potential V _DD rises slowly, the amount of charge accumulated in the transistor also gradually increases, so that the potentials of the nodes NA and NC also gradually increase.

Next, when the power supply potential V _DD exceeds a predetermined potential, the drain current I _D2 flows due to the operation of the current mirror circuit, so that the charge accumulated in the transistor QP11 is released at the node NA and the potential V _A at the node NA is released. Goes down. FIG. 4 shows a case where the amount of charge released by the drain current _ID2 flowing is larger than the amount of charge that increases as the power supply potential V _DD rises. In this case as well, the potential _{VA of the} node NA is the _sum of the drain-source voltage V _DSN7 of the transistor QN7 and the threshold voltage V _{THN8 of the} transistor QN8.

Further, when the difference between the potential _{VA of the} node NA and the power supply potential V _DD widens and satisfies the relationship of Expression (9), the potential of the node NB transitions to the high potential side, and the potential of the node NC decreases to the low potential. The potential of the output terminal ND transitions to the high potential side. As a result, the current mirror circuit stops operating, so that the discharge of the charge accumulated in the transistor QP11 is stopped at the node NA, and the potential of the node NA follows the rise of the power supply potential V _DD .

In order for this power-on reset circuit to perform the original operation, the power supply potential V _DD should satisfy the following equation (10).
V _DD ≧ V _THP2 + V _THN8 + V _DSN7 (10)
Here, V _DSN7 represents the drain-source voltage of the transistor QN7.

The threshold voltage V _TH of a general transistor is about 0.6 V ± 0.2 V in consideration of variation, and this power-on reset circuit assumes that the drain-source voltage when the transistor is turned on is 0.01 V. However, in order to perform the original operation, it is sufficient that the power supply potential V _DD is 1.61V or higher, and therefore, sufficient operation is possible even with a low voltage power supply of about 1.8V.

  According to the present embodiment, since a circuit can be configured with only MOS transistors, a resistance element and a capacitance are not required, and it can be mass-produced at a small size and at low cost. Further, after the reset mode is released, the operation of the current mirror circuit is stopped by turning off the transistor QN5 and turning on the transistor QN6, so that it is possible to cut power consumption in a static state.

  INDUSTRIAL APPLICABILITY The present invention can be used in a semiconductor integrated circuit, in particular, a semiconductor integrated circuit having a built-in power-on reset circuit that detects a rising edge of a power supply voltage and outputs an initial reset signal to a sequential logic circuit inside the semiconductor integrated circuit. is there.

The figure which shows the structure of the power-on reset circuit in one Embodiment of this invention. The figure which shows the circuit to which each node in FIG. 1 is connected. The figure which shows the electric potential of each node in case power supply potential _VDD rises sharply The figure which shows the electric potential of each node in case power supply potential _VDD rises slowly. The figure which shows the structure of the conventional power-on reset circuit.

Explanation of symbols

QP1 to QP5, QP11 to QP13 P-channel MOS transistors, QN1 to QN8, QN11 to QN13 N-channel MOS transistors

Claims (8)

A semiconductor integrated circuit that activates an initial reset signal for a predetermined period in response to a rise of a power supply voltage,
A potential holding unit configured by at least one transistor and holding the potential of the first node so as to have a predetermined ratio to the power supply voltage;
Potential changing means for changing the potential of the first node by causing a current to flow through the first node when the power supply voltage reaches a predetermined value;
Level determining means for comparing one power supply potential with the potential of the first node and determining the level of the initial reset signal based on the comparison result;
Control means for controlling the operation of the potential changing means according to the level of the initial reset signal determined by the level determining means;
A semiconductor integrated circuit comprising:   2. The semiconductor integrated circuit according to claim 1, wherein said potential holding means is constituted by a capacitance ratio of a plurality of groups of transistors connected to be equivalent to a reverse-biased diode. The potential changing means is
A first transistor through which a current flows when the power supply voltage reaches a predetermined value;
A second transistor that causes a current to flow to the first node by forming a current mirror circuit with the first transistor;
The semiconductor integrated circuit according to claim 1, comprising:   4. The semiconductor integrated circuit according to claim 3, wherein the control means stops the operation of the current mirror circuit when an initial reset signal is deactivated.   When the difference between the one power supply potential and the first node potential reaches a predetermined value, the level determining means resets the initial reset signal activated to low level to high level. The semiconductor integrated circuit according to claim 1, wherein the mode is released.   The level determining means compares one power supply potential with the potential of the first node, determines the potential of the second node based on the comparison result, and inverts the potential of the second node. 6. The semiconductor integrated circuit according to claim 1, wherein an initial reset signal is generated by determining a potential of the third node and inverting the potential of the third node. Second potential holding means configured to include at least one transistor and hold the potential of the second node so as to have a predetermined ratio to the power supply voltage;
A third potential holding unit configured by at least one transistor and holding the potential of the third node so as to have a predetermined ratio to the power supply voltage;
The semiconductor integrated circuit according to claim 6, further comprising:   A power-on reset circuit that activates an initial reset signal for a predetermined period in response to a rise of a power supply voltage,
  A potential holding unit configured by at least one transistor to hold the potential of the first node;
  A potential changing means for changing the potential of the first node when the power supply voltage reaches a predetermined value;
  Level determining means for determining a level of an initial reset signal based on a result of comparing the power supply potential and the potential of the first node;
  Control means for controlling the operation of the potential changing means based on the level;
A power-on reset circuit comprising:

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