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JP4192430B2 - Manufacturing method of nitride semiconductor epitaxial wafer - Google Patents

Manufacturing method of nitride semiconductor epitaxial wafer Download PDF

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Publication number
JP4192430B2
JP4192430B2 JP2001055028A JP2001055028A JP4192430B2 JP 4192430 B2 JP4192430 B2 JP 4192430B2 JP 2001055028 A JP2001055028 A JP 2001055028A JP 2001055028 A JP2001055028 A JP 2001055028A JP 4192430 B2 JP4192430 B2 JP 4192430B2
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nitride semiconductor
substrate
layer
epitaxial wafer
semiconductor epitaxial
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JP2002261024A (en
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祐一 大島
春典 坂口
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、窒化物半導体エピタキシャルウェハの製造方法に関する。
【0002】
【従来の技術】
近年、発光ダイオード(LED)やレーザダイオード(LD)等の高出力化、高効率化等を図るため、バンドギャップが大きく(3.4eV)、直接遷移型であり、しかもバンドギャップを広範囲で制御できることから窒化物半導体が用いられるようになってきた。
【0003】
【発明が解決しようとする課題】
ところで、GaNあるいはその混晶であるAlGaNやInGaN等は実用的な同種の基板がないため、サファイアやSiC等の異種基板上で結晶成長が行われる。これら異種基板は格子定数が成長層と大きく異なるために成長層の結晶欠陥が多い。また、膨張係数も大きく異なるために厚膜成長時や成長後に反りやクラックが発生する。これらの反りやクラックは特に窒化物半導体厚膜を成長させるときに深刻な問題となる。
【0004】
そこでこのような問題を根本的に解決するためにGaN基板の開発が進められており、高温高圧下でGaN単結晶を合成する高温高圧法(S.Porowski et al,J.Cryst.Growth 178(1997)p174)やサファイヤ基板上にHVPE法で数百μm程度の厚膜を成長させた後、サファイア基板を取り除くことによってGaNの自立単結晶基板を得る方法(Michael K.Kelly et al,Jpn.J.Appl.Phys.38(1999)Pt.2,No.3A,pp.L217)等の方法が代表的である。
【0005】
しかし、高温高圧法は超高圧セル中で結晶成長が行われるため、得られるGaN単結晶のサイズをあまり大きくすることができず、現在のところ直径10mm程度のものしか得られていない。そのうえ製造コストが非常に高く、実用的ではない。HVPE(ハイドライド気相成長法:Hydride Vapor Phase Epitaxy)でサファイア基板上に直接GaN厚膜を成長させる方法はより現実的ではあるが、この場合でも結晶欠陥はかなり多く、サファイア基板の実用的な除去方法が無い。しかも、除去後もGaN厚膜には反りが残る等の問題がある。
【0006】
窒化物半導体のエピタキシャル成長の時サファイア基板の反りは、窒化物半導体のエピタキシャル成長中に、例えばグラファイトのサセプタ等の加熱物体との接触の不均一を生じ、成長層のキャリア濃度や組成等の特性を不均一にする。特にInGaNではこの濃度不均一は致命的である。また、成長後のサファイア基板の反りは、フォトリソグラフィにおける微細パターンの露光で大きな問題となる。
【0007】
また、結晶欠陥は光素子の発光特性や信頼性を悪化させ、電子デバイスのリーク電流や非線形性、信頼性低下等の原因となる。
【0008】
この対策として、選択成長によるラテラル方向成長を利用したELO法(O.H.Nam et al,Appl.phys.Lett.71(1997)2472)やFIELO法(A.Sakai et al,Appl.Phys.Lett.71(1997)2259)等が開発されているが、いまだに結晶欠陥は106 〜107 cm-3ほど存在し、反りの問題はまったく改善されていないという問題があった。
【0009】
一方、反りを軽減する方法に関しては例えば特開平9−223819号公報に開示されているように、Si基板の表面より下に酸素若しくは窒素のイオン打ち込みによって緩和層兼剥離層を形成し、さらに表面を炭化してSiCとしたSi基板上に窒化物半導体を成長させ、その後のエッチングによってSi基板を除去する方法がある。
【0010】
しかし、この方法では窒化物半導体への応力を軽減するためにSi基板とそのSi基板上に形成するSiC層、AlGaNバッファ層及び窒化物半導体層構造の厚さのバランスを精密に制御しなければならない。特に窒素打ち込みによって形成した窒化物半導体層を歪み緩和層とした場合、Si基板をエッチングによって除去するためにはSiC層と歪み緩和層との間にSiの層を残さなければならないので、表面炭化の条件が厳しく、かつ歪み緩和層が窒化物半導体成長層から遠くなるので、歪み緩和効果が小さくなってしまう。また、基板表面を完全に覆うほどに表面炭化を行うのは量産を考えた場合困難である。
【0011】
そこで、本発明の目的は、上記課題を解決し、結晶欠陥が少なく、反りやクラックの少ない窒化物半導体エピタキシャルウェハの製造方法を提供することにある。
【0012】
【課題を解決するための手段】
上記目的を達成するために本発明の窒化物半導体エピタキシャルウェハの製造方法は、サファイア基板上に第一の窒化物半導体層を形成した基板の表面または裏面からイオンを打ち込み、上記サファイア基板中に周囲より機械的強度の小さい中間層を形成し、上記中間層を形成した基板の上記第一の窒化物半導体層の上に第二の窒化物半導体層をエピタキシャル成長させるものである。
【0014】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、第一の窒化物半導体半導体層の厚さを5μm以下とするのが好ましい。
【0015】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、打ち込むイオンを水素イオン、窒素イオン、酸素イオンのいずれか若しくはそれらの混合とするのが好ましい。
【0016】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、イオンの打ち込みの加速電圧を1keV以上1MeV以下とし、かつ、イオンのドーズ量を1×1015cm-2以上1×1019cm-2以下とするのが好ましい。
【0017】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、イオンを打ち込んだ後で熱処理を行うことにより第一の窒化物半導体層の表面結晶層のイオン打ち込みによるダメージを回復させると共に、中間層に微細なボイド及びボイドの集合体を生じさせるのが好ましい。
【0020】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、中間層を境にしてサファイア基板を剥離、除去してもよい。
【0021】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、第二の窒化物半導体層の表面に他の基板を貼り付けた後で中間層を境にしてサファイア基板を剥離、除去してもよい。
【0022】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、他の基板としてSi基板、AlN基板、Cu基板、Al基板のいずれかを用いるのが好ましい。
【0023】
上記構成に加え本発明の窒化物半導体エピタキシャルウェハの製造方法は、除去、剥離した第二の窒化物半導体層の裏面に残ったサファイア基板の一部を研磨により部分的若しくは全て除去するのが好ましい。
【0026】
本発明は表面に第一の窒化物半導体層を形成したサファイア基板の表面または裏面から水素、窒素等のイオンを打ち込み、サファイア基板中に機械的強度の弱い中間層を形成したものを基板とし、その基板上に第二の窒化物半導体のエピタキシャル成長を行うものである。成長する層構造は1層以上のエピタキシャル構造であり、pn接合やヘテロ接合等の半導体構造が形成されたり、発光ダイオードやレーザダイオード、受光素子、電界効果トランジスタ、HEMT(高電子移動度トランジスタ)、HBT(ヘテロ接合バイポーラトランジスタ)等の種々の半導体素子に適した層構造、あるいはその一部を構成するエピタキシャル層構造となる。
【0027】
また、イオン打ち込み後の基板に熱処理を加えることで中間層に多数の微細なボイドを形成することにより中間層の機械的強度をさらに弱めることもできる。この中間層が窒化物半導体結晶とサファイア基板との熱膨張係数の相違を緩和するバッファ層として機能するため、従来問題となっていたクラックや反りが解消し、高品質な窒化物半導体エピタキシャルウェハが得られる。さらにこの中間層を境にしてサファイア基板を容易に剥離、除去することができる。剥離、除去後に窒化物半導体層の裏面にわずかに残ったサファイア基板を研磨等によって除去することにより、大口径でフラットな自立窒化物半導体エピタキシャルウェハを容易に得ることができる。
【0028】
【発明の実施の形態】
以下、本発明の実施の形態を添付図面に基づいて詳述する。
【0029】
図1(a)〜(f)は本発明の窒化物半導体エピタキシャルウェハの製造方法の一実施の形態を示す工程図である。
【0030】
サファイア基板1の表面に第一の窒化物半導体層2を形成した基板を準備する(図1(a))。
【0031】
基板の表面または裏面からサファイア基板1中に水素、窒素あるいは酸素等のイオンを打ち込んでイオン打ち込み層3を形成する(図1(b))。
【0032】
イオン打ち込み層3が形成された基板に熱処理を施す(図1(c))。
【0033】
熱処理が終了した基板の第一の窒化物半導体層2の上に第二の窒化物半導体層4をエピタキシャル成長させる。
【0034】
成長する層構造は少なくとも1層のエピタキシャル構造であり、pn接合、ヘテロ接合、発光ダイオード、レーザ、受光素子、電界効果トランジスタ、HEMT、HBT等の電子デバイス等、種々の半導体素子に適した層構造、あるいはその一部を構成するエピタキシャル層構造となる。イオン打ち込み層3はアモルファス的な構造となっているので、歪みを吸収し、緩和し、クラックや反り等がなくなる。また、水素イオンの打ち込み層3は窒化物半導体結晶の成長中に加熱されることにより、中間層としてのボイド層5となる。これはUnibond法と言われるSOI(絶縁膜上に単結晶Siを成長させたウェハ)の作製法(A.J.Auberton−Herve et al 電子材料6月号(1997)29)の一部と原理は同じである。このボイド層5は歪みの吸収、緩和効果が高く、クラックや反り等の問題を解決し、結晶欠陥を減少させる。
【0035】
本方法で用いられる基板は、表面が窒化物半導体であり、ボイド層5の歪み吸収効果が大きいため、例えば特開平9−223819号公報に開示されているような面倒な表面炭化処理や複数の層の膜厚バランスを精密に制御する必要もなく、高品質な窒化物半導体エピタキシャルウェハを容易に得ることができる(図1(d))。
【0036】
さらに、このボイド層(あるいはアモルファス層)5は第一の窒化物半導体結晶2やサファイア基板1の単結晶部に比べ機械的に弱いため、熱処理や機械衝撃等の種々の方法で第二の窒化物半導体結晶層4をサファイア基板1から剥離することができる。
【0037】
この剥離方法は、窒化物半導体結晶膜成長過程での加熱による自然剥離、あるいはその後の熱処理に剥離、側面からの窒素ジェットによる剥離、ウォータージェットによる剥離、レーザ照射による剥離等種々の方法が使用できる(図1(e))。
【0038】
剥離した第二の窒化物半導体層4の裏面にわずかに残ったサファイアを部分的に、または全て研磨等の方法によって除去すれば、大口径でフラットな自立窒化物半導体エピタキシャルウェハ4を容易に得ることができる(図1(f))。
(最適条件に関する根拠)
第一の窒化物半導体層2の膜厚を5μm以下とする第一の理由は、基板の反りを防止するためであり、これ以上の厚さにすると第一の窒化物半導体2とサファイア基板1との熱膨張差によって基板が反ってしまうためである。
【0039】
第二の理由は、第一の窒化物半導体層2の膜厚を5μm以上の厚さにすると、第一の窒化物半導体層2の表面の結晶性を良好に保ったままでサファイア基板1中にイオン打ち込みを行うことが困難になるからである。
【0040】
イオン打ち込みの加速電圧を1keV以上1MeV以下としたのは、中間層5の形成深さを適切にし、基板表面の結晶状態を良好に保つためである。1keV以下では中間層5の形成される位置が浅すぎて、基板表面の結晶性に悪影響を与える。これとは逆に1MeV以上では打ち込んだイオンが基板表面に与えるダメージが無視できなくなる。また、中間層5の形成される位置が深くなり過ぎて中間層による歪み緩衝効果が小さくなったり、基板剥離後に窒化物半導体単結晶の裏面に残るサファイア等が厚くなるために除去するため、研磨に手間がかかってしまう。
【0041】
ドーズ量を1×1015cm-2以上1×1019cm-2以下としたのは、基板表面の結晶のダメージを無視できる範囲に抑えつつ反りを緩和し、歪み緩衝及び基板の剥離に充分なほどのボイドを発生させるためである。ドーズ量が1×1015cm-2以下ではボイドの発生密度が小さいため、歪み緩衝効果が小さく、基板を剥離するのにも不十分である。ドーズ量が1×1019cm-2以上になると、打ち込んだイオンが基板表面の結晶に与えるダメージが無視できなくなってしまう。
【0042】
次に本発明の窒化物半導体エピタキシャルウェハの製造方法の実施例について添付図面に基づいて詳述する。尚、具体的な数値を挙げて説明するが限定されるものではない。
【0043】
【実施例】
(実施例1)
(1) サファイア基板(直径50mm、厚さ0.33mm)にMOVPE法(有機金属気相成長法)を用いてGaN単結晶層を2μmの厚さにエピタキシャル成長させた。成長炉は横型常圧MOVPE炉を用い、原料としてアンモニアガスとトリメチルガリウムとを用い、キャリアガスとして水素と窒素との混合ガスを用いた。まず、基板を水素雰囲気で1100℃に加熱し、表面の酸化物等をクリーニングした。続いて基板温度を550℃に下げて、GaN層を20nmの厚さに成長させ、さらに基板温度を1050℃に上げてGaN層を2μmの厚さに成長させた。
(2) (1) のGaN単結晶層側からサファイア基板中に水素をイオン打ち込みする。その条件はドーズ量を1×1017cm-2とし、加速電圧を120keVとし、GaN単結晶層との界面から約0.5μmの深さに厚さ0.1μm程度の中間層を形成した。
(3) 水素を打ち込んだGaNエピタキシャル成長基板表面には単結晶層が形成されており、サファイア基板中に水素の打ち込み層が形成されている。
(4) (3) で水素を打ち込んだGaNエピタキシャル成長基板をアンモニア雰囲気中、800℃で30分間熱処理した。熱処理の終了した試料の断面を走査型電子顕微鏡で観察したところ、中間層は微細なボイドの多数発生したボイド層になっていた。
(5) (4) で熱処理の終了したGaNエピタキシャル成長基板上に、HVPE法を用いてGaN単結晶層を300μmの厚さにエピタキシャル成長させた。成長に用いた装置は横型常圧HVPE炉であった。原料としてアンモニアガス及び金属GaとHClガスとを850℃で反応させて得られたGaClを用い、n型の導電型を得るため、SiH2 Cl2 とを同時に流した。キャリアガスには水素ガスを用いた。成長温度は1050℃、成長速度は80μm/hである。
(6) (5) のエピタキシャル成長終了後、成長温度から室温までの冷却過程において中間層(ボイド層)を境にサファイア基板が自然に剥離した。GaN単結晶層の裏面にわずかに残ったサファイアを研磨して除去することにより、n型GaN自立単結晶基板が得られた。
(7) (6) で得られたn型GaN自立単結晶基板は直径50mm、厚さ約300μmの無色透明のものであり、クラックや反りの全く無いものであった。
(実施例2)
(1) サファイア基板(直径50mm、厚さ0.15mm)にMOVPE法を用いてGaN単結晶層を2μmの厚さにエピタキシャル成長させた。成長炉には横型常圧MOVPE炉を用い、原料としてアンモニアガスとトリメチルガリウムとを用い、キャリアガスとして水素と窒素との混合ガスを用いた。まず、基板を水素雰囲気で1100℃に加熱し、表面の酸化物等をクリーニングした。続いて基板温度を550℃に下げてGaN層を20nmの厚さに成長させ、さらに基板温度を1050℃に上げてGaN層を2μmの厚さに成長させた。
(2) (1) のサファイア基板側からサファイア基板中に水素をイオン打ち込みする。その条件はドーズ量を1×1017cm-2とし、加速電圧を200keVとし、GaN単結晶層との界面から約0.5μmの深さに厚さ0.1μm程度の中間層を形成した。
(3) 水素を打ち込んだGaNエピタキシャル成長基板表面には単結晶層が形成され、サファイア基板中に水素の打ち込み層が形成されている。
(4) (3) 水素を打ち込んだGaNエピタキシャル成長基板をアンモニア雰囲気中、800℃で30分熱処理した。熱処理の終了した試料の断面を走査型電子顕微鏡で観察したところ、中間層は微細なボイドの多数発生したボイド層になっていた。
(5) (4) で熱処理の終了したGaNエピタキシャル成長基板上に、HVPE法を用いてGaN単結晶層を300μmの厚さにエピタキシャル成長させた。成長に用いた装置は横型常圧HVPE炉である。原料としてアンモニアガス及び金属GaとHClガスとを850℃で反応させて得られたGaClを用い、n型の導電型を得るためにSiH2 Cl2 を同時に流した。キャリアガスには水素ガスを用いた。成長温度は1050℃、成長速度は80μm/hである。
(6) (5) のエピタキシャル成長終了後、成長温度から室温までの冷却過程において中間層を境にサファイア基板が自然に剥離した。GaN単結晶層の裏面にわずかに残ったサファイアを研磨して除去することにより、n型GaN自立単結晶基板が得られた。
(7) (6) で得られたn型GaN自立単結晶基板は直径50mm、厚さ約300μmの無色透明のものであり、クラックや反りの全く無いものであった。
(実施例3)
(1) 実施例2で得られたn型GaN自立単結晶基板上にMOVPE法によって図2に示すようなLD構造を形成した。図2は図1(a)〜(f)に示した製造方法を適用したGaN自立単結晶基板上に形成されたLDの断面構造模式図である。
(2) LD構造は、GaN自立単結晶基板10側から順にSiドープGaNバッファ層(厚さ2μm、n=5×1017cm-3)11、SiドープAl0.07Ga0.93Nクラッド層(厚さ1.0μm、n=5×1017cm-3)12、SiドープGaN SCH層(厚さ0.1μm、n=1×1017cm-3)13、アンドープIn0.2 Ga0.8 N/In0.05Ga0.95N多重量子井戸層(厚さ3nm/厚さ5nm×3)14、MgドープAl0.2 Ga0.8 Nオーバーフロー防止層(厚さ20nm、p=2×1019cm-3)15、MgドープGaN光閉込層(厚さ0.1μm、p=2×1019cm-3)16、MgドープAl0.07Ga0.93Nクラッド層(厚さ0.5μm、p=2×1019cm-3)17及びMgドープGaNコンタクト層(厚さ50nm、p=2×1019cm-3)18からなる。
(3) p側にドライエッチングにより幅4μm、深さ0.4μmのリッジ構造を作製し、電流狭窄を行った。さらにリッジ上部にNi/Au電極を形成し、p型オーミック電極19とした。裏面のGaN自立単結晶基板10側にはTi/Al電極を全面に形成し、n型オーミック電極20とした。さらに両端面にTiO2 /SiO2 からなる高反射コーティング膜を形成することにより半導体デバイスとしてのLD素子が得られた。素子長は500μmとした。
(4) このLD素子に通電すると閾値電流密度4.5kA/cm2 であり、閾値電圧5.5Vで室温連続発振した。また、結晶欠陥が低減されているため、LD素子の寿命は室温25℃で、30mW駆動時において5000時間と良好な特性を有していた。
(5) さらに本発明による自立基板は反りが無い上にサファイア基板上にLD構造を形成した場合に比べて劈開が容易なため、プロセス時の歩留りが大幅に改善され、90%以上の素子で良好な特性が得られた。
(実施例4)
(1) 実施例2の(1) 〜(4) で得られたGaNエピタキシャル成長基板上にLED構造を成長させた。
(2) LED構造は、基板側から順にSiドープGaNクラッド層(厚さ3μm、n=5×1017cm-3)35、アンドープIn0.2 Ga0.8 N量子井戸層(3nm)34、MgドープAl0.2 Ga0.8 Nクラッド層(厚さ0.5μm、p=2×1019cm-3)33及びMgドープGaNコンタクト層(厚さ50nm、p=2×1019cm-3)32からなる。
(3) 成長したLEDエピタキシャルウェハ表面にNi/Au層を真空蒸着し、そのNi/Au層の上に直径50mm、厚さ0.2mmのAl基板を電気炉中、窒素雰囲気下660℃で融着した。融着終了後、ウェハ側面からの窒素ジェットによって中間層からサファイア基板までの部分を剥離、除去した。サファイア基板を除去したLEDエピタキシャルウェハの、Al基板と反対側にTi/Al電極を形成した。このLEDエピタキシャルウェハを図3に示す。図3は図1(a)〜(f)に示した製造方法を適用したGaN自立単結晶基板上に形成されたLEDの断面構造模式図である。
【0044】
すなわち、LEDエピタキシャルウェハは、Al基板30上にNi/Au層31、MgドープGaN層32、MgドープAl0.2 Ga0.8 Nクラッド層33、アンドープIn0.2 Ga0.8 N量子井戸層34、SiドープGaNクラッド層35及びn型電極36が順次形成されたものである。
【0045】
このようなLEDエピタキシャルウェハを300μm角にカットし、得られたチップの上下両面にAuワイヤをボンディングすることにより半導体デバイスとしてのLED素子が得られた。
(4) このLED素子に通電したところ、発光波長は450nmで、発光出力は20mA通電時で約7mWであった。サファイア上に直接成長したLEDとは異なり、結晶欠陥が少なく、放熱特性も良いため素子の信頼性が高く、樹脂モールドした状態で室温40℃、湿度100%、電流20mAで1000時間の連続通電試験を行ったところ、1000時間通電後においても発光出力は初期状態とほぼ変わらなかった。
(変形例)
上述した実施例では基板として表面に窒化物半導体層を形成したサファイア基板を用い、打ち込むイオンとして水素イオンを用いた場合について説明したが、本発明はこれに限定されるものではなく、サファイア以外の基板や水素イオン以外のイオンを用いてもよい。
【0046】
また、窒化物半導体のエピタキシャル成長法としては、MOVPE法、HVPE法、MBE法等のすでに公知の方法があり、利用することができる。また、窒化ガリウムや窒化アルミニウム等の低温バッファ層を用いる二段階成長法、直接高温で成長させる方法、成長の途中で微細加工と再成長を用いてラテラル成長による転位低減を図るELO法、FIELO法等公知の種々の方法を用いることができる。
【0047】
中間層をボイド層とするのは第二の窒化物半導体層の成長前の昇温中、成長中、冷却中、成長後のいずれかあるいは全ての工程、あるいは幾つかの工程で行うことができる。またイオン打ち込み後、第二の窒化物半導体層の成長開始前に他の熱処理によって行ってもよい。
【0048】
中間層を境にサファイア基板を剥離する方法は、成長後の熱処理による剥離、側面からの窒素ジェットによる剥離、ウォータジェットによる剥離、レーザ照射による剥離等の種々の方法でも実施できる。
【0049】
実施例4ではAl基板を貼り付けた上で剥離を行ったが、その他に例えば、Si基板、ガラス基板、Cu等の金属基板、AlN等の熱伝導性のよい薄膜を積層した金属基板等、その後の素子作製プロセスに適した基板を用いることができる。
【0050】
ここで、従来、窒化物半導体のエピタキシャル成長は熱膨張係数の大きく異なるサファイア等の基板上で行われていたため、結晶欠陥が多かったり、厚膜を成長させると反りやクラックが発生するという問題があった。この問題を根本的に解決するために窒化物半導体基板の開発も行われてきたが、窒化物半導体基板の作製は超高圧下で行われていたためにコストが非常に高い上に直径10mm程度の小さなものしか得られなかった。また、HVPE法で数百μm程度のGaN厚膜をサファイア基板上に成長させた後、サファイア基板を除去することによってGaNの自立基板を得る方法はより現実的ではあるが、サファイア基板と窒化物半導体との熱膨張率の差に起因するクラックが発生する上に結晶欠陥がかなり多い。さらに、サファイア基板の実用的な除去方法が無い、除去後も反りが残る等の問題があった。
【0051】
しかし、本発明を用いれば、水素打ち込みと熱処理とによって基板中に形成された中間層が熱膨張率の差を緩和するバッファ層として機能し、従来問題となっていた結晶欠陥が著しく減少し、反りやクラックが解消された高品質な窒化物半導体エピタキシャルウェハを容易に得ることができる。また、窒化物半導体層をこの中間層を境に基板から剥離して窒化物半導体の大面積でフラットな自立エピタキシャルウェハを容易に得ることができる。
【0052】
【発明の効果】
以上要するに本発明によれば、次のような優れた効果を発揮する。
【0053】
結晶欠陥が少なく、反りやクラックの少ない窒化物半導体エピタキシャルウェハの製造方法の提供を実現することができる。
【図面の簡単な説明】
【図1】(a)〜(f)は本発明の窒化物半導体エピタキシャルウェハの製造方法の一実施の形態を示す工程図である。
【図2】図1(a)〜(f)に示した製造方法を適用したGaN自立単結晶基板上に形成されたLDの断面構造模式図である。
【図3】図1(a)〜(f)に示した製造方法を適用したGaN自立単結晶基板上に形成されたLEDの断面構造模式図である。
【符号の説明】
1 サファイア基板
2 第一の窒化物半導体層
3 イオン打ち込み層
4 第二の窒化物半導体層
5 ボイド層(中間層)
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a nitride semiconductor epitaxial wafer .
[0002]
[Prior art]
In recent years, the band gap is large (3.4 eV), direct transition type, and the band gap is controlled over a wide range in order to increase the output and efficiency of light emitting diodes (LEDs) and laser diodes (LDs). For this reason, nitride semiconductors have been used.
[0003]
[Problems to be solved by the invention]
By the way, GaN or its mixed crystals such as AlGaN and InGaN do not have practically the same type of substrates, and therefore crystal growth is performed on different types of substrates such as sapphire and SiC. These dissimilar substrates have many crystal defects in the growth layer because the lattice constant is significantly different from that of the growth layer. Further, since the expansion coefficients are greatly different, warping and cracking occur during or after the thick film growth. These warpages and cracks are particularly serious problems when growing a nitride semiconductor thick film.
[0004]
Therefore, development of a GaN substrate has been underway in order to fundamentally solve such problems, and a high-temperature high-pressure method (S. Porowski et al, J. Cryst. Growth 178 ( 1997) p174) or a method of obtaining a GaN free-standing single crystal substrate by removing a sapphire substrate after growing a thick film of about several hundred μm by HVPE method on a sapphire substrate (Michael K. Kelly et al, Jpn. J. Appl.Phys.38 (1999) Pt.2, No.3A, pp.L217) and the like are typical.
[0005]
However, in the high-temperature and high-pressure method, since crystal growth is performed in an ultra-high pressure cell, the size of the obtained GaN single crystal cannot be increased so much, and currently only a diameter of about 10 mm is obtained. In addition, the manufacturing costs are very high and not practical. Although a method of growing a GaN thick film directly on a sapphire substrate by HVPE (hydride vapor phase epitaxy) is more realistic, there are still many crystal defects in this case, and practical removal of the sapphire substrate is practical. There is no way. Moreover, there is a problem that the GaN thick film remains warped after removal.
[0006]
During epitaxial growth of nitride semiconductors, warpage of the sapphire substrate causes non-uniform contact with a heated object such as a graphite susceptor during the epitaxial growth of nitride semiconductors, and the characteristics such as carrier concentration and composition of the growth layer are not uniform. Make uniform. In particular, this concentration non-uniformity is fatal in InGaN. Further, warping of the sapphire substrate after growth becomes a serious problem in exposure of a fine pattern in photolithography.
[0007]
In addition, the crystal defect deteriorates the light emission characteristics and reliability of the optical element, and causes leakage current, nonlinearity, and deterioration of reliability of the electronic device.
[0008]
As countermeasures, the ELO method using lateral growth by selective growth (OH Nam et al, Appl. Phys. Lett. 71 (1997) 2472) or the FIELO method (A. Sakai et al, Appl. Phys. Lett. 71 (1997) 2259) and the like have been developed, but there are still crystal defects of about 10 6 to 10 7 cm −3 , and the problem of warping has not been improved at all.
[0009]
On the other hand, with respect to a method for reducing the warpage, for example, as disclosed in JP-A-9-223819, a relaxation layer / peeling layer is formed by ion implantation of oxygen or nitrogen below the surface of the Si substrate. There is a method in which a nitride semiconductor is grown on a Si substrate that is carbonized to form SiC, and the Si substrate is removed by subsequent etching.
[0010]
However, in this method, in order to reduce the stress on the nitride semiconductor, the balance of the thickness of the Si substrate and the SiC layer, AlGaN buffer layer, and nitride semiconductor layer structure formed on the Si substrate must be precisely controlled. Don't be. In particular, when a nitride semiconductor layer formed by nitrogen implantation is used as a strain relaxation layer, a Si layer must remain between the SiC layer and the strain relaxation layer in order to remove the Si substrate by etching. And the strain relaxation layer becomes far from the nitride semiconductor growth layer, so that the strain relaxation effect is reduced. In addition, it is difficult to carry out surface carbonization so as to completely cover the substrate surface in consideration of mass production.
[0011]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and provide a method for manufacturing a nitride semiconductor epitaxial wafer with less crystal defects and less warpage and cracks.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a method for producing a nitride semiconductor epitaxial wafer according to the present invention includes implanting ions from the front surface or the back surface of a substrate on which a first nitride semiconductor layer is formed on a sapphire substrate, and surrounding the sapphire substrate. An intermediate layer having a lower mechanical strength is formed, and a second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer of the substrate on which the intermediate layer is formed .
[0014]
In addition to the above configuration, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, the thickness of the first nitride semiconductor semiconductor layer is preferably 5 μm or less.
[0015]
In the nitride semiconductor epitaxial wafer manufacturing method of the present invention in addition to the above configuration, ions to be implanted are preferably hydrogen ions, nitrogen ions, oxygen ions, or a mixture thereof.
[0016]
In addition to the above-described configuration, the nitride semiconductor epitaxial wafer manufacturing method of the present invention has an ion implantation acceleration voltage of 1 keV to 1 MeV and an ion dose of 1 × 10 15 cm −2 to 1 × 10 19 cm. -2 or less is preferable.
[0017]
In addition to the above-described structure, the nitride semiconductor epitaxial wafer manufacturing method of the present invention recovers damage caused by ion implantation of the surface crystal layer of the first nitride semiconductor layer by performing a heat treatment after implanting ions. It is preferable to produce fine voids and aggregates of voids in the layer.
[0020]
In addition to the above configuration, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention may peel and remove the sapphire substrate with the intermediate layer as a boundary.
[0021]
In addition to the above-described configuration, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention includes peeling off and removing the sapphire substrate with the intermediate layer as a boundary after attaching another substrate to the surface of the second nitride semiconductor layer. Also good.
[0022]
In addition to the above configuration, the method for producing a nitride semiconductor epitaxial wafer of the present invention preferably uses any one of a Si substrate, an AlN substrate, a Cu substrate, and an Al substrate as another substrate.
[0023]
In addition to the above configuration, the method for producing a nitride semiconductor epitaxial wafer of the present invention preferably removes part or all of the sapphire substrate remaining on the back surface of the removed and peeled second nitride semiconductor layer by polishing. .
[0026]
The present invention implants ions such as hydrogen and nitrogen from the front or back surface of the sapphire substrate on which the first nitride semiconductor layer is formed on the surface, and forms a substrate having a weak mechanical strength in the sapphire substrate, The second nitride semiconductor is epitaxially grown on the substrate. The growing layer structure is an epitaxial structure of one or more layers, a semiconductor structure such as a pn junction or a heterojunction is formed, a light emitting diode, a laser diode, a light receiving element, a field effect transistor, a HEMT (high electron mobility transistor), A layer structure suitable for various semiconductor elements such as an HBT (heterojunction bipolar transistor), or an epitaxial layer structure constituting a part thereof.
[0027]
Further, the mechanical strength of the intermediate layer can be further reduced by forming a large number of fine voids in the intermediate layer by applying heat treatment to the substrate after ion implantation. Since this intermediate layer functions as a buffer layer that alleviates the difference in thermal expansion coefficient between the nitride semiconductor crystal and the sapphire substrate, cracks and warpage that have been problems in the past are eliminated, and a high-quality nitride semiconductor epitaxial wafer can be obtained. can get. Furthermore, the sapphire substrate can be easily peeled and removed with this intermediate layer as a boundary. By removing the sapphire substrate slightly left on the back surface of the nitride semiconductor layer after peeling and removal by polishing or the like, a large-diameter flat self-standing nitride semiconductor epitaxial wafer can be easily obtained.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0029]
1A to 1F are process diagrams showing an embodiment of a method for producing a nitride semiconductor epitaxial wafer of the present invention.
[0030]
A substrate having the first nitride semiconductor layer 2 formed on the surface of the sapphire substrate 1 is prepared (FIG. 1A).
[0031]
An ion implantation layer 3 is formed by implanting ions such as hydrogen, nitrogen, or oxygen into the sapphire substrate 1 from the front surface or the back surface of the substrate (FIG. 1B).
[0032]
A heat treatment is performed on the substrate on which the ion implantation layer 3 is formed (FIG. 1C).
[0033]
A second nitride semiconductor layer 4 is epitaxially grown on the first nitride semiconductor layer 2 of the substrate after the heat treatment.
[0034]
The growing layer structure is an epitaxial structure of at least one layer, and is a layer structure suitable for various semiconductor elements such as pn junction, heterojunction, light emitting diode, laser, light receiving element, field effect transistor, HEMT, HBT and other electronic devices. Or an epitaxial layer structure constituting a part thereof. Since the ion implantation layer 3 has an amorphous structure, it absorbs and relaxes strain and eliminates cracks and warpage. The hydrogen ion implantation layer 3 becomes a void layer 5 as an intermediate layer by being heated during the growth of the nitride semiconductor crystal. This is a part and principle of a method for manufacturing SOI (wafer in which single crystal Si is grown on an insulating film), which is referred to as the Unibond method (AJ Auberton-Herve et al Electronic Materials June issue (1997) 29). Are the same. This void layer 5 has a high strain absorption and relaxation effect, solves problems such as cracks and warpage, and reduces crystal defects.
[0035]
Since the substrate used in this method has a nitride semiconductor surface and the void layer 5 has a large strain absorption effect, for example, a troublesome surface carbonization treatment as disclosed in Japanese Patent Laid-Open No. 9-223819 or a plurality of There is no need to precisely control the thickness balance of the layers, and a high-quality nitride semiconductor epitaxial wafer can be easily obtained (FIG. 1 (d)).
[0036]
Further, since the void layer (or amorphous layer) 5 is mechanically weaker than the first nitride semiconductor crystal 2 and the single crystal portion of the sapphire substrate 1, the second nitridation is performed by various methods such as heat treatment and mechanical shock. The physical semiconductor crystal layer 4 can be peeled from the sapphire substrate 1.
[0037]
As this peeling method, various methods such as natural peeling by heating in the growth process of a nitride semiconductor crystal film, or subsequent heat treatment, peeling by a nitrogen jet from the side, peeling by a water jet, peeling by laser irradiation can be used. (FIG. 1 (e)).
[0038]
If the sapphire slightly remaining on the back surface of the peeled second nitride semiconductor layer 4 is partially or entirely removed by a method such as polishing, a large-diameter flat self-standing nitride semiconductor epitaxial wafer 4 can be easily obtained. (FIG. 1 (f)).
(Reason for optimum conditions)
The first reason for setting the film thickness of the first nitride semiconductor layer 2 to 5 μm or less is to prevent the substrate from warping, and if the thickness is larger than this, the first nitride semiconductor 2 and the sapphire substrate 1 This is because the substrate warps due to the difference in thermal expansion.
[0039]
The second reason is that when the film thickness of the first nitride semiconductor layer 2 is set to 5 μm or more, the crystallinity of the surface of the first nitride semiconductor layer 2 is maintained in the sapphire substrate 1 in a good condition. This is because it becomes difficult to perform ion implantation.
[0040]
The reason why the acceleration voltage of ion implantation is set to 1 keV or more and 1 MeV or less is to make the formation depth of the intermediate layer 5 appropriate and to keep the crystal state of the substrate surface favorable. Below 1 keV, the position where the intermediate layer 5 is formed is too shallow, which adversely affects the crystallinity of the substrate surface. On the contrary, at 1 MeV or higher, the damage given to the substrate surface by the implanted ions cannot be ignored. Further, the intermediate layer 5 is formed too deeply so that the strain buffering effect by the intermediate layer is reduced, or sapphire remaining on the back surface of the nitride semiconductor single crystal after the substrate is peeled off is removed to increase the thickness. Takes time and effort.
[0041]
A dose of 1 × 10 15 cm −2 or more and 1 × 10 19 cm −2 or less is sufficient for strain buffering and peeling of the substrate while suppressing the crystal damage on the substrate surface to a negligible range. This is to generate as many voids as possible. When the dose amount is 1 × 10 15 cm −2 or less, the generation density of voids is small, so the strain buffering effect is small and it is insufficient for peeling off the substrate. When the dose amount is 1 × 10 19 cm −2 or more, the damage given to the crystals on the substrate surface by the implanted ions cannot be ignored.
[0042]
Next, an embodiment of the method for producing a nitride semiconductor epitaxial wafer according to the present invention will be described in detail with reference to the accompanying drawings. In addition, although it demonstrates with a specific numerical value, it is not limited.
[0043]
【Example】
(Example 1)
(1) A GaN single crystal layer was epitaxially grown to a thickness of 2 μm on a sapphire substrate (diameter 50 mm, thickness 0.33 mm) using the MOVPE method (metal organic vapor phase epitaxy). The growth furnace was a horizontal atmospheric MOVPE furnace, using ammonia gas and trimethyl gallium as raw materials, and a mixed gas of hydrogen and nitrogen as carrier gases. First, the substrate was heated to 1100 ° C. in a hydrogen atmosphere to clean the surface oxide and the like. Subsequently, the substrate temperature was lowered to 550 ° C., the GaN layer was grown to a thickness of 20 nm, the substrate temperature was further raised to 1050 ° C., and the GaN layer was grown to a thickness of 2 μm.
(2) Hydrogen is ion-implanted into the sapphire substrate from the GaN single crystal layer side of (1). The conditions were such that the dose was 1 × 10 17 cm −2 , the acceleration voltage was 120 keV, and an intermediate layer having a thickness of about 0.1 μm was formed at a depth of about 0.5 μm from the interface with the GaN single crystal layer.
(3) A single crystal layer is formed on the surface of the GaN epitaxial growth substrate implanted with hydrogen, and a hydrogen implantation layer is formed in the sapphire substrate.
(4) The GaN epitaxial growth substrate into which hydrogen was implanted in (3) was heat-treated at 800 ° C. for 30 minutes in an ammonia atmosphere. When the cross section of the sample after the heat treatment was observed with a scanning electron microscope, the intermediate layer was a void layer in which many fine voids were generated.
(5) A GaN single crystal layer was epitaxially grown to a thickness of 300 μm using the HVPE method on the GaN epitaxial growth substrate after the heat treatment in (4). The apparatus used for the growth was a horizontal atmospheric HVPE furnace. In order to obtain n-type conductivity, ammonia gas and GaCl obtained by reacting ammonia gas and metallic Ga and HCl gas at 850 ° C. were used as raw materials, and SiH 2 Cl 2 was simultaneously flowed. Hydrogen gas was used as the carrier gas. The growth temperature is 1050 ° C., and the growth rate is 80 μm / h.
(6) After the epitaxial growth of (5) was completed, the sapphire substrate naturally separated at the intermediate layer (void layer) in the cooling process from the growth temperature to room temperature. An n-type GaN free-standing single crystal substrate was obtained by polishing and removing the sapphire slightly remaining on the back surface of the GaN single crystal layer.
(7) The n-type GaN free-standing single crystal substrate obtained in (6) was a colorless and transparent substrate having a diameter of 50 mm and a thickness of about 300 μm, and had no cracks or warpage.
(Example 2)
(1) A GaN single crystal layer was epitaxially grown on a sapphire substrate (diameter 50 mm, thickness 0.15 mm) to a thickness of 2 μm using the MOVPE method. A horizontal normal pressure MOVPE furnace was used as the growth furnace, ammonia gas and trimethylgallium were used as raw materials, and a mixed gas of hydrogen and nitrogen was used as a carrier gas. First, the substrate was heated to 1100 ° C. in a hydrogen atmosphere to clean the surface oxide and the like. Subsequently, the substrate temperature was lowered to 550 ° C. to grow the GaN layer to a thickness of 20 nm, and the substrate temperature was further raised to 1050 ° C. to grow the GaN layer to a thickness of 2 μm.
(2) Hydrogen is ion-implanted into the sapphire substrate from the sapphire substrate side of (1). The conditions were a dose of 1 × 10 17 cm −2 , an acceleration voltage of 200 keV, and an intermediate layer having a thickness of about 0.1 μm was formed at a depth of about 0.5 μm from the interface with the GaN single crystal layer.
(3) A single crystal layer is formed on the surface of the GaN epitaxial growth substrate implanted with hydrogen, and a hydrogen implantation layer is formed in the sapphire substrate.
(4) (3) The hydrogen-implanted GaN epitaxial growth substrate was heat-treated at 800 ° C. for 30 minutes in an ammonia atmosphere. When the cross section of the sample after the heat treatment was observed with a scanning electron microscope, the intermediate layer was a void layer in which many fine voids were generated.
(5) A GaN single crystal layer was epitaxially grown to a thickness of 300 μm using the HVPE method on the GaN epitaxial growth substrate after the heat treatment in (4). The apparatus used for the growth was a horizontal atmospheric HVPE furnace. As a raw material, ammonia gas and GaCl obtained by reacting metal Ga and HCl gas at 850 ° C. were used, and SiH 2 Cl 2 was simultaneously flowed in order to obtain an n-type conductivity type. Hydrogen gas was used as the carrier gas. The growth temperature is 1050 ° C., and the growth rate is 80 μm / h.
(6) After the epitaxial growth in (5) was completed, the sapphire substrate naturally separated from the intermediate layer in the cooling process from the growth temperature to room temperature. An n-type GaN free-standing single crystal substrate was obtained by polishing and removing the sapphire slightly remaining on the back surface of the GaN single crystal layer.
(7) The n-type GaN free-standing single crystal substrate obtained in (6) was a colorless and transparent substrate having a diameter of 50 mm and a thickness of about 300 μm, and had no cracks or warpage.
(Example 3)
(1) An LD structure as shown in FIG. 2 was formed on the n-type GaN free-standing single crystal substrate obtained in Example 2 by the MOVPE method. FIG. 2 is a schematic cross-sectional view of an LD formed on a GaN free-standing single crystal substrate to which the manufacturing method shown in FIGS.
(2) The LD structure includes a Si-doped GaN buffer layer (thickness 2 μm, n = 5 × 10 17 cm −3 ) 11, a Si-doped Al 0.07 Ga 0.93 N cladding layer (thickness) in order from the GaN free-standing single crystal substrate 10 side. 1.0 μm, n = 5 × 10 17 cm −3 ) 12, Si-doped GaN SCH layer (thickness 0.1 μm, n = 1 × 10 17 cm −3 ) 13, undoped In 0.2 Ga 0.8 N / In 0.05 Ga 0.95 N multiple quantum well layer (thickness 3 nm / thickness 5 nm × 3) 14, Mg-doped Al 0.2 Ga 0.8 N overflow prevention layer (thickness 20 nm, p = 2 × 10 19 cm −3 ) 15, Mg-doped GaN light Confinement layer (thickness 0.1 μm, p = 2 × 10 19 cm −3 ) 16, Mg-doped Al 0.07 Ga 0.93 N cladding layer (thickness 0.5 μm, p = 2 × 10 19 cm −3 ) 17 and Mg-doped GaN contact layer (thickness 50 nm, p = 2 × Consisting 0 19 cm -3) 18.
(3) A ridge structure having a width of 4 μm and a depth of 0.4 μm was fabricated by dry etching on the p side, and current confinement was performed. Further, a Ni / Au electrode was formed on the ridge to form a p-type ohmic electrode 19. A Ti / Al electrode was formed on the entire surface of the rear surface of the GaN free-standing single crystal substrate 10 side to form an n-type ohmic electrode 20. Furthermore, an LD element as a semiconductor device was obtained by forming a highly reflective coating film made of TiO 2 / SiO 2 on both end faces. The element length was 500 μm.
(4) When this LD element was energized, the threshold current density was 4.5 kA / cm 2 , and continuous oscillation occurred at room temperature at a threshold voltage of 5.5 V. In addition, since the crystal defects are reduced, the lifetime of the LD element is as good as 5000 hours at a room temperature of 25 ° C. and 30 mW drive.
(5) Furthermore, the self-standing substrate according to the present invention has no warpage and is easier to cleave than the case where the LD structure is formed on the sapphire substrate. Good characteristics were obtained.
Example 4
(1) An LED structure was grown on the GaN epitaxial growth substrate obtained in (1) to (4) of Example 2.
(2) The LED structure consists of a Si-doped GaN cladding layer (thickness 3 μm, n = 5 × 10 17 cm −3 ) 35, an undoped In 0.2 Ga 0.8 N quantum well layer (3 nm) 34, an Mg-doped Al It consists of a 0.2 Ga 0.8 N cladding layer (thickness 0.5 μm, p = 2 × 10 19 cm −3 ) 33 and a Mg-doped GaN contact layer (thickness 50 nm, p = 2 × 10 19 cm −3 ) 32.
(3) A Ni / Au layer is vacuum-deposited on the surface of the grown LED epitaxial wafer, and an Al substrate having a diameter of 50 mm and a thickness of 0.2 mm is melted on the Ni / Au layer in an electric furnace at 660 ° C. in a nitrogen atmosphere. I wore it. After the fusion was completed, the portion from the intermediate layer to the sapphire substrate was peeled off and removed by a nitrogen jet from the side surface of the wafer. Ti / Al electrodes were formed on the opposite side of the Al substrate from the LED epitaxial wafer from which the sapphire substrate was removed. This LED epitaxial wafer is shown in FIG. FIG. 3 is a schematic cross-sectional view of an LED formed on a GaN free-standing single crystal substrate to which the manufacturing method shown in FIGS.
[0044]
That is, the LED epitaxial wafer includes an Ni / Au layer 31, an Mg-doped GaN layer 32, an Mg-doped Al 0.2 Ga 0.8 N cladding layer 33, an undoped In 0.2 Ga 0.8 N quantum well layer 34, an Si-doped GaN cladding on an Al substrate 30. The layer 35 and the n-type electrode 36 are sequentially formed.
[0045]
An LED element as a semiconductor device was obtained by cutting such an LED epitaxial wafer into 300 μm squares and bonding Au wires to the upper and lower surfaces of the obtained chip.
(4) When this LED element was energized, the emission wavelength was 450 nm and the emission output was about 7 mW when 20 mA was applied. Unlike LEDs grown directly on sapphire, there are few crystal defects and good heat dissipation characteristics, so the reliability of the device is high, and continuous energization test at room temperature 40 ° C, humidity 100%, current 20 mA in resin-molded state for 1000 hours As a result, the light emission output remained almost unchanged from the initial state even after 1000 hours of energization.
(Modification)
In the above-described embodiments, the case where a sapphire substrate having a nitride semiconductor layer formed on the surface is used as a substrate and hydrogen ions are used as ions to be implanted is described. However, the present invention is not limited to this, Ions other than the substrate and hydrogen ions may be used.
[0046]
In addition, as an epitaxial growth method of a nitride semiconductor, there are already known methods such as MOVPE method, HVPE method, MBE method, and the like can be used. Also, a two-stage growth method using a low-temperature buffer layer such as gallium nitride or aluminum nitride, a method of directly growing at a high temperature, an ELO method or a FIELO method for reducing dislocation by lateral growth using microfabrication and regrowth during the growth Various known methods such as these can be used.
[0047]
The intermediate layer may be a void layer during the temperature rise, growth, cooling, post-growth, or after the growth of the second nitride semiconductor layer, or in several steps. . Further, after the ion implantation, the heat treatment may be performed by another heat treatment before starting the growth of the second nitride semiconductor layer.
[0048]
The method of peeling the sapphire substrate with the intermediate layer as a boundary can be implemented by various methods such as peeling by heat treatment after growth, peeling by nitrogen jet from the side, peeling by water jet, peeling by laser irradiation, and the like.
[0049]
In Example 4, the Al substrate was attached and then peeled, but for example, a Si substrate, a glass substrate, a metal substrate such as Cu, a metal substrate laminated with a thin film having good thermal conductivity such as AlN, etc. A substrate suitable for the subsequent element manufacturing process can be used.
[0050]
Here, conventionally, epitaxial growth of nitride semiconductors has been performed on a substrate such as sapphire having a significantly different coefficient of thermal expansion, so there are problems that there are many crystal defects and warping and cracks occur when a thick film is grown. It was. In order to fundamentally solve this problem, a nitride semiconductor substrate has been developed. However, since the production of the nitride semiconductor substrate has been performed under an ultra-high pressure, the cost is very high and the diameter is about 10 mm. Only a small one was obtained. Further, a method of obtaining a GaN free-standing substrate by growing a GaN thick film of about several hundred μm on the sapphire substrate by HVPE method and then removing the sapphire substrate is more realistic, but the sapphire substrate and nitride Cracks are generated due to the difference in thermal expansion coefficient from the semiconductor, and there are many crystal defects. Further, there are problems such as no practical removal method of the sapphire substrate and warping remaining after the removal.
[0051]
However, if the present invention is used, the intermediate layer formed in the substrate by hydrogen implantation and heat treatment functions as a buffer layer that relaxes the difference in thermal expansion coefficient, and crystal defects that have been a problem in the past are significantly reduced. A high-quality nitride semiconductor epitaxial wafer in which warpage and cracks are eliminated can be easily obtained. In addition, the nitride semiconductor layer is peeled off from the substrate with the intermediate layer as a boundary, and a large-area flat self-supporting epitaxial wafer of the nitride semiconductor can be easily obtained.
[0052]
【The invention's effect】
In short, according to the present invention, the following excellent effects are exhibited.
[0053]
It is possible to provide a method for manufacturing a nitride semiconductor epitaxial wafer with less crystal defects and less warpage and cracks.
[Brief description of the drawings]
FIGS. 1A to 1F are process diagrams showing an embodiment of a method for producing a nitride semiconductor epitaxial wafer of the present invention.
2 is a schematic cross-sectional view of an LD formed on a GaN free-standing single crystal substrate to which the manufacturing method shown in FIGS. 1A to 1F is applied. FIG.
3 is a schematic cross-sectional view of an LED formed on a GaN free-standing single crystal substrate to which the manufacturing method shown in FIGS. 1A to 1F is applied. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 1st nitride semiconductor layer 3 Ion implantation layer 4 2nd nitride semiconductor layer 5 Void layer (intermediate layer)

Claims (9)

サファイア基板上に第一の窒化物半導体層を形成した基板の表面または裏面からイオンを打ち込み、上記サファイア基板中に周囲より機械的強度の小さい中間層を形成し、上記中間層を形成した基板の上記第一の窒化物半導体層の上に第二の窒化物半導体層をエピタキシャル成長させることを特徴とする窒化物半導体エピタキシャルウェハの製造方法。Ions are implanted from the front or back surface of the substrate on which the first nitride semiconductor layer is formed on the sapphire substrate, an intermediate layer having a mechanical strength lower than that of the surrounding is formed in the sapphire substrate, and the intermediate layer is formed. A method for producing a nitride semiconductor epitaxial wafer, wherein a second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer . 上記第一の窒化物半導体半導体層の厚さを5μm以下とする請求項に記載の窒化物半導体エピタキシャルウェハの製造方法。The method for manufacturing a nitride semiconductor epitaxial wafer according to claim 1 , wherein the thickness of the first nitride semiconductor semiconductor layer is 5 μm or less. 上記打ち込むイオンを水素イオン、窒素イオン、酸素イオンのいずれか若しくはそれらの混合とする請求項1または2に記載の窒化物半導体エピタキシャルウェハの製造方法。The method for producing a nitride semiconductor epitaxial wafer according to claim 1 or 2 , wherein the ions to be implanted are hydrogen ions, nitrogen ions, oxygen ions, or a mixture thereof. 上記イオンの打ち込みの加速電圧を1keV以上1MeV以下とし、かつ、上記イオンのドーズ量を1×1015cm-2以上1×1019cm-2以下とする請求項1からのいずれかに記載の窒化物半導体エピタキシャルウェハの製造方法。The acceleration voltage of the implantation of the ions and 1keV above 1MeV or less, and, according to any one of claims 1 to 3, the dose of the ion 1 × 10 15 cm -2 or more 1 × 10 19 cm -2 or less A method for manufacturing a nitride semiconductor epitaxial wafer. 上記イオンを打ち込んだ後で熱処理を行うことにより上記第一の窒化物半導体層の表面結晶層のイオン打ち込みによるダメージを回復させると共に、上記中間層に微細なボイド及びボイドの集合体を生じさせる請求項1からのいずれかに記載の窒化物半導体エピタキシャルウェハの製造方法。Claims of recovering damage caused by ion implantation of the surface crystal layer of the first nitride semiconductor layer by performing a heat treatment after implanting the ions, and generating fine voids and aggregates of voids in the intermediate layer Item 5. The method for producing a nitride semiconductor epitaxial wafer according to any one of Items 1 to 4 . 上記中間層を境にして上記サファイア基板を剥離、除去する請求項1からのいずれかに記載の窒化物半導体エピタキシャルウェハの製造方法。The method for producing a nitride semiconductor epitaxial wafer according to any one of claims 1 to 5 , wherein the sapphire substrate is peeled off and removed with the intermediate layer as a boundary. 上記第二の窒化物半導体層の表面に他の基板を貼り付けた後で上記中間層を境にして上記サファイア基板を剥離、除去する請求項に記載の窒化物半導体エピタキシャルウェハの製造方法。The method for producing a nitride semiconductor epitaxial wafer according to claim 6 , wherein after the other substrate is attached to the surface of the second nitride semiconductor layer, the sapphire substrate is peeled off and removed with the intermediate layer as a boundary. 上記他の基板としてSi基板、AlN基板、Cu基板、Al基板のいずれかを用いる請求項に記載の窒化物半導体エピタキシャルウェハの製造方法。The method for producing a nitride semiconductor epitaxial wafer according to claim 7 , wherein any one of a Si substrate, an AlN substrate, a Cu substrate, and an Al substrate is used as the other substrate. 上記除去、剥離した第二の窒化物半導体層の裏面に残ったサファイア基板の一部を研磨により部分的若しくは全て除去する請求項6から8のいずれかに記載の窒化物半導体エピタキシャルウェハの製造方法。The method for producing a nitride semiconductor epitaxial wafer according to any one of claims 6 to 8 , wherein a part or all of the sapphire substrate remaining on the back surface of the removed and peeled second nitride semiconductor layer is removed by polishing. .
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