JP4183556B2 - Display device and multi-display system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a daisy chain circuit used for daisy chaining a plurality of display devices, a display device having a daisy chain circuit, and a multi-display system configured by daisy chaining a plurality of display devices. It is about.
[0002]
[Prior art]
There is a proposal of a multi-display system that sequentially transmits a video signal, a synchronization signal, and the like to a subsequent display device by connecting a plurality of display devices in a daisy chain (see, for example, Patent Document 1 and Patent Document 2).
[0003]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-112252 (page 7-9, FIG. 2)
[Patent Document 2]
JP 2001-86428 A (page 4-7, FIG. 1)
[0004]
[Problems to be solved by the invention]
However, in the conventional multi-display system described above, re-sampling is not performed on the digital signal input to the first stage display device or the digital signal generated by AD conversion of the input analog signal. The digital signal is output to the subsequent display device. For this reason, as the display device at the subsequent stage becomes, the noise of the input digital signal (for example, in the case of daisy chain connection by a digital output circuit using a differential driver using a PLL and a digital input circuit, the jitter of the PLL) Noise and the like occur in the display image, and there is a problem that the number of stages of display devices that can be daisy chain connected is limited.
[0005]
Therefore, the present invention has been made to solve the above-described problems of the prior art, and the object thereof is a daisy chain circuit that can eliminate the limitation of the number of stages of display devices connected in a daisy chain, It is an object of the present invention to provide a display device including the same and a multi-display system configured by daisy chaining a plurality of such display devices.
[0006]
[Means for Solving the Problems]
  According to the present inventionThe display device receives a vertical synchronization signal, a horizontal synchronization signal, an input clock, and an input signal including image data. The display unit displays an image based on the input signal, and the input signal is input to the display device. A display device having a horizontal synchronization signal, an output clock, and a daisy chain circuit that outputs image data as an input signal of a subsequent display device, the daisy chain circuit including storage means and input image data; Write means for storing in the storage means in synchronization with an input clock, clock generation means for generating an output clock, horizontal sync signal for output using the output clock from the input horizontal sync signal and vertical sync signal, and Synchronizing signal generating means for generating a vertical synchronizing signal, and in synchronization with the output clock A reading means for reading image data from the storage means, and a control means for controlling operations of the writing means and the reading means, and a vertical synchronizing signal and a horizontal synchronizing signal generated by the synchronizing signal generating means, and the output Output the clock and the image data read from the storage means as the input signal of the display device in the subsequent stageTo do.
[0007]
  Further, according to the present inventionThe multi-display system is a multi-display system having display devices from the first stage to the p-th (p is an integer of 2 or more) stages connected in series, the display devices from the first stage to the p-th stage Each of which is inputted with an input signal including a vertical synchronization signal, a horizontal synchronization signal, an input clock, and image data, and a display unit for displaying an image based on the input signal, and the input signal is inputted, and a vertical synchronization signal, A daisy chain circuit that outputs a horizontal synchronization signal, an output clock, and image data as an input signal of a display device at a subsequent stage, wherein the daisy chain circuit synchronizes the input image data with the input clock. Writing means for storing in the storage means, clock generating means for generating an output clock, Synchronization signal generation means for generating a horizontal synchronization signal and a vertical synchronization signal for output from the input horizontal synchronization signal and vertical synchronization signal using the output clock, and image data from the storage means in synchronization with the output clock. A reading means for reading, and a control means for controlling the operation of the writing means and the reading means, from the vertical synchronizing signal and horizontal synchronizing signal generated by the synchronizing signal generating means, the output clock, and the storage means Outputs the read image data as an input signal for the display device at the subsequent stage.To do.
[0008]
  Furthermore, the multi-display system according to the present invention is a multi-display system having display devices from the first stage to the p-th stage (p is an integer of 2 or more) connected in series, the first stage to the first stage. Each of the display devices up to p-stage receives a vertical synchronization signal, a horizontal synchronization signal, an input clock, and an input signal including image data, and displays an image based on the input signalEach of the display devices from the first stage to the (p−1) th stage is supplied with the input signal, and displays the vertical synchronization signal, horizontal synchronization signal, output clock, and image data at the subsequent stage. A daisy chain circuit that outputs as an input signal, and the daisy chain circuit generates a storage means, a writing means for storing input image data in the storage means in synchronization with the input clock, and an output clock Clock generating means for generating, using the output clock from the input horizontal synchronizing signal and vertical synchronizing signal, synchronizing signal generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal for output, and in synchronization with the output clock Read means for reading image data from the storage means, and control means for controlling operations of the write means and the read means Has the door, said generated by the synchronization signal generating means a vertical synchronizing signal and a horizontal synchronizing signal, outputs the output clock, and the image data read out from said memory means as an input signal for subsequent display deviceTo do.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
[Description of Multi-Display System and Display Device]
FIG. 1 is a block diagram schematically showing a configuration of a multi-display system (and a configuration of a display device) according to Embodiment 1 of the present invention. As shown in FIG. 1, the multi-display system of the first embodiment is from the first stage to the p-th stage (p is an integer of 2 or more, for example, 4, 9, 16, 25, etc.). , 100-p and signal lines for daisy chain connecting the display devices 100-1, 100-2,..., 100-p are the main components. The first-stage display device 100-1 includes, for example, a vertical synchronization signal, a horizontal synchronization signal, an input clock (dot clock), image data (analog or digital video signal), and image data from a personal computer (PC) or the like. A data enable signal (DEN signal) indicating the valid period of the image is received, and an image is displayed on its own display unit 6, and is transmitted to its subsequent display device 100-2 via its own daisy chain circuit 7 and digital output circuit 8. A vertical synchronizing signal, a horizontal synchronizing signal, an output clock (dot clock), image data (digital video signal), and a DEN signal are transmitted. Similarly to the first-stage display device 100-1, the second-stage display device 100-2 and the subsequent display devices also have a vertical synchronization signal, a horizontal synchronization signal, an input clock (that is, an output clock output from the previous-stage display device). ), Image data (digital video signal), and DEN signal, and displays an image on its own display unit 6, and through its own daisy chain circuit 7 and digital output circuit 8, A vertical synchronizing signal, a horizontal synchronizing signal, an output clock, image data, and a DEN signal are sent to the input circuit 2.
[0010]
As shown in FIG. 1, each of the display devices 100-1, 100-2,..., 100-p is a digital device that receives an input digital signal when the input image data is input as a digital signal. An input circuit 2, an analog / digital conversion circuit (AD input circuit) 3 that receives an input analog signal and converts it into a digital signal when the input image data is input as an analog signal, and a digital input circuit 2 and a selector circuit 4 that selects and outputs either the output of the AD input circuit 3 or the output of the AD input circuit 3.
[0011]
In addition, each display device 100-1, 100-2,..., 100-p converts the resolution of the input image data (or cuts out a part of the input image data and the resolution of the extracted image data). And a display unit 6 that receives a vertical synchronization signal, a horizontal synchronization signal, an input clock, image data, and a DEN signal and displays an image based on these signals. Further, each display device 100-1, 100-2,..., 100-p receives a vertical synchronizing signal, a horizontal synchronizing signal, an input clock, image data, and a DEN signal, and outputs a vertical synchronizing signal, a horizontal synchronizing signal, and an output. A daisy chain circuit 7 for outputting a clock, image data, and a DEN signal (which may be different from the DEN signal input to the pixel conversion circuit 5), and an output from the daisy chain circuit 7 as a digital input circuit for a display device in the subsequent stage 2 and a digital output circuit 8 for sending out the signal.
[0012]
In FIG. 1, a digital signal and / or an analog signal output from a PC or the like (not shown) is input to the digital input circuit 2 and / or the AD input circuit 3 in the first stage display device 100-1. The output of the digital input circuit 2 and the output of the AD input circuit 3 are input to the selector circuit 4. The selector circuit 4 selects either the output of the digital input circuit 2 or the output of the AD input circuit 3 and outputs it to the pixel conversion circuit 5 and the daisy chain circuit 7. However, the number of input signals is not limited to two, and may be three or more. For example, there may be a configuration in which there are two analog signal inputs and one digital signal input, and the selector circuit 4 selects any one of these inputs.
[0013]
The pixel conversion circuit 5 enlarges / reduces the input image data, converts the image data into a signal format that can be displayed by the display unit 6, and outputs the signal format to the display unit 6. For example, when the monitor resolution of the display unit 6 is XGA (1024 × 768 pixels) and a VGA (640 × 480 pixel) signal is input to the input signal, the pixel conversion circuit 5 converts the input signal to 1024 ×. The size is changed to 768 pixels and output to the display unit 6. In addition, a part of the image data input in the pixel conversion circuit 5 can be enlarged and displayed at the monitor resolution of the display unit 6.
[0014]
The daisy chain circuit 7 (shown in FIG. 3) re-samples input image data by temporarily writing the input image data into the memory using the input clock (write clock) WCLK and reading it from the memory using the output clock (read clock) RCLK. I do. In this case, the effective period of the video signal output from the daisy chain circuit 7 (period in which the DEN signal is at a high level) is a period corresponding to the entire effective image area included in the input image data. This is not necessarily the same as the period corresponding to the partially enlarged video area.
[0015]
The digital signal output from the digital output circuit 8 of the first stage display apparatus 100-1 is input to the digital input circuit 2 of the second stage display apparatus 100-2. The selector circuit 4 of the second-stage display device 100-2 selects the digital input circuit 2, and displays the image on the display unit 6 as well as the daisy chain circuit similarly to the first-stage display device 100-1. 7, the input digital signal is resampled with the output clock RCLK, and the digital signal is sent to the subsequent display device via the digital output circuit 8. The display devices 100-3,..., 100-p after the third stage operate in the same manner.
[0016]
FIG. 2 is a diagram showing a display screen when the multi-display system according to Embodiment 1 is configured by nine display devices arranged in three rows and three columns. In FIG. 2, the multi-display system is configured such that the display units 6 of the nine display devices 100-1,..., 100-9 are arranged in 3 rows and 3 columns to display a large screen. As shown in FIG. 2, the digital output circuit and the digital input circuit of each display device are connected in the order of the first to ninth display devices 100-1,... If input to the display device 100-1 of the first stage, the signals input to the display device 100-1 of the first stage are sequentially transmitted to the display devices 100-2, ..., 100-9 of the second to ninth stages. Is done. In the first embodiment, data of the entire effective image area (effective image data) among the image data input to the first-stage display device 100-1 is sequentially transmitted. Further, in the pixel conversion circuit of each display device, a necessary area in the effective image area is cut out, and the cut-out area is enlarged. As a result, as shown in FIG. 2, an image based on the input image data can be enlarged and displayed on one entire screen constituted by a plurality of screens constituting the multi-display system.
[0017]
For example, in FIG. 1, an analog signal input to the first stage display apparatus 100-1 is digitized into 8 bits each of R, G, and B by the AD input circuit 3, and the subsequent stage display apparatus 100- Enter in 2. Therefore, noise caused by the quantization error of the AD converter in the AD input circuit 3 of each of the subsequent display devices 100-2,..., 100-p does not occur in the image data, and a multi-display system is configured. The image quality between the screens of the display devices 100-1,..., 100-p can be kept uniform. Here, in the digital output circuit 8 of a certain display device and the digital input circuit 2 of the subsequent display device, for example, a TMDS (Transition Minimized Differential Signaling) type driver and receiver are used. In order to perform TMDS signal transmission, the digital output circuit 8 has a PLL circuit therein and converts R, G, B signals input in parallel at 8 bits into differential serial signals and outputs them. On the other hand, in the digital input circuit 2, the transmitted differential serial signal is converted into an 8-bit parallel signal for each of R, G, and B.
[0018]
The daisy chain circuit 7 in each display device 100-1,..., 100-p is, for example, from VGA (640 × 480 pixels) 60 Hz (vertical frequency 60 Hz) to UXGA (1600 × 1200 pixels) 60 Hz (vertical frequency 60 Hz). When the video signal is input, data is written to the memory in synchronization with the input clock input, and data is read from the memory in synchronization with the output clock. In this case, the output clock used in the daisy chain circuit 7 is set to the highest frequency of a signal that can be input. That is, when the input signal supports signals from VGA 60 Hz (clock 25.17 MHz) to UXGA 60 Hz (clock 162 MHz), the output clock is set to 162 MHz which is the highest frequency of the input signal.
[0019]
Temporarily, a driver and a receiver having a PLL circuit are used for data transmission between the display devices 100-1,..., 100-p, and image data input to the digital output circuit 8 includes PLL noise during AD conversion. If present, the PLL noise is amplified in the subsequent digital output circuit 8 and the digital input circuit 2 and propagates to the subsequent display device. On the other hand, in the multi-display system of the first embodiment, the daisy chain circuit 7 always resamples the input signal with a stable output clock (fixed clock), so that PLL jitter generated at the time of signal input is displayed in the subsequent stage. It does not propagate to the device. Therefore, no matter how many display devices are connected by a daisy chain as shown in FIG. 1, an image error due to noise such as PLL jitter does not occur in the display device in the subsequent stage of the daisy chain.
[0020]
In the above description, the case where the selector circuit 4 is a circuit that outputs either the output of the digital input circuit 2 or the output of the AD input circuit 3 to the pixel conversion circuit 5 and the daisy chain circuit 7 is exemplified. The selector circuit 4 outputs either the output of the digital input circuit 2 or the output of the AD input circuit 3 to the pixel conversion circuit 5 and daisy-chains either the output of the digital input circuit 2 or the output of the AD input circuit 3. A matrix switch circuit that outputs to the chain circuit 7 may be used. In this case, for example, the output of the AD input circuit 3 can be input to the pixel conversion circuit 5 and the output of the digital input circuit 2 can be input to the daisy chain circuit 7.
[0021]
In the above description, the display devices 100-1, 100-2,..., 100-p have the same configuration, but the display devices 100-1, 100-2,. Except for the AD input circuit 3 and the selector circuit 4, the output of the digital input circuit 2 is directly input to the pixel conversion circuit 5 and the daisy chain circuit 7 in each of the display devices 100-1, 100-2,. It is good.
[0022]
Further, the digital input circuit 2 and the selector circuit 4 are removed from the first stage display device 100-1, and the output of the AD input circuit 3 is sent to the pixel conversion circuit 5 and the daisy chain circuit 7 in the first stage display device 100-1. The second stage to the p-th stage display device 100-2, except that the AD input circuit 3 and the selector circuit 4 are excluded from the second to p-th stage display devices 100-2,..., 100-p. ,..., 100-p, the output of the digital input circuit 2 may be directly input to the pixel conversion circuit 5 and the daisy chain circuit 7.
[0023]
Furthermore, the configuration may be such that the daisy chain circuit 7 and the digital output circuit 8 are excluded from the p-th stage display device 100-p which is the final stage.
[0024]
[Description of Daisy Chain Circuit]
FIG. 3 is a block diagram schematically showing the configuration of the daisy chain circuit 7 according to the first embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the daisy chain circuit 7 of FIG.
[0025]
As shown in FIG. 3, the daisy chain circuit 7 includes an input terminal (V signal input terminal) 21 for a vertical synchronization signal VSYNC, an input terminal (H signal input terminal) 22 for a horizontal synchronization signal HSYNC, and an input clock WCLK. It has an input terminal 23 and an input terminal 24 for RGB 8-bit image data (R [7: 0], G [7: 0], B [7: 0]). The daisy chain circuit 7 includes a vertical / horizontal synchronization signal generation circuit (output H and V signal generation circuit) 25, an input horizontal synchronization signal measurement circuit (input H measurement circuit) 26, and an output horizontal synchronization signal measurement circuit (output). H measurement circuit) 27, a control circuit 28, a write address generation circuit 29, a read address generation circuit 30, a memory 31, and an output fixed clock oscillation circuit 32 that generates an output clock RCLK. Further, the daisy chain circuit 7 includes a vertical synchronization signal output terminal (V signal output terminal) 33, a data enable signal (DEN signal) output terminal 34, a horizontal synchronization signal output terminal (H signal output terminal) 35, It has an output terminal 36 for an output clock RCLK and an output terminal 37 for output image data (R [7: 0], G [7: 0], B [7: 0]) each having 8 bits for RGB.
[0026]
The output H and V signal generation circuit 25 latches and outputs the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC input from the V signal input terminal 21 and the H signal input terminal 22 with the output clock RCLK. However, the method of generating the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC is not limited to the method of latching data with the output clock RCLK, and can be generated by other methods. The horizontal synchronization signal output from the output H and V signal generation circuit 25 is input to the output H measurement circuit 27 and the period is counted by the output clock RCLK. On the other hand, the horizontal synchronizing signal HSYNC input from the H signal input terminal 22 is input to the input H measuring circuit 26 and counts the period by the input clock WCLK. The measurement results of the input H measurement circuit 26 and the output H measurement circuit 27 are input to the control circuit 28, and the control circuit 28 controls the write address generation circuit 29 and the read address generation circuit 30 based on these measurement results.
[0027]
For example, as shown in FIG. 4, the control circuit 28 controls the write address generation circuit 29, the read address generation circuit 30, and the memory 31. In FIG. 4, when the measurement result of the input H measurement circuit 26 is n and the measurement result of the output H measurement circuit 27 is m (m> n), it is input in one cycle of the horizontal synchronization signal (that is, 1H period). All data is written to the memory 31. Here, the memory 31 is, for example, a dual port memory. In other words, the address counter of the write address generation circuit 29 is reset with reference to the falling edge of the horizontal synchronization signal HSYNC, and address control is performed so that n pieces of data are written in the memory 31.
[0028]
On the other hand, when reading data from the memory 31, the address counter of the read address generation circuit 30 is loaded with nm at the falling edge of the horizontal synchronizing signal, counted up by the output clock RCLK, and the value of the read counter is n. Data is not read between −m and −1, and the address control is performed so that the read counter starts reading data from the memory 31 in the period from 0 to n. Further, the control circuit 28 outputs a DEN signal (high level in the effective period) indicating the effective period of the read data.
[0029]
As described above, in the daisy chain circuit 7, as shown in FIG. 4, the 1H period of the input signal is the input clock WCLK for the n clock width signal, and the 1H period is the output clock (fixed clock) RCLK for m clocks. While converting to a width signal format and re-sampling the image data with an output clock RCLK that is completely different from the input clock WCLK, the horizontal period of the signal itself is not changed. Further, the entire effective area of the image data can be output as daisy chain data to a subsequent display device.
[0030]
In FIG. 4, the memory capacity required for the memory 31 is the memory 31 when the memory is of the address cyclic type (the access order is the address order and the system returns to the first address when the final address is reached). The amount of data written (written) before the start of reading (reading) from the memory becomes the minimum required memory capacity. Therefore, the memory capacity required for the memory 31 is maximized when the difference between the output clock RCLK and the input clock WCLK is maximized, that is, when the signal input to the display device has the lowest frequency.
[0031]
For example, when the output clock RCLK is 162 MHz and the input lowest frequency signal is VGA 60 Hz (clock 25.17 MHz), the measurement result of the input H measurement circuit 26 is n = 800, and the measurement result of the output H measurement circuit 27 is m = 4352, and when reading from the memory 31 is started (in FIG. 4, mn clocks have elapsed), the memory 31 has
(Mn) × n / m
= (4352-800) x 800/4352
= 653 words
Data must be written. Therefore, in this case, the capacity of the memory 31 needs to be at least 654 words. In this case, the read counter of the output H measurement circuit 27 is a 13-bit signed counter, and the write counter of the input H measurement circuit 26 is 12 bits (when the horizontal direction corresponds to up to 4096 pixels).
[0032]
However, when the memory 31 is an address cyclic type, as shown in FIG. 4, the read counter is a signed 14-bit cyclic counter and the write counter is an 11-bit counter, both of which operate at multiples of 2. To simplify the control, the memory 31 has a capacity of 1024 words. Since nm = -3552, the read counter of FIG. 4 requires a 13-bit counter. Therefore, in the case of the VGA 60 Hz signal, the control circuit 28 loads mn = −3552 = (1220H) into the read counter at the falling edge of the horizontal synchronization signal HSYNC in FIG. Control is performed so that data is read from the memory 31 when becomes zero.
[0033]
If the memory 31 is controlled as described above, the address control is performed so that the timing at which the last data in the 1H period is written and the timing at which the last data in the 1H period is read are the same as shown in FIG. Therefore, overtaking of data in the memory 31 does not occur. In a normal dual port memory, a certain time is required until data can be read after data is written to the memory. In the case of FIG. 4, the control of the memory is controlled by the horizontal synchronization signal HSYNC. Since the counter is reset with reference to the falling edge of, the last data written to the memory is always invalid data, so no problem occurs.
[0034]
In the above description, the case where the image data is handled by single pixels of 8 bits for each of R, G, and B is exemplified. However, it is not always necessary to handle the image data by single pixels. The frequency of the clock WCLK and the output clock RCLK may be halved.
[0035]
In the above description, the timing of data writing to the memory 31 is based on the rising edge of the horizontal synchronization signal HSYNC. However, since image data in the horizontal direction usually has a front porch for several clocks, Data writing may be started with reference to the falling edge of the horizontal synchronization signal HSYNC. Further, the reference for determining the timing of data writing and reading to the memory 31 may be configured to be selectable for either falling or rising of the horizontal synchronization signal HSYNC.
[0036]
Furthermore, although the case where the output clock is set to the highest frequency of the input signal has been exemplified in the above description, it may be set to a frequency higher than the highest frequency of the input signal.
[0037]
Furthermore, in the above description, the case where a dual port memory is used as the memory 31 is illustrated, but the dual port memory is not necessarily used, and the same effect can be obtained even if a FIFO memory or the like is used.
[0038]
Embodiment 2. FIG.
In the first embodiment, as shown in FIG. 1, the case where the selector circuit 4 selects and outputs either the output of the digital input circuit 2 or the output of the AD input circuit 3 has been described. In the second embodiment, as shown in FIG. 5, the output of the digital input circuit 2, the output of the AD input circuit 3, and the output of the video input circuit 9 are switched by a matrix switch circuit 10. The multi-display system and the display device according to the second embodiment are provided with the video input circuit 9 and the matrix switch circuit 10 instead of the selector circuit. Different from the device.
[0039]
FIG. 5 is a block diagram schematically showing the configuration of the multi-display system (and the configuration of the display device) according to Embodiment 2 of the present invention. In FIG. 5, the same or corresponding components as those in FIG. As shown in FIG. 5, the multi-display system according to the second embodiment includes a plurality of stages of display devices 110-1, 110-2,... Connected in a daisy chain, and display devices 110-1, 110-2,. The signal lines that connect them are the main components. The first-stage display device 110-1 receives, for example, a vertical synchronization signal, a horizontal synchronization signal, an input clock, image data, and a data enable signal (DEN signal) indicating the valid period of the image data from a PC or the like, and displays them. An image is displayed on the unit 6, and a vertical synchronizing signal, a horizontal synchronizing signal, an output clock, image data, and a DEN signal are sent to the display device 110-2 at the subsequent stage via the daisy chain circuit 7. Similarly to the first stage display apparatus 110-1, the display apparatuses after the second stage display apparatus 110-2 receive the vertical synchronization signal, the horizontal synchronization signal, the input clock, the image data, and the DEN signal. In addition to displaying an image, a vertical synchronizing signal, a horizontal synchronizing signal, an output clock, image data, and a DEN signal are sent to the subsequent display device via the daisy chain circuit 7.
[0040]
The matrix switch circuit 10 of the first-stage display device 110-1 outputs any one of the output of the digital input circuit 2, the output of the AD input circuit 3, and the output of the video input circuit 9 to the pixel conversion circuit 5, Any one of the output of the digital input circuit 2, the output of the AD input circuit 3, and the output of the video input circuit 9 is output to the daisy chain circuit 7. Similarly, the matrix switch circuit 10 of the display devices 110-2,... In the second and subsequent stages also uses one of the output of the digital input circuit 2, the output of the AD input circuit 3, and the output of the video input circuit 9 as a pixel conversion circuit. 5, and any one of the output of the digital input circuit 2, the output of the AD input circuit 3, and the output of the video input circuit 9 is output to the daisy chain circuit 7.
[0041]
For example, the matrix switch circuit 10 of the first stage display device 110-1 selects the image of the AD input circuit 3 and outputs it to the pixel conversion circuit 5, and simultaneously the image from the video input circuit 9 is sent to the daisy chain circuit 7. Is selected and output, the display device 110-1 displays an image based on the input AD signal, and the display device 110-1 displays the video signal on the subsequent display device 110-2,. Can be sent and displayed.
[0042]
As described above, according to the multi-display system of the second embodiment, the matrix switch circuit 10 is provided in each display device, so that each display device can freely combine inputs from the daisy chain with other inputs. Thus, various display patterns can be displayed in the multi-display system.
[0043]
In the second embodiment, the case where three types of signals are input to each display device has been described. However, the number of input signals is not limited to three types, and may be two types or four or more types. . For example, there may be two analog signal inputs, two video signal inputs, and one digital signal input, and the matrix switch circuit 10 may select one of these inputs. Good.
[0044]
In the second embodiment, the points other than the above are the same as those in the first embodiment.
[0045]
Embodiment 3 FIG.
FIG. 6 is a timing chart showing the operation of the daisy chain circuit according to the third embodiment of the present invention. In the first embodiment, the control circuit 28 of the daisy chain circuit 7 writes all the data for the 1H period of the input signal in the memory 31 as shown in FIG. On the other hand, in the third embodiment, as shown in FIG. 6, memory control is performed so that only image data (“Write valid data” in FIG. 6) of an image valid period is written in the memory 31.
[0046]
In the case of FIG. 6, the effective period within the 1H period of the input signal (the “memory writing period” in FIG. 6) is the i + 1 clock, and the back porch period from the falling edge of the horizontal synchronization signal HSYNC to the start of the effective data Is j clocks, data is written to the memory 31 in the valid period (i + 1 clocks) after being counted by j clocks by the write address counter of FIG. On the other hand, on the data reading side, if data reading from the memory 31 is started when the read counter is counted mn−j, the memory 31 is controlled without causing overtaking in the memory. Can do.
[0047]
In this case, as for the capacity of the memory 31, the amount of data written before reading from the memory is the minimum memory capacity. That is, when the output clock is 162 MHz and the signal having the lowest frequency of the input signal is VGA 60 Hz (clock 25.17 MHz), the measurement result of the input H measurement circuit 26 is n = 800, from the falling edge of the horizontal synchronization signal HSYNC. The back porch up to the valid data is j = 136 clocks, and the measurement result of the output H measurement circuit 27 is m = 4352, and at the start of reading from the memory 31, the memory 31
(M−n−j) × n / m
= (4352−800−136) × 800/4352 = 628 words is the minimum required memory capacity.
[0048]
As described above, the memory capacity required in the memory 31 can be reduced by controlling the control circuit 28 of the daisy chain circuit 7 so that data is written into the memory 31 only during the data valid period. Further, since data read / write access is performed only during the valid period, the data in the invalid data period within one cycle (1H) of the horizontal synchronization signal can be masked to a fixed value.
[0049]
In FIG. 6 of the third embodiment, the reset of the write counter and the read counter is based on the falling edge of the horizontal synchronization signal HSYNC. However, the reset is not necessarily the falling edge, and the rising edge is used as a reference. Good.
[0050]
Further, in the third embodiment, the points other than the above are the same as those in the first or second embodiment.
[0051]
Embodiment 4 FIG.
In the first and third embodiments, the case where the output clock RCLK used in the daisy chain circuit 7 is fixed to the highest frequency of the signal that can be input to the daisy chain circuit 7 has been described. However, as shown in FIG. 7, the daisy chain circuit is provided with a clock frequency dividing circuit that divides the output fixed frequency by 1 / k, and the output clock RCLK used in the daisy chain circuit according to the input signal to the daisy chain circuit. You may comprise so that it can change.
[0052]
FIG. 7 is a block diagram schematically showing a configuration of a daisy chain circuit according to the fourth embodiment of the present invention. As shown in FIG. 7, the daisy chain circuit according to the fourth embodiment includes an input terminal (V signal input terminal) 21 for a vertical synchronization signal VSYNC, an input terminal (H signal input terminal) 22 for a horizontal synchronization signal HSYNC, It has an input terminal 23 for an input clock WCLK and an input terminal 24 for RGB image data (R [7: 0], G [7: 0], B [7: 0]) for each of RGB. The daisy chain circuit according to the fourth embodiment includes a vertical / horizontal synchronization signal generation circuit (output H and V signal generation circuit) 25, an input horizontal synchronization signal measurement circuit (input H measurement circuit) 26, and an output horizontal synchronization signal. A measurement circuit (output H measurement circuit) 27, a control circuit 40, a write address generation circuit 29, a read address generation circuit 30, a memory 31, an output fixed clock oscillation circuit 32 that generates a fixed clock, and an output fixed clock And a clock frequency dividing circuit 41 that divides the fixed clock generated by the oscillation circuit 32 to generate the output clock RCLK. Furthermore, the daisy chain circuit of the fourth embodiment includes a vertical synchronization signal output terminal (V signal output terminal) 33, a data enable signal (DEN signal) output terminal 34, and a horizontal synchronization signal output terminal (H signal output terminal). ) 35, an output terminal 36 for the output clock RCLK, and an output terminal 37 for output image data (R [7: 0], G [7: 0], B [7: 0]) of 8 bits for each of RGB. .
[0053]
Of the configuration shown in FIG. 7, the circuits other than the control circuit 40 and the clock frequency dividing circuit 41 operate in the same manner as the configuration with the same reference numeral shown in FIG. 3 (Embodiment 1).
[0054]
As for the capacity of the memory 31, the amount of data written (written) before the start of reading (reading) of data from the memory 31 is the minimum memory capacity. This maximizes the memory capacity required when the difference between the frequency of the input signal and the output frequency is the largest. Therefore, when the frequency of the input signal is low, the memory 31 is controlled by dividing the output of the output fixed clock oscillation circuit 32 by the clock frequency dividing circuit 41 so as to reduce the difference between the output frequency and the input frequency. It is possible to reduce the required capacity.
[0055]
Next, the operation of the control circuit 40 will be described. The control circuit 40 outputs the count value n of the horizontal synchronization signal HSYNC by the input clock WCLK output from the input H measurement circuit 26 and the horizontal synchronization signal HSYNC by the output clock RCLK output from the output H measurement circuit 27. One cycle count value m is input. In this case, the minimum required capacity TMemW for the memory 31 is given by the following equation.
TMemW = (mn) × n / m
If the storage capacity of the memory 31 is MemW, the control circuit 40
MemW> TMemW
The clock frequency divider circuit 41 is controlled so that the clock frequency divider circuit 41 performs 1 / k frequency division. When the clock frequency dividing circuit 41 performs 1 / k frequency division, the output m of the output H measuring circuit 27₀Becomes m / k. At this time, the minimum required capacity TMemW for the memory 31 is expressed by the following equation.
TMemW = (m₀-N) * n / m₀
Therefore, the control circuit 40
MemW> TMemW = (m₀-N) * n / m₀
The frequency division ratio k of the clock frequency dividing circuit 41 is selected so that
[0056]
For example, when the capacity MemW of the memory 31 is 256 words, the output clock of the output fixed clock oscillation circuit 32 is 162 MHz, and the input signal is VGA 60 Hz (clock 25.17 MHz), the result of the input H measurement circuit 26 is n = 800, output H The measurement result m of the measurement circuit 27 is 4352. At this time, the minimum required capacity TMemW for the memory 31 is expressed by the following equation.
TMemW = (4352 / k−800) × 800 <256
When k = 2 is selected
TMemW = (4352 / 2-800) × 800 = 253 <256
Thus, since it falls within the capacity range of the memory 31, an error such as overtaking does not occur. In this case, the fixed frequency of the output clock RCLK is 162/2 = 81 MHz.
[0057]
As described above, in the daisy chain circuit according to the fourth embodiment, the control circuit 40 determines the frequency division ratio k of the clock frequency dividing circuit 41. When the frequency division ratio is changed by the control circuit 40, the frequency of the output H measurement circuit 27 is measured again at the output fixed frequency after frequency division, and the write to the memory 31 is performed according to FIG. 4 as in the first embodiment. Controls address and read address. In this case, the signal output from the display device 100-1 (the output from the daisy chain circuit) is resampled with a fixed clock divided by 1 / k and is output to the subsequent display device.
[0058]
As described above, the memory capacity required for the memory 31 can be reduced by changing the output frequency division ratio k based on the difference between the count results of the input H measurement circuit 26 and the output H measurement circuit 27. .
[0059]
In the fourth embodiment, points other than those described above are the same as those in the first to third embodiments.
[0060]
In the above description of the first to fourth embodiments, the image data of each color of R, G, and B has been described as being 8 bits. However, the present invention is not limited to 8-bit image data. The present invention can also be applied to image data of 7 bits or less or 9 bits or more.
[0061]
【The invention's effect】
As described above, the daisy chain circuit of the present invention generates an output clock different from the input clock, resamples the input image data using this output clock, and outputs it. Therefore, according to the daisy chain circuit, the display device, and the multi-display system of the present invention, the number of display devices that can be daisy chain connected without propagating noise such as clock jitter to the subsequent device is limited. There is an effect that can be eliminated.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a configuration of a multi-display system (and a configuration of a display device) according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a display screen when the multi-display system according to the first embodiment is configured by nine display devices arranged in three rows and three columns.
FIG. 3 is a block diagram schematically showing a configuration of a daisy chain circuit according to the first embodiment.
FIG. 4 is a timing chart showing an operation of the daisy chain circuit according to the first embodiment.
FIG. 5 is a block diagram schematically showing a configuration of a multi-display system (and a configuration of a display device) according to Embodiment 2 of the present invention.
FIG. 6 is a timing chart showing an operation of the daisy chain circuit according to the third embodiment of the present invention.
FIG. 7 is a block diagram schematically showing a configuration of a daisy chain circuit according to a fourth embodiment of the present invention.
[Explanation of symbols]
100-1, ..., 100-p display device, 110-1,110-2, ... display device, 2 digital input circuit, 3 analog / digital conversion circuit (AD input circuit), 4 selector circuit, 5 pixel conversion circuit, 6 display unit, 7 daisy chain circuit, 8 digital output circuit, 9 video input circuit, 10 matrix switch circuit, 25 horizontal / vertical synchronization signal generation circuit (H, V generation circuit), 26 input horizontal synchronization signal measurement circuit (input H) Measurement circuit), 27 output horizontal synchronization signal measurement circuit (output H measurement circuit), 28, 40 control circuit, 29 write address generation circuit, 30 read address generation circuit, 31 memory, 32 output fixed clock oscillation circuit, 41 clock division Circuit, VSYNC vertical sync signal, SYNC Horizontal synchronization signal, WCLK input clock, RCLK output clock, DEN data enable signal, DATA image data.

Claims (17)

A display unit for receiving an input signal including a vertical synchronization signal, a horizontal synchronization signal, an input clock, and image data, and displaying an image based on the input signal;
A display device having a daisy chain circuit that receives the input signal and outputs a vertical synchronization signal, a horizontal synchronization signal, an output clock, and an image data as an input signal of a subsequent display device;
The daisy chain circuit is
Storage means;
Writing means for storing input image data in the storage means in synchronization with the input clock;
Clock generation means for generating an output clock;
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal for output from the input horizontal synchronization signal and vertical synchronization signal using the output clock;
Reading means for reading out image data from the storage means in synchronization with the output clock;
Control means for controlling operations of the writing means and the reading means;
Have
Display device and outputs the synchronizing signal the vertical synchronizing signal generated by the generation means and horizontal synchronizing signal, the output clock, and the image data read out from said memory means as an input signal for subsequent display device . The daisy chain circuit is
First measuring means for measuring a value n obtained by counting one period of an input horizontal synchronizing signal with the input clock;
Second measuring means for measuring a value m (m> n) obtained by counting one period of the input horizontal synchronizing signal with the output clock;
Have
When the second measuring unit counts mn from the start point of one cycle of the input horizontal synchronization signal, the output of the image data of one cycle of the horizontal synchronization signal from the storage unit is started. The control means controls the reading means
The display device according to claim 1. 3. The display device according to claim 1, wherein the control unit controls the writing unit and the reading unit so that writing and reading of data to and from the storage unit are performed in an address cyclic manner. . 4. The display according to claim 1, wherein the control unit controls the writing unit so that data is written into the storage unit only during an effective period of image data. 5. apparatus. The clock generation means includes a fixed clock generation means for generating a fixed clock; and a frequency dividing means for dividing the frequency of the fixed clock to generate the output clock;
The control means sets a frequency dividing ratio of the frequency dividing means according to the frequency of the input clock and the frequency of the fixed clock generated by the fixed clock generating means.
The display device according to claim 1, wherein the display device is a display device. Display device according to any one of claims 1 to 5, characterized in that it comprises a pixel converter for converting all or part of the resolution of the image data input to the display unit. 7. The apparatus according to claim 6 , further comprising digital input means for receiving the input digital signal and outputting it to the pixel conversion means and the daisy chain circuit when the input image data is input as a digital signal. The display device as described. Digital input means for receiving an input digital signal when the input image data is input as a digital signal;
A plurality of video input means for receiving a plurality of other video signals and outputting a digital signal;
One of the output of the digital input means and the output of the plurality of video input means is output to the pixel conversion means, and one of the output of the digital input means and the outputs of the plurality of video input means The display device according to claim 6 , further comprising: a switch unit that outputs a signal to the daisy chain circuit. A multi-display system having display devices from a first stage to a p-th stage (p is an integer of 2 or more) connected in series,
Each of the display devices from the first stage to the p-th stage
A display unit for receiving an input signal including a vertical synchronization signal, a horizontal synchronization signal, an input clock, and image data, and displaying an image based on the input signal;
Wherein the input signal is input, a vertical sync signal, horizontal sync signal, the output clock, and the image data and a daisy chain circuit which outputs as an input signal for subsequent display equipment,
The daisy chain circuit is
Storage means;
Writing means for storing input image data in the storage means in synchronization with the input clock;
Clock generation means for generating an output clock;
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal for output from the input horizontal synchronization signal and vertical synchronization signal using the output clock;
Reading means for reading out image data from the storage means in synchronization with the output clock;
Control means for controlling operations of the writing means and the reading means;
Have
A multi-display that outputs the vertical and horizontal synchronization signals generated by the synchronization signal generation means, the output clock, and the image data read from the storage means as input signals of a display device at a subsequent stage. system. 10. The display device according to claim 9 , wherein each of the display devices from the first stage to the p-th stage has pixel conversion means for converting the resolution of all or part of image data input to the display unit. Multi-display system. Each of the display devices from the first stage to the p-th stage receives the inputted digital signal when the inputted image data is inputted as a digital signal, and sends it to the pixel converting means and the daisy chain circuit. 11. The multi-display system according to claim 10 , further comprising digital input means for outputting. Each of the display devices from the first stage to the p-th stage
Digital input means for receiving an input digital signal when the input image data is input as a digital signal;
A plurality of video input means for receiving a plurality of other video signals and outputting a digital signal;
One of the output of the digital input means and the output of the plurality of video input means is output to the pixel conversion means, and one of the output of the digital input means and the outputs of the plurality of video input means The multi-display system according to claim 10 , further comprising: a switch unit that outputs a signal to the daisy chain circuit. A multi-display system having display devices from a first stage to a p-th stage (p is an integer of 2 or more) connected in series,
Each of the display devices from the first stage to the p-th stage includes a display unit that receives an input signal including a vertical synchronization signal, a horizontal synchronization signal, an input clock, and image data, and displays an image based on the input signal. Have
Each of the display device from the first stage to the (p-1) stage, wherein the input signal is inputted, the vertical synchronizing signal, horizontal synchronizing signal, the output clock, and the image data subsequent display equipment of an input signal A daisy chain circuit that outputs as
The daisy chain circuit is
Storage means;
Writing means for storing input image data in the storage means in synchronization with the input clock;
Clock generation means for generating an output clock;
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal for output from the input horizontal synchronization signal and vertical synchronization signal using the output clock;
Reading means for reading out image data from the storage means in synchronization with the output clock;
Control means for controlling operations of the writing means and the reading means;
Have
A multi-display that outputs the vertical and horizontal synchronization signals generated by the synchronization signal generation means, the output clock, and the image data read from the storage means as input signals of a display device at a subsequent stage. system. 14. The display device according to claim 13 , wherein each of the display devices from the first stage to the p-th stage has pixel conversion means for converting the resolution of all or part of the image data input to the display unit. Multi-display system. Each of the display devices from the first stage to the p-th stage receives the inputted digital signal when the inputted image data is inputted as a digital signal, and sends it to the pixel converting means and the daisy chain circuit. 15. The multi-display system according to claim 14 , further comprising digital input means for outputting. When the input image data is input as an analog signal, the first-stage display device receives the input analog signal and converts it into a digital signal, which is output to the pixel conversion means and the daisy chain circuit Analog / digital conversion means for
Each of the display devices from the second stage to the (p−1) th stage receives the input digital signal when the input image data is input as a digital signal, Having digital input means for outputting to the daisy chain circuit;
The p-th stage display device has digital input means for receiving an input digital signal and outputting it to the pixel conversion means when the input image data is input as a digital signal. The multi-display system according to claim 14 . Each of the display devices from the first stage to the p-th stage
Digital input means for receiving an input digital signal when the input image data is input as a digital signal;
A plurality of video input means for receiving a plurality of other video signals and outputting a digital signal;
One of the output of the digital input means and the output of the plurality of video input means is output to the pixel conversion means, and one of the output of the digital input means and the outputs of the plurality of video input means The multi-display system according to claim 14 , further comprising: a switch unit that outputs a signal to the daisy chain circuit.

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