JP4151644B2 - Memory card drive - Google Patents

Description

  The present invention relates to a memory card drive for accessing a memory card having a built-in nonvolatile memory, and more particularly to a method for writing moving image data or the like to a plurality of memory cards.

  In recent years, memory cards using a non-volatile memory are spreading to consumer digital devices not only as audio but also as video signal recording media. However, the maximum recording capacity of memory cards currently on the market is 1 gigabyte (GB), and the effective recording rate is 2 megabytes (MB) / sec. In order to record DV (digital video) video and audio signals on the memory card as described above, a bandwidth of about 4 MB / sec is required, and only about 4 minutes are recorded on a 1 GB memory card. I can't. Therefore, a method for increasing the bandwidth and capacity by recording data in parallel on a plurality of memory cards has been proposed. In Patent Document 1, a memory card drive main body having an external interface is provided with a plurality of memory card mounting portions, and a plurality of memory cards are mounted on these mounting portions, so that a single memory card drive can be used. A technology for enabling recording of capacity information is disclosed.

  On the other hand, the capacity of memory cards is increasing at an annual rate of 50% or more. However, in a memory card composed of a nonvolatile memory, the number of rewrites is limited to about 100,000. Therefore, in order to avoid rewriting concentrated on a specific recording page, the logical address issued by the host device accessing the memory card is converted into a physical address inside the memory card for rewriting. That is, even if the same logical address is issued, processing is performed on the memory card so that it is written to another physical address. As described above, the method of recording while circulating the physical address to be recorded is called leveling.

Thus, when recording while performing leveling, it is necessary to record a conversion table of logical addresses and physical addresses (hereinafter abbreviated as AT table) in a nonvolatile memory inside the memory card. Come. The recording steps of the memory card as described above are as follows.
(1) Read the AT table stored in the nonvolatile memory and store it in the volatile memory in the host device.
(2) The logical address issued from the host device is converted into a physical address with reference to the AT table, and the data is written to the recording page of the nonvolatile memory indicated by the physical address. When leveling is necessary due to repeated overwriting or the like, the AT table is updated on the volatile memory.
(3) The AT table on the volatile memory is reflected in the nonvolatile memory at a predetermined timing.

  In proportion to the increase in the capacity of the memory card, this AT table also increases. For example, in the case of a 1 GB memory card having 512 bytes (B) of recording pages, there are about 2,000,000 recording pages, but in the case of a 4 GB memory card, 8,000,000 recording pages. Thus, since the AT table increases in proportion to the number of recorded pages, the time required for the above (1) and (3) also becomes longer. Note that (1) is the time required to initialize the AT table, and (3) is the time required to write to the AT table.

Also, in Patent Document 2, an AT table divided into a plurality of pieces and ATI information that is information indicating a physical address to which the AT table is written are recorded in a nonvolatile memory, and each time an AT table is updated a predetermined number of times. By updating the ATI information at the same time, the physical address to which the AT table is written is changed appropriately, thereby preventing an increase in the number of rewrites of the AT table for the same physical address.
JP 2002-189992 A Japanese Patent Laid-Open No. 2004-199605

  In the conventional memory card, the logical address / physical address conversion table (AT table) increases in proportion to the increase in recording capacity, so the influence of the update of the AT table and ATI information on the recording rate can be ignored. It will disappear. In addition to this characteristic, the conventional memory card drive that operates in parallel using a plurality of large-capacity memory cards causes the AT table and ATI information to be updated for each memory card. There is a problem that the influence on the recording rate becomes large.

  For example, when the AT table is managed in a volatile memory and a memory card that updates the AT table on the nonvolatile memory under conditions such as a timer or the number of times of writing is operated in parallel, each memory card has the same operation. Therefore, there is a high possibility that the AT table in the nonvolatile memory is not updated at the same time. Therefore, in a memory card drive composed of four memory cards, the worst AT table is updated at different times, so the amount of degradation of the recording rate due to the AT table update is quadrupled.

  Also, in the conventional memory card drive, the AT table is updated every time data is written in order to guarantee the written data even when the power is interrupted or the memory card is unexpectedly removed, and the AT table is written. A method is adopted in which ATI information indicating a physical address is recorded in a non-volatile memory, and when the AT table is updated a predetermined number of times, the ATI information is updated to appropriately change the physical address to which the AT table is written. Yes. However, in this method, the writing is temporarily delayed due to the update of the ATI information. For this reason, when the memory cards are operated in parallel, the number of updates of the AT table of each memory card is not always the same, so the update of the ATI information of each memory card occurs asynchronously. Therefore, in the memory card drive constituted by four memory cards, the worst ATI information is updated at different times, and the write delay due to the update of the ATI information is quadrupled.

  In view of such problems, an object of the present invention is to update an AT table or an ATI information for managing an AT table in a memory card drive that is composed of a plurality of memory cards and is accelerated by operating the memory cards in parallel. To provide a memory card drive and a memory card system that minimize deterioration of a recording rate.

In order to solve the above problems, the memory card drive according to the present invention converts an address to each of the plurality of memory cards based on an external interface means, a plurality of memory cards, and a command from the external interface means. and a control means for issuing an information update commands simultaneously, each of the plurality of memory cards, as well as data to be recorded, the memory card is built with the logical address of the recording destination of the data issued to the memory card When the address translation information indicating a correspondence relationship with the physical address of the nonvolatile memory and the recording destination address of the address translation information are held in the nonvolatile memory and the address translation information update command is issued, the address translation information The recording destination address is updated, and the control means updates the address conversion information update code. Counting the write data amount to each of the plurality of memory cards command issued after, the maximum value of the write data amount reaches a predetermined amount, at the same time the address translation information update command to each of the plurality of memory cards It is characterized by issuing.

  With the above configuration, the address conversion information update of each memory card can be synchronized, so that the deterioration of the write transfer rate can be minimized.

  In addition, the memory card control means issues an address conversion information update command to all the installed memory cards in an initialization process for recognizing the memory card, and then issues a write command that the host device issues to the memory card. If the number of times of issuing the write command to each memory card is limited to be uniform, the address conversion information update of each memory card can be synchronized, so that the deterioration of the write transfer rate can be minimized. .

  Further, the number of write commands issued for each memory card after issuing the address translation information update command is counted, and when the maximum value of the number of write command issuance reaches a predetermined number, all the memories on which the address translation information update command is mounted If issued to the card, it is possible to synchronize the address conversion information update of each memory card without limiting the command of the host device, so that the deterioration of the write transfer rate can be minimized.

  Embodiments of a memory card drive according to the present invention will be described below. First, among the implementation actions of the memory card drive according to the present invention, the mode of use action will be described. FIG. 1 is a diagram showing a form of usage of a memory card drive according to the present invention. In FIG. 1, the memory card drive according to the present invention is used in a video signal recording / reproducing apparatus formed by a host device 1 and a memory card drive 2, and the video signal is sent to a memory card (5a, 5b) inside the memory card drive. , 5c, 5d).

  In the figure, reference numeral 1a denotes a video signal input / output means. A signal processing unit 1b compresses and decompresses a video signal transmitted and received via the video signal input / output unit 1a. Reference numeral 1c denotes a drive control means for controlling the memory card drive 2 and reading / writing data from / to the memory card drive 2. On the other hand, the memory card drive 2 includes an external interface unit 3, a memory card controller 4 as a control unit for the memory card, and memory cards 5a, b, c, and d. The external interface unit 3 receives commands from the host device 1 and inputs / outputs data to / from the host device. The memory card controller 4 controls each memory card based on a command from the host device, and reads / writes data from / to each memory card. In the use of a recording / reproducing apparatus, video quality and audio quality equivalent to those of a digital video tape (DV) are required. In order to realize such quality, a bandwidth of 25 Mbps must be ensured, and this recording / reproducing apparatus operates four memory cards 5a, b, c, and d in parallel to ensure such bandwidth.

  The parallel operation of memory cards is done by striping. Striping is to divide data to be written into recording blocks and write them in parallel on a plurality of recording media. In this embodiment, since four memory cards are connected in series, the data to be written is divided into four for each block. For example, in a sector number to be written, (sector number)% 4 (% indicates a remainder) is used as a memory card number (memory card 0, memory card 1, memory card 2, memory card 3), and data is stored in each memory card. Will be written. At the time of reading, data is read from the memory card with (sector number)% 4 as the memory card number.

  By such striping, the memory cards 5a, b, c, d constitute one virtual drive. In such striping, if the number of sectors to be written is equal to or greater than the number of divisions (that is, 4 blocks or more if the number of divisions is 4), the write efficiency increases, and if it is 3 or less, the write efficiency decreases. The above is an example of an embodiment of a memory card drive.

  Next, the writing operation of the memory card will be described. At the time of writing, the memory card controller 4 converts the logical address designated as the data recording destination by the host device 1 into the logical address of the nonvolatile memory built in each memory card, The logical address at the beginning of writing in the memory card is asserted, and write data is sequentially transferred to each memory card.

  Next, the internal operation of the memory card will be described with reference to FIG. FIG. 5 shows an address map inside the memory card. The nonvolatile memory built in the memory card is composed of a management area 101 and a data area 102. The data area 102 is an area for storing data read / written from the host device 1, and is divided into, for example, four areas (data area 0 to data area 3) every 1024 blocks. The management area 101 is an area for storing management information such as an address conversion table to be described later, an address conversion table (hereinafter abbreviated as AT table) as address conversion information and an index (hereinafter referred to as a recording destination address) of the address conversion table. Are abbreviated as ATI information). The memory card controller 4 performs address conversion using the AT table and the ATI table.

  Here, the AT table and ATI information will be briefly described. The logical address and physical address of the memory are managed by ATI information and a plurality of AT table groups. Each AT table describes a conversion table indicating the correspondence between logical addresses and physical addresses in a predetermined range. The ATI information stores a physical address where each AT table is recorded. For example, when accessing the logical address 0, first, ATI information is read to obtain position information where the AT table storing the physical address conversion table corresponding to the logical address 0 is obtained, and then the AT table is read to actually perform the logical operation. The physical address information corresponding to address 0 is obtained.

The AT table 104 includes AT0 to AT3 to manage the data areas 0 to 3, respectively. The number of entries managed by AT0 to AT3 matches the number of blocks, and has a physical address and an allocation flag corresponding to each logical address. The allocation flag is a flag for identifying whether valid data is allocated to the physical address.
The ATI information 103 has a physical address in which AT0 to AT3 are recorded and its allocation flag.

  A write operation of the memory card configured as described above will be described. For example, when writing of the logical address 0 is designated from the host device, the ATI information 103 is read and the physical address information stored in the AT table 104 is obtained. Since logical address 0 to logical address 1023 are written in data area 0, it can be seen that the address conversion table corresponding to logical address 0 is stored in AT0. Therefore, next, AT0 is read, and an address conversion table corresponding to the data area 0 is obtained. When the allocation flag corresponding to the logical address 0 is not allocated, data is written to the physical block of the data area 0 corresponding to the logical address, and the allocation flag is allocated. If the allocation flag corresponding to the logical address 0 is allocated, the physical address number not allocated is searched from all the physical blocks corresponding to the logical addresses 0 to 1023 (for example, the physical address 10), and the physical address Data is written to the physical block in area 0 corresponding to number 10. Further, the physical address number corresponding to the logical address 0 of AT0 is updated (the physical address 0 is updated to the physical address 10), and the physical block corresponding to the logical address 0 already allocated in the data area 0 is erased. By performing such processing, a leveling function can be realized. The above is the basic operation of writing to the memory card. At the time of overwriting, updating of the AT table and writing of data occur.

  However, the nonvolatile memory is a memory with a limited number of rewrites, and the number of rewrites of the AT table cannot be ignored as the data capacity increases. For example, when data is written in units of 1 MB to a 1 GB card, the number of rewrites of the AT table required to write to all 1 GB cards is 1000 times, whereas in the case of 4 GB cards, it is 4000 times. Become. Therefore, in this method, the area of the AT table first reaches the end of its life in the memory card, thereby making the memory card itself unusable. Therefore, every time the AT table is rewritten a predetermined number of times, the ATI information indicating the physical address stored in the AT table is updated to change the storage position of the AT table. Reduces the number of rewrites.

According to the above algorithm, with one write command,
(A) Data write and AT table update (b) Data write, AT table update, and ATI information update occur. For example, when the ATI information is updated every time the AT table is updated 20 times, a delay corresponding to the update of the ATI information occurs at a rate of 1/20 compared to the update of the AT table alone. The memory card of the present invention has the above-described (b), that is, an address conversion information update command capable of controlling the timing of ATI information update from the outside. When the address conversion information update command is issued from the memory card controller 4, the ATI information of each memory card is forcibly updated simultaneously.

  FIG. 2 is a diagram showing the internal configuration of the memory card drive 2 of the present invention. In FIG. 2, the inside of the memory card controller 4 in FIG. 1 is shown in detail. 4a in the figure is command analysis / conversion means for analyzing a command issued via the external interface means 3 and converting it into a command for a memory card. 4b is a write command number measuring means for counting the number of write commands issued to the memory cards (5a to 5d) (number of write command issuances). 4c is an issued write command number comparing means for comparing the maximum value of the number of write commands issued to each memory card counted by the write command number measuring means 4b with a preset number. The address translation information update command issuing means 4d issues an address translation information update command simultaneously to all the mounted memory cards (5a to 5d) according to the comparison result of the issued write command number comparison means 4c. When the address conversion information update command is issued, the ATI information of each memory card is forcibly updated at the same time, and as a result, the physical address for storing the AT table is changed. At the same time, the number of write commands counted by the write command number measuring means 4b is reset to zero.

The operation of the memory card drive having the above configuration will be described below. When power is supplied to the memory card drive 2, the memory card controller 4 recognizes each memory card (5a to 5d), initializes the memory card, and issues an address conversion information update command to each memory card. At the same time, the number of write commands for each memory card is shifted to the initial state. That is, each of the write command number measuring means 4b is reset to 0. After the initialization process, the host device 1 writes / reads data to / from the memory card drive 2. The command issued to the memory card controller 4 via the external interface means 3 is converted into a command for each memory card after the command is analyzed by the command analysis / conversion means 4a. In the present embodiment, (sector number)% 4 is associated with the memory card number, and (sector number) / 4 is the logical address of the memory card. For example, if the issuance command from the host device 1 is a six-sector write starting from sector number 0, it is converted into the following write command for each memory card.
Writing to sector number 0 and sector number 4 → Writing two consecutive sectors from logical address 0 of memory card 0 Writing sector number 1 and sector number 5 → Writing two consecutive sectors from logical address 0 of memory card 1 Write of number 2 → Write to logical address 0 of memory card 2 Write of sector number 3 → Write to logical address 0 of memory card 3 Next, if host device 1 issues continuous sector write from sector number 6 The command to each memory card is
Writing sector number 6 → Writing to logical address 1 of memory card 2 Writing sector number 7 → Writing to logical address 1 of memory card 3, and no command is issued to memory card 0 and memory card 1.

  Further, if the host device 1 issues a write to the sector number 11, the command to each memory card is a write to the logical address 2 of the memory card 3.

When the above three commands are issued from the host device 1, the write command number measuring means 4b
Number of write commands to memory card 0 = 1,
Number of write commands to memory card 1 = 1,
Number of write commands to memory card 2 = 2,
Number of write commands to memory card 3 = 3,
And measure.

  The number of write commands to each memory card is input to the issued write command number comparison means 4c, where the maximum value is obtained. As described above, the current maximum value is 3, and if the update period of the ATI information of the memory card is 20, 3 <20, and the address translation information update command is not issued. Thereafter, when the maximum value reaches 20 by repeating writing, it is issued to all the memory cards (5a to 5d) on which the address translation information update command is mounted by the address translation information update command issuing means 4d. The When an address translation information update command is issued, the number of write commands is reset to zero.

  FIG. 3 is a timing chart when the host device issues 20 consecutive 4 sector write commands from sector 0 after issuing the above three commands. (A) is the timing of issuing the address translation information update command, (b) is the timing of the write command issued by the host device 1, and W18, W19, W20, W21, W22, and W23 are the 18th and 19th, respectively. This indicates that the write command is issued at the 20th, 21st, 22nd, and 23rd times. FIG. 4C shows the timing required for writing to the memory card 0. The reference numeral in the drawing indicates the number of write commands issued to the memory card 0 and is stored in the write command number measuring means 4b as described above. . The number of write commands is reset to 0 when an address conversion information update command is issued, and is incremented by 1 every time a write command is issued to the memory card. FIG. 4D shows the timing required for writing to the memory card 1, and the reference numerals in the figure are given in the same manner as in FIG. FIG. 4E shows the timing required for writing to the memory card 2, and the reference numerals in the figure are given in the same manner as in FIG. FIG. 8F shows the timing required for writing to the memory card 3, and the reference numerals in the figure are given in the same manner as in FIG.

  As shown in this timing diagram, when the number of write commands to the memory card 3 first reaches 20 times in the 20th write, and the maximum value of the number of write commands to the memory card reaches 20, the address conversion information update command Is issued. As a result, in the next (21st) writing, the ATI information is updated at the same time for all the memory cards, so that writing delay occurs in all four memory cards. However, since this delay occurs at the same time, it is possible to minimize the deterioration of the write rate due to the write delay for updating the ATI information.

  FIG. 4 is a timing chart when no address translation information update command is issued, and (a) to (f) in FIG. 4 show timings of the same elements as those in FIG. In the figure, writing with the reference numerals 1 to (f) indicating the update of the ATI information is not performed simultaneously on the four memory cards. For example, in the 21st writing, a delay occurs in the memory card 3, and a waiting time occurs after the writing is completed in the other three memory cards. For this reason, the influence of the delay due to the writing of ATI information is larger than that in FIG. When calculating with the transfer rate, if the time required for normal writing is t, and the time required for writing with the update of ATI information is 2t, 21t is required for 20 writes in FIG. 3, whereas 23t in FIG. Will be required. In the worst case, the update timing of the ATI information of the memory card 0 and the memory card 1 is also different, so that 24 t is required. Compared with this, according to the present embodiment, about 14% (24 t / 21 t = 1. 14) The transfer rate can be improved.

  As described above, the configuration shown in the present embodiment can synchronize the address conversion information update of each memory card, so that the write transfer rate can be improved.

  In the memory card according to the present embodiment, the case where the address conversion information is updated when the number of times of issuing the write command reaches 20 has been described. Needless to say, the update cycle is not limited to 20 times.

  The logical address / physical address conversion table (AT table) has been described with an example of a memory card that updates the AT table of the nonvolatile memory when a write command is executed. The memory card may be a memory card that is developed in a volatile memory and the AT table developed in the volatile memory at a predetermined timing is written back to the nonvolatile memory and reflected. In this case, the determination of the timing for reflecting the AT table in the nonvolatile memory is not necessarily based on the number of write commands issued to the memory card.

  For example, if the memory card is such that only the AT table difference information is written in the nonvolatile memory and the AT data is updated when the difference data reaches a predetermined amount, the AT table update timing depends on the write data amount. Managed. Therefore, the memory card controller may manage the amount of data written to each memory card, and when the amount of data reaches a predetermined number, the address conversion information update command may be issued simultaneously to all the memory cards.

  Further, in this embodiment, the memory card controller manages the number of write commands to each memory card, but the same effect can be obtained even if each memory card manages. That is, the memory card itself stores the number of write commands after receiving the address conversion information update command as an update phase (corresponding to the reference numerals shown in FIGS. 3C to 3F in this embodiment). A phase detection command for notifying the update phase to the outside is provided, and when the memory card controller reaches a predetermined value (for example, 20 times) when the maximum value of the update phase of each memory card detected by the phase detection command is reached. The address conversion information update command may be issued simultaneously to all mounted memory cards.

  Since the memory card drive according to the present invention can increase the transfer rate at the time of writing to the memory card, it is optimal for the case where the memory card is used for recording moving image data. The memory card drive according to the present invention is highly likely to be used in the video equipment industry related to the manufacture of video equipment because it is suitable for use in recording moving image data.

The figure which shows the form about the usage act of the memory card drive based on this invention The figure which shows the internal structure of the memory card drive 2 Timing diagram in writing of memory card drive of the present invention Timing diagram for writing to a conventional memory card drive Figure showing the address map inside the memory card

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host apparatus 1a Video signal input / output means 1b Signal processing means 1c Drive control means 2 Memory card drive 3 External interface means 4 Memory card controller 4a Command analysis / conversion means 4b Write command number measurement means 4c Issued write command number comparison means 4d Address translation information update command issuing means 5a to 5d Memory card

Claims (2)

An external interface means for inputting / outputting data to / from the host device;
Multiple memory cards,
Based on the command from said external interface means, and control means for issuing an address translation information update command simultaneously to each of the plurality of memory cards,
Each of the plurality of memory cards includes data to be recorded and an address indicating a correspondence relationship between a logical address of a recording destination of the data issued to the memory card and a physical address of a nonvolatile memory built in the memory card The conversion information and the recording destination address of the address conversion information are held in the nonvolatile memory, and when the address conversion information update command is issued, the recording destination address of the address conversion information is updated,
The control means counts the amount of write data to each of the plurality of memory cards after the address conversion information update command is issued, and when the maximum value of the write data amount reaches a predetermined amount, the address conversion information update command A memory card drive for simultaneously issuing the memory card to each of the plurality of memory cards . An external interface means for inputting / outputting data to / from the host device;
Multiple memory cards,
Based on the command from said external interface means, and control means for issuing an address translation information update command simultaneously to each of the plurality of memory cards,
Each of the plurality of memory cards includes data to be recorded and an address indicating a correspondence relationship between a logical address of a recording destination of the data issued to the memory card and a physical address of a nonvolatile memory built in the memory card The conversion information and the recording destination address of the address conversion information are held in the nonvolatile memory, and when the address conversion information update command is issued, the recording destination address of the address conversion information is updated,
The control means issues a phase detection command to each of the plurality of memory cards,
Each of the plurality of memory cards stores the write command issuance count after receiving the address conversion information update command as an update phase, and when the phase detection command is issued, notifies the update phase to the outside,
The control means is a memory card drive that simultaneously issues the address translation information update command to the plurality of memory cards based on the update phase notified from each of the plurality of memory cards .

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