JP4024341B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device using a semiconductor thin film and a manufacturing method thereof, and more particularly to a thin film transistor (TFT) using a crystalline film containing silicon.
[0002]
In this specification, a semiconductor device refers to all devices that function using a semiconductor, and includes not only semiconductor elements such as TFTs and MOSFETs (IGFETs), but also electro-optical devices (liquid crystal display devices, etc.) Application products (electronic devices, etc.) on which they are mounted are also included in the category of semiconductor devices. In this specification, in order to clarify the distinction, a semiconductor element, a display device, and the like are described as appropriate.
[0003]
[Prior art]
2. Description of the Related Art In recent years, there has been remarkable progress in technology for forming semiconductor circuits using thin film transistors (TFTs) formed on a substrate. In particular, an active matrix display device using a crystalline silicon film (polysilicon film or the like) as a thin film semiconductor and mounting a peripheral circuit and a pixel matrix circuit on the same substrate has reached a practical level.
[0004]
In particular, active matrix liquid crystal display devices (hereinafter referred to as AM-LCDs) are being actively developed for displays such as notebook computers, projectors, and portable devices. AM-LCDs are roughly classified into transmissive LCDs and reflective LCDs according to their operation modes.
[0005]
At present, the development of high-definition and bright liquid crystal display devices is urgently required, and each pixel has a very fine structure of 30 μm square or less like XGA (1024 × 768 pixels) and SXGA (1280 × 1024 pixels). Has been developed.
[0006]
The AM-LCD as described above performs on / off control of light by changing the optical response characteristics of the liquid crystal layer according to the voltage applied to the liquid crystal layer. In general, an auxiliary capacitor is provided in each pixel in order to compensate for leakage of charges held in the liquid crystal layer.
[0007]
By the way, the present inventors have disclosed a method for obtaining a crystalline film by utilizing a catalytic element (typically nickel) that promotes crystallization as a method for forming a crystalline film containing silicon (Japanese Patent Laid-Open No. Hei. 7-130652).
[0008]
In this publication, a region crystallized by adding a catalyst element directly (hereinafter referred to as a vertical growth region) and a crystallized region formed around a region to which a catalyst element is added (hereinafter referred to as a lateral growth region). A technique for forming the above is disclosed.
[0009]
However, since most of the catalyst elements are metal elements, if they remain after crystallization, the reliability of the TFT may be impaired, which is not preferable.
[0010]
[Problems to be solved by the invention]
It is an object of the present invention to provide a technique for simplifying a manufacturing process in a method for manufacturing a semiconductor device including a process of effectively removing or reducing the catalytic element.
[0011]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
Holding or adding a catalytic element for promoting crystallization of the silicon to all or a part of the amorphous film containing silicon;
Crystallizing the element forming portion of the amorphous film containing silicon by heat treatment;
Simultaneously adding an element selected from Group 15 to a region adjacent to the element forming portion and a region to be a lower electrode of an auxiliary capacitor;
A step of gettering the catalytic element in a region to which an element selected from the group 15 is added by heat treatment;
It is characterized by having.
[0012]
A basic object of the present invention is to simplify a process in a manufacturing method in which a catalytic element used for crystallization of an amorphous film containing silicon is gettered from a formed crystalline film.
[0013]
Here, a method for gettering the catalyst element will be briefly described. One of the features of the present invention is that it uses a gettering effect by an element selected from Group 15.
[0014]
Typical examples of the catalytic element include Ni (nickel), Co (cobalt), Fe (iron), Pd (palladium), Pt (platinum), Cu (copper), and Au (gold). In our experiments, nickel has been found to be the most suitable element.
[0015]
Examples of the group 15 element for gettering the catalyst element include N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth). Shown is phosphorus.
[0016]
As a typical example, when nickel is used as a catalyst element and phosphorus is used as a gettering element (group 15 element), the heat treatment at around 600 ° C. shows a stable bonding state between phosphorus and nickel. At this time, Ni _Three P, Ni _Five P ₂ , Ni ₂ P, Ni _Three P ₂ , Ni ₂ P _Three , NiP ₂ , NiP _Three The combined state can be taken.
[0017]
As described above, when nickel is used as a catalyst element for promoting crystallization of an amorphous film containing silicon, it can be removed or reduced from the crystalline film by the gettering action of an element selected from Group 15 it can.
[0018]
【Example】
[Example 1]
An example of manufacturing a reflective liquid crystal display device using the present invention will be described with reference to FIGS. In this embodiment, a process of forming a CMOS circuit and a pixel matrix circuit which are basic circuits constituting a peripheral circuit on the same substrate will be described.
[0019]
For the convenience of drawing, the scale ratio of the peripheral circuit and the pixel matrix circuit does not correspond, and the pixel matrix circuit portion is shown larger.
[0020]
Further, the peripheral circuit includes not only a driver circuit typified by a shift resist and the like, but also a logic circuit that performs other signal processing. For example, a memory, a D / A converter, an operational amplifier, a pulse generator, and the like are included in the logic circuit.
[0021]
First, a glass substrate on which a silicon oxide film or the like is deposited as a base film is prepared as the substrate 101 having an insulating surface. Further, a quartz substrate, a silicon substrate, a ceramic substrate, or the like may be used instead of the glass substrate.
[0022]
Next, an amorphous silicon film 102 is formed to a thickness of 10 to 75 nm (preferably 15 to 45 nm) by using a plasma CVD method or a low pressure CVD method. In addition to the amorphous silicon film, an amorphous semiconductor film containing silicon, for example, Si _X Ge _1-X (0 <X <1) can also be used.
[0023]
Next, the amorphous silicon film 102 is crystallized by applying the technique described in JP-A-8-78329. The feature of this publication is that a catalytic element is selectively added to the amorphous silicon film to obtain a region (lateral growth region) in which crystal growth is substantially parallel to the substrate.
[0024]
First, a mask insulating film 103 made of a silicon oxide film is formed on the amorphous silicon film 102 to a thickness of 50 to 150 nm. Then, first openings 104 and 105 are provided in a region where nickel is added by patterning the mask insulating film 103.
[0025]
The first openings 104 and 105 are formed so that the vicinity of a region (element formation portion) where a semiconductor element (TFT in this embodiment) is to be formed later is exposed. That is, the lateral growth region is designed so as to be formed just in the element formation portion.
[0026]
Next, a thin oxide film (not shown) is formed on the exposed surface of the amorphous silicon film. This step may be performed by UV light irradiation in an oxygen atmosphere. This oxide film has an effect of improving the wettability in the next solution coating step.
[0027]
Next, an amorphous silicon film containing a solution (for example, a nickel acetate salt solution, a nickel nitrate salt solution, etc.) containing 100 ppm in terms of weight of a catalyst element (in this specification, nickel is used as an example) that promotes crystallization of silicon The nickel-containing layer 106 is formed by spin coating on the mask 102 and the mask insulating film 103. (Fig. 1 (A))
[0028]
When the technique described in the publication is used, the surface of the amorphous silicon film exposed through the first openings 104 and 105 formed in the mask insulating film is approximately 2 × 10 ¹⁴ atoms / cm ² Of nickel is retained.
[0029]
In this state, heat treatment for crystallization is performed. This heat treatment is performed at a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.), and the treatment time is 4 to 24 hours (typically 8 to 15 hours). By this treatment, nickel diffuses into the film and crystallizes to form crystalline silicon films 107-110. (Fig. 1 (B))
[0030]
Here, 107 and 108 are regions where nickel is added, which contain nickel in a very high concentration. Reference numerals 109 and 110 denote lateral growth regions where crystallization has progressed in the lateral direction. ¹⁸ ~ 1 × 10 ¹⁹ atoms / cm ^Three Contains about nickel. In addition, the region that has not been crystallized remains amorphous.
[0031]
This laterally grown region has a crystal structure in which needle-like or columnar crystals are arranged in a specific direction with regularity. Further, each acicular crystal is characterized by growing substantially parallel to each other and macroscopically in the same direction.
[0032]
Next, the mask insulating film 103 is patterned again to form a second opening 111 for forming an electrode portion (lower electrode portion) to be an auxiliary capacitance later. Note that a resist mask having an opening may be newly provided after the mask insulating film 103 is completely removed.
[0033]
In this state, P (phosphorus) ions are added by an ion plantation method or a plasma doping method. It is also effective to use As (arsenic) ions instead of P ions. (Figure 1 (C))
[0034]
In the ion implantation process of this embodiment, the acceleration voltage is 5 to 25 kV, and the dose is 1 × 10 ¹³ ~ 8 × 10 ¹⁵ atoms / cm ² (Preferably 5 × 10 ¹³ ~ 1 × 10 ¹⁵ atoms / cm ² ). With this setting, the exposed amorphous silicon film has 5 × 10 ¹⁹ ~ 2 × 10 ^{twenty one} atoms / cm ^Three P ions are added at a concentration of
[0035]
A feature of this embodiment is that the first openings 104 and 105 that function as nickel-added regions also function as regions to which phosphorus is added. The phosphorus-added regions 112 and 113 formed under the first openings 104 and 105 function as gettering regions for collecting nickel.
[0036]
In addition, the phosphorus-added region 114 formed under the second opening 111 serves as a lower electrode of an auxiliary capacitor having N-type conductivity. At the same time, it functions as a gettering region for collecting nickel.
[0037]
Thus, one of the most important configurations of the present invention is that the step of adding P ions for the purpose of forming the gettering region also serves as the step of forming the lower electrode of the auxiliary capacitor.
[0038]
After the addition process of P ions is completed, the mask insulating film 103 is removed, and then in a nitrogen atmosphere, 400 to 700 ° C. (typically 550 to 600 ° C.), 2 to 24 hours (typically 8 to 12 hours) And the nickel existing in the lateral growth regions 109 and 110 are moved toward the phosphorus addition regions 112 to 114. (Fig. 2 (A))
[0039]
Note that this step may be performed before the mask insulating film 103 is removed. It is also effective to disperse phosphorus in the silicon film by performing a process such as laser annealing before the heat treatment. When performing this laser annealing, it is more effective to perform laser annealing after removing the mask insulating film 103. As the laser light, excimer laser using KrF, ArF, XeCl or the like as an excitation gas, CO ₂ Lasers and YAG lasers can be used.
[0040]
Thus, the nickel remaining in the lateral growth regions 109 and 110 is gettered to the phosphorus addition regions 112 to 114, and the lateral growth regions 115 and 116 in which nickel is reduced are obtained. The present inventors have disclosed a gettering process using phosphorus element in Japanese Patent Application No. 9-94607. (Fig. 2 (A))
[0041]
The phosphorus-added regions 112 to 114 become amorphous in the process of adding P ions, but are crystallized again in this heat treatment process.
[0042]
As a result of confirmation by SIMS (mass secondary ion analysis) by the present inventors, the concentration of nickel contained in the lateral growth regions 115 and 116 after the step shown in FIG. ¹⁷ atoms / cm ^Three It was found that it was reduced to the following (below this becomes a detection lower limit and measurement is impossible).
[0043]
At this time, the phosphorus-added regions 112 to 114 are regions containing nickel at a high concentration because nickel is gettered and collected. In the analysis by SIMS
1 × 10 ¹⁸ ~ 1 × 10 ²⁰ atoms / cm ² The presence of nickel was confirmed at a concentration of.
[0044]
However, there is no problem as long as the phosphorus-added region 114 that functions as a lower electrode of the auxiliary capacitor later functions as an electrode even if nickel remains. Further, the phosphorus-added regions 112 and 113 are not used at least in a channel formation region (can be used as a source / drain region). Therefore, since it is basically removed when the active layer is formed, the presence or absence of nickel is not a problem.
[0045]
When the state of FIG. 2A is thus obtained, the silicon film is patterned to form active layers 117-119. The active layers 117 and 118 are mainly N-type TFTs and P-type TFTs of CMOS circuits that constitute peripheral circuits, respectively. The active layer 119 is a pixel TFT (in this embodiment, an N-type TFT) constituting a pixel matrix circuit.
[0046]
Next, the oxide (not shown) formed on the silicon film surface is removed. Since such a surface oxide takes in contaminants and the like in the silicon film, a clean silicon film surface can be obtained by removing the surface oxide.
[0047]
Then, a silicon oxide film 120 to be a gate insulating film is immediately formed to a thickness of 10 to 150 nm using a plasma CVD method. Of course, a low pressure thermal CVD method or a sputtering method can also be used. The ECR plasma CVD method and the high density plasma CVD method are also effective. (Fig. 2 (B))
[0048]
Next, electrode patterns 121 to 124 made of aluminum or a material mainly containing aluminum are formed. Electrode pattern 121- 123 Are prototypes of gate electrodes constituting a CMOS circuit or a pixel TFT, respectively. The electrode pattern 124 is a prototype of the upper electrode of the auxiliary capacitor.
[0049]
In this embodiment, a triple gate type TFT is used as the pixel TFT. Therefore, although the electrode pattern 123 is divided into three, it is actually the same electrode that is all connected.
[0050]
When the state shown in FIG. 3A is obtained in this manner, two anodic oxidation processes are performed next. The steps from the anodic oxidation step described below to ion implantation (phosphorus (P) or boron (B)) are based on the technique described in Japanese Patent Laid-Open No. 7-13318 by the present inventors. Therefore, the detailed conditions and the like should be referred to the same publication.
[0051]
After the electrode patterns 121 to 124 are formed, first, anodization is performed in a 3% oxalic acid aqueous solution to form porous anodic oxide films 125 to 128. Next, anodic oxidation is performed in an ethylene glycol solution mixed with 3% tartaric acid to form nonporous anodic oxide films 129 to 132. After these two anodic oxidation steps, the gate electrodes 133 to 135 and the upper electrode 136 of the auxiliary capacitor are defined.
[0052]
When the state shown in FIG. 3B is thus obtained, the gate insulating film 120 is dry-etched using the gate electrode and the porous anodic oxide film as a mask. From this step, a gate insulating film as shown by 137 to 140 is formed. The gate insulating film 140 functions as an auxiliary capacitor insulating film. (Figure 3 (C))
[0053]
Next, as shown in FIG. 3D, the porous anodic oxide films 125 to 128 are removed, and high acceleration P ion implantation and low acceleration P ion implantation are performed. Through this process, a source region 141, a drain region 142, a pair of low-concentration impurity regions (also referred to as LDD regions) 143, and a channel formation region 144 of the N-type TFT are formed.
[0054]
In this embodiment, since the pixel TFT is composed of an N-type TFT, a source region 145, a drain region 146, a pair of low-concentration impurity regions 147 to 149, and channel formation regions 150 to 152 are formed.
[0055]
At this time, P ions are also added to the active layer of the P-type TFT, and regions 153 and 154 containing P ions having the same concentration as the source / drain regions and the P ions having the same concentration as those of the low concentration impurity regions are used. A region 155 including a portion is formed. Further, no P ions are added to the region indicated by 156, and the P ion concentration added in advance is maintained, but the pixel TFT and the drain region 146 are substantially integrated.
[0056]
Next, a resist mask 157 is provided so that only the P-type TFT is exposed, and high acceleration B ion implantation and low acceleration B ion implantation are performed. Through this process, the regions 153 to 155 containing P ions in FIG. 3D are all inverted to P-type, and the source region 158 and drain region 159 of the P-type TFT, the pair of low-concentration impurity regions 160, and the channel formation region 161 Is formed. (Fig. 4 (A))
[0057]
When the ion implantation process as described above is used, the source / drain regions of the N-type TFT and the P-type TFT can be formed by only one patterning process.
[0058]
Next, the implanted P ions and B ions are activated by any one of furnace annealing, laser annealing, lamp annealing or a combination of these with the resist mask 157 removed. At the same time, the crystallinity of the active layer broken by ion implantation is repaired.
[0059]
Next, a stacked film including a silicon oxide film and a silicon nitride film is formed as the first interlayer insulating film 162. Then, after forming contact holes, source electrodes 163 to 165 and drain electrodes 166 and 167 are formed. (Fig. 4 (B))
[0060]
Next, an organic resin film (polyimide, polyamide, polyimideamide, acrylic, or the like) is formed as the second interlayer insulating film 168 to a thickness of 0.5 to 3 μm (preferably 1.5 to 2.5 μm). The most significant feature of the organic resin film is that the relative dielectric constant is low (about 2.0 to 3.4), which can greatly reduce the parasitic capacitance between the wirings. That is, it is possible to effectively suppress a decrease in operation speed when configuring a circuit that requires high-frequency driving, such as a logic circuit.
[0061]
Next, contact holes are formed in the second interlayer insulating film 168 to form pixel electrodes 169. In this embodiment, the pixel electrode 169 is made of aluminum or a material mainly containing aluminum.
[0062]
Finally, the entire TFT obtained is heat-treated in a hydrogen atmosphere and hydrogenated to reduce dangling bonds in the active layer. Thus, an active matrix substrate in which the CMOS circuit and the pixel TFT are integrally formed on the same substrate as shown in FIG. 4C is completed.
[0063]
Thereafter, a reflective liquid crystal display device is completed by sandwiching a liquid crystal layer between the active matrix substrate and the counter substrate by a known cell assembling process.
[0064]
A practitioner may appropriately determine design items such as the type of liquid crystal material and the cell gap. In this embodiment, the black mask is provided on the opposite side. However, the black mask may be provided on a necessary portion on the active matrix substrate side.
[0065]
[Example 2]
In this embodiment, an example in which a crystalline silicon film is formed by means different from that in Embodiment 1 will be described. Note that basically the only different process is the process corresponding to FIGS. 1A, 1B, and 1C of the first embodiment (the process before the gettering process using phosphorus element), and only these processes will be described. I decided to.
[0066]
In this embodiment, as a means for crystallizing the amorphous silicon film, a method of forming a vertical growth region according to the technique described in Japanese Patent Laid-Open No. 7-30625 is used.
[0067]
In FIG. 5A, reference numeral 501 denotes a substrate and 502 denotes an amorphous silicon film. When forming the vertical growth region, the mask insulating film as in the first embodiment is not necessary, and the nickel-containing layer 503 may be formed on the entire surface of the amorphous silicon film 502.
[0068]
At this time, the nickel concentration in the solution containing nickel is 10 ppm in terms of weight (about 3 × 10 × 10 on the surface of the amorphous silicon film). ¹³ atoms / cm ² )
[0069]
In this state, heat treatment for crystallization is performed. In this embodiment, the temperature is 600 ° C. for 4 hours. By this heat treatment, the entire surface of the amorphous silicon film 502 is crystallized, and a crystalline silicon film 504 called a vertical growth region is obtained. (Fig. 5 (B))
[0070]
Next, a resist mask 505 is formed. Openings 506 to 508 for adding P ions are formed in the resist mask 505. When the openings 506 to 508 are formed, a P ion implantation step is performed to form phosphorus addition regions 509 to 511. (Fig. 5 (C))
[0071]
At this time, the regions 509 and 510 to which P ions are added from the openings 506 and 507 function as gettering regions for collecting nickel. The gettering region is preferably formed in a region adjacent to the element forming portion because the gettering effect is reduced if it is too far from the element forming portion.
[0072]
The region 511 to which P ions are added from the opening 508 functions as a lower electrode of the auxiliary capacitor. Of course, in addition to the function as the lower electrode, it also functions as a gettering region.
[0073]
The state shown in FIG. 5C is obtained by the process as described above. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.
[0074]
Example 3
In this embodiment, an example in which a semiconductor device is manufactured using a vertical growth region and a horizontal growth region on the same substrate will be described. Basically, only the gettering process using phosphorus element is different, and the process is similar to that in the first and second embodiments, so only the necessary parts will be described.
[0075]
In FIG. 6A, reference numeral 601 denotes a substrate, and 602 denotes an amorphous silicon film. In this embodiment, the peripheral circuit is formed in the lateral growth region and the pixel matrix circuit is formed in the vertical growth region. Therefore, the mask insulating film 603 is not formed in a region to be a pixel matrix circuit, and an opening 604 is provided in a necessary portion in a region to be a peripheral circuit.
[0076]
Then, a nickel-containing layer 605 is formed by applying a solution containing nickel and performing spin coating. At this time, the nickel concentration in the solution may be 100 ppm in terms of weight as in Example 1. If the concentration is lower than this, the growth distance of the lateral growth region may not reach the desired length. (Fig. 6 (A))
[0077]
In this state, heat treatment for crystallization is performed. In this embodiment, the temperature is set to 600 ° C. for 8 hours in order to sufficiently perform the lateral growth. By this heat treatment, a nickel-added region (also referred to as a vertical growth region) 606 and a horizontal growth region 607 are formed in a region serving as a peripheral circuit. Further, the entire surface of the amorphous silicon film 602 is crystallized in a region to be a pixel matrix circuit, and a vertical growth region 608 is formed. (Fig. 6 (B))
[0078]
Then, after removing the mask insulating film 603, a resist mask 609 provided with openings 610 to 612 is formed, and a P ion implantation step is performed to form phosphorus added regions 613 to 615. (Fig. 6 (C))
[0079]
In this embodiment, similarly to the first and second embodiments, the phosphorus-added regions 613 and 614 function as gettering regions for collecting nickel, and the phosphorus-added region 615 functions as a lower electrode of an auxiliary capacitor. Of course, in addition to the function as the lower electrode, it also functions as a gettering region.
[0080]
The state shown in FIG. 6C is obtained by the process as described above. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.
[0081]
Example 4
In this embodiment, an example in which the vertical growth region and the horizontal growth region are selectively used with a configuration different from that of the third embodiment will be described. In this embodiment, only the gettering process using phosphorus element will be described.
[0082]
In FIG. 7A, reference numeral 701 denotes a substrate, and reference numeral 702 denotes an amorphous silicon film. In this embodiment, the peripheral circuit is formed in the vertical growth region and the pixel matrix circuit is formed in the horizontal growth region. Therefore, the mask insulating film 703 is not formed in a region to be a peripheral circuit, and an opening 704 is provided in a necessary portion in a region to be a pixel matrix circuit.
[0083]
Then, a nickel-containing layer 705 is formed by applying a solution containing nickel and performing spin coating. At this time, the nickel concentration in the solution may be 100 ppm in terms of weight as in Example 3. (Fig. 7 (A))
[0084]
In this state, heat treatment for crystallization is performed. In this embodiment, the temperature is set to 600 ° C. for 8 hours in order to sufficiently perform the lateral growth. By this heat treatment, a vertical growth region 706 and a horizontal growth region 707 are formed by addition of nickel in a region that becomes a pixel matrix circuit. Further, the entire surface of the amorphous silicon film 702 is crystallized in a region to be a peripheral circuit, and a vertical growth region 708 is formed. (Fig. 7 (B))
[0085]
Then, after removing the mask insulating film 703, a resist mask 709 provided with openings 710 to 712 is formed, and a P ion implantation step is performed to form phosphorus-added regions 713 to 715. (Fig. 7 (C))
[0086]
In this embodiment, as in the first to third embodiments, the phosphorus-added regions 713 and 714 function as gettering regions for collecting nickel, and the phosphorus-added region 715 functions as a lower electrode of the auxiliary capacitor. Of course, in addition to the function as the lower electrode, it also functions as a gettering region.
[0087]
The state shown in FIG. 7C is obtained by the process as described above. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.
[0088]
Example 5
In this embodiment, an example will be described in which a region constituting the lower electrode of the auxiliary capacitor is used as a nickel addition region. In this embodiment, only the gettering process using phosphorus element will be described.
[0089]
In FIG. 8A, reference numeral 801 denotes a substrate, and 802 denotes an amorphous silicon film. A mask insulating film 803 is formed thereon, and openings 804 and 805 are formed in the mask insulating film 803. At this time, the feature of this embodiment is that the opening 805 is formed in a region that will later become a lower electrode of the auxiliary capacitor.
[0090]
Then, a nickel-containing layer 806 is formed by applying a solution containing nickel and performing spin coating. At this time, the nickel concentration in the solution may be 100 ppm in terms of weight in the same manner as in Example 3 and Example 4. (Fig. 8 (A))
[0091]
In this state, heat treatment for crystallization is performed. In this embodiment, this heat treatment is performed at 570 ° C. for 14 hours. Thus, by lowering the crystallization temperature to 560 ° C., crystallization due to the generation of natural nuclei can be sufficiently prevented. If natural nucleation occurs, it is not preferable because lateral crystal growth may stop there.
[0092]
By this heat treatment, a vertical growth region 807 and a horizontal growth region 808 are formed by adding nickel in a region that becomes a peripheral circuit. Further, in a region to be a pixel matrix circuit, a vertical growth region 809 and a horizontal growth region 810 are formed by adding nickel. (Fig. 8 (B))
[0093]
Then, as shown in FIG. 8C, a P ion implantation process is performed using the mask insulating film 803 as a mask to form phosphorus-added regions 811 and 812. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.
[0094]
In this embodiment, since the mask insulating film 803 used in the nickel addition process can be used as it is as a mask in the phosphorus addition process, there is an advantage that the manufacturing process is simplified.
[0095]
Example 6
In this embodiment, an example in which no nickel is added to the pixel matrix circuit will be described. In this configuration, the peripheral circuit may be formed of a vertical growth region or a horizontal growth region. In this embodiment, an example in which the peripheral circuit is formed of a horizontal growth region will be described.
[0096]
In FIG. 9A, 901 is a substrate, 902 is an amorphous silicon film, and 903 is a mask insulating film. In this embodiment, an opening 904 is formed in the mask insulating film 603 in a region to be a peripheral circuit. No opening is formed in a region to be a pixel matrix circuit.
[0097]
And the nickel containing layer 905 is formed by apply | coating the solution containing nickel and spin-coating. At this time, the nickel concentration in the solution may be 100 ppm in terms of weight. (Fig. 9 (A))
[0098]
In this state, heat treatment for crystallization is performed. In this embodiment, the crystallization process is performed at 560 ° C. for 20 hours. By this heat treatment, a vertical growth region 906 and a horizontal growth region 907 are formed by adding nickel in a region that becomes a peripheral circuit. Further, since nickel is not added at all in a region to be a pixel matrix circuit, an amorphous region 908 remains. (Fig. 9 (B))
[0099]
Then, after removing the mask insulating film 903, a resist mask 909 provided with openings 910 and 911 is formed, and a P-ion implantation process is performed to form phosphorus-added regions 912 and 913. At this time, the phosphorus-added regions 912 and 913 are once made amorphous. (Fig. 9 (C))
[0100]
Next, heat treatment is performed at 600 ° C. for about 24 hours to perform a gettering step with phosphorus element. Through this step, nickel contained in the lateral growth region 914 is gettered to the phosphorus addition region 915. (Fig. 10 (A))
[0101]
Further, the phosphorus-added region 915 that has become a gettering region is recrystallized by this heat treatment. Further, the phosphorus addition region 916 that functions as a lower electrode of the auxiliary capacitor later is recrystallized by this heat treatment.
[0102]
The above-described amorphous region 908 is also crystallized by the generation of natural nuclei and becomes a crystal region 917. In this case, the phosphorus-added region 916 that will later become the lower electrode of the auxiliary capacitor does not function as a gettering region, and therefore contains almost no nickel.
[0103]
Then, when the state of FIG. 10A is obtained, the active layers 918 to 920 are formed by leaving necessary portions by patterning. Then, a gate insulating film 921 is formed according to the process of the first embodiment.
[0104]
The state shown in FIG. 10B is obtained by the process as described above. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.
[0105]
Example 7
In this embodiment, an example in which lamp annealing is used as a heating method in the gettering step using the phosphorus element shown in FIG.
[0106]
RTA (rapid thermal annealing) is known as a heat treatment by lamp annealing. This is a technique for heating a thin film by irradiating a sample with infrared light using a halogen lamp or the like.
[0107]
When RTA is used as the heat treatment in the gettering step, a high-temperature annealing process of 700 to 1100 ° C. can be performed in a short time from several seconds to several minutes. Accordingly, the gettering effect of the catalytic element is improved because a higher temperature treatment can be performed than the furnace annealing. In addition, since the processing time is much shorter, the throughput is greatly improved.
[0108]
Further, the heat treatment at a high temperature of 700 to 1100 ° C. causes rearrangement of silicon atoms existing in the vicinity of the crystal grain boundary of the crystalline silicon film, thereby promoting inactivation of the crystal grain boundary. That is, crystal defects such as dangling bonds are greatly reduced and the possibility that carriers are trapped is reduced, and the overall crystallinity is remarkably improved.
[0109]
Example 8
In the present invention, an ion plantation method can also be used as a method for adding a catalyst element (typically nickel). In this case, the dose is 0.5 x 10 ¹³ ~ 1 × 10 ¹⁵ atoms / cm ² (Preferably 2 × 10 ¹³ ~ 2 × 10 ¹⁴ atoms / cm ² It is preferable to adjust so that.
[0110]
When the catalyst element is added by the ion plantation method as in this embodiment, the width (short side) of the opening provided in the mask insulating film may be about 0.01 to 5 μm (typically 0.25 to 2 μm). That is, a sufficient amount of nickel can be added to the opening formed in a fine pattern.
[0111]
Accordingly, the area occupied by the addition region of the catalyst element that becomes a dead space in the circuit design stage can be greatly reduced, and the advantage that the degree of freedom in circuit design is improved can be obtained.
[0112]
Example 9
In Embodiment 1, aluminum or a material mainly composed of aluminum is used as the gate electrode. However, in the present invention, a crystalline silicon film having one conductivity can be used as the gate electrode.
[0113]
Further, a metal material such as titanium, tantalum, tungsten, or molybdenum, or a metal silicide formed of a compound of these metal materials and silicon can be used as the gate electrode.
[0114]
Example 10
In Examples 1 to 9, an example of a planar type TFT is shown as an example of a typical TFT structure. However, a bottom gate type TFT such as an inverted stagger type TFT can also be applied to the present invention. is there.
[0115]
Further, the present invention can be applied not only to the TFT but also to a MOSFET formed on a silicon wafer.
[0116]
Thus, the present invention can be applied regardless of the structure of the semiconductor element (semiconductor device), and is not limited to a semiconductor element having a specific structure.
[0117]
Example 11
In this embodiment, an example of a pixel configuration constituting the pixel matrix circuit is shown in FIG. However, in order to simplify the structure, the pixel electrode is omitted.
[0118]
In FIG. 11, reference numeral 11 denotes an active layer, which corresponds to the active layer 119 in FIG. The present embodiment is characterized in that the drain side of the active layer 11 is formed so as to spread all over the pixel, and also serves as the lower electrode 12 of the auxiliary capacitor.
[0119]
Above that, a gate line 13 is arranged via a gate insulating film. The gate line 13 corresponds to the gate electrode 135 in FIG. In addition to the gate line 13, a storage capacitor upper electrode 14 is formed. The upper electrode 14 corresponds to the upper electrode 136 in FIG.
[0120]
In this case, the upper electrode 14 is provided in a shape that substantially coincides with the active layer that becomes the lower electrode, and forms an auxiliary capacitance that substantially corresponds to the area occupied by the pixel. Further, the upper electrode 14 is electrically connected between adjacent pixels (connected in parallel with the gate line so as not to cross the gate line). That is, the upper electrode of the auxiliary capacitor is kept at the same potential in all the pixels.
[0121]
Next, a source electrode (source line) 15 and a drain electrode 16 are formed on the gate line 13 and the upper electrode 14 of the auxiliary capacitor via a first interlayer insulating film. These electrodes correspond to the source electrode 165 and the drain electrode 167 in FIG.
[0122]
Although not shown, after that, as shown in FIG. 4C, an interlayer insulating film 168 and a pixel electrode 169 are formed, and a known liquid crystal display device is completed by performing a known cell assembling process. With the structure as in this embodiment, even when the pixel area is reduced, it is possible to secure the auxiliary capacitance by making the most of the area.
[0123]
Example 12
The present invention can also be applied to a transmissive liquid crystal display device. Since the TFT manufacturing process is basically the same as that described in Embodiment 1, detailed description thereof is omitted.
[0124]
In Example 1, a material mainly composed of aluminum is used as the pixel electrode, but in this example, an ITO film is used as the transparent conductive film. In addition, since it is an important issue to increase the aperture ratio in the transmission type, the electric field shielding film, the black mask, and the like may be provided in a necessary size at a minimum size.
[0125]
Here, FIG. 12 shows a top view of the transmissive liquid crystal display device of this example. In order to easily explain a specific structure, a top view of a state where source / drain electrodes are formed will be described. Accordingly, description of the pixel electrode, the electric field shielding film, the black mask, and the like is omitted.
[0126]
In FIG. 12, reference numeral 21 denotes an active layer, and a lower electrode portion 22 of an auxiliary capacitor is formed on a part (drain region side). Further, a gate electrode (gate line) 23 is disposed on the active layer 21, and an auxiliary electrode upper electrode 24 is disposed on the lower electrode 22. Since the lower electrode 22 is covered with the upper electrode 24, it is indicated by a dotted line in FIG. Of course, a gate insulating film is sandwiched between the lower electrode 22 and the upper electrode 24 to form an auxiliary capacitor.
[0127]
A source electrode (source line) 25 is formed so as to intersect the gate electrode 23 and the upper electrode 24. The source electrode 25 is electrically connected to the source region of the active layer 21 through a contact portion 26.
[0128]
Actually, a black mask is provided to shield the active layer and each wiring, or an electric field shielding film is provided between the upper and lower wirings. A pixel electrode (not shown) is electrically connected to the drain region of the active layer 21 through the contact portion 27.
[0129]
With the above structure, a transmissive liquid crystal display device can be manufactured. Needless to say, the present invention is not limited to the device structure shown in FIG.
[0130]
Example 13
A simplified cross-sectional view of the reflective liquid crystal display device described in Example 1 is shown in FIG. Note that since the description of the active matrix substrate has already been made in the first embodiment, other structures will be described here.
[0131]
In FIG. 13, 31 is a light-transmitting substrate, and 302 is a transparent conductive film. Although omitted here, a color filter, an alignment film, a black mask, and the like may be provided on the light-transmitting substrate 31 in addition. These are collectively called a counter substrate.
[0132]
A liquid crystal layer 34 is sandwiched between the counter substrate and the active matrix substrate surrounded by the sealing material 33. Since the present invention is compatible with all modes such as the ECB mode and the guest host mode, the liquid crystal material may be changed accordingly. In addition, a color filter may be required depending on such a drive mode. Furthermore, a polarizing plate may be used depending on the driving mode of the liquid crystal display device.
[0133]
In this embodiment, the liquid crystal layer is not disposed above the peripheral circuit, and a parasitic capacitance is prevented from being formed between the peripheral circuit and the transparent conductive film 32 on the opposite side. Of course, the liquid crystal layer may be arranged on the entire surface of the substrate.
[0134]
FIG. 14 shows an example of an arrangement configuration of each circuit arranged on the active matrix substrate. In FIG. 14, 41 is a substrate, 42 is a base film, 43 is a pixel matrix circuit, 44 is a source driver circuit, 45 is a gate driver circuit, and 46 is a logic circuit.
[0135]
The above is the outline of the reflective liquid crystal display device, but the basic configuration of the transmissive liquid crystal display device is not changed. Thus, the present invention can be applied to a liquid crystal display device having any structure.
[0136]
Example 14
The present invention can also be applied to electro-optical devices other than liquid crystal display devices. Examples of such an electro-optical device include an EL (electroluminescence) display device and an EC (electrochromic) display device.
[0137]
Example 15
In this embodiment, an example of an application product (electronic device) using the electro-optical device using the present invention is shown in FIG. Application products using the present invention include video cameras, still cameras, projectors, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, etc.), and the like.
[0138]
FIG. 15A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the display device 2004.
[0139]
FIG. 15B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102.
[0140]
FIG. 15C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205.
[0141]
FIG. 15D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.
[0142]
FIG. 15E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.
[0143]
FIG. 15F illustrates a front type projector which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.
[0144]
As described above, the application range of the present invention is extremely wide and can be applied to display media in various fields. In particular, when the liquid crystal display device is used in a projection type display device such as a projector, a very high resolution is required. In such a case, the present invention is a very effective technique.
[0145]
【The invention's effect】
The manufacturing process is simplified by sharing the step of forming the region for gettering the catalyst element and the step of forming the lower electrode of the auxiliary capacitor. Therefore, throughput, yield, etc. are improved, which is economically beneficial.
[0146]
Furthermore, the crystalline film obtained by using the present invention is very excellent in crystallinity due to the effect of the catalytic element, and the catalytic element is removed or reduced by the gettering treatment. Therefore, when used as an active layer of a semiconductor device, a semiconductor device having excellent electrical characteristics and high reliability can be obtained.
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of a semiconductor device. FIGS.
FIGS. 2A to 2D are diagrams illustrating a manufacturing process of a semiconductor device. FIGS.
FIGS. 3A to 3D are diagrams illustrating a manufacturing process of a semiconductor device. FIGS.
4A and 4B illustrate a manufacturing process of a semiconductor device.
FIGS. 5A to 5D are diagrams illustrating a manufacturing process of a semiconductor device. FIGS.
6A and 6B illustrate a manufacturing process of a semiconductor device.
FIGS. 7A to 7C illustrate a manufacturing process of a semiconductor device. FIGS.
FIGS. 8A to 8D are diagrams illustrating a manufacturing process of a semiconductor device. FIGS.
FIG. 9 illustrates a manufacturing process of a semiconductor device.
10 is a diagram illustrating a manufacturing process of a semiconductor device. FIG.
FIG. 11 is a top view of a pixel region.
FIG. 12 is a top view of a pixel region.
FIG. 13 is a cross-sectional view of a liquid crystal display device.
FIG. 14 is a diagram schematically showing an active matrix substrate.
FIG. 15 is a diagram showing an example of an applied product.
[Explanation of symbols]
101 Quartz substrate
102 Amorphous silicon film
103 Mask insulation film
104, 105 opening
106 Nickel-containing layer
107,108 Nickel added region
109, 110 Horizontal growth region
111 opening
112, 113 Phosphorus added region (gettering site)
114 Phosphorus added region (lower electrode of auxiliary capacitance)
115, 116 lateral growth region
117-119 active layer
120 Gate insulation film

Claims (13)

Forming a first insulating film having a first opening on an amorphous film containing silicon ;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask ;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment ,
Forming a second opening in the first insulating film on the region serving as the lower electrode of the storage capacitor ;
Wherein among the film containing the obtained silicon crystallization step, adding the first opening and the second 15 group element against the bottom of the opening at the same time,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment ;
Patterning the region to be the lower electrode of the active layer and the storage capacitor of the semiconductor element of the element forming portion,
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor ;
Through each of the second insulating film on the lower electrode of the active layer and the storage capacitor, a method for manufacturing a semiconductor device according to claim Rukoto forming form a crystalline silicon film having a metal film or one conductivity . In a method for manufacturing a semiconductor device having a peripheral circuit and a pixel matrix circuit over the same substrate,
Forming a first insulating film having an opening only in a region to be the pixel matrix circuit on the amorphous film containing silicon ;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask ;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment ,
Group 15 elements for the region to be the lower electrode area and the auxiliary capacitor adjacent to the element forming portion simultaneously added,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment ;
Patterning a region to be an active layer of a semiconductor element of the element formation portion and a lower electrode of the auxiliary capacitor;
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor;
Through each of the second insulating film on the lower electrode of the active layer and the storage capacitor, a method for manufacturing a semiconductor device which is characterized that you form a crystalline silicon film having a metal film or one conductivity . In a method for manufacturing a semiconductor device having a peripheral circuit and a pixel matrix circuit over the same substrate,
Forming a first insulating film having an opening only in a region to be the peripheral circuit on the amorphous film containing silicon ;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask ;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment ,
Group 15 elements for the region to be the lower electrode area and the auxiliary capacitor adjacent to the element forming portion simultaneously added,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment ;
Patterning a region to be an active layer of a semiconductor element of the element formation portion and a lower electrode of the auxiliary capacitor;
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor;
Through each of the second insulating film on the lower electrode of the active layer and the storage capacitor, a method for manufacturing a semiconductor device which is characterized that you form a crystalline silicon film having a metal film or one conductivity . Forming a first insulating film having a first opening on an amorphous film containing silicon;
Forming an oxide film on the surface of the amorphous film containing silicon in the region exposed by the first opening;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment,
Forming a second opening in the first insulating film on the region serving as the lower electrode of the storage capacitor;
Of the silicon-containing film obtained in the crystallization step, a group 15 element is simultaneously added to the bottom of the first opening and the second opening,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment;
Patterning a region to be an active layer of a semiconductor element of the element forming portion and a lower electrode of the auxiliary capacitor;
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor;
  A method for manufacturing a semiconductor device, comprising: forming a metal film or a crystalline silicon film having one conductivity over the active layer and the lower electrode of the storage capacitor through the second insulating film, respectively. In a method for manufacturing a semiconductor device having a peripheral circuit and a pixel matrix circuit over the same substrate,
Forming a first insulating film having an opening only in a region to be the pixel matrix circuit on the amorphous film containing silicon;
Forming an oxide film on the surface of the amorphous film containing silicon in the region to be the peripheral circuit and the region exposed by the opening;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment,
A group 15 element is simultaneously added to a region adjacent to the element formation portion and a region serving as a lower electrode of a storage capacitor,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment;
Patterning a region to be an active layer of a semiconductor element of the element forming portion and a lower electrode of the auxiliary capacitor;
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor;
A method for manufacturing a semiconductor device, comprising: forming a metal film or a crystalline silicon film having one conductivity over the active layer and the lower electrode of the storage capacitor through the second insulating film, respectively. In a method for manufacturing a semiconductor device having a peripheral circuit and a pixel matrix circuit over the same substrate,
Forming a first insulating film having an opening only in a region to be the peripheral circuit on the amorphous film containing silicon;
Forming an oxide film on a surface of the amorphous film containing silicon in a region to be the pixel matrix circuit and a region exposed by the opening;
Holding or adding a catalyst element for promoting crystallization of the silicon to the amorphous film containing silicon using the first insulating film as a mask;
The element forming part of the amorphous film containing silicon is crystallized by heat treatment,
A group 15 element is simultaneously added to a region adjacent to the element formation portion and a region serving as a lower electrode of a storage capacitor,
Gettering the catalyst element in the region where the group 15 element is added by heat treatment;
Patterning a region to be an active layer of a semiconductor element of the element forming portion and a lower electrode of the auxiliary capacitor;
Forming a second insulating film on the patterned active layer and the lower electrode of the auxiliary capacitor;
A method for manufacturing a semiconductor device, comprising: forming a metal film or a crystalline silicon film having one conductivity over the active layer and the lower electrode of the storage capacitor through the second insulating film, respectively. In any one of claims 1 to 6, the addition of the Group 15 element, a method for manufacturing a semiconductor device, characterized in that also serves as a form Chengdu of the lower electrode of the storage capacitor and the formation of the gettering region.   8. The method for manufacturing a semiconductor device according to claim 1, wherein the catalyst element is Ni, Co, Fe, Pd, Pt, Cu, or Au.   9. The method for manufacturing a semiconductor device according to claim 1, wherein the catalytic element is added by an ion plantation method.   10. The method for manufacturing a semiconductor device according to claim 1, wherein the Group 15 element is P, As, Sb, or Bi. In any one of claims 1 to 10, wherein the Group 15 elemental a method for manufacturing a semiconductor device characterized by being added by an ion implantation method or plasma doping method. In any one of claims 1 to 11, wherein the Group 15 elemental a method for manufacturing a semiconductor device characterized by being added with a dose of ^{1 × 10 13 ~8 × 10 15} atoms / cm 2. In any one of claims 1 to 12, a method for manufacturing a semiconductor device characterized by gettering grayed by the Group 15 element is carried out at 500 to 700 ° C..

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