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JP4019989B2 - Semiconductor device - Google Patents

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Publication number
JP4019989B2
JP4019989B2 JP2003085504A JP2003085504A JP4019989B2 JP 4019989 B2 JP4019989 B2 JP 4019989B2 JP 2003085504 A JP2003085504 A JP 2003085504A JP 2003085504 A JP2003085504 A JP 2003085504A JP 4019989 B2 JP4019989 B2 JP 4019989B2
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relay member
heat radiating
heat
semiconductor switching
semiconductor
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JP2004296663A (en
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康嗣 大倉
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for coping with both a low surge voltage and high heat radiation properties. <P>SOLUTION: A semiconductor package 100 comprises a pair of flat semiconductor switching elements 1, 2; a relay member 4 for forming a middle point electrode; radiating members 3, 5 arranged at a side opposite to the relay member 4 to each of the semiconductor switching elements 1, 2; and a mold resin section 15. The relay member 4 has an element mounting section 41 directly or indirectly joined to each of the semiconductor switching elements 1, 2 and heat radiation sections 42, 42 provided adjacent to the element mounting section 41. The section has an H shaped profile. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関する。
【０００２】
【従来の技術】
モータ駆動用インバータ回路に使用される半導体パワー素子において、放熱性能を向上させるため、ボンディングワイヤが接続されている表面（ＩＧＢＴではエミッタ面）側にも放熱部材（ヒートシンク）を設けるとともに、一体に樹脂モールドしたパワー素子パッケージが考案されている。代表的なパワー素子であるＩＧＢＴ（Insulated Gate Bipolar Transistor）を例にすると、パワー素子の上下面にそれぞれ露出するエミッタとコレクタは、そのパワー素子（以下、半導体スイッチング素子ともいう）の上下に配されるヒートシンクに直接またはスペーサを介してそれぞれ半田接続される。この場合のヒートシンクは、大電流経路としての機能も有する。一方、パワー素子のゲート（制御電極）と、モールド樹脂の外に延出する制御信号リード端子とは、ボンディングワイヤにより導通接続される。
【０００３】
インバータ回路を構成する場合、上相スイッチング素子と下相スイッチング素子とが直列接続される。そのため、各スイッチング素子を１つ１つ個別に樹脂モールドするよりも、予め直列接続した形で樹脂モールドすることが提案されている。すなわち、下記特許文献１には、上相スイッチング素子と下相スイッチング素子とを一体に樹脂モールドした２ｉｎ１半導体パワーパッケージの構造が開示されている。このような半導体パワーパッケージは、部品点数の低減という観点で極めて有利である。また、各スイッチング素子に共有される放熱部材が、モータ等の負荷に接続される中点電極となるため、中点電極が持つインダクタ成分も小さくできる。インダクタ成分の低減は、サージ電圧の低減に直結するので非常に好ましい。
【０００４】
インダクタ成分の低減という点に着目すれば、上相スイッチング素子と下相スイッチング素子とを、なるべく接近させるほうがよい。すなわち、下記特許文献２には、上相スイッチング素子と下相スイッチング素子とを、縦積みして一体樹脂モールドしたパッケージ構造が開示されている。
【０００５】
【特許文献１】
特開２００１−３０８２６３号公報
【特許文献２】
特開２００２−２６２５１号公報
【０００６】
【発明が解決しようとする課題】
確かに、上記特許文献２に記載された構造によれば、上記特許文献１に記載された構造よりも中点電極のインダクタ成分を小さくできるため、サージ電圧の低減という点では有利である。しかしながら、上記特許文献２に記載された構造では、各スイッチング素子の冷却が、一方の主面側からしか行なわれないという問題がある。放熱性という点では、特許文献１に記載されているように、各スイッチング素子を面内方向に並べて配置し、両面から冷却できるようにする構造のほうが好ましい。
【０００７】
本発明の課題は、低サージ電圧と、高放熱性とを両立した半導体装置を提供することにある。
【０００８】
【課題を解決するための手段及び作用・効果】
上記課題を解決するために第１の本発明の半導体装置は、厚さ方向に所定の間隔を置いて平行配置された、１対の板状の半導体スイッチング素子と、それら半導体スイッチング素子の中点電極をなす中継部材と、半導体スイッチング素子の各々に対し、中継部材とは反対側に配置された放熱部材と、それら放熱部材と中継部材との間を充填するモールド樹脂部とを備え、半導体スイッチング素子の厚さ方向を上下方向としたとき、中継部材は、上下に配置された半導体スイッチング素子の各々に直接または間接接合された素子搭載部と、該素子搭載部に隣接して設けられ、上下方向に関して素子搭載部よりも厚肉に形成された放熱部と、を含み、前記放熱部材の各々は、互いに略平行な放熱面を有し、前記中継部材の前記放熱部は、前記放熱部材の各放熱面と略平行な第一放熱面と、該第一放熱面に隣接する第二放熱面とを形成し、前記放熱部材が有する放熱面と、前記中継部材の前記第一放熱面とが面一となるように調整されていることを特徴とする。
【０００９】
上記本発明の半導体装置は、２つの半導体スイッチング素子を、中継部材を介して縦積みし、さらに上下に放熱部材を配置したものである。１対の放熱部材は、たとえば板状の金属部材であり、電流経路に兼用することができる。各スイッチング素子の間に介挿される中継部材は、中点電極をなしている。各半導体スイッチング素子が縦積みされる構造なので、中継部材の持つインダクタ成分を小さくすることができる。この中継部材は、従来の縦積み構造（特許文献２参照）だとモールド樹脂部に埋もれて冷却機能を有していなかった。ところが本発明の半導体装置では、半導体スイッチング素子が接合される素子搭載部よりも、上下方向に厚肉な放熱部を素子搭載部に隣接して設けるようにしている。したがって、放熱部の少なくとも一部がモールド樹脂部から露出するようにすれば、半導体スイッチング素子→素子搭載部→放熱部→外気（または冷却器）という放熱経路を確保でき、中継部材自体の冷却機能を、十分に期待できる。
【００１０】
好適な態様において、放熱部材の各々は、互いに略平行な放熱面を有し、中継部材の放熱部は、放熱部材の各放熱面と略平行な第一放熱面と、該第一放熱面に隣接する第二放熱面とを形成している。このように、中継部材の持つ放熱面を、各半導体スイッチング素子の上または下に配置される放熱部材の放熱面と平行にすれば、それらの放熱面を同一方向より冷却することが可能となる。すなわち、冷却器を配置するような場合に有利である。
【００１１】
具体的に、上記好適態様において、放熱部は、素子搭載部と一体に成形されたものであるとともに、上下方向において放熱部材のいずれとも重ならない位置で上記した第一放熱面を形成している。素子搭載部と放熱部とを一体にすることにより、熱抵抗をできるだけ小さくできる。また、各半導体スイッチング素子に専用の放熱部材に、放熱部が形成する第一放熱面が上下方向で重ならないようにしているので、第一放熱面を露出させるようにモールド樹脂部を形成することも、比較的容易にできる。
【００１２】
より好適には、放熱部材が有する放熱面と、中継部材の第一放熱面とが面一となるように構成することである。これによれば、上記の両放熱面を同一方向より冷却することが一層容易になる。
【００１３】
また、本発明の半導体装置を製造するにあたって、半導体スイッチング素子と中継部材との接合、半導体スイッチング素子と放熱部材との接合は、各部品同士を治具で固定して行なうこととなる。放熱部材が有する放熱面と、中継部材の第一放熱面とが面一である場合、第一放熱面を基準に、放熱部材と中継部材との組付けおよび治具固定を、容易かつ高精度に行なえる。これにより、たとえば半田リフロー後、あるいは樹脂モールド後における、本半導体装置を構成する各部品同士の組付け精度の向上を見込める。また、放熱部材同士の平行出しが高精度に行なわれていると、各放熱部材と冷却器との密着性が高まり、冷却効率も高くなる。
【００１４】
また、本発明の半導体装置は、一端がモールド樹脂部に埋設されて半導体スイッチング素子の制御電極に導通し、他端が前記モールド樹脂部の外側に引き出される制御信号リード端子が設けられる。そして、中継部材の素子搭載部には、制御信号リード端子の引き出し方向と略直交する方向の両側に放熱部を隣接させることができる。このようにすると、放熱部を一方側にのみ設ける場合よりも、放熱面の面積を単純に２倍にできる。また、四方からの冷却が可能となる点も見逃せない。
【００１５】
また、中継部材は、上下方向に関する断面でＨ形状を呈するように構成されているとよい。つまり、アルファベットの“Ｈ”に基づく２箇所の凹所に、１対の半導体スイッチング素子をちょうど収容できるので、Ｈ形状は、極めて都合よくできた形状であるといえる。
【００１６】
また、中継部材は、放熱部の第一放熱面と第二放熱面とが略垂直に交差するように構成するとよい。そして、素子搭載部の上下面と、放熱部の内側面とにより半導体スイッチング素子の収容凹所が形成される。このような構成によれば、モールド樹脂部の成形容易性も高い。なお、成形金型との間に要求される抜き角度程度の傾きは、略垂直に含まれる。
【００１７】
また、第２の本発明の半導体装置は、厚さ方向に所定の間隔を置いて平行配置された、１対の板状の半導体スイッチング素子と、それら半導体スイッチング素子の中点電極をなす中継部材と、前記半導体スイッチング素子の各々に対し、前記中継部材とは反対側に配置された放熱部材と、それら放熱部材と前記中継部材との間を充填するモールド樹脂部とを備え、前記半導体スイッチング素子の厚さ方向を上下方向としたとき、前記中継部材は、上下に配置された前記半導体スイッチング素子の各々に直接または間接接合された素子搭載部と、該素子搭載部に隣接して設けられ、前記上下方向に関して前記素子搭載部よりも厚肉に形成された放熱部と、を含み、前記上下方向に関し、前記中継部材の前記素子搭載部は、前記放熱部材よりも厚肉であることを特徴とする。この構成によれば、半導体スイッチング素子に発生する熱を、放熱部に素早く伝達させることができる。
【００１８】
また、一方の半導体スイッチング素子が、上下方向に関し、他方の半導体スイッチング素子の真上または真下に位置している。この配置によれば、各半導体スイッチング素子の距離を最小、すなわち、中継部材が持つインダクタ成分を、できるだけ小さくできる。
【００１９】
【発明の実施の形態】
以下、添付の図面を参照しつつ本発明の実施形態について説明する。
図１および図２に示すのは、本発明にかかる２ｉｎ１両面放熱半導体パッケージ１００（場合によっては４面冷却）の斜視図である。図３に示すのは、図２中に示すＡ−Ａ’線を含む断面模式図である。ただし、図１では、モールド樹脂部１５を除去した形態を示している。
【００２０】
このような半導体パッケージ１００は、たとえばブラシレスモータ用の三相インバータ回路の一部を構成する。半導体スイッチング素子１，２（以下、単に半導体チップともいう）の種類には、たとえばＩＧＢＴやパワーＭＯＳＦＥＴを示すことができる。本実施形態では、パワーＭＯＳＦＥＴを例示している。
【００２１】
図１および図２に示すように、半導体パッケージ１００は、厚さ方向の上下に平行配置された１対の半導体チップ１，２と、中点電極をなすＨ形状の中継部材４と、半導体チップ１，２の各々に対し、中継部材４の素子搭載部４１とは反対側に配置された放熱部材３，５とを互いに組付けて一体化したものである。中継部材４は、半導体チップ１，２が直接または導体ブロック６を介して接合される素子搭載部４１と、該素子搭載部４１に隣接する放熱部４２，４２とから構成されている。この中継部材４は、素子搭載部４１が半導体チップ１，２より取得した熱を、放熱部４２，４２より半導体パッケージ１００の外部に放出させることが可能である。以下、詳しく説明する。
【００２２】
薄板状の半導体チップ１，２は、互いに等価な回路構成を有し、一方の主面側にゲートとソース（ＩＧＢＴの場合はエミッタ）が露出し、他方の主面側にドレイン（ＩＧＢＴの場合はコレクタ）が露出するように構成されている。インバータ回路の上相をなす上相半導体チップ１と放熱部材３とは、半田や銀ロウなどの接合材１３により直接接合されおり、上相半導体チップ１のドレインと放熱部材３とが導通して同電位となっている。また、上相半導体チップ１と、中継部材４の素子搭載部４１とは、導体ブロック６を介して接合材１３，１３により接合されており、上相半導体チップ１のソースと中継部材４とが導通して同電位となっている。
【００２３】
インバータ回路の下相をなす下相半導体チップ２と放熱部材５とは、導体ブロック７を介して接合材１３，１３により接合され、下相半導体チップ２のソースと放熱部材５とが導通して同電位となっている。また、下相半導体チップ２と、中継部材４の素子搭載部４１とは、接合材１３により直接接合されており、下相半導体チップ２のドレインと中継部材４とが導通して同電位となっている。
【００２４】
また、半導体パッケージ１００には、一端がモールド樹脂部１５に埋設されて半導体チップ１，２のゲート等の電極に導通し、他端がモールド樹脂部１５の外側に引き出される制御信号リード端子群１１，１２（または端子）が設けられている。個々の制御信号リード端子は、ボンディングワイヤ１４により半導体チップ１，２に接続されている。制御信号リード端子群１１，１２は、たとえばゲート制御リード端子、温度検出リード端子（アノード側とカソード側を含む）、電流検出リード端子、電位検出リード端子などを含む。
【００２５】
各半導体チップ１，２に専用の放熱部材３，５は、それぞれ扁平状または板状の形態をなす。放熱部材３，５は、モールド樹脂部１５の外側に露出し、互いに略平行な放熱面３ｐ，５ｐを有する。各放熱部材３，５は、熱伝導性および電気伝導性の観点から、たとえばＣｕ、Ｗ、ＭｏおよびＡｌのグループから選択される１種の金属材料、もしくはそれらの金属材料を主体とする合金により構成されることが好ましい。なお、中継部材４および導体ブロック６，７についても、放熱部材３，５と同様の材料にて構成するとよい。
【００２６】
なお、樹脂バリの発生により、外観上、放熱部材３，５の放熱面３ｐ，５ｐがモールド樹脂部１５に埋没する場合がある。その場合には、研削などの加工により、放熱面３ｐ，５ｐをモールド樹脂部１５から露出させるとよい。これについては、以下に説明する中継部材４の、第一放熱面４ｐおよび第二放熱面４ｑについても同様のことが言える。
【００２７】
上相半導体チップ１側の放熱部材３には、電源正極に接続されるＰ側電極リード端子８が一体に取り付けられている。下相半導体チップ２側の放熱部材５には、電源負極に接続されるＮ側電極リード端子１０が一体に取り付けられている。中継部材４には、中点電極リード端子９が一体に取り付けられている。Ｐ側電極リード端子８、Ｎ側電極リード端子１０および中点電極リード端子９は、モールド樹脂部１５の外側に延出している。
【００２８】
本実施形態においては、上記した電流経路用の各リード端子８，９，１０と、制御信号リード端子群１１，１２とを同一方向に引き出すようにして、製造時の利便性を図っている（詳細は後述）。ただし、電流経路用のリード端子８，９，１０と、制御信号リード端子群１１，１２とを１８０°反対側方向、もしくは９０°の角度で交差する方向に引き出すことも不可能ではない。
【００２９】
モールド樹脂部１５は、半導体チップ１，２の周側面を被覆するとともに、中継部材４および放熱部材３，５により形成される空間を充填している。モールド樹脂部１５は、たとえばエポキシ樹脂により構成されるものであり、半導体パッケージ１００を構成する各部品を接合材１３で接合した後に、インサート成形法等の樹脂成形方法により形成される。
【００３０】
上相半導体チップ１と、下相半導体チップ２との中点電極（具体的にはインバータ回路の中点電極）をなす中継部材４は、素子搭載部４１と放熱部４２，４２とから構成されている。素子搭載部４１が受けた熱は、放熱部４２，４２に伝達されて、半導体パッケージ１００の外部に放出される。これにより、上相半導体チップ１のソース露出面と、下相半導体チップ２のドレイン露出面との冷却が可能となる。
【００３１】
素子搭載部４１には、中点電極リード端子９が一体に取り付けられている。中点電極リード端子９は、モータ等の負荷に接続されるものである。放熱部４２，４２は、素子搭載部４１の両側に位置している。素子搭載部４１と、放熱部４２，４２とは鋳造等の金属成形法により一体成形される。そのため、両者の間の熱伝達性は良好である。
【００３２】
半導体チップ１，２の厚さ方向を上下方向と定義する。放熱部４２，４２は、中継部材４のうち、上下方向において、素子搭載部４１よりも厚肉に形成された部分を構成している。素子搭載部４１には、半導体チップ１，２の制御信号リード端子群１１，１２、Ｐ側電極リード端子８、中点電極リード端子９およびＮ側電極リード端子１０の、モールド樹脂部１５の外側への引き出し方向に直交する方向の両側に放熱部４２，４２が位置する形となっている。これは、放熱部４２，４２の形成により、リードの引き出しが邪魔されない構造である。
【００３３】
図２に示すように、放熱部４２，４２は、モールド樹脂部１５の外側に露出する放熱面４ｐ，４ｑを形成している。放熱部４２，４２が形成する放熱面は、放熱部材３，５の放熱面３ｐ，５ｐと略平行な第一放熱面４ｐと、該第一放熱面４ｐに隣接する第二放熱面４ｑとを含む。本実施形態の半導体パッケージ１００においては、第一放熱面４ｐと、第二放熱面４ｑとが互いに略直交している。モールド樹脂部１５成形用の金型に対する微小な抜き角度を、上記第二放熱面４ｐに付与してもよい（略直交とする理由の１つ）。
【００３４】
図１〜図３に示す半導体パッケージ１００においては、各半導体チップ１，２に専用の放熱部材３，５と、放熱部４２，４２が形成する複数（半導体パッケージ１００では４面）の第一放熱面４ｐとが、上下方向において互いに重ならない位置関係となっている。具体的には、図３から明らかなように、各放熱部材３，５の放熱面３ｐ，５ｐと、中継部材４の１対の放熱部４２，４２に２面ずつ形成される第一放熱面４ｐ，４ｐとは面一である。これにより、放熱部材３，５の放熱面３ｐ，５ｐを冷却する冷却器と、中継部材４の第一放熱面４ｐ，４ｐを冷却する冷却器との兼用が容易である。また、半田リフローに先立って行なうべき、放熱部材３，５と中継部材４との組付けおよび治具固定を、中継部材４の第一放熱面４ｐ，４ｐを基準に行なえる。したがって、半田リフロー後における、放熱部材３、放熱部材５および中継部材４の、３者の組付け精度を高くできる。放熱部材３，５の放熱面３ｐ，５ｐの平行精度が高いと、図示しない冷却器との密着性も良好となり、高冷却効率を期待できる。
【００３５】
図３に示すように、半導体パッケージ１００を構成する中継部材４は、放熱部４２，４２を含む上下方向に関する断面でＨ形状を呈している。具体的には、放熱部４２，４２の第一放熱面４ｐと、第二放熱面４ｑとが略垂直に交わり、さらに、素子搭載部４１の上下面４１ｒ，４１ｒと、放熱部４２，４２の内側面４２ｒ，４２ｒとにより、半導体チップ１，２の収容凹所が形成されている。この凹所の深さは、半導体チップ１、放熱部材３、導体ブロック６および３層の接合部１３の合計厚さに等しく調整される。
【００３６】
また、図３に示すように、素子搭載部４１の厚さは一定とされ、その厚さｄ１は、各放熱部材３，５の厚さｄ２よりも大となるように調整されている。これにより、半導体チップ１，２から素子搭載部４１に付与された熱が、効率良く放熱部４２，４２に伝達される。
【００３７】
なお、図５の断面模式図に示す半導体パッケージ１０２の中継部材４ｂも、Ｈ形状の概念に含まれる。すなわち、上下方向に関する素子搭載部４３の厚さを一定とし、第一放熱面４ｐおよび第二放熱面４ｑを有する放熱部４４，４４の、上下方向に関する厚さが連続的に変化していてもよい。場合によっては、その方が（図５の形態）、素子搭載部４３の上下面４３ｒ，４３ｒと、放熱部４４，４４の内側面４４ｒ，４４ｒとにより形成された収容凹所への、モールド樹脂の流れ込み性の良化を期待できる。
【００３８】
また、図４の断面模式図に示す半導体パッケージ１０１も、好適な実施形態の１つとして示せる。半導体パッケージ１０１は、断面Ｔ字形状を呈する中継部材４ａを備えている。図１〜図３に示した中継部材４のうち、一方の放熱部４２を省略した形態が、図４に示す中継部材４ａである。断面Ｔ字形状の中継部材４ａによれば、断面Ｈ形状の中継部材４に比べ、冷却効率は若干低下するものの、以下に示す利点が得られる。すなわち、中継部材４ａのうち、素子搭載部４１の一方の端に放熱部４２を設け、その放熱部４２が設けられた側とは１８０°反対側から、制御信号リード端子１１，１２、Ｐ側電極リード端子８（図示せず）、中点電極リード端子９（図示せず）およびＮ側電極リード端子１０をモールド樹脂部１５の外側に引き出すことができる。もちろん、半導体パッケージ１０２自体もコンパクトである。
【００３９】
なお、図１〜図５に示す半導体パッケージ１００，１０１，１０２のいずれについても、上相半導体チップ１が、下相半導体チップ２の真下（または真上）に位置する配置が採用されている。つまり、両半導体チップ１，２が上下方向において並進対称である。この配置は、中継部材４，４ａ，４ｂの持つインダクタ成分をできる限り小さくするという観点において有利である。
【００４０】
半導体パッケージ１００の組立は、以下の手順にて行なうことができる。図６に示すように、まず、上相半導体チップ１を、放熱部材３に載置する。放熱部材３には、半田接合材１３がスクリーン印刷等の方法により形成されている。上相半導体チップ１のゲート等の電極と、上相制御信号リード端子群１１とをボンディングワイヤ１４で接続する。上相半導体チップ１の上に、半田接合材１３を介して導体ブロック６を載置する。その後、半田リフローを行なう。
【００４１】
なお、上記の組立工程には、リードフレームを使用した公知の方法を採用するとよい。すなわち、放熱部材３と一体形成されたＰ側電極リード端子８が、モールド樹脂部１５の形成後に切断可能な連結部により上相制御信号リード端子群１１と連結されてなる、リードフレームを使用することができる。つまり、Ｐ側電極リード端子８と上相制御信号リード端子群１１とを同一方向に引き出すのは、リードフレームを用いた製法上の要請でもある。
【００４２】
同様の手順にて、下相半導体チップ２と中継部材４とを接合する。そして、図７に示すように、上相半導体チップ１と、下相半導体チップ２とを位置決めおよび治具固定して、導体ブロック６と中継部材４、導体ブロック７と放熱部材５とを半田接合する。その後、インサート成形法等によりモールド樹脂部１５を形成し、各リード端子同士を分離させることにより、図２に示す半導体パッケージ１００が得られる。
【図面の簡単な説明】
【図１】本発明の半導体パッケージの斜視図（モールド樹脂部無し）。
【図２】本発明の半導体パッケージの斜視図（モールド樹脂部有り）。
【図３】本発明の半導体パッケージの断面模式図。
【図４】半導体パッケージの好適な別形態を示す断面模式図。
【図５】半導体パッケージの好適な別形態を示す断面模式図。
【図６】図１の半導体パッケージの組立手順を示す分解斜視図。
【図７】図６に続く半導体パッケージの分解斜視図。
【符号の説明】
１ 半導体スイッチング素子（上相）
２ 半導体スイッチング素子（下相）
３，５ 放熱部材
３ｐ，５ｐ 放熱部材の放熱面
４，４ａ，４ｂ 中継部材
４ｐ 第一放熱面
４ｑ 第二放熱面
６，７ 導体ブロック（スペーサ）
１１ 上相制御信号リード端子群
１２ 下相制御信号リード端子群
１５ モールド樹脂部
４１，４３ 素子搭載部
４２，４４ 放熱部
１００，１０１，１０２ 半導体パッケージ（半導体装置）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device.
[0002]
[Prior art]
In a semiconductor power device used in an inverter circuit for driving a motor, a heat radiating member (heat sink) is also provided on the surface (emitter surface in IGBT) side to which a bonding wire is connected in order to improve heat radiating performance. A molded power element package has been devised. Taking an IGBT (Insulated Gate Bipolar Transistor) as a typical power element as an example, the emitter and collector exposed on the upper and lower surfaces of the power element are arranged above and below the power element (hereinafter also referred to as a semiconductor switching element). Soldered to the heat sink directly or via a spacer. The heat sink in this case also has a function as a large current path. On the other hand, the gate (control electrode) of the power element and the control signal lead terminal extending out of the mold resin are conductively connected by a bonding wire.
[0003]
When configuring an inverter circuit, an upper phase switching element and a lower phase switching element are connected in series. For this reason, it has been proposed that resin molding is performed in advance in series rather than individually molding each switching element individually. That is, Patent Document 1 below discloses a structure of a 2-in-1 semiconductor power package in which an upper phase switching element and a lower phase switching element are integrally resin-molded. Such a semiconductor power package is extremely advantageous from the viewpoint of reducing the number of parts. Moreover, since the heat radiating member shared by each switching element serves as a midpoint electrode connected to a load such as a motor, the inductor component of the midpoint electrode can be reduced. Reduction of the inductor component is very preferable because it directly leads to reduction of the surge voltage.
[0004]
If attention is paid to the reduction of the inductor component, it is better to bring the upper phase switching element and the lower phase switching element as close as possible. That is, the following Patent Document 2 discloses a package structure in which an upper phase switching element and a lower phase switching element are stacked vertically and integrally molded with resin.
[0005]
[Patent Document 1]
JP 2001-308263 A [Patent Document 2]
JP-A-2002-26251 [0006]
[Problems to be solved by the invention]
Certainly, according to the structure described in Patent Document 2, the inductor component of the midpoint electrode can be made smaller than that in the structure described in Patent Document 1, so that it is advantageous in terms of reducing the surge voltage. However, the structure described in Patent Document 2 has a problem that each switching element is cooled only from one main surface side. In terms of heat dissipation, as described in Patent Document 1, a structure in which the switching elements are arranged in the in-plane direction and can be cooled from both sides is preferable.
[0007]
An object of the present invention is to provide a semiconductor device that achieves both low surge voltage and high heat dissipation.
[0008]
[Means for solving the problems and actions / effects]
In order to solve the above-described problems, a semiconductor device according to a first aspect of the present invention includes a pair of plate-like semiconductor switching elements arranged in parallel at a predetermined interval in the thickness direction, and a midpoint of these semiconductor switching elements. a relay member having an electrode, against each of the semiconductor switching element, comprising: a heat radiating member arranged on the opposite side of the relay member, and a mold resin portion filling the between their heat radiating member and the relay member, the semiconductor When the thickness direction of the switching element is the vertical direction, the relay member is provided adjacent to each of the element mounting parts directly or indirectly joined to each of the semiconductor switching elements arranged above and below, seen including a heat radiating portion which is formed thicker than the element mounting portion in the vertical direction, the each of the heat radiating member has a substantially parallel radiating surfaces to each other, the heat radiating portion of the relay member, the heat dissipation Forming a first heat dissipating surface substantially parallel to each heat dissipating surface of the material and a second heat dissipating surface adjacent to the first heat dissipating surface, the heat dissipating surface of the heat dissipating member, and the first heat dissipating surface of the relay member And are adjusted to be flush with each other.
[0009]
In the semiconductor device of the present invention, two semiconductor switching elements are stacked vertically via a relay member, and heat dissipating members are further arranged on the upper and lower sides. The pair of heat radiating members are, for example, plate-like metal members, and can also be used as current paths. The relay member inserted between the switching elements forms a middle point electrode. Since the semiconductor switching elements are vertically stacked, the inductor component of the relay member can be reduced. This relay member was buried in the mold resin portion and had no cooling function in the conventional vertically stacked structure (see Patent Document 2). However, in the semiconductor device of the present invention, a heat dissipation portion that is thicker in the vertical direction than the element mounting portion to which the semiconductor switching element is bonded is provided adjacent to the element mounting portion. Therefore, if at least a part of the heat radiation part is exposed from the mold resin part, a heat radiation path of semiconductor switching element → element mounting part → heat radiation part → outside air (or cooler) can be secured, and the relay member itself has a cooling function. Can be expected enough.
[0010]
In a preferred embodiment, each of the heat radiating members has a heat radiating surface substantially parallel to each other, and the heat radiating portion of the relay member is formed on a first heat radiating surface substantially parallel to each heat radiating surface of the heat radiating member, and on the first heat radiating surface. An adjacent second heat radiating surface is formed. Thus, if the heat dissipation surface of the relay member is parallel to the heat dissipation surface of the heat dissipation member disposed above or below each semiconductor switching element, it is possible to cool those heat dissipation surfaces from the same direction. . That is, it is advantageous when a cooler is arranged.
[0011]
Specifically, in the preferred embodiment, the heat radiating portion is formed integrally with the element mounting portion, and forms the first heat radiating surface at a position where it does not overlap any of the heat radiating members in the vertical direction. . By integrating the element mounting portion and the heat radiating portion, the thermal resistance can be made as small as possible. In addition, since the first heat dissipation surface formed by the heat dissipation portion does not overlap the heat dissipation member dedicated to each semiconductor switching element in the vertical direction, the mold resin portion should be formed so that the first heat dissipation surface is exposed. Can also be done relatively easily.
[0012]
More preferably, the heat radiating surface of the heat radiating member and the first heat radiating surface of the relay member are configured to be flush with each other. According to this, it becomes easier to cool both the heat radiation surfaces from the same direction.
[0013]
Further, in manufacturing the semiconductor device of the present invention, the joining between the semiconductor switching element and the relay member and the joining between the semiconductor switching element and the heat radiating member are performed by fixing each component with a jig. When the heat radiating surface of the heat radiating member and the first heat radiating surface of the relay member are flush with each other, the assembly of the heat radiating member and the relay member and fixing of the jig can be performed easily and with high accuracy based on the first heat radiating surface. It can be done. As a result, for example, it is possible to expect an improvement in the assembling accuracy of the parts constituting the semiconductor device after solder reflow or after resin molding. Further, when the heat radiating members are paralleled with high accuracy, the adhesion between the heat radiating members and the cooler is increased, and the cooling efficiency is also increased.
[0014]
Also, the semiconductor device of the present invention is provided with a control signal lead terminal having one end embedded in the mold resin portion and conducting to the control electrode of the semiconductor switching element, and the other end drawn out of the mold resin portion. The element mounting portion of the relay member can be adjacent to the heat radiating portion on both sides in a direction substantially orthogonal to the direction in which the control signal lead terminal is pulled out. If it does in this way, the area of a heat sink can be simply doubled compared with the case where a heat sink is provided only on one side. In addition, it is not overlooked that cooling from all sides is possible.
[0015]
Moreover, the relay member is good to be comprised so that it may exhibit H shape in the cross section regarding an up-down direction. That is, since a pair of semiconductor switching elements can be accommodated in two recesses based on the alphabet “H”, the H shape can be said to be a very convenient shape.
[0016]
Further, the relay member may be configured such that the first heat radiating surface and the second heat radiating surface of the heat radiating portion intersect substantially perpendicularly. And the accommodation recess of a semiconductor switching element is formed by the upper and lower surfaces of an element mounting part, and the inner surface of a thermal radiation part. According to such a configuration, the mold resin part is easily molded. In addition, the inclination about the extraction angle required between the molding dies is included substantially vertically.
[0017]
A semiconductor device according to a second aspect of the present invention includes a pair of plate-like semiconductor switching elements arranged in parallel at a predetermined interval in the thickness direction, and a relay member forming a midpoint electrode of the semiconductor switching elements Each of the semiconductor switching elements includes a heat dissipating member disposed on the opposite side of the relay member, and a mold resin portion filling between the heat dissipating member and the relay member. When the thickness direction is the vertical direction, the relay member is provided adjacent to the element mounting portion, directly or indirectly joined to each of the semiconductor switching elements disposed above and below, A heat dissipating part formed thicker than the element mounting part in the vertical direction, and the element mounting part of the relay member is thicker than the heat dissipating member in the vertical direction. And characterized in that. According to this configuration, heat generated in the semiconductor switching element can be quickly transmitted to the heat radiating unit.
[0018]
One semiconductor switching element is positioned directly above or below the other semiconductor switching element in the vertical direction. According to this arrangement, the distance between the semiconductor switching elements can be minimized, that is, the inductor component of the relay member can be made as small as possible.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 and FIG. 2 are perspective views of a 2-in-1 double-sided heat radiation semiconductor package 100 (sometimes four-sided cooling) according to the present invention. FIG. 3 is a schematic cross-sectional view including the AA ′ line shown in FIG. However, in FIG. 1, the form which removed the mold resin part 15 is shown.
[0020]
Such a semiconductor package 100 constitutes a part of a three-phase inverter circuit for a brushless motor, for example. Examples of the types of semiconductor switching elements 1 and 2 (hereinafter also simply referred to as semiconductor chips) include IGBTs and power MOSFETs. In the present embodiment, a power MOSFET is illustrated.
[0021]
As shown in FIG. 1 and FIG. 2, a semiconductor package 100 includes a pair of semiconductor chips 1 and 2 arranged in parallel in the thickness direction, an H-shaped relay member 4 forming a middle point electrode, and a semiconductor chip. For each of 1 and 2, the heat dissipating members 3 and 5 disposed on the opposite side of the relay member 4 from the element mounting portion 41 are assembled and integrated with each other. The relay member 4 includes an element mounting portion 41 to which the semiconductor chips 1 and 2 are joined directly or via the conductor block 6, and heat radiating portions 42 and 42 adjacent to the element mounting portion 41. The relay member 4 can release the heat acquired by the element mounting unit 41 from the semiconductor chips 1 and 2 to the outside of the semiconductor package 100 from the heat dissipation units 42 and 42. This will be described in detail below.
[0022]
The thin-plate semiconductor chips 1 and 2 have equivalent circuit configurations, with the gate and source (emitter in the case of IGBT) exposed on one main surface side, and the drain (in the case of IGBT) on the other main surface side. The collector is exposed. The upper phase semiconductor chip 1 forming the upper phase of the inverter circuit and the heat dissipation member 3 are directly bonded by a bonding material 13 such as solder or silver solder, and the drain of the upper phase semiconductor chip 1 and the heat dissipation member 3 are electrically connected. The potential is the same. Further, the upper phase semiconductor chip 1 and the element mounting portion 41 of the relay member 4 are joined by the joining materials 13 and 13 via the conductor block 6, and the source of the upper phase semiconductor chip 1 and the relay member 4 are connected. Conductive and have the same potential.
[0023]
The lower phase semiconductor chip 2 forming the lower phase of the inverter circuit and the heat radiating member 5 are joined by the joining materials 13 and 13 via the conductor block 7, and the source of the lower phase semiconductor chip 2 and the heat radiating member 5 are electrically connected. The potential is the same. Further, the lower phase semiconductor chip 2 and the element mounting portion 41 of the relay member 4 are directly bonded by the bonding material 13, and the drain of the lower phase semiconductor chip 2 and the relay member 4 are electrically connected to have the same potential. ing.
[0024]
Further, in the semiconductor package 100, one end of the control signal lead terminal group 11 is embedded in the mold resin portion 15 to be electrically connected to electrodes such as gates of the semiconductor chips 1 and 2, and the other end is drawn to the outside of the mold resin portion 15. , 12 (or terminals). Individual control signal lead terminals are connected to the semiconductor chips 1 and 2 by bonding wires 14. The control signal lead terminal groups 11 and 12 include, for example, a gate control lead terminal, a temperature detection lead terminal (including the anode side and the cathode side), a current detection lead terminal, a potential detection lead terminal, and the like.
[0025]
The heat dissipating members 3 and 5 dedicated to the semiconductor chips 1 and 2 each have a flat shape or a plate shape. The heat radiating members 3 and 5 are exposed to the outside of the mold resin portion 15 and have heat radiating surfaces 3p and 5p substantially parallel to each other. Each of the heat radiating members 3 and 5 is made of, for example, one metal material selected from the group of Cu, W, Mo, and Al, or an alloy mainly composed of these metal materials from the viewpoint of thermal conductivity and electrical conductivity. Preferably, it is configured. The relay member 4 and the conductor blocks 6 and 7 may be made of the same material as that of the heat radiating members 3 and 5.
[0026]
In addition, due to the occurrence of resin burrs, the heat radiation surfaces 3p and 5p of the heat radiation members 3 and 5 may be buried in the mold resin portion 15 in appearance. In that case, the heat radiation surfaces 3p and 5p may be exposed from the mold resin portion 15 by processing such as grinding. The same applies to the first heat radiation surface 4p and the second heat radiation surface 4q of the relay member 4 described below.
[0027]
A P-side electrode lead terminal 8 connected to the power supply positive electrode is integrally attached to the heat dissipation member 3 on the upper phase semiconductor chip 1 side. An N-side electrode lead terminal 10 connected to the power source negative electrode is integrally attached to the heat dissipation member 5 on the lower phase semiconductor chip 2 side. A midpoint electrode lead terminal 9 is integrally attached to the relay member 4. The P-side electrode lead terminal 8, the N-side electrode lead terminal 10, and the midpoint electrode lead terminal 9 extend outside the mold resin portion 15.
[0028]
In the present embodiment, the lead terminals 8, 9, 10 for current paths and the control signal lead terminal groups 11, 12 are drawn out in the same direction for convenience during manufacture ( Details will be described later). However, it is not impossible to draw out the current path lead terminals 8, 9, 10 and the control signal lead terminal groups 11, 12 in a direction opposite to 180 ° or in a direction intersecting at an angle of 90 °.
[0029]
The mold resin portion 15 covers the peripheral side surfaces of the semiconductor chips 1 and 2 and fills a space formed by the relay member 4 and the heat dissipation members 3 and 5. The mold resin portion 15 is made of, for example, an epoxy resin, and is formed by a resin molding method such as an insert molding method after joining the components constituting the semiconductor package 100 with the bonding material 13.
[0030]
The relay member 4 that forms the midpoint electrode (specifically, the midpoint electrode of the inverter circuit) between the upper phase semiconductor chip 1 and the lower phase semiconductor chip 2 includes an element mounting portion 41 and heat radiating portions 42 and 42. ing. The heat received by the element mounting portion 41 is transmitted to the heat radiating portions 42 and 42 and released to the outside of the semiconductor package 100. As a result, the source exposed surface of the upper phase semiconductor chip 1 and the drain exposed surface of the lower phase semiconductor chip 2 can be cooled.
[0031]
The midpoint electrode lead terminal 9 is integrally attached to the element mounting portion 41. The midpoint electrode lead terminal 9 is connected to a load such as a motor. The heat dissipating parts 42 are located on both sides of the element mounting part 41. The element mounting portion 41 and the heat radiation portions 42 and 42 are integrally formed by a metal forming method such as casting. Therefore, the heat transferability between them is good.
[0032]
The thickness direction of the semiconductor chips 1 and 2 is defined as the vertical direction. The heat radiating portions 42 and 42 constitute a portion of the relay member 4 that is formed thicker than the element mounting portion 41 in the vertical direction. The element mounting portion 41 includes the control signal lead terminal groups 11 and 12 of the semiconductor chips 1 and 2, the P-side electrode lead terminal 8, the midpoint electrode lead terminal 9, and the N-side electrode lead terminal 10 outside the mold resin portion 15. The heat dissipating parts 42 and 42 are located on both sides in the direction orthogonal to the direction of drawing out. This is a structure in which the lead-out is not obstructed by the formation of the heat radiation portions 42 and 42.
[0033]
As shown in FIG. 2, the heat radiating portions 42 and 42 form heat radiating surfaces 4 p and 4 q exposed to the outside of the mold resin portion 15. The heat radiating surface formed by the heat radiating portions 42, 42 includes a first heat radiating surface 4p substantially parallel to the heat radiating surfaces 3p, 5p of the heat radiating members 3, 5 and a second heat radiating surface 4q adjacent to the first heat radiating surface 4p. Including. In the semiconductor package 100 of the present embodiment, the first heat radiating surface 4p and the second heat radiating surface 4q are substantially orthogonal to each other. A minute draft angle with respect to the mold for molding the resin part 15 may be given to the second heat radiating surface 4p (one reason for making it substantially orthogonal).
[0034]
In the semiconductor package 100 shown in FIGS. 1 to 3, a plurality of (four surfaces in the semiconductor package 100) first heat radiation members formed by the heat radiation members 3 and 5 and the heat radiation portions 42 and 42 dedicated to the semiconductor chips 1 and 2, respectively. The surface 4p is in a positional relationship that does not overlap with each other in the vertical direction. Specifically, as is apparent from FIG. 3, the first heat radiating surface formed on each of the heat radiating surfaces 3 p and 5 p of the heat radiating members 3 and 5 and the pair of heat radiating portions 42 and 42 of the relay member 4. 4p and 4p are flush with each other. This makes it easy to use the cooler that cools the heat radiation surfaces 3p and 5p of the heat radiation members 3 and 5 and the cooler that cools the first heat radiation surfaces 4p and 4p of the relay member 4. Further, the assembly of the heat dissipating members 3 and 5 and the relay member 4 and the jig fixing, which should be performed prior to the solder reflow, can be performed based on the first heat dissipating surfaces 4p and 4p of the relay member 4. Therefore, the assembly accuracy of the three members of the heat radiating member 3, the heat radiating member 5, and the relay member 4 after solder reflow can be increased. When the parallel accuracy of the heat radiating surfaces 3p and 5p of the heat radiating members 3 and 5 is high, the adhesion to a cooler (not shown) is also good, and high cooling efficiency can be expected.
[0035]
As shown in FIG. 3, the relay member 4 constituting the semiconductor package 100 has an H shape in a cross section in the vertical direction including the heat radiation portions 42 and 42. Specifically, the first heat radiating surface 4p and the second heat radiating surface 4q of the heat radiating portions 42 and 42 intersect substantially perpendicularly, and further, the upper and lower surfaces 41r and 41r of the element mounting portion 41 and the heat radiating portions 42 and 42 A housing recess for the semiconductor chips 1 and 2 is formed by the inner side surfaces 42r and 42r. The depth of the recess is adjusted to be equal to the total thickness of the semiconductor chip 1, the heat radiating member 3, the conductor block 6, and the three-layer joint portion 13.
[0036]
Further, as shown in FIG. 3, the thickness of the element mounting portion 41 is constant, and the thickness d1 is adjusted to be larger than the thickness d2 of the heat dissipating members 3 and 5. As a result, the heat applied from the semiconductor chips 1 and 2 to the element mounting portion 41 is efficiently transmitted to the heat radiating portions 42 and 42.
[0037]
The relay member 4b of the semiconductor package 102 shown in the schematic cross-sectional view of FIG. 5 is also included in the H-shaped concept. That is, even when the thickness of the element mounting portion 43 in the vertical direction is constant and the thickness in the vertical direction of the heat radiating portions 44 and 44 having the first heat radiating surface 4p and the second heat radiating surface 4q is continuously changed. Good. In some cases (in the form of FIG. 5), the mold resin into the housing recess formed by the upper and lower surfaces 43r, 43r of the element mounting portion 43 and the inner side surfaces 44r, 44r of the heat radiating portions 44, 44 is used. It can be expected to improve the flowability.
[0038]
Also, the semiconductor package 101 shown in the schematic cross-sectional view of FIG. 4 can be shown as one of the preferred embodiments. The semiconductor package 101 includes a relay member 4a having a T-shaped cross section. Among the relay members 4 shown in FIGS. 1 to 3, a form in which one heat radiating portion 42 is omitted is a relay member 4 a shown in FIG. 4. According to the relay member 4a having a T-shaped cross section, the cooling efficiency is slightly lowered as compared with the relay member 4 having an H-shaped cross section, but the following advantages are obtained. That is, in the relay member 4a, the heat radiating portion 42 is provided at one end of the element mounting portion 41, and the control signal lead terminals 11, 12, P side from the side opposite to the side where the heat radiating portion 42 is provided. The electrode lead terminal 8 (not shown), the midpoint electrode lead terminal 9 (not shown), and the N-side electrode lead terminal 10 can be pulled out of the mold resin portion 15. Of course, the semiconductor package 102 itself is also compact.
[0039]
In any of the semiconductor packages 100, 101, and 102 shown in FIGS. 1 to 5, an arrangement is employed in which the upper phase semiconductor chip 1 is located directly below (or directly above) the lower phase semiconductor chip 2. That is, both semiconductor chips 1 and 2 are translationally symmetric in the vertical direction. This arrangement is advantageous from the viewpoint of minimizing the inductor component of the relay members 4, 4a, 4b as much as possible.
[0040]
The assembly of the semiconductor package 100 can be performed by the following procedure. As shown in FIG. 6, first, the upper phase semiconductor chip 1 is placed on the heat radiating member 3. A solder bonding material 13 is formed on the heat dissipation member 3 by a method such as screen printing. An electrode such as a gate of the upper phase semiconductor chip 1 and the upper phase control signal lead terminal group 11 are connected by a bonding wire 14. The conductor block 6 is placed on the upper phase semiconductor chip 1 via the solder bonding material 13. Thereafter, solder reflow is performed.
[0041]
In addition, it is good to employ | adopt the well-known method using a lead frame for said assembly process. That is, a lead frame is used in which the P-side electrode lead terminal 8 formed integrally with the heat radiating member 3 is connected to the upper phase control signal lead terminal group 11 by a connecting portion that can be cut after the molding resin portion 15 is formed. be able to. In other words, drawing out the P-side electrode lead terminal 8 and the upper-phase control signal lead terminal group 11 in the same direction is also a requirement in a manufacturing method using a lead frame.
[0042]
The lower phase semiconductor chip 2 and the relay member 4 are joined in the same procedure. Then, as shown in FIG. 7, the upper-phase semiconductor chip 1 and the lower-phase semiconductor chip 2 are positioned and fixed with a jig, and the conductor block 6 and the relay member 4, and the conductor block 7 and the heat dissipation member 5 are soldered together. To do. Thereafter, the mold resin portion 15 is formed by an insert molding method or the like, and the lead terminals are separated from each other, whereby the semiconductor package 100 shown in FIG. 2 is obtained.
[Brief description of the drawings]
FIG. 1 is a perspective view of a semiconductor package of the present invention (without a mold resin portion).
FIG. 2 is a perspective view of the semiconductor package of the present invention (with a mold resin portion).
FIG. 3 is a schematic cross-sectional view of a semiconductor package of the present invention.
FIG. 4 is a schematic cross-sectional view showing another preferred embodiment of a semiconductor package.
FIG. 5 is a schematic cross-sectional view showing another preferred embodiment of a semiconductor package.
6 is an exploded perspective view showing an assembling procedure of the semiconductor package of FIG. 1;
7 is an exploded perspective view of the semiconductor package following FIG. 6. FIG.
[Explanation of symbols]
1 Semiconductor switching element (upper phase)
2 Semiconductor switching element (lower phase)
3, 5 Heat radiation member 3p, 5p Heat radiation surface 4, 4a, 4b of heat radiation member Relay member 4p First heat radiation surface 4q Second heat radiation surface 6, 7 Conductor block (spacer)
DESCRIPTION OF SYMBOLS 11 Upper phase control signal lead terminal group 12 Lower phase control signal lead terminal group 15 Mold resin part 41, 43 Element mounting part 42, 44 Heat radiation part 100, 101, 102 Semiconductor package (semiconductor device)

Claims (8)

厚さ方向に所定の間隔を置いて平行配置された、１対の板状の半導体スイッチング素子と、それら半導体スイッチング素子の中点電極をなす中継部材と、前記半導体スイッチング素子の各々に対し、前記中継部材とは反対側に配置された放熱部材と、それら放熱部材と前記中継部材との間を充填するモールド樹脂部とを備え、
前記半導体スイッチング素子の厚さ方向を上下方向としたとき、
前記中継部材は、上下に配置された前記半導体スイッチング素子の各々に直接または間接接合された素子搭載部と、該素子搭載部に隣接して設けられ、前記上下方向に関して前記素子搭載部よりも厚肉に形成された放熱部と、を含み、
前記放熱部材の各々は、互いに略平行な放熱面を有し、前記中継部材の前記放熱部は、前記放熱部材の各放熱面と略平行な第一放熱面と、該第一放熱面に隣接する第二放熱面とを形成し、
前記放熱部材が有する放熱面と、前記中継部材の前記第一放熱面とが面一となるように調整されていることを特徴とする半導体装置。A pair of plate-like semiconductor switching elements arranged in parallel at a predetermined interval in the thickness direction, a relay member forming a middle point electrode of the semiconductor switching elements, and for each of the semiconductor switching elements, A heat dissipating member disposed on the opposite side of the relay member, and a mold resin portion filling between the heat dissipating member and the relay member,
When the thickness direction of the semiconductor switching element is the vertical direction,
The relay member is provided adjacent to the element mounting portion, which is directly or indirectly joined to each of the semiconductor switching elements disposed above and below, and is thicker than the element mounting portion in the vertical direction. and the heat radiating portion which is formed in the flesh, only including,
Each of the heat radiating members has a heat radiating surface substantially parallel to each other, and the heat radiating portion of the relay member is adjacent to the first heat radiating surface substantially parallel to each heat radiating surface of the heat radiating member, and the first heat radiating surface. Forming a second heat dissipation surface ,
A semiconductor device , wherein the heat dissipation surface of the heat dissipation member and the first heat dissipation surface of the relay member are adjusted to be flush with each other . 前記放熱部は、前記素子搭載部と一体に成形されたものであるとともに、前記上下方向において前記放熱部材のいずれとも重ならない位置で前記第一放熱面を形成している請求項１記載の半導体装置。The heat radiation member, together with the one in which elements are formed on the mounting portion integral with the radiator either said first heat radiation surface is formed by that claim 1, wherein at a position that does not overlap even of members in the vertical direction semiconductor apparatus. 一端が前記モールド樹脂部に埋設されて前記半導体スイッチング素子の制御電極に導通し、他端が前記モールド樹脂部の外側に引き出される制御信号リード端子を備え、
前記中継部材の前記素子搭載部には、前記制御信号リード端子の引き出し方向と略直交する方向の両側に前記放熱部が隣接している請求項１又は２に記載の半導体装置。One end is embedded in the mold resin portion and is connected to the control electrode of the semiconductor switching element, and the other end is provided with a control signal lead terminal that is drawn out of the mold resin portion,
3. The semiconductor device according to claim 1, wherein the heat dissipating part is adjacent to the element mounting part of the relay member on both sides in a direction substantially orthogonal to a direction in which the control signal lead terminal is pulled out. 前記中継部材は、前記上下方向に関する断面でＨ形状を呈するように構成されている請求項１又は２に記載の半導体装置。The relay member, the semiconductor device according to claim 1 or 2 is configured to exhibit a H-shaped in cross-section about the vertical direction. 前記中継部材は、前記放熱部の前記第一放熱面と前記第二放熱面とが略垂直に交差するように構成され、前記素子搭載部の上下面と、前記放熱部の内側面とにより前記半導体スイッチング素子の収容凹所が形成されている請求項４記載の半導体装置。The relay member is configured so that the first heat radiating surface and the second heat radiating surface of the heat radiating portion intersect substantially perpendicularly, and the upper and lower surfaces of the element mounting portion and the inner side surface of the heat radiating portion The semiconductor device according to claim 4 , wherein an accommodation recess for the semiconductor switching element is formed. 前記上下方向に関し、前記中継部材の前記素子搭載部は、前記放熱部材よりも厚肉である請求項１ないし５のいずれか１項に記載の半導体装置。Relates to the aforementioned vertical direction, the element mounting portion of the relay member, the semiconductor device according to any one of 5 claims 1 is thicker than the heat radiation member. 厚さ方向に所定の間隔を置いて平行配置された、１対の板状の半導体スイッチング素子と、それら半導体スイッチング素子の中点電極をなす中継部材と、前記半導体スイッチング素子の各々に対し、前記中継部材とは反対側に配置された放熱部材と、それら放熱部材と前記中継部材との間を充填するモールド樹脂部とを備え、
前記半導体スイッチング素子の厚さ方向を上下方向としたとき、
前記中継部材は、上下に配置された前記半導体スイッチング素子の各々に直接または間接接合された素子搭載部と、該素子搭載部に隣接して設けられ、前記上下方向に関して前記素子搭載部よりも厚肉に形成された放熱部と、を含み、
前記上下方向に関し、前記中継部材の前記素子搭載部は、前記放熱部材よりも厚肉であることを特徴とする半導体装置。 A pair of plate-like semiconductor switching elements arranged in parallel at a predetermined interval in the thickness direction, a relay member forming a middle point electrode of the semiconductor switching elements, and for each of the semiconductor switching elements, A heat dissipating member disposed on the opposite side of the relay member, and a mold resin portion filling between the heat dissipating member and the relay member,
When the thickness direction of the semiconductor switching element is the vertical direction,
The relay member is provided adjacent to the element mounting portion, which is directly or indirectly joined to each of the semiconductor switching elements disposed above and below, and is thicker than the element mounting portion in the vertical direction. Including a heat dissipating part formed on the meat,
In the vertical direction, the element mounting portion of the relay member is thicker than the heat dissipation member . 一方の前記半導体スイッチング素子が、前記上下方向に関し、他方の前記半導体スイッチング素子の真上または真下に位置している請求項１ないし７のいずれか１項に記載の半導体装置。One of the semiconductor switching elements, relates the vertical direction, the other semiconductor device according to any one directly above or claims 1 located beneath 7 of the semiconductor switching element.
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