JP4090431B2 - Scan vector support in event-based test systems - Google Patents

Description

[0001]
Field of the Invention
The present invention relates to an event type test system for testing a semiconductor device. In particular, the present invention relates to an event type test system that can generate a scan vector for testing a semiconductor device by a scan design without using a large-capacity scan memory.
[0002]
BACKGROUND OF THE INVENTION
When testing a semiconductor device (large scale integrated circuit) such as an IC or LSI with a semiconductor test system such as an IC tester, the semiconductor device under test is connected to the corresponding pin at a predetermined test timing. The test signal generated by the IC tester, that is, the test pattern is supplied. The IC tester receives an output signal in response to the test signal from the device under test. The output signal is strobed, ie, sampled with a strobe signal at a predetermined timing, and compared with expected value data to verify whether the device under test is functioning normally.
Scan design is one approach established as an integrated circuit design (design for testing within an integrated circuit) to improve test efficiency. The present invention relates to an event type test system for testing an IC device in which such a scan design is used or not used. Before testing the IC device under test using the scan design, the test signal and circuit configuration in the semiconductor test system will be described before explaining in detail the problems in the conventional semiconductor test system when the scan vector is generated. Briefly described.
[0003]
In a conventional semiconductor test system, the timing of a test signal, a strobe signal, etc. is defined based on a tester rate or a tester cycle of the semiconductor test system. Such a test system is also called a cycle type (cycled) test system. There is another type of test system called an event type test system. In this test system, a test signal and a strobe signal are directly generated for each pin (per pin) based on event data from an event memory. . The present invention relates to such an event type semiconductor test system.
The event type test system uses the concept of events. This event represents each change point of a logic state such as a test signal used for testing a semiconductor device under test. For example, such a logic state change point corresponds to a rising edge or falling edge of a test signal, a timing edge of a strobe signal, or the like. The timing of each event is defined as the time length from the reference time point. In general, such a reference time is the timing of the immediately preceding event. Alternatively, this reference time point may be a fixed start time common to all events.
[0004]
In an event type test system, that is, an event tester, the timing data stored in the timing memory (event memory) is a complex type information such as individual waveforms, vectors, and delay times for all test cycles, as in the cycle type test system. Since it is not necessary to include it, the description of timing data can be greatly simplified. However, a large memory capacity is required to store the timing data in the event memory.
In the event type test system, the timing (event) data for each event stored in the event memory is generally expressed by a time difference (delay time) between the current event and the immediately preceding event. In order to achieve high timing accuracy, the time difference (delay time value) between events is the integer multiple of the reference clock cycle (also called “integer part” or “event count”) and the fractional data of the reference clock cycle (“fractional”). Part "or" event vernier "). The timing relationship between the event count and the event vernier is shown in the timing charts of FIGS. 3A-3E. In this example, the reference clock (also referred to as master clock or system clock) in FIG. 3A has a clock cycle (also referred to as a period) T. Event 0, event 1, and event 2 have a timing relationship as shown in FIG. 3C.
[0005]
Since event 1 is described based on event 0, the time difference between both events (delay time) ΔV ₁ As defined in the event memory. The timing of event 2 is the time difference from event 1 (delay time) ΔV ₂ Is defined as Similarly, the timing of event 3 in FIG. 3E is the time difference (delay time) ΔV from event 2. ₃ And store it in the event memory. In an event type test system, the timing data in the event memory is read and the timing data of all previous events is added to determine the final timing of the current event.
Therefore, in the example of FIG. 3C, the timing relationship of FIG. 3B is used to generate the event 1. Here, in the timing relationship of FIG. ₁ T is an event count value, and N of the reference clock period T ₁ △ ₁ T is an event vernier value and represents a fractional value of the reference clock period T. Similarly, to generate event 3 in FIG. 3E relative to event 0, all timing data of previous events is ₃ T + △ ₃ Add to produce an overall time difference represented by T. Where N ₃ T is an event count value, and N of the reference clock period T ₃ △ ₃ T is an event vernier value and represents a fractional value of the reference clock period T.
[0006]
In actual device testing, at one pin of the device under test, the applied test signal does not change over a long period of time, such as a few hundred milliseconds, while at the other most pins The test signal varies at a higher rate, such as tens of nanoseconds or hundreds of nanoseconds. That is, the time difference between two adjacent events is greatly different, and a large number of data bits is required to express the maximum possible time difference. The semiconductor test system is a large-scale system having, for example, several hundred test channels (pins), and each test channel needs to have an event memory. Therefore, in order to reduce the overall cost of the test system, it is desirable to minimize the capacity of each event memory.
Such reduction in memory capacity is particularly important for storing test vectors for testing IC devices using scan design. Scan design is an excellent design method established for easy testing of IC devices (design for test) in IC design. In the full scan method, a scan flip-flop is used in the circuit instead of a normal D flip-flop or J · K flip-flop. The scan flip-flop has a multiplexer so that it can be connected as a shift register mode during testing.
[0007]
FIG. 6 shows a basic scan configuration in an IC device using a scan design. In this example, in order to test a combinational logic (combination logic) of a semiconductor device under test, a pair of a scan flip-flop 132 and a switch SW (multiplexer) 142, and a pair of a scan flip-flop 134 and a switch SW (multiplexer) 144 are used. Show. The basic configuration of this scan design is well known in the art and is described in more detail in “Digital Hardware Testing”, Rochith Rajsumman, Artech House, 1992, pp 197-238. The general test process for scan design is as follows.
(1) Connect the flip-flop to the shift register (using the test mode) and shift in (scan in) the test vector in series.
(2) Switch to the normal operation mode, apply the value of the flip-flop (test vector) to the circuit, and capture the response to the flip-flop.
(3) Return to test mode and shift out (scan out) serially to evaluate response.
[0008]
In general, the scan vector is enormous, from 16 million (million) to 128 million. In the event type test system described above, a test vector is stored based on a change in logic value (event) and an event occurrence time. This time information is defined with reference to a reference time such as a time when the power is turned on or a clock start time, or a previous event as shown in FIGS. However, in order to store a large number of scan vectors (for example, 128 million) in this form, a very large physical memory is required.
[0009]
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a scan vector generation method and apparatus for use in an event type test system, which can test an IC device having a scan configuration using a small-capacity event memory. It is in.
In the present invention, the event type test system can generate a scan vector for testing a semiconductor device using a scan design without requiring a large-capacity scan memory. This event type test system has an event memory for storing timing data and event type data of each event, and the timing data defines one test vector. N (N is an integer) Represented by data bits. The event type test system also includes an event generator for generating an event using timing data and event type data stored in the event memory, and a mode change circuit provided between the event memory and the event generator. . The mode change circuit changes the signal path between a normal mode for generating a test vector and a scan mode for generating a scan vector. When the event type data in the event memory indicates a predetermined word, it is detected that the scan mode is set. The test system of the present invention has the event memory. N Each of the data bits defines each scan vector, and N data bits are fed serially to the event generator, for each access of the event memory, 2 ^N Generate scan vectors.
[0010]
According to the present invention, an event type test system includes an event memory. N A bit of data can be used in parallel to generate a scan vector, N 2 bits of data ^N By converting to serial data of bits, 2 using the memory area corresponding to 1 test vector ^N A scan vector can be generated.
In the event type test system of the present invention, the timing data in the event memory includes delay count data composed of integer multiples (integer part data) data of the reference clock period and fractional data (fraction part data) data of the reference clock period. And configured delay vernier data. Further, timing data for generating the scan vector is stored in a register provided separately from the event memory, and is supplied to the event generator in the scan mode.
The mode change circuit N 2 bits for each access to the event memory ^N A parallel to serial converter for converting to bit serial data and 2 from the parallel to serial converter ^N In order to select the serial data of bits and generate a scan vector, it consists of a multiplexer for supplying it to the event generator during the scan mode.
[0011]
[Detailed Description of the Invention]
In order to facilitate understanding of the present invention, a basic configuration of an event type test system and a method for storing data in an event memory provided in the test system for generating a test vector will be briefly described below. To do. In the description of the present invention, a “test vector” means a test pattern (for example, a drive event or a strobe event) for testing a general IC device, and a “scan vector” is designed using a scan design. It means a test pattern for testing an IC device.
FIG. 1 is a schematic block diagram showing a basic configuration of an event type test system. The event type test system includes a host computer 12 connected to a system bus 14 and a bus interface 13, an internal bus 15, an address control logic 18, a fail memory 17, an event memory 20, an event decoder 23, an event timing unit 21, an event occurrence The device 24 and the pin electronics 26 are included. The event type test system evaluates a semiconductor device under test (DUT) 28 connected to the pin electronics 26.
[0012]
An example of the host computer 12 is a workstation equipped with a UNIX (registered trademark) operating system. The host computer 12 functions as a user interface for starting and stopping a test operation, loading a test program and other test conditions (conditions), and analyzing a test result by the host computer. The host computer 12 interfaces with a hardware test system via a system bus 14 and a bus interface 13. Although not shown in the figure, the host computer 12 is preferably connected to a communication network (communication circuit) in order to send and receive test information from other test systems and computer networks.
The internal bus 15 is a bus in the hardware test system and is connected to most functional blocks such as an address control logic 18, a fail memory 17, an event timing unit 21, an event decoder 23, and an event generator 24. is doing. An example of the address control logic 18 is a tester processor dedicated to a hardware test system and is generally not accessible to the user. The address control logic 18 supplies instructions to other functional blocks in the test system based on the test program and test conditions from the host computer 12. The fail memory 17 stores a test result such as fail information of the DUT 28 at an address designated by the address control logic 18, for example. Information stored in the fail memory 17 is used in fail analysis of the device under test.
[0013]
The address control logic 18 supplies address data to the event memory 20 as shown in FIG. In an actual test system, a plurality of event memories are used, and each memory has a configuration corresponding to a test pin of the test system. The event memory stores timing data for representing each event forming the test signal or strobe signal. As shown in FIG. 5, the event memory 20 stores timing data that is an integer multiple of the reference clock (delay count) and timing data that is a fraction of the reference clock (delay vernier). The event memory 20 stores event type data (drive, strobe, etc.) supplied to the event decoder 24.
The event timing unit 21 uses the timing data from the event memory 20 to generate data indicating the overall timing of each corresponding event. Basically, such comprehensive timing data is formed by adding delay count data and delay vernier data. In the process of adding such timing data, a carry-over operation of fraction data (offset to delay count data) is performed in the event timing unit 21. Further, in the process of generating the overall timing, a scaling function may be provided to change the overall timing, and the timing data may be multiplied by a predetermined scaling factor.
[0014]
The event decoder 23 decodes (decodes) event type data indicating the event type, and supplies the event type information to the event generator 24. The event generator 24 actually generates an event based on the comprehensive timing data from the event timing unit 21 and the event type from the event decoder 23. The event (test signal or strobe signal) generated in this way is supplied to the DUT 28 via the pin electronics 26. Basically, the pin electronics 26 has a circuit configuration including a large number of drivers, comparators, switches, and the like, and by these circuit configurations, a switching operation that forms a relationship between input and output to the DUT 28 is performed. Do.
FIG. 2 is a block diagram showing a more detailed configuration of the pin electronics 26 having the driver 35 and the analog comparator 36. The event generator 24 generates a drive event and supplies it as a test signal to the input pin of the DUT 28 via the driver 35. Further, the event generator 24 generates a sampling event and supplies it to the analog comparator 36 as a strobe signal for sampling the output signal of the DUT 28. The output signal of the analog comparator 36 is compared with the expected value data from the event generator 24 by the pattern comparator 38. If there is a mismatch between the two, a fail signal is transmitted to the fail memory 17 of FIG.
[0015]
3C, D, and E show waveform examples of a drive event (test pattern), an output signal from the DUT, and a sampling event (strobe signal), respectively. When the drive event of FIG. 3C is given to the DUT 28 via the driver 35, in response, the DUT 28 generates the output signal shown in FIG. 3D. This output signal is strobed at a timing determined by the sampling event shown in FIG. 3E. As shown in FIG. 3C, the drive event defines the timing of the rising edge and the falling edge of the test pattern. On the other hand, as shown in FIG. 3E, the sampling event defines the timing of the strobe point. That is, when such an event is a sampling event, a strobe signal is generated by only one event data. This is because the pulse width of the strobe signal is small, and it is practically impossible to generate the strobe signal by defining both the rising edge and the falling edge.
[0016]
FIG. 4 is a timing chart showing the time relationship between various events based on the time difference (delta time) between two adjacent events. As described above in connection with FIGS. 3A-E, the time length between events (delay time value) is an integer multiple of the reference clock period (integer part or delay count) and the fraction of the reference clock period (fractional part or It is specified in combination with delay vernier).
In the example of FIG. 4, events 0 to 7 are expressed with reference to a reference clock having a time interval T = 1. For example, event 0 delta time (delay) ΔV ₀ Is 0.75 (delay count “0”, delay vernier “0.75”), and event 1 delta time ΔV ₁ May be 1.50 (delay count “1”, delay vernier “0.50”). In such a configuration, the total delay for event 1 is 2.25, and the test system logic counts the two event clocks as “2.0” and the remaining fraction delay is the total fraction of the delay vernier. The part “0.25” is calculated.
[0017]
FIG. 5 is a table showing an example of storing timing data defining the continuous delay-related events shown in FIG. 4 in the event memory in the event type test system. Delay time △ V _n (△ V ₀ , △ V ₁ , △ V ₂ . . . ) Is represented by a combination of a delay count Cn (C1, C2, C3...) And a delay vernier Vn (V1, V2, V3...). The delay count is the number of reference clocks from the time reference point, ie, the coarse delay. The delay vernier is the number of minute precision units, that is, a minute delay, and is, for example, 1/128 unit of the reference clock period in order to express the actual exact time of the event. Therefore, for example, in a reference clock of 8 nanoseconds, a minute delay of 62.5 picoseconds as a minimum resolution can be realized by a delay vernier. In the table of FIG. 5, a field expressed as an event type stores event type data for generating different event types during the test.
In this example, each field is defined by the number of bits shown in FIG. That is, the delay count (coarse delay) has 8 bits, the delay vernier (fine delay) has 7 bits, and the event type has 3 bits. With this configuration, considerable flexibility in event formation can be obtained. In addition, this configuration can function for generating scan vectors without providing additional software support. However, in the background of the present invention, as explained above, scan vectors are generally many times longer than normal functional test test vectors, so additional memory is required to store them.
[0018]
As a first solution to this problem, it is conceivable to use a large-capacity event memory for a designated scan pin (a test pin connected to the scan input of the device under test). However, this solution is expensive and the flexibility of the event-type test system is lost because dedicated memory can only be used for a small number of designated test pins. For example, if the event data (test) pin has 16M events, 16M scan vectors will be supported. However, to support 128M scan vectors, the test pins need to upgrade the event memory from 16M to 128M events. Furthermore, since the test pin is dedicated to the scan test, it cannot be used for other tests.
[0019]
Therefore, the present invention provides a new method for constructing words in an event memory in order to generate scan vectors. FIG. 7A shows the word structure for such a scan vector in the event memory. In this configuration, a 3-bit field (event type in FIG. 5) is assigned to identify the event type. In this example, as shown in FIG. 7B, this assigned field is indicated as “111”, indicating that the event type is the event scan mode. In the present invention, when the least significant bit of the event word indicates a value of “111”, all other bits are supported by the scan vector regardless of the event type, delay count, and delay vernier. It is meant to be used as Other values in the 3-bit field of FIG. 7C are used to specify other event types.
In the example of FIGS. 7A and 7B, since the “scan event” at one event memory location is a 15-bit long field, a total of 2 ¹⁵ Can be identified. This is a great improvement compared to the configuration of FIG. 5 in which only one scan vector is stored in the event memory.
[0020]
The timing for generating a scan event is defined by timing data stored in another timing register (shown in FIG. 8). FIG. 8 is a block diagram showing a hardware configuration (mode change circuit) arranged between a pair of event decoder 23 and event timing unit 21 and event memory 20. The main reason for providing such additional hardware is to switch the signal path between the normal mode (test vector generation) and the event scan mode (scan vector generation). In the configuration of FIG. 8, by adding very small hardware and reconfiguring the event word as shown in FIGS. 7A and B, only one scan vector is available in the original format as shown in FIG. 2 can only occur ¹⁵ Can be stored in each event word.
[0021]
The additional hardware shown in FIG. 8 includes a parallel-serial converter 152, a scan timing register 154, an event scan decoder 156, and multiplexers 162 and 164. When the word representing the event type from the event memory 20 indicates a value representing the event scan mode, for example, “111” described above, the event scan decoder 156 changes the logic state of the selection signal applied to the multiplexers 162 and 164. Data from the event memory 20 is converted into serial data, that is, a scan vector by the parallel-serial converter 152. Therefore, in the event scan mode, the scan vector is transferred to the event generator 24 via the multiplexer 162 and the event decoder 23. The timing of the scan vector is controlled by timing data stored in the scan timing register 154, and the timing data is supplied to the event timing unit 21 via the multiplexer 164.
In the above examples in FIGS. 5 and 8, an 18-bit word is used to represent the event word, and a 3-bit field therein is used to specify the event type. However, such a bit number is used only for explaining the present invention, and any size event word and field can be used based on the idea of the present invention.
[0022]
As described above, the main effects of the present invention are as follows. 2 In an event type test system, the material size of the event memory is not increased. ^N This means that double scan vectors can be supported. In this case, N is the number of bits of the event word that defines the coarse delay and the minute delay. In addition, the present invention can support scanning in a format incorporated in the normal event program flow, and therefore does not require a dedicated scan pin. That is, any test pin may be a scan pin.
Although only preferred embodiments are specified, various forms and modifications of the present invention are possible based on the above disclosure without departing from the spirit and scope of the present invention within the scope of the appended claims.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a basic configuration of an event type test system according to the present invention, in which scan support is provided.
FIG. 2 is a block diagram showing a more detailed configuration of the pin electronics of FIG. 1 and a drive event (test signal) and a sampling event (strobe signal) from an event generator in relation thereto.
FIGS. 3A to 3E are timing charts showing the time relationship between various events in order to show the basic concept of the event timing relationship, and a reference clock, and a drive event and a sampling event based on the reference clock. have.
FIG. 4 is a timing chart showing a timing relationship between various events by each time difference (delta time) between two adjacent events.
5 is a diagram showing an example of data storage in an event memory provided in the event type test system, and shows data representing a delay time between a series of events shown in FIG. 4. FIG.
FIG. 6 is a block diagram showing a basic circuit configuration example of an IC device using a scan design concept.
FIGS. 7A to 7C are diagrams showing examples of data storage in an event memory provided in the event type test system of the present invention in order to store scan vectors. FIGS.
FIG. 8 is a block diagram showing a circuit configuration example for enabling switching between a normal test vector generation mode and a scan vector generation mode by the event type test system of the present invention.

Claims (10)

In an apparatus provided in a semiconductor test system for generating a test vector in a normal test of a semiconductor device and generating a scan vector in a scan test of a semiconductor device ,
It has an event memory that stores the timing data and event type data of each event, and the current event timing data in the event memory has N (N is an integer) data bits in parallel as a delay time from a predetermined reference point. In the event memory, the N data bits include a field describing timing data that is an integral multiple of the reference clock period and timing data corresponding to a fraction of the reference clock period. Consists of two fields of the field to describe,
Having an event generator which generates an event by using the timing data and the event type data from the event memory, each event is generated from the event generator as test vector or scan vectors,
The mode change circuit is provided between the event memory and the event generator and switches a signal path between a normal mode for generating a test vector and a scan mode for generating a scan vector. When the event type data of a represents a predetermined word, the signal path is switched ,
Each bit of the N data bits in the event memory forms each scan vector, and the mode conversion circuit converts the N data bits read in parallel from the event memory to serial and applies them to the event generator. To generate 2 ^N scan vectors for each access to the event memory,
An apparatus included in a semiconductor test system. Timing data of the two fields in the event memory includes a delay count data is an integer multiple (integer part data) data of the reference clock period, delay vernier data is fractional (fractional part data) data of the reference clock period The apparatus which has in the semiconductor test system of Claim 1 comprised by these.   2. The apparatus included in a semiconductor test system according to claim 1, wherein the timing data for generating the scan vector is stored in a register provided separately from the event memory and is supplied to the event generator in a scan mode. The mode change circuit,
A parallel-serial converter for converting the serial data of 2 ^N bits for each access parallelism of the N data bits from the event memory to the event memory,
A multiplexer that selects 2 ^N bits of serial data from the parallel to serial converter and supplies the serial data to the event generator when in scan mode to generate a scan vector ;
The apparatus included in the semiconductor test system according to claim 1, comprising: The mode change circuit,
A parallel-serial converter for converting the serial data of 2 ^N bits for each access parallelism of the N data bits from the event memory to the event memory,
A scan timing register for storing scan timing data to define the timing of the scan vector ;
A first multiplexer for selecting 2 ^N bits of serial data from the parallel to serial converter and supplying the serial data to the event generator when in scan mode to generate a scan vector ;
A second multiplexer for selecting scan timing data from the scan timing register and generating scan vectors in scan mode for supplying the scan timing data to an event generator ;
The apparatus included in the semiconductor test system according to claim 1, comprising: The test vector generated by the normal testing semiconductor devices, provided in the event based semiconductor test system to generate a scan vector in the scan test of the semiconductor device unit,
It has an event memory that stores the timing data and event type data of each event, and the current event timing data in the event memory has N (N is an integer) data bits in parallel as a delay time from a predetermined reference point. In the event memory, the N data bits include a field describing timing data that is an integral multiple of the reference clock period and timing data corresponding to a fraction of the reference clock period. Consists of two fields of the field to describe,
Having an event generator which generates an event by using the timing data and the event type data from the event memory, each event is generated from the event generator as test vector or scan vectors,
The mode change circuit is provided between the event memory and the event generator and switches a signal path between a normal mode for generating a test vector and a scan mode for generating a scan vector. When the event type data of a represents a predetermined word, the signal path is switched,
Supplying a test vector or a scan vector to a predetermined pin of the semiconductor device under test, and having pin electronics for receiving a response output of the semiconductor device under test for evaluation with respect to an expected value ,
Each bit of the N data bits in the event memory forms each scan vector, and the mode conversion circuit converts the N data bits read in parallel from the event memory to serial and applies them to the event generator. To generate 2 ^N scan vectors for each access to the event memory ,
An event-type semiconductor test system. Timing data of the two fields in the event memory includes a delay count data is an integer multiple (integer part data) data of the reference clock period, delay vernier data is fractional (fractional part data) data of the reference clock period The event type semiconductor test system according to claim 6, comprising:   7. The event type semiconductor test system according to claim 6, wherein the timing data for generating the scan vector is stored in a register provided separately from the event memory and is supplied to the event generator in the scan mode. The mode change circuit,
A parallel-serial converter for converting the serial data of 2 ^N bits for each access parallelism of the N data bits from the event memory to the event memory,
A multiplexer that selects 2 ^N bits of serial data from the parallel to serial converter and supplies the serial data to the event generator when in scan mode to generate a scan vector ;
The event type semiconductor test system according to claim 6, comprising: The mode change circuit,
A parallel-serial converter for converting the serial data of 2 ^N bits for each access parallelism of the N data bits from the event memory to the event memory,
A scan timing register for storing scan timing data to define the timing of the scan vector ;
A first multiplexer for selecting 2 ^N bits of serial data from the parallel to serial converter and supplying the serial data to the event generator in scan mode to generate a scan vector ;
A second multiplexer for selecting scan timing data from the scan timing register and generating scan vectors to supply the scan timing data to the event generator in scan mode ;
The event type semiconductor test system according to claim 6, comprising:

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