JP4086597B2 - Wafer for package evaluation of semiconductor circuit and chip evaluation apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor circuit package evaluation wafer used for evaluating a hybrid integrated circuit package and a chip evaluation apparatus using the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor circuit device set in an electronic device is employed in a mobile phone, a portable computer, and the like, and thus further reduction in size, thickness, and weight is required. As the semiconductor circuit device described above, there is a package type semiconductor device in which a semiconductor element is attached to a conventional semiconductor substrate and the semiconductor substrate is sealed with a normal transfer mold.
[0003]
FIG. 9 shows a conventional package type semiconductor device. The package type semiconductor device 1 has a bare chip 2 of a semiconductor element attached to a semiconductor substrate K, and the lead terminals 3 and 3 of the bare chip 2 are attached to the printed wirings 4 and 4 printed on the printed board PS by soldering. The periphery of the semiconductor substrate 2 is covered with an insulating resin layer 5. Other chip resistors 6 and the like are attached to the printed wirings 4 and 7 of the printed circuit board PS. Since the package type semiconductor device 1 has the lead terminals 3 and 3 exposed to the outside from the insulating resin layer 5, the overall size is large, and there is a difficulty in miniaturization, thickness reduction, and weight reduction.
[0004]
7 and 8 are a plan view and a sectional view of a part of a hybrid integrated circuit device obtained by improving the package type semiconductor device 1 described above.
[0005]
A bare chip 10 of an IC or LSI circuit element is attached to the conductive pattern 11. The conductive pads 13A1, 13A2,... Of the bare chip 10 are connected by the thin metal wires 16A1, 162A2,. Yes.
[0006]
As shown in FIG. 8A, in the state described above, the conductive patterns 11, 14A1, 14A2,... Are electrically separated at the upper portions by the separation grooves 12, 12, but the lower portions are still continuous.
[0007]
The conductive pattern 11, the conductive patterns 14A1, 14A2,..., The circuit element 10 attached to the conductive pattern 11 and the fine metal wires 16A1, 16A2,. Thereafter, the conductive pattern 11 and the lower continuous portions of the conductive patterns 14A1 and 14A2 are cut together with the insulating resin 19 as indicated by the dotted line, so that the conductive pattern 11 and the conductive patterns 14A1 and 14A2 are completely electrically separated.
[0008]
As shown in FIG. 8B, the lower surfaces of the conductive patterns 11, 14A1, 14A2,... Are exposed from the insulating resin 19. The exposed portions of the conductive patterns 11, 14A1, 14A2,... Are provided with solder and the like to form the external electrodes 17A1, 17A2,. Further, the portions where the external electrodes of the conductive patterns 11, 14A1, and 14A2 are not provided are covered with a resist 20 for the purpose of protecting the conductive patterns, thereby forming a hybrid integrated circuit device.
[0009]
In the hybrid integrated circuit formed as described above, the external electrodes 17A1, 17A2,..., 18 are directly joined to the printed wiring provided with the necessary wiring on the printed circuit board, and the power supply circuit is easily configured.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 02-240940
[Problems to be solved by the invention]
The above-described hybrid integrated circuit device (hereinafter referred to as the present integrated circuit) does not use a substrate that supports the circuit elements, but covers the circuit elements and the conductive patterns that form the electrodes and the fine metal wires that connect them with an insulating resin. Since it is fixed together, it can be reduced in thickness and size.
[0012]
However, in this hybrid integrated circuit device in which circuit elements and conductive patterns are molded by using an insulating resin without using a substrate, the conductive pattern having electrodes and pads formed is molded by using an insulating resin. Evaluation of package reliability is important.
[0013]
Package reliability is evaluated by checking whether or not the metal wire or the like bonded to the circuit element electrode, conductive pattern, or electrode of the circuit element and the wire bonding pad of the conductive pattern is cut by external stress, etc. I do. Further, it is confirmed that the external electrode of the hybrid integrated circuit device molded with an insulating resin is in good contact with the printed wiring of the printed board.
[0014]
The reliability evaluation of this package requires a large number of evaluation samples because all the materials related to the built-in chip size, molded insulating resin, base substrate structure, wire bonding, etc. are combined. Time is also tremendous.
[0015]
The reliability evaluation of the semiconductor device packaged with the insulating resin, including the hybrid integrated circuit described above, is the same shape as a chip used for mass production without using a prototype hybrid integrated circuit and without mounting circuit elements. Using a test chip for evaluation in which the outer and inner wire bonding pads to be connected to the electrode are connected to the daisy chain, a one-stroke pattern is formed in combination with the printed circuit board, and the conductive pattern of the test chip is connected as designed. The reliability is evaluated such as
[0016]
At this time, it is naturally desirable that the test chip has substantially the same shape as the chip actually used for mass production, but it is very inefficient to newly create a semiconductor wafer for each chip used for mass production. Costs are also incurred.
[0017]
[Means for Solving the Problems]
In the present invention, test chips of various sizes used for package evaluation of a hybrid integrated circuit device or the like in which a semiconductor circuit is molded with an insulating resin can be created from a single semiconductor wafer. A semiconductor wafer in which a plurality of single chips each having a size necessary for forming a circuit element are formed by forming wire bonding pads, and adjacent wire bonding pads inside and outside the single chip are connected to the semiconductor wafer. Chips used for mass production from the semiconductor wafer are connected so as to form a daisy chain and wire bonding pads with a single chip facing each diagonal line so as to form a daisy chain. A semiconductor circuit pattern in which test chips of approximately the same size and shape are cut and formed. It is to provide a cage for evaluation wafer.
[0018]
Further, the present invention is a chip evaluation apparatus that actually evaluates a package of a test chip, a test chip having a plurality of wire bonding pads having substantially the same size and shape as a chip used for mass production cut out from a semiconductor wafer, The die bonding pad to which the test chip is attached, the conductive pad connected to the wire bonding pad of the test chip and the test chip and the conductive pad attached to the die bonding pad are exposed to the outside at the lower end of the conductive pad. A test hybrid integrated circuit having an insulating resin to be coated and fixed and a printed board on which a printed wiring connecting the conductive pads is provided, and the hybrid integrated circuit is placed on the printed board By doing so, the wire bond that becomes the electrode of the test chip Completing the daisy chain of the pad and inspecting the wire bonding pad on the outside of the test chip, connecting the wire bonding pad on the inside of the test chip to the daisy chain, applying a test current to the daisy chain, Provided is a chip evaluation device for inspecting a pad.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
A test board for package evaluation of a hybrid integrated circuit device of the present invention will be described with reference to FIGS.
[0020]
FIG. 1 is a plan view of a wafer for package evaluation according to the present invention.
[0021]
The semiconductor wafer 20 is made of silicon, and has a single chip 21A, 21B, 21C, 21D having a size necessary for forming a plurality of transistors or circuit elements such as resistors necessary for constituting an LSI or IC. ... and form a plurality. A single chip 21A, 21B, 21C, 21D,..., A test chip of an arbitrary size required for each unit is cut out.
[0022]
FIG. 2 is an enlarged plan view of a single chip constituting the semiconductor wafer 20, and FIG. 3 is a cross-sectional view of the single chip 21A.
[0023]
A plurality of wire bonding pads 22A1, 22A2, 22A3,... Serving as electrodes made of Al or the like are formed on the semiconductor wafer 20 on the outer periphery of the single chip 21A. The other single substrates 21B, 21C, 21D... Have the same configuration, and a plurality of these single chips 21A, 21B, 21C, 21D.
[0024]
The single chips 21A, 21B, 21C, 21D... Are made as small as possible in order to be applied to many chip sizes that are actually used to form LSIs or ICs. For this reason, the wire bonding pads 22A1, 22A2, 22A3,... Described above are the smallest pads that are possible for bonding wires.
[0025]
As shown in FIG. 1, adjacent wire bonding pads 22A1, 22A2, 22A3..., 22B1, 22C1, 22D1... Are partly within each single chip 21A, 21B, 21C, 21D. When connected externally, they are connected in pairs so that a daisy chain is formed, and wire bonding pads 22A1, 22A2, 22A3..., 22B1, 22C1, 22D1. One set is connected to form a daisy chain.
[0026]
An example will be described. Adjacent wire bonding pads 22A2 and 22A3 and wire bonding pads 22A4 and 22A5... Of a single chip 21A are connected to each other by conductive patterns 23A1, 23A2. ing.
[0027]
The wire bonding pad 22A2 of the single chip 21A is connected to the wire bonding pad 22B2 of the adjacent single chip 21B on the semiconductor wafer 20 by the conductive pattern 23B1. Similarly, the wire bonding pad 22A11 of the single chip 21A is connected to the wire bonding pad 22D2 of the adjacent single chip 21D on the semiconductor wafer 20 by the conductive pattern 23D1.
[0028]
As shown in FIG. 3A, in the present invention, the wire bonding pad 22A10 of the single chip 21A and the wire bonding pad 22C1 of the chip 21C that are diagonally facing each other are connected by the conductive pattern 23C1, and the diagonal direction is also directed. The wire bonding pad 22B10 of the matching single chip 21B and the wire bonding pad 22D1 of the chip 21D are connected to the conductive pattern 23C1 by a two-layer conductive pattern 23B1.
[0029]
As shown in FIG. 3B, the wire bonding pad 22A10 of the single chip 21A facing the diagonal line and the wire bonding pad 22C1 of the chip 21C are connected by the conductive pattern 23C1 in the same manner as described above. If the wire bonding pad 22B10 of the matching single chip 21B and the wire bonding pad 22D1 of the chip 21D are connected by the metal thin wire 23B11, it is not necessary to have two conductive patterns.
[0030]
FIG. 4 shows a test chip 25 produced by cutting a semiconductor wafer 20 into a single chip unit to a size close to the chip size of an LSI used in a hybrid integrated circuit device or the like used for mass production as an output circuit of a cellular phone. . Four single substrates 21A, 21B, 21C, and 21D are diced at the positions indicated by the dotted lines in FIG. 1 in accordance with the chip size of the LSI or the like used in the hybrid integrated circuit device to form a test chip for package evaluation. To do. As an example, four single substrates are cut out, but any number of single chips may be cut out according to the size of the chip used for the LSI.
[0031]
FIG. 5 and FIG. 6 are a plan view and a cross-sectional view of a chip evaluation apparatus for evaluating a test chip cut out from the semiconductor wafer 20 as described above.
[0032]
First, the test chip 25 is molded with an insulating resin to form a hybrid integrated circuit for testing. Therefore, the test chip 25 cut out from the semiconductor wafer 20 is attached to the die bonding pad 30 </ b> A having the conductive pattern 30. Further, the wire bonding pads 22X1, 22X2, 22X3... Of the test chip 25 are electrically connected to the conductive pads 31A, 31B, 31C... By wire-bonded metal thin wires 32A, 32B, 32C.
[0033]
As shown in FIGS. 6A and 6B, in this state, the upper part of the conductive pattern 30 and the conductive pads 31A, 31B, 31C... Are separated by the separation grooves 35, 35, but the lower part is connected. Yes. The test chip 25 is attached to the die bonding pad 30A, and the wire bonding pads 22X1, 22X2, 22X3... And the conductive pads 31A, 31B, 31C... Are electrically connected by the fine metal wires 32A, 32B, 32C. After that, the test chip 25, the conductive pattern 30, the conductive pads 31A, 31B, 31C... And the metal thin wires 32A, 32B, 32C. To do.
[0034]
After that, the lower part where the conductive pattern 30 and the conductive pads 31A, 31B, 31C... Are connected together with the insulating resin 36 is cut as indicated by the dotted line, and the conductive pattern 30 and the conductive pads 31A, 31B, 31C. .. Separate completely. In this state, the lower ends of the conductive pads 31A, 31B, 31C... Are not covered with the insulating resin 36 and are exposed.
[0035]
As shown in FIGS. 6C and 6D, external electrodes 38A, 38B, 38C,... Are formed on the exposed portions with solder or the like, and a hybrid integrated circuit 37 for testing is completed. The hybrid integrated circuit 37 is further placed on the printed board 40. As shown in FIG. 5, printed wirings 41A, 41B, 41C,... Are printed on the printed board 40 so that the wire bonding pads 22X1, 22X2, 22X3,. When the hybrid integrated circuit 37 is placed on the printed circuit board 40, for example, the external electrodes 38D and 38E of the conductive pads 31D and 31E are in contact with and connected to the printed wiring 41D. Therefore, the wire bonding pads 22X5 and 22X6 that are not connected are connected.
[0036]
As described above, the wire bonding pads not connected on the semiconductor wafer 20 are all daisy chain connected by the conductive patterns 23A1, 23A2,... On the semiconductor wafer and the printed wirings 41A, 41B.
[0037]
Next, a test voltage is applied between the test terminals T1 and T2. As a result, when a current flows through the conductive pattern on the semiconductor wafer and the printed wiring on the wire bonding pads 22X1, 22X2, 22X3... Of the test chip 25, the test chip is molded with the insulating resin 36. It can be evaluated whether a current can flow normally without disconnection of a conductive pattern or a fine metal wire due to heat or stress. Further, the contact state between the electrodes 38A, 38B... And the printed wirings 41A1, 41B.
[0038]
If the conductive pattern, electrode, or fine metal wire is disconnected in the temperature test or storage test, no current flows between the test terminals T1 and T2. Further, no current flows between the test terminals T1, T2 due to poor contact between the external electrodes 38A, 38B,... And the printed wirings 41A, 41B,.
[0039]
In such a case, it is possible to find a cutting point by sequentially connecting a tester between external electrodes not connected by the printed wirings 41A, 41B..., For example, between the external electrodes 31A and 31B. it can.
[0040]
In the above description, the disconnection of the wire bonding pad provided on the outer periphery of the test chip 25 was inspected. However, as shown in FIG. 4, in the test chip 25 in which the single chips 21A, 21B, 21C, and 21D are cut out, the wire bonding pads 22A10 of the single chip 21A and the wire bonding pads 22C1 of the chip 21C that face diagonally are connected. Therefore, daisy chains are completed for the wire bonding pads 22B1, 22B2, 22A2, 22A3,... 22B10, 22D1,.
[0041]
Accordingly, when a test current is applied between the test terminals T3 and T4, a disconnection test of the wire bonding pad and the conductive pattern connected between them can be performed as described above.
[0042]
Further, the wire bonding pad 22B10 of the single chip 21B and the wire bonding pad 22D1 of the chip 21D are connected by the conductive pattern 23B1 and the two-layer conductive pattern 23B1, and therefore, the wire bonding pad 22C10 positioned in the central vertical direction. , 22C9, 22B19... 22B11, 22C2, 22C1, 22A10, 22A11, 22D2,... 22D9, 22A19, 22A20 have completed daisy chains.
[0043]
Therefore, when a test current is applied between the test terminals T5 and T6, a disconnection test of the wire bonding pad and the conductive pattern connected between them can be performed as described above. In this way, it is possible to inspect the disconnection of the wire bonding pad, the conductive pattern, etc. inside the test chip 25.
[0044]
Electrical evaluation or the like is performed using a test chip for package evaluation, and when the test chip for package evaluation is confirmed to be suitable for mass production, it is used as a chip for mass production.
[0045]
In the above description, the case where an LSI or the like formed by a chip is incorporated in a hybrid integrated circuit has been described.
[0046]
【The invention's effect】
The semiconductor circuit package evaluation wafer of the present invention can be cut out from a single semiconductor wafer into almost the same size and shape as chips used for mass production of various sizes, and a test chip for package evaluation can be formed. Accordingly, since it is not necessary to create a test chip for each required test hybrid integrated circuit device, it is possible to reduce the initial cost for manufacturing a semiconductor wafer.
[0047]
Moreover, since adjacent wire bonding pads are connected on the semiconductor wafer so that a daisy chain can be configured, the daisy chain is completed by electrically connecting the outside wire bonding pads that are not connected, and the reliability of the package In addition to being able to test the evaluation, the daisy chain of the wire bonding pads inside the test chip has also been completed, so the reliability of these wire bonding pads can be tested.
[0048]
In addition, since the wire bonding pad is the smallest possible pad for bonding the fine metal wire, it is possible to cut out a test chip having the same size and shape as a chip used for mass production.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor circuit package evaluation wafer of the present invention.
FIG. 2 is a plan view of a single chip of a wafer for package evaluation of a semiconductor circuit of the present invention.
FIG. 3 is a cross-sectional view of a single chip constituting a wafer for package evaluation of a semiconductor circuit of the present invention. FIG. 3A is a cross-sectional view in which wire bonding pads facing diagonally are connected by a conductive pattern. 3 (B) is a cross-sectional view in which wire bonding pads facing diagonally are connected by a thin metal wire.
FIG. 4 is a plan view of a test chip cut out from a wafer for package evaluation of a semiconductor circuit of the present invention.
FIG. 5 is a plan view of the chip evaluation apparatus of the present invention.
6A and 6B are cross-sectional views of a chip evaluation apparatus according to the present invention, and FIGS. 6A and 6B are hybrid integrated circuit portions for testing used in the chip evaluation apparatus, and are cross sections taken along lines AA and BB in FIG. FIG. 6C is a cross-sectional view taken along line AA in FIG. 5, and FIG. 6D is a cross-sectional view taken along line BB in FIG.
FIG. 7 is a plan view of a hybrid integrated circuit for explaining the present invention.
8A and 8B are cross-sectional views of FIG. 7, in which FIG. 8A shows a manufacturing process of the hybrid integrated circuit, and FIG. 8B is a completed diagram of the hybrid integrated circuit.
FIG. 9 is a cross-sectional view of a conventional circuit device.
[Explanation of symbols]
20 Semiconductor wafers 21A, 21B, 21C ··· Single wafers 22A1, 22A2 ... Wire bonding pads 23A1, 23A2 ... Conductive pattern 25 Test chip

Claims (5)

A plurality of wire bonding pads are formed around, and to form a plurality of single chip having a size required to provide a LCI or IC and circuit elements required to constitute a part circuit of the hybrid integrated circuit, said A semiconductor wafer in which a wire bonding pad and a single chip can be separated for each unit ,
Together with the single daisy chain during testing adjacent wire bonding outside and inside the chip chip semiconductor wafer within connects to consist, when tested with wire bonding with a single chip fits direction at each diagonally Connect to form a daisy chain,
A test chip having the same size and shape as a hybrid integrated circuit chip used for mass production by combining a single chip facing the adjacent or diagonal line from the semiconductor wafer and having the wire bonding pad around it. A wafer for package evaluation of a semiconductor circuit, characterized by being cut and formed.   2. The wafer for package evaluation of a semiconductor circuit according to claim 1, wherein a wire bonding pad with a single chip facing each diagonal line is connected by a two-layer conductive pattern.   2. The wafer for package evaluation of a semiconductor circuit according to claim 1, wherein wire bonding pads for connecting each of the diagonally facing single chips are connected by a thin metal wire.     Connect one set of wire bonding pads to each diagonally facing single chip with a conductive pattern, and connect each diagonally facing single chip to the other set of wire bonding pads with fine metal wires The wafer for package evaluation of a semiconductor circuit according to claim 1. A single chip facing adjacently and diagonally from a semiconductor wafer in which a plurality of single chips having a size necessary for forming a partial circuit of a hybrid integrated circuit are formed around which wire bonding pads are formed A single chip that is substantially the same size and shape as a chip of a hybrid integrated circuit used for mass production that is formed by combining and cutting, and adjacent wire bonding inside and outside the single chip and diagonally facing each other Test chip connected so that a daisy chain is formed at the time of wire bonding with
A plurality of conductive pads having a die bonding pad to which the test chip is attached and a wire bonding pad arranged around the die bonding pad, wherein the upper part is electrically separated by the separation groove but the lower part is connected. A conductive pattern having
After connecting the conductive pad having the die bonding pad of the test chip and the wire bonding pad with a thin metal wire, and molding the conductive pad and the test chip on which the diving pad is mounted with an insulating resin, the insulating pad A test hybrid integrated circuit formed by removing the lower part of the resin and exposing the lower part of the conductive pad separately ;
A printed circuit board with printed wiring connecting the exposed conductive pads ;
By placing the test hybrid integrated circuit on a printed circuit board, the wire bonding pads of the test chip are connected so as to complete the daisy chain, and a test current is applied to the daisy chain to thereby connect the wire bonding pads of the test chip. A chip evaluation apparatus characterized by performing the inspection.

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