JP4061888B2 - Frequency control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a frequency control circuit that controls a clock frequency of a system clock supplied to a target circuit that performs predetermined processing in synchronization with a system clock.
[0002]
[Prior art]
The power consumption in the electronic circuit system is determined by the power supply voltage and clock frequency for operating the system.
However, the system, such as a computer that executes a given program, does not always perform predetermined processing. When there is a task to be processed, the system enters an operating state and processes that task. Some may enter a standby state if there is no.
In such a system, a method of reducing wasteful power consumption by observing the operating state of the system and controlling the clock according to the operating state is employed.
For example, the following two methods are known as this type of method.
[0003]
The first method is a method of reducing the frequency by detecting that the system is in a standby state as described in, for example, Japanese Patent Application Laid-Open No. 11-219237.
[0004]
In the second method, as described in Japanese Patent Application Laid-Open No. 11-184554, the bus load state is measured, the bus access rate within a predetermined time is calculated, and the clock is set according to the access rate. It is a method of switching.
[0005]
[Problems to be solved by the invention]
However, in the first method described above, when the system frequently repeats the standby state and the operating state, it is necessary to perform processing for switching the clock frequency each time.
Also, when considering the power consumption of the system, a low clock frequency corresponding to the ratio of the operating state is supplied over a certain period of time, the standby state is reduced, and the clock frequency is lowered (lowered) for supply. Lowering the power supply voltage is expected to reduce power consumption.
[0006]
In the second method, it is necessary to create a circuit for monitoring the bus load status according to the bus protocol, and depending on the system, the bus load status and the system load status may not always match. There is a problem with versatility.
There is also a method of controlling the clock frequency by observing the operating state of the system by software. Although control by software has a high degree of freedom, there is a problem that this processing itself increases the load on the system.
[0007]
The present invention has been made in view of such circumstances, and an object of the present invention is to automatically change the frequency of the clock supplied to the system in accordance with the ratio of the operating state of the system, and to reduce the power consumption of the system. It is an object to provide a frequency control circuit that can control the system to an optimum value according to the activity, is highly versatile, and can reduce the load on the system.
[0008]
[Means for Solving the Problems]
  In order to achieve the above object, the frequency control circuit according to the first aspect of the present invention is capable of supplying a system clock having a plurality of clock frequencies, and for at least one target circuit that performs processing in synchronization with the system clock. A clock supply circuit for supplying a system clock having a clock frequency according to the control signal;Measure the clock pulse of the system clock based on the signal indicating the operating state of the target circuit,Observing means for observing the operating state of the target circuit at regular intervals, and determining the system clock frequency based on the operating state of the target circuit observed by the observing means, and supplying the system clock of the determined clock frequency Control means for outputting the control signal instructing to the clock supply circuit;And the target circuit includes a flag register that sets a flag indicating whether the target circuit is in an operating state or a standby state, and the observation unit uses the flag set in the flag register as a signal indicating the operating state The observation means has a timer circuit that measures a predetermined time, and calculates the ratio of the operating state of the target circuit in the time measured by the timer circuit..
[0009]
  A frequency control circuit according to a second aspect of the present invention is capable of supplying a system clock having a plurality of clock frequencies, and is used as a first control signal for at least one target circuit that performs processing in synchronization with the system clock. A clock supply circuit that supplies a system clock having a corresponding clock frequency, a power supply voltage supply circuit that supplies at least the power supply voltage corresponding to the second control signal to the target circuit, andMeasure the clock pulse of the system clock based on the signal indicating the operating state of the target circuit,Observing means for observing the operating state of the target circuit at regular intervals, and determining the system clock frequency based on the operating state of the target circuit observed by the observing means, and supplying the system clock of the determined clock frequency The first control signal instructed to output is output to the clock supply circuit, and a power supply voltage in the vicinity of the minimum value at which the operation of the target circuit is guaranteed at the clock frequency instructed to the clock supply circuit is supplied. Control means for outputting the second control signal to the power supply voltage supply circuit.The target circuit includes a flag register that sets a flag indicating whether the target circuit is in an operating state or a standby state, and outputs the flag set in the flag register to the observation unit as a signal indicating the operating state. The observation means has a timer circuit for measuring a predetermined time, and calculates the operating state ratio of the target circuit in the time measured by the timer circuit..
[0011]
Further, in the present invention, when there are a plurality of the target circuits, the observing means uses a signal obtained by ORing signals indicating the operation states of the target circuits as a signal indicating the operation states, and based on the signals. To measure the clock pulse of the system clock.
Preferably, each of the target circuits includes a flag register that sets a flag indicating whether the target circuit is in an operating state or a standby state, and the observation unit uses the flag set in the flag register as a signal indicating the operating state Output to.
[0013]
In the present invention, the control means determines the frequency of the system clock by adding a margin to the operating state ratio calculated by the observation means.
[0014]
In the present invention, the control means determines to increase the clock frequency when the calculated operating state ratio is larger than a value obtained by subtracting the margin from the current frequency.
[0015]
In the present invention, the control means determines the next clock frequency to a frequency higher than the current frequency by a predetermined increment of the frequency gradation.
[0016]
In the present invention, the control means lowers the clock frequency when the calculated operating state ratio is smaller than a value obtained by subtracting a margin from a frequency lower than the current frequency by a predetermined increment of the frequency gradation. Make a decision.
[0017]
In the present invention, the control means may be configured such that the calculated operating state ratio is equal to or less than a value obtained by subtracting a margin from the current frequency, and the calculated operating state ratio is a gradation of the frequency from the current frequency. If the frequency is equal to or higher than a value obtained by subtracting the margin from the frequency lower by a predetermined increment, a decision is made to maintain the current clock frequency.
[0018]
In the present invention, when the calculated operating state ratio is larger than a value obtained by subtracting the margin from the current frequency, the control unit determines to increase the clock frequency, and the calculated operating state ratio is If the current frequency is smaller than the value obtained by subtracting the margin from the current frequency by a predetermined increment of the frequency gradation, a decision is made to lower the clock frequency, and the calculated operating state ratio will be deducted from the current frequency. The current clock frequency is maintained if it is less than or equal to the subtracted value and the calculated operating state ratio is equal to or higher than the current frequency minus the frequency minus the margin by a predetermined step of the frequency gradation. Make a decision.
[0019]
According to the present invention, for example, a target circuit operates in synchronization with a system clock supplied from a clock supply circuit capable of generating a multi-gradation clock frequency, and repeats a standby state and an operating state while performing a desired operation. Processing is performed.
In the target circuit, when it is in the operating state, an activity flag indicating that it is active is set in the flag register as, for example, logic “1”. In the target circuit, in the standby state, inactive logic “0” is set in the flag register.
Then, an activity flag set in the flag register is sent from the target circuit to the observation means, thereby indicating the operating state.
The observing means operates in synchronization with the system clock, for example, counts the pulses of the system clock when the target circuit is in operation according to the activity flag by the target circuit, and outputs this count value to the control means.
[0020]
In the control means, for example, based on the number of system clock pulses in the operation state counted by the observation means, the ratio of the operation state of the target circuit in the predetermined measurement time T (hereinafter referred to as activity) is calculated.
Then, for example, it is determined whether or not the obtained activity is larger than a value obtained by subtracting a margin from the current frequency.
At this time, if it is determined that the activity is greater than the current frequency minus the margin, the system clock frequency needs to be increased (increased), and the frequency increment of the current frequency, for example, the current frequency A decision is made to set the next higher frequency as the next higher (increased) frequency, and a control signal instructing the selected frequency selection is output to the clock supply circuit.
[0021]
For example, if it is determined that the activity is not greater than the current frequency minus the margin, the activity is subtracted from the current frequency by a frequency step, for example, a frequency that is one step lower (lowered). A determination is made as to whether or not the value is smaller.
At this time, for example, if it is determined that the activity is smaller than the value obtained by subtracting the margin from the frequency that is one step lower than the current frequency, the frequency of the system clock needs to be lowered, and the frequency increment of the current frequency, for example, A determination is made that a frequency that is one step lower than the current frequency is set as the next frequency, and a signal instructing the determined frequency selection is output to the clock supply circuit.
[0022]
For example, if it is determined that the activity is not smaller than the value obtained by subtracting the margin from the frequency that is one step lower than the current frequency, that is, if none of the above conditions is satisfied, the current frequency is maintained. A signal instructing to do so is output to the clock supply circuit.
In the clock supply circuit, a system clock having a clock frequency designated by a control signal from the control means is selected and supplied to the target circuit.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a block diagram showing a first embodiment of an electronic circuit system to which a frequency control circuit according to the present invention is applied.
[0024]
As shown in FIG. 1, the circuit system 10 includes a CPU 11 as a target circuit, a timer 12, a counter 13, a control circuit 14, and a clock supply circuit 15.
Among these components, the timer 12, the counter 13, the control circuit 14, and the clock supply circuit 15 constitute a frequency control circuit, and the timer 12 and the counter 13 constitute observation means.
[0025]
  The target of the system for which the CPU 11 is the control target of the clock frequencyConfigure circuitAs will be described later, the system operates in synchronization with the system clock SYSCLK supplied from the clock supply circuit 15 capable of generating a multi-tone clock frequency, and performs a desired task while repeating the standby state and the operating state. To process.
  The CPU 11 has an activity flag register 111 in which a 1-bit activity flag ACFLG indicating that it is active is set when in the operating state. In the activity flag register 111, for example, a logic “1” flag is set when the CPU 11 is in an operating state, and an inactive logic “0” is set when the CPU 11 is in a standby state.
  The CPU 11 indicates the operating state by sending a 1-bit activity flag ACFLG set in the register 111 to the counter 13.
  The measurement time T for measuring the activity of the CPU 11 is measured by the timer 12.
[0026]
The timer 12 operates in synchronization with the clock FXCLK having a fixed frequency to measure a certain time, and outputs the measurement result to the counter 13 and the control circuit 14 as the coincidence signal S12 each time.
[0027]
FIG. 2 is a diagram illustrating a specific configuration example of the timer of FIG.
As shown in FIG. 2, the timer 12 includes a counter 121 that operates in synchronization with the clock CLK, a compare register 122 that holds a comparison value VCMP to be compared with the count value VCNT of the counter 121, and a count value VCNT of the counter 121. And a comparison value VCMP held in the compare register 122.
[0028]
In this timer 12, the comparison value VCMP held in the compare register 122 is set as the signal S141 by the control circuit 14, and when the count value VCNT of the counter 121 matches the comparison value VCMP, a match is notified. The signal S12 is output from the comparator 123 to the counter 13 and the control circuit 14.
In the timer 12, the count value of the counter 121 is cleared every time the count value VCNT of the counter 121 matches the comparison value VCMP. Accordingly, the coincidence signal S12 is output at a constant period according to the comparison value set in the compare register 122, in other words, the measurement time T.
[0029]
The counter 13 is a circuit that measures the activity of the CPU 11 (the ratio of the operating state), operates in synchronization with the system clock SYSCLK, and in accordance with the activity flag ACFLG by the CPU 11, the pulse of the system clock SYSCLK when the CPU 11 is in the operating state. Counting is performed, and this count value is output to the control circuit 14 as a signal S13.
[0030]
FIG. 3 is a diagram illustrating a configuration example of the counter of FIG.
As shown in FIG. 3, this counter 13 is a counter that uses an activity flag ACFLG by the CPU 11 as an enable signal, and adds a count value in synchronization with the system clock SYSCLK when the activity flag ACFLG is activated.
The counter 13 uses the coincidence signal S12 from the timer 12 as a clear signal, and initializes the count value every time the coincidence signal S12 is input.
[0031]
FIG. 4 is a timing chart for explaining the operation of the counter 13 of FIG.
[0032]
As shown in FIG. 4C, the counter 13 initializes the count value according to the coincidence signal S12 sent from the timer 12 every measurement time T.
Then, as shown in FIG. 4B, when the value of the activity flag ACFLG by the CPU 11 indicates the operating state of the CPU 11 (in this example, the activity flag ACFLG is at a high level (logic “1”)). Performs addition processing.
On the other hand, when the value of the activity flag ACFLG by the CPU 11 indicates the standby state of the CPU 11 (in this example, when the activity flag ACFLG is at a low level (logic “0”)), the addition process is stopped.
[0033]
The control circuit 14 takes in the signal S13 indicating the value of the counter 13 in synchronization with the coincidence signal S12 from the timer 12, measures the activity of the CPU 11 at a predetermined measurement time T, and sets the next based on the measured activity. The frequency of the system clock SYSCLK is determined, the determined frequency is selected, and a control signal S142 for changing the frequency of the system clock is output to the clock supply circuit 15.
Further, as described above, the control circuit 14 outputs the comparison value VCMP to be set in the compare register 122 of the timer 12 to the timer 12 as the signal S141.
[0034]
The clock supply circuit 15 can generate a system clock SYSCLK having a multi-tone clock frequency, and supplies the CPU 11 and the counter 13 with a system clock SYSCLK having a clock frequency designated by a control signal S142 by the control circuit 14. .
The clock supply circuit 15 can realize multi-gradation clock frequencies by using, for example, a method of selecting one of a plurality of clocks at a frequency or a method of changing the setting of the clock oscillation circuit.
[0035]
FIG. 5 is a diagram showing a specific configuration example of the clock supply circuit of FIG.
As shown in FIG. 5, the clock supply circuit 15 includes a phase synchronization circuit (PLL circuit) 151 that oscillates a clock having a predetermined frequency, and a plurality of, for example, four clock frequencies f0, f1, f2, and a plurality of division ratios. A frequency divider 152 that generates a clock of f3 and a selector 153 that selects and outputs a system clock having a clock frequency designated by a control signal S142 from the control circuit 14 are configured.
[0036]
In the clock supply circuit 15, an oscillation clock having a frequency of 300 MHz, for example, from the PLL circuit 151 is supplied to the frequency divider 152.
The frequency divider 152 divides the oscillation clock of the PLL circuit 15 at a plurality of frequency division ratios, for example, 1/3, 1/4, 1/6, and 1/12, thereby providing, for example, f0. Clocks having clock frequencies of (= 100 MHz), f1 (= 75 MHz), f2 (= 50 MHz), and f3 (= 25 MHz) are generated and supplied to the selector 153.
In the selector 153, a clock having a desired frequency is selected in accordance with the control signal S142 from the control circuit 14, and is supplied to the CPU 11 and the counter 13 as the system clock SYSCLK.
[0037]
The above-described 10 clock frequency control method of the circuit system according to the present embodiment is a feedback type process for determining the frequency of the next clock from the current activity. There is no guarantee that the next activity will be equivalent.
In addition, in the target system, an increase in unpredictable processing such as interruption can be considered. For this reason, it is expected that the activity will increase.
Therefore, a certain margin may need to be taken into account in determining the system frequency.
In addition, the clock supply circuit 15 includes a frequency divider 152 that generates a clock having a multi-grayscale frequency, but it is necessary to consider gradation of the frequency.
[0038]
Next, the operation of the above-described configuration will be described with reference to the flowchart of FIG. 6 when the control circuit 14 considers a certain margin in the determination of the system frequency and the clock supply circuit 15 also considers multi-tone frequency increments. This will be explained in relation to.
[0039]
The CPU 11 operates in synchronization with the system clock SYSCLK supplied from the clock supply circuit 15 capable of generating a multi-tone clock frequency, and a desired task is processed while repeating the standby state and the operating state. .
In the CPU 11, when the CPU 11 is in an operating state, a 1-bit activity flag ACFLG indicating that it is active is set in the register 111 as a logic “1”. In the CPU 11, inactive logic “0” is set in the register 111 in the standby state.
The CPU 11 sends a 1-bit activity flag ACFLG set in the register 111 to the counter 13 to indicate its operating state.
[0040]
In the timer 12, when the count value VCNT of the counter 121 matches the comparison value VCMP held in the compare register 122, a coincidence signal S <b> 12 informing that the coincidence is output from the comparator 123 to the counter 13 and the control circuit 14. Is done.
In the timer 12, the count value of the counter 121 is cleared every time the count value VCNT of the counter 121 matches the comparison value VCMP. Thus, the coincidence signal S12 is output from the timer 12 at a constant period according to the measurement time T.
[0041]
The counter 13 operates in synchronization with the system clock SYSCLK, counts the pulses of the system clock SYSCLK when the CPU 11 is in operation according to the activity flag ACFLG by the CPU 11, and outputs this count value to the control circuit 14 as a signal S13. Is done.
[0042]
In the control circuit 14, the system activity ACT at a predetermined measurement time T is calculated based on the number of pulses of the system clock SYSCLK in the operating state counted by the counter 13 (ST1).
[0043]
Then, it is determined whether or not the obtained activity ACT is larger than a value obtained by subtracting the margin MGN from the current frequency CF (ST2).
[0044]
If it is determined in step ST2 that the activity ACT is larger than the value obtained by subtracting the margin MGN from the current frequency CF, it is necessary to increase the frequency of the system clock SYSCLK. The next frequency is determined to be a frequency that is one step higher than the previous frequency FC, and the control signal S142 instructing the determined frequency selection is output to the clock supply circuit 15 (ST3), and the process returns to step ST1.
[0045]
If it is determined in step ST2 that the activity ACT is not larger than the value obtained by subtracting the margin MGN from the current frequency CF, the activity ACT is margined from the current frequency FC by a frequency step, for example, the margin MGN from the frequency lowered by one step. It is determined whether the value is smaller than the value obtained by subtracting (ST4).
[0046]
If it is determined in step ST4 that the activity ACT is smaller than the value obtained by subtracting the margin from the frequency that is one step lower than the current frequency FC, it is necessary to lower the frequency of the system clock SYSCLK. A determination is made that the next frequency is a step, for example, a frequency that is one step lower than the current frequency FC, and a signal S142 instructing the determined frequency selection is output to the clock supply circuit 15 (ST5). Return to processing.
[0047]
If it is determined in step ST4 that the activity ACT is not smaller than the value obtained by subtracting the margin from the frequency that is one step lower than the current frequency FC, that is, if neither of the conditions in steps ST2 and ST4 is satisfied. Then, a signal S142 for instructing to maintain the current frequency is output to the clock supply circuit 15 (ST6), and the process returns to step ST1.
[0048]
In order to determine the frequency of the next system clock, (1) conditions for increasing the frequency, (2) conditions for decreasing the frequency, (3) how to give the next frequency when increasing the frequency (4) What is necessary is just to prescribe | regulate how to give the next frequency when lowering a frequency.
[0049]
In the clock supply circuit 15, the system clock SYSCLK having the clock frequency designated by the control signal S 142 from the control circuit 14 is selected and supplied to the CPU 11 and the counter 13.
[0050]
In this way, the frequency is changed every predetermined measurement time T, and this flow is repeated.
[0051]
As described above, according to the first embodiment, one bit that operates in synchronization with the system clock SYSCLK, processes a desired task while repeating the standby state and the operating state, and is set in the register 111. The activity flag ACFLG is sent to the counter 13 to operate in synchronism with the CPU 11 indicating the operating state and the clock FXCLK having a fixed frequency, thereby measuring a certain time, and the measurement result is shown as a coincidence signal each time. The timer 12 that is output as S12 operates in synchronization with the system clock SYSCLK, counts the pulses of the system clock SYSCLK when the CPU 11 is in operation according to the activity flag ACFLG by the CPU 11, and outputs this count value as the signal S13. Counter 13 and timer The signal S13 indicating the value of the counter 13 is taken in synchronization with the coincidence signal S12 from 2, the CPU 11 activity is measured at a predetermined measurement time T, and the frequency of the system clock SYSCLK to be set next is determined based on the measured activity. The control circuit 14 that outputs the control signal S142 for determining, selecting the determined frequency, and changing the frequency of the system clock, and the system clock SYSCLK having a multi-tone clock frequency can be generated. 14 is provided with the clock supply circuit 15 for supplying the system clock SYSCLK having the clock frequency specified by the control signal S142 to the CPU 11 and the counter 13, so that the system is supplied to the system according to the system activity (operating state ratio). Clock circumference The number automatically can be changed, there is an advantage that it becomes possible to control the power consumption of the system to the optimum ones according to the activity.
In addition, by specifying the operating state by a 1-bit activity flag, versatility is high for both system components and control circuits.
In addition, the system load does not increase because of control by dedicated hardware.
[0052]
Second embodiment
FIG. 7 is a block diagram showing a second embodiment of an electronic circuit system to which the frequency control circuit according to the present invention is applied.
[0053]
The second embodiment is different from the first embodiment described above in that the target circuit for controlling the clock frequency is not limited to the CPU 11 but includes a plurality of peripheral circuits 16-1,. It is in.
[0054]
In an actual electronic circuit system, the target circuit whose clock frequency is to be controlled is not limited to the CPU 11 and includes a plurality of peripheral circuits 16-1,. −1,... May be in an operating state at the same time, or the CPU 11 may be in an operating state and the peripheral circuit 16-1 may be in a standby state.
Conversely, the CPU 11 may be in a standby state and the peripheral circuit 16-1 may be in an operating state.
[0055]
According to the second embodiment, in such a system 10A, in order to grasp the operating state of the entire system, in addition to the CPU 11, the peripheral circuits 16-1,. That is, the peripheral circuits 16-1,... Also include the activity flag register 161, and the operation state is indicated by the contents of the register 161.
[0056]
In the second embodiment, a logical sum of a plurality of activity flags ACFLG by the CPU 11 and the peripheral circuits 16-1,... Is taken by the OR gate 17, and the result is outputted to the count 13 as a signal S17.
The counter 13 can measure the activity of the entire system by regarding the logical sum of the plurality of activity flags as an activity flag indicating the operating state of the entire system.
[0057]
According to the second embodiment, desired control can be performed regardless of the number of peripheral circuits.
In addition, each component circuit of the system only needs to output a 1-bit activity flag, and can be realized with easy modification from the conventional circuit.
[0058]
In addition, according to the second embodiment, the same function can be obtained regardless of the number and type of components only by adding a function for calculating the logical sum of the activity flags of the CPU 11 and the peripheral circuits 16-1,. This control method can be employed and has the advantage of high versatility.
[0059]
Third embodiment
FIG. 8 is a block diagram showing a third embodiment of an electronic circuit system to which the frequency control circuit according to the present invention is applied.
[0060]
The third embodiment is different from the first embodiment described above in that a configuration for controlling the power supply voltage is added to the control of the clock frequency.
[0061]
The circuit system 10B according to the third embodiment is capable of supplying a power supply voltage having multiple gradations, and the power supply voltage having a value corresponding to the control signal (second control signal) S142B of the control circuit 14B is supplied to the CPU 11. The power supply voltage supply circuit 18 is supplied to the power supply.
[0062]
In this system 10B, when the frequency of the system clock SYSCLK is lowered, the power supply voltage can be lowered (lowered) within a range in which the operation of the system is guaranteed.
Since the power consumption of the system is proportional to the frequency of the system clock and proportional to the square of the power supply voltage, the power consumption can be further reduced.
[0063]
In the circuit system 10B of FIG. 5, the frequency of the system clock STSCLK supplied from the clock supply circuit 15 is changed or held as it is in accordance with the instruction of the control signal S142B (first control signal) from the control circuit 14B.
At this time, the control circuit 14B provides the lowest power supply voltage V at which the operation of the system is guaranteed at the frequency designated by the clock supply circuit 15._DDIs supplied to the power supply voltage supply circuit 18.
The power supply voltage supply circuit 18 supplies the power supply voltage V supplied to the system in accordance with the instruction of the control signal (second control signal) S142B of the control circuit 14B._DDFluctuate or hold as it is.
[0064]
According to the third embodiment, in addition to the effects of the first embodiment described above, there is an advantage that more efficient low power consumption can be realized.
[0065]
In addition to the control of the clock frequency clock frequency according to the third embodiment, the configuration for controlling the power supply voltage can also be applied to the system according to the second embodiment described in relation to FIG. is there.
[0066]
【The invention's effect】
As described above, according to the present invention, more efficient low power consumption can be realized by calculating the ratio of the operating state of the system.
Also, by specifying the operating state by a 1-bit activity flag, both system components and control circuits are versatile.
Furthermore, because of control by dedicated hardware, there is an advantage that an increase in system load can be prevented.
Further, according to the present invention, efficient power consumption can be reduced by adding power supply voltage control.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of an electronic circuit system to which a frequency control circuit according to the present invention is applied.
FIG. 2 is a diagram illustrating a specific configuration example of a timer according to the present embodiment.
FIG. 3 is a diagram illustrating a configuration example of a counter according to the present embodiment.
FIG. 4 is a timing chart for explaining the operation of the counter according to the present embodiment.
FIG. 5 is a diagram illustrating a specific configuration example of a clock supply circuit according to the present embodiment.
FIG. 6 is a flowchart for explaining the operation of determining the frequency of the system clock to be set next based on the activity according to the embodiment.
FIG. 7 is a block diagram showing a second embodiment of an electronic circuit system to which the frequency control circuit according to the present invention is applied.
FIG. 8 is a block diagram showing a third embodiment of an electronic circuit system to which a frequency control circuit according to the present invention is applied.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Electronic circuit system, 11 ... CPU, 12 ... Timer, 121 ... Counter, 122 ... Compare register, 123 ... Comparator, 13 ... Counter, 14 ... Control circuit, 15 ... Clock supply circuit, 151 ... Phase synchronization Circuit (PLL circuit), 152... Frequency divider, 153... Selector, 16-1... Peripheral circuit, 17.

Claims (20)

A clock supply circuit capable of supplying a system clock having a plurality of clock frequencies and supplying a system clock having a clock frequency according to a control signal to at least one target circuit which performs processing in synchronization with the system clock;
An observation means for measuring a clock pulse of a system clock based on a signal indicating an operation state of the target circuit, and observing the operation state of the target circuit at regular intervals;
Control means for determining the frequency of the system clock based on the operating state of the target circuit observed by the observation means, and outputting the control signal for instructing to supply the system clock of the determined clock frequency to the clock supply circuit and,
Have
The target circuit is
Including a flag register that sets a flag indicating whether it is in an operating state or a standby state, and outputs the flag set in the flag register to the observation means as a signal indicating the operating state;
The observation means is
A frequency control circuit having a timer circuit for measuring a predetermined time and calculating a ratio of an operating state of the target circuit in the time measured by the timer circuit. When there are a plurality of the target circuits, the observation means uses a signal obtained by logically summing signals indicating the operation states of the target circuits as a signal indicating the operation states, and a clock pulse of the system clock based on the signals. The frequency control circuit according to claim 1 . Each of the target circuits includes a flag register that sets a flag indicating whether the target circuit is in an operating state or a standby state, and outputs the flag set in the flag register to the observation unit as a signal indicating the operating state. Item 3. The frequency control circuit according to Item 2 . The frequency control circuit according to claim 1 , wherein the control unit determines a frequency of the system clock by adding a margin to a ratio of the operating state calculated by the observation unit. The frequency control circuit according to claim 4 , wherein the control means determines to increase the clock frequency when the calculated ratio of the operating state is larger than a value obtained by subtracting a margin from the current frequency. The frequency control circuit according to claim 5 , wherein the control means determines a next clock frequency to a frequency higher than the current frequency by a predetermined increment of a frequency gradation. The control means determines to lower the clock frequency when the calculated operating state ratio is smaller than a value obtained by subtracting a margin from a frequency that is lower than a current frequency by a predetermined increment of a frequency gradation. 4. The frequency control circuit according to 4 . In the control means, the calculated operating state ratio is equal to or less than a value obtained by subtracting a margin from the current frequency, and the calculated operating state ratio is low by a predetermined increment of the frequency gradation from the current frequency. The frequency control circuit according to claim 4 , wherein if the frequency is equal to or greater than a value obtained by subtracting a margin from the frequency, a determination is made to maintain the current clock frequency. When the calculated operating state ratio is greater than the current frequency minus the margin, the control means determines to increase the clock frequency, and the calculated operating state ratio is calculated from the current frequency to the frequency. If it is smaller than the value obtained by subtracting the margin from the low frequency by a predetermined step of the gradation, the clock frequency is decided to be lowered, and the calculated operating state ratio is less than the value obtained by subtracting the margin from the current frequency. and, if the calculated ratio is a predetermined increment amount corresponding low frequency tone frequency from the current frequency of the operating state of greater than or equal to minus the margin, claim 4 to make a decision to maintain the current clock frequency The frequency control circuit described. The frequency control circuit according to claim 9 , wherein the control means determines a next clock frequency to a frequency higher than a current frequency by a predetermined increment of a frequency gradation. A clock supply circuit capable of supplying a system clock having a plurality of clock frequencies and supplying a system clock having a clock frequency corresponding to the first control signal to at least one target circuit which performs processing in synchronization with the system clock; ,
A power supply voltage supply circuit for supplying a power supply voltage having a value corresponding to a second control signal to at least the target circuit;
An observation means for measuring a clock pulse of a system clock based on a signal indicating an operation state of the target circuit, and observing the operation state of the target circuit at regular intervals;
Based on the operating state of the target circuit observed by the observing means, the system clock frequency is determined, and the first control signal instructing to supply the system clock having the determined clock frequency is output to the clock supply circuit. And a control means for outputting the second control signal to the power supply voltage supply circuit so as to supply a power supply voltage in the vicinity of the lowest value at which the operation of the target circuit is guaranteed at the clock frequency instructed to the clock supply circuit. I have a,
The target circuit is
Including a flag register that sets a flag indicating whether it is in an operating state or a standby state, and outputs the flag set in the flag register to the observation means as a signal indicating the operating state;
The observation means is
A frequency control circuit having a timer circuit for measuring a predetermined time and calculating a ratio of an operating state of the target circuit in the time measured by the timer circuit. When there are a plurality of the target circuits, the observation means uses a signal obtained by logically summing signals indicating the operation states of the target circuits as a signal indicating the operation states, and a clock pulse of the system clock based on the signals. The frequency control circuit according to claim 11 . Each of the target circuits includes a flag register that sets a flag indicating whether the target circuit is in an operating state or a standby state, and outputs the flag set in the flag register to the observation unit as a signal indicating the operating state. Item 13. A frequency control circuit according to Item 12 . The frequency control circuit according to claim 11 , wherein the control means determines the frequency of the system clock by adding a margin to the operating state ratio calculated by the observation means. The frequency control circuit according to claim 14 , wherein the control means determines to increase the clock frequency when the calculated ratio of the operating state is larger than a value obtained by subtracting a margin from the current frequency. The frequency control circuit according to claim 15 , wherein the control means determines the next clock frequency to a frequency higher than the current frequency by a predetermined increment of the frequency gradation. The control means determines to lower the clock frequency when the calculated operating state ratio is smaller than a value obtained by subtracting a margin from a frequency that is lower than a current frequency by a predetermined increment of a frequency gradation. 14. The frequency control circuit according to 14 . In the control means, the calculated operating state ratio is equal to or less than a value obtained by subtracting a margin from the current frequency, and the calculated operating state ratio is low by a predetermined increment of the frequency gradation from the current frequency. The frequency control circuit according to claim 14 , wherein when the frequency is equal to or greater than a value obtained by subtracting a margin, a determination is made to maintain the current clock frequency. When the calculated operating state ratio is greater than the current frequency minus the margin, the control means determines to increase the clock frequency, and the calculated operating state ratio is calculated from the current frequency to the frequency. If it is smaller than the value obtained by subtracting the margin from the low frequency by a predetermined step of the gradation, the clock frequency is decided to be lowered, and the calculated operating state ratio is less than the value obtained by subtracting the margin from the current frequency. and, if the calculated ratio is a predetermined increment amount corresponding low frequency tone frequency from the current frequency of the operating state of greater than or equal to minus the margin, claim make a decision to maintain the current clock frequency 14 The frequency control circuit described. The frequency control circuit according to claim 19 , wherein the control means determines the next clock frequency to a frequency higher than the current frequency by a predetermined increment of the frequency gradation.

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