JP4040393B2 - Jitter test circuit, semiconductor device equipped with jitter test circuit, and jitter test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a jitter test, and more particularly to a jitter test circuit for detecting jitter of a timing signal that periodically repeats a high level and a low level, such as a clock signal, a semiconductor device equipped with the jitter test circuit, and a jitter test method.
[0002]
[Prior art]
A PLL (Phase-Locked Loop) circuit is widely used as a circuit for generating a reference frequency such as a clock signal of a microprocessor or a local oscillation signal of a wireless device. As is well known, the PLL circuit has a phase difference by comparing a reference timing signal (for example, an external input clock signal) and a PLL output timing signal (for example, a clock signal supplied to the inside of the semiconductor device). In some cases, it operates to match the phase.
[0003]
A timing signal that periodically repeats a high level and a low level, such as a clock signal output from the PLL circuit, generally includes jitter that is a temporal fluctuation of the signal. In a digital logic circuit or the like to which a clock signal is supplied, jitter causes a malfunction, so that it is necessary to measure the jitter value of the clock signal and manage the jitter below a certain value.
[0004]
An example of a test circuit for measuring jitter is described in Japanese Patent Laid-Open No. 2001-166007. FIG. 29 is a block diagram of a first conventional example of a jitter test circuit.
[0005]
In FIG. 29, the clock signal CLK output from the PLL circuit and the delayed clock signal DF that has passed through the reference delay circuit 171 are compared by the comparison circuit 172. For example, the delay difference signal DK that becomes high during the period corresponding to the delay difference. Is output. The jitter detection circuit 173 calculates a jitter value from the high level fluctuation width of the delay difference signal DK, and outputs a defective signal NG when the jitter value is larger than the jitter standard value JS.
[0006]
However, in the first conventional example of FIG. 29, since the delay value of the reference delay circuit 171 changes depending on manufacturing factors and usage environment, the jitter value is calculated from the ratio of the high-level width of the delay difference signal DK and the fluctuation width due to jitter. In this case, there is a problem that an accurate jitter value cannot be calculated.
[0007]
As a method for measuring the pulse width, a technique for counting the number of sampling pulses included in the pulse width to be measured using a sampling signal having a period smaller than the pulse width to be measured is described in Japanese Patent Laid-Open No. Sho 62-131537. Yes. By applying this technique to the jitter detection circuit 173 of the first conventional example and supplying a signal having a constant frequency as a sampling signal from the outside, the fluctuation range due to the high-level width jitter of the delay difference signal DK can be used for manufacturing factors and use. Measurement can be performed without being affected by the environment. However, when the jitter test circuit is configured in this way, a new problem arises that the jitter value can be measured only in the unit of the period of the sampling signal and can only be measured with rough accuracy.
[0008]
On the other hand, Japanese Patent Laid-Open No. 2001-166007 discloses a second conventional example in which the accuracy of jitter measurement is improved by calibrating changes in delay values of the delay circuit due to manufacturing factors and usage environments. Yes. FIG. 30 is a block diagram of a second conventional example.
[0009]
In FIG. 30, the delay circuit in the measurement unit 181 and the voltage controlled oscillation circuit (VCO) in the calibration unit 182 have the same configuration except that the output is fed back to the input, and is delayed by the control signal CD. The delay value of the circuit and the oscillation period of the VCO are changed simultaneously and similarly. In the jitter test circuit of FIG. 30, the delay circuit is calibrated prior to jitter measurement. When the external calibration signal CG is selected by the selector of the calibration unit 182 and supplied to the VCO as the control signal CD, the VCO outputs an oscillation signal PO having a frequency based on the voltage value of the control signal CD. On the other hand, an analog / digital converter (A / D) in the calibration unit 182 converts the control signal CD from analog to digital and outputs a digital control signal DC. The VF measurement circuit 24 in the calibration unit 182 measures a VF characteristic that is a relationship between the voltage of the control signal CD corresponding to the digital control signal DC and the frequency of the oscillation signal PO, and outputs a delay calibration signal VF.
[0010]
In jitter measurement, the selector of the calibration unit 182 selects the delay value detection signal CS from the measurement unit 181 as the control signal CD. At the time of jitter measurement, the measurement unit 181 compares the phase of the clock signal CLK with the delay signal DV that has passed through the delay circuit, and outputs a DC voltage corresponding to the phase shift from the charge pump as the delay value detection signal CS. A delay value detection signal CS is output as a control signal CD from the selector and supplied to the A / D. The A / D converts the voltage value of the control signal CD into a digital signal and sends it as a digital detection signal DS to the delay value detection circuit in the jitter calculator 183.
[0011]
The delay value detection circuit is supplied with the digital detection signal DS, and the maximum delay value MAX and the minimum delay of the delay signal DV of the delay circuit in the measurement unit 181 represented by the digital detection signal based on the delay calibration signal VF supplied in advance. The value MIN is detected, and each of the maximum delay value MAX and the minimum delay value MIN is supplied to the arithmetic circuit in the jitter calculator 183. The arithmetic circuit calculates a jitter value DT which is a delay difference between the maximum delay value MAX and the minimum delay value MIN, and supplies it to the comparison circuit. The comparison circuit compares the supplied jitter value DT with the standard value JS, and outputs a defective signal NG when the jitter value DT exceeds the standard value JS.
[0012]
As described above, in the second conventional example, in the calibration mode, the VF characteristic which is the relationship with the frequency of the oscillation signal PO with respect to the voltage value of the calibration signal CG is measured, and the delay calibration signal VF corresponding to this VF characteristic is measured. In the jitter measurement mode, the delay value of the clock signal CLK, which is the signal under measurement, is measured based on the delay calibration signal VF, and the jitter is calculated from the maximum and minimum values. Since the change in the delay amount of the circuit is calibrated, more accurate jitter measurement is possible as compared with the first conventional example.
[0013]
[Problems to be solved by the invention]
However, in the second conventional example, the charge pump in the measuring unit 181 has a built-in low-pass filter, and the calibration unit requires an analog / digital converter. Since these circuits handle analog voltages, they are sensitive to noise, and their arrangement must be devised so as not to be affected by noise from surrounding digital circuits, which complicates the design. In addition to the area occupied by the element circuits that make up each of the measurement unit, calibration unit, and jitter calculation unit, a region for isolating the low-pass filter and analog / digital conversion circuit from ambient noise is required. The second conventional example requires a large occupied area.
[0014]
The present invention has been made in view of such a situation, and the object of the present invention is to accurately measure the jitter amount without being affected by the manufacturing factors and the use environment as in the second conventional example. It is to provide a jitter test circuit that is configured with a digital circuit and is easier to design than the second conventional example and can be realized with a small occupied area, a semiconductor device equipped with the jitter circuit, and a jitter test method.
[0015]
[Means for Solving the Problems]
A jitter test circuit according to a first aspect of the present invention is a jitter test circuit for detecting jitter of a timing signal that periodically and periodically repeats a high level and a low level, wherein the timing signal and the delay time are the number of basic delay units. Delay control information to be designated as a reference timing signal, and a timing signal for comparison generated by delaying the timing signal by a first time based on the delay control information and a signal obtained by delaying the timing signal by a second time. A window signal generating circuit for generating and outputting a window signal provided with a window having a predetermined signal level in the third time width before and after the rising point and the falling point, and the comparison timing signal And the window signal, and the rising and falling points of the comparison timing signal indicate the window signal. A comparison circuit that detects whether or not the signal is within the output and outputs a comparison result; a command including an operation mode designation and the comparison result are input to control generation of the delay control information and execution of the test operation; and calibration In the mode, the second time is searched for delay control information that is equal to the time obtained by adding one period of the timing signal when there is no jitter in the first time. In the pass / fail judgment mode, the calibration mode And a test control circuit that sets the second time based on the delay control information searched in step 3, sets the third time as a jitter standard value, and determines pass / fail based on the comparison result from the comparison circuit. Is done. Further, in the calibration mode, the test control circuit sets the second time to a time larger than a time obtained by adding the first time and the third time to one cycle of the timing signal. When the control information is initialized and then the delay control information is manipulated to gradually reduce the delay time of the second time in increments of basic delay units, and the comparison result from the comparison circuit is monitored and there is no jitter And searching for delay control information corresponding to the second time when the rising and falling points of the comparison timing signal are located at the center of the window, and in the pass / fail judgment mode, search in the calibration mode. The second time is set based on the received delay control information, the delay control information is generated based on the command input from the outside, and the jitter standard value The third time is set, a plurality of comparison results in the comparison circuit are taken in, and the number of comparison results generated indicating deviations from the window at the rising and falling points of the comparison timing signal is greater than or equal to a predetermined number. It may be configured to determine that it is defective.
[0016]
A jitter test circuit according to a second aspect of the present invention is a jitter test circuit for detecting jitter of a timing signal that periodically and periodically repeats a high level and a low level, wherein the timing signal and the delay time are the number of basic delay units. Delay control information to be designated as a reference timing signal, and a timing signal for comparison generated by delaying the timing signal by a first time based on the delay control information and a signal obtained by delaying the timing signal by a second time. A window signal generating circuit for generating and outputting a window signal provided with a window having a predetermined signal level in the third time width before and after the rising point and the falling point, and the comparison timing signal And the window signal, and the rising and falling points of the comparison timing signal indicate the window signal. A comparison circuit that detects whether or not the signal is within the output and outputs a comparison result; a command including an operation mode designation and the comparison result are input to control generation of the delay control information and execution of the test operation; and calibration In the case of the jitter mode, the second time is searched for delay control information that is equal to the time obtained by adding one period of the timing signal when there is no jitter in the first time. A test control circuit that sets the second time based on the delay control information searched in step, and changes the third time by the comparison circuit and determines a jitter value based on a result of comparison multiple times; and And an encoding circuit that generates and outputs encoded jitter information from the jitter value determined by the test control circuit and the delay control information. It is. Further, in the calibration mode, the test control circuit sets the second time to an initial time larger than a time obtained by adding the first time and the third time to one cycle of the timing signal. When the delay control information is set and then the delay control information is operated to gradually reduce the delay time of the second time in increments of basic delay units, and the comparison result from the comparison circuit is monitored and there is no jitter And searching for delay control information corresponding to the second time when the rising and falling points of the comparison timing signal are located at the center of the window, and in the jitter measurement mode, search in the calibration mode. The second time is set based on the delay control information, and the width of the window is changed by controlling the third time based on the delay control information. May be configured to determine a comparison result with the jitter value from the delay control information corresponding to a third time threshold value determination changes from good to monitor in correspondence to a defective of said comparator circuit while.
[0017]
According to a third aspect of the present invention, there is provided a test circuit for detecting jitter with respect to a timing signal output from a clock recovery PLL circuit that inputs a data signal and extracts and reproduces a timing signal synchronized with the data signal. In the test circuit, the timing signal and delay control information designating the delay time as the number of basic delay units are input, and the timing signal is generated by delaying the timing signal by a first time based on the delay control information. A timing signal and a window signal provided with a window having a predetermined signal level in a third time width before and after the rising point and the falling point of the signal obtained by delaying the timing signal by a second time. A window signal generation circuit that generates and outputs the timing signal for comparison and the window signal; A comparison circuit that detects whether or not the rising and falling points of the comparison timing signal are within the window and outputs a comparison result, and data of the same sign in the data signal is continuous for a predetermined number of data or more The same sign continuous data detection circuit that outputs the same sign continuous data detection signal when it is detected, the command including the operation mode designation, and the comparison result are input to generate the delay control information and execute the test operation In the calibration mode, the second time is searched for delay control information that is equal to the time obtained by adding one period of the timing signal when there is no jitter in the first time. Sometimes the second time is set based on the delay control information searched in the calibration mode, and the third time is The comparison result from the comparison circuit sets the standard value constituted and a determining test control circuit acceptability. Further, in the calibration mode, the test control circuit sets the second time to an initial time larger than a time obtained by adding the first time and the third time to one cycle of the timing signal. When the delay control information is set and then the delay control information is operated to gradually reduce the delay time of the second time in increments of basic delay units, and the comparison result from the comparison circuit is monitored and there is no jitter And searching for delay control information corresponding to the second time when the rising and falling points of the comparison timing signal are located at the center of the window, and in the pass / fail judgment mode, search in the calibration mode. The second time is set based on the received delay control information, the delay control information is generated based on the command input from the outside, and the jitter standard value The third time is set, a plurality of comparison results in the comparison circuit are taken in, and the number of comparison results generated indicating deviations from the window at the rising and falling points of the comparison timing signal is greater than or equal to a predetermined number. It may be configured to determine that it is defective.
[0018]
A semiconductor device according to a fourth aspect of the present invention includes any one of the jitter test circuit according to the first aspect, the jitter test circuit according to the second aspect, and the jitter test circuit according to the third aspect. It is characterized by that. A divider circuit may be mounted and the output of the divider circuit may be input to the jitter test circuit, or a PLL circuit may be mounted and the output of the PLL circuit may be input to the jitter test circuit, or A multiplying PLL circuit may be mounted and the output of the multiplying PLL circuit may be input to the jitter test circuit, or a clock recovery PLL circuit may be mounted and the output of the clock recovery PLL circuit may be input to the jitter test circuit. May be.
[0019]
A jitter test method according to a fifth aspect of the present invention is a jitter test method for detecting jitter of a timing signal that periodically repeats a high level and a low level alternately, and is generated by delaying a timing signal to be measured for jitter. When the rising and falling points of the comparison timing signal are free from jitter, the number of basic delay units of the delay circuit is adjusted so that it is positioned at the center of a window of a predetermined width provided for each. A calibration phase for determining the position of the window; a window provided at a position adjusted in the calibration phase; and a rising point and a falling point of the comparison timing signal, and a rising point or a falling point Is determined to be outside the window having the predetermined width. Number of times is characterized by comprising a failure and determining quality determination phase in the case where a predetermined number of times or more.
[0020]
A jitter test method according to a sixth aspect of the present invention is a jitter test method for detecting jitter of a timing signal that periodically repeats a high level and a low level alternately, and is generated by delaying a timing signal to be measured for jitter. When the rising and falling points of the comparison timing signal are free from jitter, the number of basic delay units of the delay circuit is adjusted so that it is positioned at the center of a window of a predetermined width provided for each. The calibration phase for determining the position of the window, the rising and falling points of the comparison timing signal, and the window adjusted in the calibration phase are changed by changing the width on both sides with respect to the center of the window. If the width is changed, it will be compared multiple times and judged as defective. The detecting window width is characterized in that it comprises a jitter measurement phase to output the determined coding jitter value.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, the following description shows typical embodiment of this invention, This invention is limited to the following description and is not interpreted.
[0022]
FIG. 1 is a diagram schematically showing a semiconductor device equipped with a jitter test circuit of the present invention. The semiconductor device 200 includes a jitter test circuit 1, a PLL circuit 2, and an internal circuit 3.
[0023]
The PLL circuit receives an input clock signal ICLK that is a reference timing signal from the outside, and outputs a clock signal CLK that is a timing signal that is phase-synchronized with the input clock signal ICLK.
[0024]
The internal circuit 3 is a digital logic circuit that operates in synchronization with the clock signal CLK, and performs digital logic operation on the input data IDAT and outputs output data ODAT.
[0025]
The jitter test circuit 1 receives the clock signal CLK and operates in a calibration mode or a pass / fail judgment mode in accordance with an input command CMD from the outside. In the calibration mode, the delay value of the delay circuit inside the jitter test circuit 1 is calibrated. In the pass / fail judgment mode, the judgment result signal JDG is output by comparing the jitter with the jitter standard value JS designated by the command CMD from the outside.
[0026]
FIG. 2 is a block diagram of an embodiment of the jitter test circuit of the present invention. The jitter test circuit 1a includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13.
[0027]
The window signal generation circuit 11 receives the clock signal CLK and the delay control information DINF, generates the comparison clock signal DCLK generated by delaying the clock signal by the first time D1 based on the delay control information DINF, and the clock signal A third time before and after the rising and falling points of the signal obtained by delaying CLK by the first time D1 by subtracting the third time D3 from the second time D2 (D2-D3). A window signal WS provided with a window having a predetermined signal level with a width of D3 is generated and output.
[0028]
For example, as shown in the window signal generation circuit 11a in FIG. 3A, the window signal generation circuit 11 receives the clock signal CLK and delays it by a time obtained by subtracting the third time D3 from the second time D2. A first variable delay circuit 21 that outputs the generated first delay signal T1, and a second delay signal that is generated by inputting the first delay signal T1 and delaying it by a time twice as long as the third time D3. A second variable delay circuit 22 for outputting T2, an exclusive OR circuit 23 for inputting the first delay signal T1 and the second delay signal T2, and an output of the exclusive OR circuit 23 for inversion And an inverter 24 that outputs it as a window signal. The window signal generation circuit 11a in FIG. 3A is an example of a window signal generation circuit when the first time D1 is set to zero. Each variable delay circuit is configured such that a plurality of basic delay units composed of, for example, two stages of inverters are connected in series, and the delay value can be varied by switching the output output position.
[0029]
The comparison circuit 13 compares the comparison clock signal DCLK with the window signal WS, detects whether the rising and falling points of the comparison clock signal DCLK are within the window of the window signal WS, and outputs the comparison result. To do.
[0030]
For example, as shown in the comparison circuit 13a of FIG. 4, the comparison circuit 13 includes a flip-flop 31 that captures the signal level of the window signal WS at the rising edge of the comparison clock signal DCLK, an inverter 32 that inverts the comparison clock signal DCLK, The flip-flop 33 that takes in the signal level of the window signal WS at the rising edge of the inverted signal of the comparison clock signal DCLK, the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 are input, and the logical sum is obtained. And an OR circuit 34 that outputs a failure determination signal NG that is high when any of them is high.
[0031]
The test control circuit 12 includes a control unit 15 that controls the operation of the entire jitter test circuit and the arithmetic unit according to the state of the failure determination signal NG from the comparison circuit 13 based on the command CMD, and an initial value specified by the command CMD. And a calculation unit 14 for generating delay control information DINF by calculation under the control of 15, and in the calibration mode, the second time D2 is the clock signal CLK when there is no jitter in the first time D1. The delay control information equal to the time obtained by adding one period is searched, and in the pass / fail judgment mode, the third time D3 is set to the jitter standard value JS, and pass / fail is judged by the state of the fault judgment signal NG from the comparison circuit 13. To do.
[0032]
In the jitter test circuit 1a, the operation mode is specified by the command CMD, the initial value of the delay control information DINF for controlling each delay of the window signal generation circuit in the designated operation mode, the number of repeated measurements, the number of passes, the number of times of failure, etc. Done.
[0033]
FIG. 5 is an operation timing chart of the window signal generation circuit 11 and the comparison circuit 13 in the pass / fail judgment mode of the jitter test circuit 1a of FIG. Description will be made assuming that the window signal generation circuit 11a of FIG. 3A is used as the window signal generation circuit and the comparison circuit 13a of FIG. 4 is used as the comparison circuit.
[0034]
In the calibration mode, the rising and falling edges of the virtual signal obtained by delaying the comparison clock signal DCLK by an ideal period Dp when there is no jitter are adjusted so as to be positioned at the center of the window of the window signal WS. Due to the calibration, the first delay signal T1 in the window signal generation circuit 11a in FIG. 3A is delayed by a third delay time D3 (that is, half the window width) from the virtual signal delayed by one cycle from the clock signal CLK. The delay of the second delay signal T2 is set to be larger by the third delay time D3 than the virtual signal delayed by one cycle from the clock signal CLK. The window signal WS includes the first delay signal T1 and the second delay signal T1. When the delay signal T2 of 2 is different, a low level window is set.
[0035]
When there is no jitter in the clock signal CLK that is the output of the PLL 2 by adjustment in the calibration mode, the rising point and the falling point of the comparison clock DCLK are located at the center of the window of the window signal WS. In the range A in which no occurrence occurs, both the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 in the comparison circuit 13a in FIG. 4 remain at low level, and the defect determination signal NG is at low level and the comparison circuit 13a. It shows that the comparison result in is good.
[0036]
On the other hand, in the range B where the jitter having a value larger than the third time D3 is generated in the clock signal CLK, the rising and falling points of the comparison clock DCLK deviate from the window of the window signal WS. In some cases, the output C1 of the flip-flop 31 or the output C2 of the flip-flop 32 in the comparison circuit 13a becomes high level, and the failure determination signal NG becomes high level, indicating that the comparison result in the comparison circuit 13a is bad. Show.
[0037]
In the jitter test circuit according to the first embodiment of FIG. 2, the window signal generation circuit is a second example instead of the window signal generation circuit 11a of FIG. 3A described as the first example. The window signal generation circuit 11b may be the 3 (b).
[0038]
That is, the window signal generation circuit 11b receives the clock signal CLK from the PLL 2, delays it by a time obtained by subtracting the third time D3 from the second time D2, and outputs the first delay signal T11. The variable delay circuit 22 that receives the first delay signal T11 and outputs the second delay signal T12 that is generated by delaying by the time twice the third time D3, the first delay signal T11 and the second delay signal T11 Of the delay signal T12 and an exclusive OR circuit 23 for taking an exclusive OR, an inverter 24 for inputting and inverting the output of the exclusive OR circuit 23, and a clock signal CLK. And a variable delay circuit 26 that delays by the time D1, and outputs the output of the variable delay circuit 26 as a comparison clock signal DCLK and the output of the inverter 24 as a window signal WS. Forces. In the window signal generation circuit 11a of FIG. 3A, the second time D2 is adjusted by calibration so as to have an ideal period Dp when there is no jitter of the clock signal CLK. The window signal generation circuit 11b is different in that the second time D2 is adjusted by calibration to be a time obtained by adding the period Dp of the clock signal CLK when there is no jitter to the first time D1. The comparison clock signal DCLK and the window signal WS are both input to the comparison circuit 13a of FIG. 4 with a delay of the first time D1. The window signal generation circuit 11a in FIG. 3A corresponds to the case where the first time D1 is set to 0 in the window signal generation circuit 11b of this embodiment. When the first time D1 is set to a value equal to the third time D3 in the window signal generation circuit 11b of this embodiment, the delay value after calibration of the variable delay circuit 25 is the period of the clock signal CLK. Since it becomes equal to Dp and the delay value of the variable delay circuit 26 becomes the third time D3, the setting of the delay value is simple and easy.
[0039]
Similarly, in the jitter test circuit of the first embodiment shown in FIG. 2, the window signal generation circuit is replaced with the window signal generation circuit 11a shown in FIG. The window signal generation circuit 11c shown in FIG.
[0040]
That is, the window signal generation circuit 11c receives the clock signal CLK, outputs a delay signal T21 generated by delaying the clock signal CLK by a time twice as long as the third time D3, and the clock signal CLK and the delay signal T21. And an exclusive OR circuit 23 for taking an exclusive OR, an inverter 24 for inputting and inverting the output of the exclusive OR circuit 23, an output of the inverter 24, and a second time D2 And a variable delay circuit 27 for delaying only the first time D1 by inputting the clock signal CLK and comparing the output of the variable delay circuit 27 for comparison. The clock signal DCLK is output and the output of the variable delay circuit 27 is output as the window signal WS.
[0041]
Also in the window signal generation circuit 11c of the present embodiment, the second time D2 is adjusted by calibration so that the second time D2 is a time obtained by adding an ideal period Dp when there is no jitter of the clock signal CLK to the first time D1. Further, the comparison clock signal DCLK and the window signal WS are input to the comparison circuit 13a of FIG. 4 with a delay of the first time D1 as compared with these signals in the window signal generation circuit 11a of the first embodiment. This is the same as the window signal generation circuit 11b of the second embodiment. Note that also in the window signal generation circuit 11c of this embodiment, when the first time D1 is set to a value equal to the third time D3, the delay value after calibration of the variable delay circuit 27 is the clock signal CLK. Since the delay value of the variable delay circuit 26 becomes equal to the period Dp and becomes the third time D3, the setting of the delay value is simple and easy as in the window signal generation circuit 11b of the second embodiment.
[0042]
FIG. 6A is a circuit diagram showing a window signal generation circuit 11d of the fourth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11d is obtained by deleting the inverter 24 from the window signal generation circuit 11a of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11d, the high level section is a window.
[0043]
FIG. 7 is a circuit diagram of the comparison circuit 13b configured corresponding to the window signal generation circuit 11d. The only difference is that a negative logical product circuit 35 is used instead of the logical sum circuit 34 of the comparison circuit 13a of FIG.
[0044]
FIG. 8 is an operation timing chart of the jitter test circuit 1a when the window signal generation circuit 11d and the comparison circuit 13b are used. As in the operation timing chart of FIG. 5, the rising and falling points of the comparison clock signal DCLK are in the center of the window in the range A in which the jitter is not generated in the clock signal CLK, but the window signal WS is the window section. Since the output C1 of the flip-flop 31 and the output C2 of the flip-flop 32 in the comparison circuit 13b of FIG. 7 are both at the high level, the failure determination signal NG is at the low level as in FIG.
[0045]
In the range B in which a large value jitter occurs in the clock signal CLK, the rising and falling points of the comparison clock DCLK deviate from the window of the window signal WS, and the output C1 or flip-flop 32 of the flip-flop 31 in the comparison circuit 13b. Output C2 becomes low level, and the defect determination signal NG becomes high level, indicating that the comparison result is defective.
[0046]
FIG. 6B is a circuit diagram showing a window signal generation circuit 11e of the fifth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11e is obtained by deleting the inverter 24 from the window signal generation circuit 11b of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11e, the high level section becomes a window, and is used together with the comparison circuit 13b of FIG.
[0047]
FIG. 6C is a circuit diagram showing a window signal generation circuit 11f of the sixth embodiment of the window signal generation circuit 11 in the jitter test circuit 1a of FIG. The window signal generation circuit 11f is obtained by deleting the inverter 24 from the window signal generation circuit 11c of FIG. Therefore, in the window signal WS output from the window signal generation circuit 11f, the high level section becomes a window, and is used together with the comparison circuit 13b of FIG.
[0048]
Next, the jitter test method by the jitter test circuit 1a of the first embodiment shown in FIG. 2 will be described in detail. As shown in the flow chart of the pass / fail judgment test in FIG. 9, the jitter test is performed when the jitter test circuit 1a is set to the calibration mode by an external command and the second time D2 is not jittered at the first time D1. A calibration phase 41 for adjusting to a value obtained by adding the period Dp of the clock signal CLK, and the jitter test circuit 1a is set to pass / fail judgment mode by an external command, and the second time D2 is set to a delay value obtained in the calibration phase. And a pass / fail judgment phase 42 for setting pass / fail judgment by setting the third time D3 to the jitter standard value JS by an external command.
[0049]
In the pass / fail judgment phase, the jitter test circuit 1a is one side back and forth with respect to the comparison clock signal DCLK obtained by delaying the clock signal by the first time D1 and the virtual signal obtained by delaying the comparison clock signal by one cycle. And a window signal WS provided with a window having a width of the third time D3. Therefore, it is necessary to set the delay values of the variable delay circuits 21, 25, and 27 of the window signal generation circuits 11a to 11f to a value obtained by adding the first time D1 to one cycle of the clock signal CLK and subtracting the third time D3. There is.
[0050]
On the other hand, these variable delay circuits are configured by connecting basic delay units such as two-stage inverters in series, and the delay value is adjusted by adjusting the number of basic delay units connected in series. Since the delay value varies depending on manufacturing factors and usage environment, a calibration phase is necessary. For example, when the frequency of the clock signal CLK is 100 MHz and the basic delay unit is 0.1 ns as a standard value, 10 ns of one cycle is obtained from the frequency of the clock signal CLK, and this is obtained as the basic delay unit of the standard delay value. If configured, 100 basic delay units connected in series are used. However, for example, if the delay value of the basic delay unit is increased by 25% due to manufacturing factors and is 0.125 ns, 80 basic delay units are connected in series to realize a delay of 10 ns for one cycle of the clock signal CLK. 100 basic delay units simply calculated from the frequency are not suitable. Here is the need for calibration.
[0051]
In the present invention, the basic delay unit serially connected so that the rising point (or falling point) of the comparison clock signal DCLK generated by delaying the clock signal CLK coincides with the center of the window delayed by one cycle. The number of basic delay units for one cycle is calibrated by adjusting the number and aligning the window positions. As a result, the number of basic delay units becomes irrelevant to 100, which is the number of basic delay units for one period calculated from the clock frequency of 100 MHz and the standard delay value of 0.1 ns of the basic delay unit. The basic delay unit of the 125 ns delay value is used to adjust to 80, which is the number required to delay 100 ns, which is one period of the comparison clock signal DCLK.
[0052]
FIG. 10 is a flowchart of the calibration phase of the jitter test method by the jitter test circuit 1a, and FIGS. 11A, 11B, and 11C are operation timing diagrams of the calibration phase. In FIG. 10, for simplification of explanation, it is assumed that the calibration is performed on the window signal generation circuit 11a of FIG. 3A in which the first time D1 is 0, and the first time D1 is not 0. The signal generation circuit will be described after the description of FIG.
[0053]
In FIG. 10, Np is the number of basic delay units corresponding to the period Dp (hereinafter referred to as the number of basic delay units for one period), that is, (the delay value Du × Np = Dp of the basic delay unit), and Npc Is a basic delay unit number temporarily set at the time of calibration (hereinafter referred to as a temporary basic delay unit number), and N3 is a basic delay unit number (a third delay time) that determines a third time D3 that is half the width of the window. And the relationship is Du × N3 = D3.
[0054]
In FIG. 10, first, in step 51, initial setting is performed. The test control circuit 12 controls the generation of the delay control information DINF based on the command CMD from the outside, and the provisional basic delay unit number Npc is set to the time from the rising edge of the comparison clock signal DCLK to the leading edge of the corresponding window. The number is set so as to be surely larger than the time obtained by adding the third time D3 to one cycle of the clock signal CLK. That is, as shown in FIG. 11A, the time Dc from the rising edge of the comparison clock signal DCLK to the leading edge of the corresponding window signal WS is set to Dc = Npc × Du = (Dp + n × Du). Further, the third basic delay unit number N3 is set so that the window is sufficiently larger than the jitter value of the comparison clock signal DCLK.
[0055]
Next, in step 52, it is determined whether or not the rising point (rising edge) or the falling point (falling edge) of the comparison clock signal DCLK is within the window of the window signal WS. If the edge is not in the window, go to step 53; if the edge is in the window, go to step 54. In FIG. 11A, for example, the point C representing the state of the window signal at the rising point of the comparison clock signal DCLK is at the high level and is outside the window, so the routine proceeds to step 53.
[0056]
In step 53, the temporary basic delay unit number Npc is reduced by one by updating the delay control information DINF and updated. That is, the time obtained by subtracting the first time D1 from the second time D2 (corresponding to the time from the rising or falling point of the comparison clock signal DCLK to the center of the window generated based on this) is 1 Decrease by the basic delay unit delay time Du. Thereafter, the process returns to step 52.
[0057]
By repeating step 52 and step 53, as shown in FIG. 11A, a window generated based on the rising edge of the comparison clock signal DCLK, for example, indicated by a thick line (displayed by a thick line on the window signal WS). ) Moves to the left in the figure and gradually approaches the rising point C after one cycle in the comparison clock signal DCLK.
[0058]
When it is first determined in step 52 that the comparison clock signal DCLK is within the window, that is, as shown in FIG. 11B, the thick line corresponding to the rising edge indicated by the thick line of the comparison clock signal DCLK. When the leading edge of the displayed window slightly precedes the next rising edge of the comparison clock signal DCLK and the point D is judged to be low level by the comparison circuit 13a, and the pass / fail judgment signal NG becomes low level Proceed to step 54.
[0059]
In step 54, the provisional basic delay unit number Npc at this time is stored as the maximum basic delay unit number Npmax. Assuming that the maximum delay value by the maximum number of basic delay units is Dmax, the period Dp (when there is no jitter) of the comparison clock signal DCLK, the third time D3, the number Np of basic delay units corresponding to the period Dp, the third The third basic delay unit number N3, which is the number of basic delay units corresponding to the time D3,
Npmax × Du = Dmax = Dp + D3
= (Np + N3) × Du
There is a relationship. In the next step 55, the provisional basic delay unit number Npc is reduced by one by updating the delay control information DINF and updated.
[0060]
In step 56, it is determined whether the rising edge and falling edge of the comparison clock signal DCLK are inside or outside the corresponding window. When the rising edge and the falling edge of the comparison clock signal DCLK are not outside the corresponding window, that is, inside the window, the process proceeds to step 57, and the temporary basic delay unit number Npc is changed by changing the delay control information DINF. Is updated by one, and the process returns to step 56.
[0061]
By repeating Step 56 and Step 57, the window indicated by the thick line corresponding to the rising edge indicated by the thick line of the comparison clock signal DCLK in FIG. 11B moves to the left.
[0062]
When it is first determined in step 56 that the comparison clock signal DCLK is outside the window, that is, as shown in FIG. 11C, the thick line corresponding to the rising edge indicated by the thick line of the comparison clock signal DCLK. When the trailing edge of the displayed window slightly precedes the next rising edge of the comparison clock signal DCLK and the point E is determined to be high level by the comparison circuit 13 and the pass / fail determination signal NG becomes high level, the step is performed. Go to 58.
[0063]
In step 58, the provisional basic delay unit number Npc at this time is stored as the minimum basic delay unit number Npmin. When the minimum delay value based on the minimum basic delay unit number is Dmin,
Npmin × Du = Dmin = Dp−D3
= (Np−N3) × Du
There is a relationship.
[0064]
Next, the routine proceeds to step 59, where the number Np of basic delay units corresponding to the period Dp is determined.
Np = (Npmax + Npmin) / 2
To complete the calibration phase.
[0065]
A value obtained by correcting the number Np of basic delay units corresponding to one period Dp when there is no jitter in the clock signal for comparison in this manner by changing the delay time of the basic delay unit due to manufacturing factors and environmental conditions. In the pass / fail judgment phase, if there is no jitter, calibration can be performed so that the rising point and falling point of the comparison clock signal are in the center of the corresponding window.
[0066]
In order to avoid a decrease in calibration accuracy due to abrupt jitter caused by strong external noise or the like and to approximate the calibration when there is no jitter in the comparison clock signal, step 52 in FIG. The edge is compared with the window at a plurality of times, and when the number of times determined to be in the window is equal to or greater than the predetermined number Nin, step 52 is determined to be in the window. In step 56, the edge and window may be compared a plurality of times, and when the number of times determined to be outside the window is equal to or greater than the predetermined number Nout, step 56 may be determined to determine that the object is outside the window. Further, in order to prevent a decrease in accuracy due to the influence of periodic jitter or the like of the comparison clock signal, the entire flow of FIG. 10 is executed a plurality of times in the calibration phase, and each corresponds to the obtained period Dp. If the average value of the number Np of basic delay units is taken to be the final Np, a decrease in calibration accuracy due to the influence of jitter can be reduced.
[0067]
The number Np of basic delay units corresponding to the period Dp is output to the outside of the semiconductor device 200 as delay control information DINF, and the actual delay value Du of the basic delay unit can be obtained by dividing the period of the clock signal by Np. . Thus, the third time D3 corresponding to the third basic delay unit number N3 can be accurately calculated, and can be accurately set to a desired window width in the pass / fail judgment phase.
[0068]
10 can be modified to a calibration flow including a window signal generation circuit in which the first time D1 is not zero. In the modified flow, instead of the calibration for determining the basic delay unit number Np for one period of the clock signal CLK, the calibration is completed, which is a time obtained by adding the first time D1 to one period Dp of the clock signal CLK. Calibration for determining the second basic delay unit number N2p corresponding to the second time is performed. The modification of FIG. 10 replaces the provisional basic delay unit number Npc (for one period) in steps 51, 53, 54, 55, 57 and 58 with the provisional basic delay unit number N2c (for the second time). In the initial setting of N2c in 51, the time from the rising or falling edge of the clock signal CLK to the leading edge of the corresponding window is longer than the time obtained by adding the first time D1 and the third time D3 to one cycle of the clock signal CLK. And the maximum basic delay unit number Npmax (for one period) in step 54 and step 59 is replaced with the maximum basic delay unit number N2max (for the second time). The minimum basic delay unit number Npmin (for one period) of step 58 is set to the minimum basic delay unit number N2 (for the second time). Replaced in, it may be replaced with basic delay unit number Np of one cycle of the clock signal CLK in step 59 to the second basic delay unit number N2p corresponding to the second time been calibrated.
[0069]
As a result, Npc, NPmax, and Npmin in each step become N2c, N2max, and N2min that are larger by the first basic delay unit number N1 corresponding to the first time D1, respectively. Therefore, the calibration calculated in step 59 The second basic delay unit number N2p corresponding to the completed second time is larger by the first basic delay unit number N1 corresponding to the first time D1 than the basic delay unit number Np for one period of the clock signal CLK. It becomes a number. To obtain the basic delay unit number Np for one period of the clock signal CLK in FIG. 10 from the second basic delay unit number N2p corresponding to the second time after calibration obtained in the modified flow described above, Np What is necessary is just to calculate as = N2p-N1.
[0070]
Next, a detailed flow of the pass / fail judgment phase will be described with reference to FIG. FIG. 12 is a flow when the window signal generation circuit 11a of FIG. 3A in which the first time D1 is 0 is used, similarly to FIG. 10 in the calibration phase. When the first time D1 is extended so that it can be applied to a window signal generation circuit that is not 0, in step 61, instead of setting the basic delay unit number Np for one cycle of the clock signal CLK, the second calibrated second time is set. What is necessary is just to change so that the 2nd basic delay unit number N2p equivalent to this time may be set.
[0071]
In the pass / fail judgment phase, first, in step 61, initial setting is performed. That is, the test control circuit 12 obtains the third delay time from the basic delay unit number Np for one cycle of the clock signal CLK obtained in the calibration phase based on the command CMD from the outside, the jitter standard value, and the basic delay unit delay value Du. A delay control information DINF is generated by calculating a third basic delay unit number N3, which is the number of basic delay units corresponding to the time D3 (half of the window width), and Np and N3 are set. The number of times PN and a predetermined number of times of failure FN are set.
[0072]
Next, the routine proceeds to step 62, where it is determined whether or not the rising edge and falling edge of the comparison clock signal DCLK are within the window. If the jitter J1 has a small jitter in FIG. 13A, as shown in the operation timing chart in the pass / fail judgment mode, the rising edge and the falling edge enter the window, and the pass / fail judgment signal NG becomes low level. If it is determined that the current position is within the window, the process proceeds to step 63, the pass count value PCNT is incremented by 1, and then the process proceeds to step 64.
[0073]
In step 64, it is determined whether or not the pass count value PCNT is less than a predetermined pass count PN. If the pass count value PCNT is less than the predetermined pass count PN, the process returns to step 62, and if it is not less than the predetermined pass count PN, it is determined as a non-defective product in step 65 and the process is terminated.
[0074]
In step 62, when the jitter J2 is large as shown in FIG. 13B, many states where the rising edge and the falling edge are outside the window occur, and the pass / fail judgment signal NG becomes high level. If it is determined that it is not within the window, the process proceeds to step 66, the count value FCNT of the number of failures is increased by 1, and the process proceeds to step 67.
[0075]
In step 67, it is determined whether or not the fail count value FCNT is less than a predetermined fail count FN. If the count value FCNT of the number of failures is less than the predetermined number of failures FN, the process returns to step 62, and if it is not less than the predetermined number of failures FN, it is determined as defective in step 68 and the process ends.
[0076]
Practically, in the pass / fail judgment phase, the test control circuit 12 fetches the signal level of the pass / fail judgment signal NG at an appropriate time interval even if it is not necessarily continuous, and the taken signal level of the pass / fail judgment signal NG is the pass level. When the count value PCNT of the number of times becomes equal to or greater than the predetermined number of passes PN, the determination signal JDG is output as a level indicating a non-defective product, and the count value FCNT of the number of times of failure in which the signal level of the accepted pass / fail determination signal NG is the fail level If the number of times of failure FN or more, the determination signal JDG may be output as a level indicating failure.
[0077]
As described above, in the first embodiment of the present invention, the calibration phase is provided before the pass / fail judgment phase, the jitter test circuit 1a is set to the calibration mode by the external command, and the positions of the comparison clock signal and the window signal are set. When the relationship is ideal when there is no jitter, the comparison clock signal DCLK is calibrated so that the rising point and the falling point are in the center of the corresponding window, and then the jitter test circuit 1a is set to pass / fail judgment mode. Then, the comparison clock signal DCLK and the window signal WS are compared, and depending on whether the rising point and the falling point of the comparison clock signal DCLK are in the corresponding window position or the position outside the window, respectively. Since pass / fail judgment is made, as in the second conventional example of FIG. Concrete factors, can be measured accurately jitter amount without being affected by environmental conditions. Since the jitter test circuit 1a is composed of the window signal generation circuit 11, the test control circuit 12, and the comparison circuit 13, which are digital circuits, it is easier to design than the second conventional example having an analog circuit portion. Since no special noise countermeasure is required, there is an advantage that it can be realized with a small occupied area.
[0078]
In the present invention, the jitter measurement unit is a delay time of a basic delay unit constituted by, for example, a two-stage inverter, and the jitter is measured by changing the number of sampling pulses within the measurement range. Compared with the method described in Japanese Patent No. 131636, the delay amount of the two-stage inverter can generally be made much smaller than the period of the sampling pulse, so that the present invention can measure with higher accuracy.
[0079]
The variable delay circuits 21 and 22 in the window signal generation circuit 11a of FIG. 3A may be configured by one variable delay circuit provided with a plurality of output taps. FIG. 14A is a circuit diagram of a variable delay circuit 71 used in place of the variable delay circuit 21 and the variable delay circuit 22. The variable delay circuit 71 includes, for example, a delay generation unit 72 in which a plurality of basic delay units 74 configured by two-stage inverters are connected in series, and a delay selection unit that selects a signal from an output point of each basic delay unit and outputs a signal. In the pass / fail judgment mode, as shown in FIG. 14A, the clock signal CLK is directly output from the first output tap as the comparison clock signal DCLK by the delay selection scan of the delay selection unit 73, The clock signal CLK is output from the second output tap as the delay signal T1 by selecting the output point delayed by the time obtained by subtracting the third time D3 from the period Dp, and the clock signal CLK as the delay signal T2 from the third output tap. Selects and outputs an output point delayed by a time obtained by adding the third time D3 to the period Dp. In the window signal generation circuit 11d shown in FIG. 6A, the variable delay circuits 21 and 22 can be replaced with the variable delay circuit 71 shown in FIG.
[0080]
Similarly, in the window signal generation circuit 11b of FIG. 3B, the variable delay circuits 22, 25, and 26 may be configured by one variable delay circuit 71 provided with a plurality of output taps. FIG. 14B is a circuit diagram of the variable delay circuit 71 corresponding to the case where the first time D1 and the third time D3 are made equal in the window signal generation circuit 11b. In the pass / fail judgment mode, as shown in FIG. 14B, the clock signal CLK is output from the first output tap as the comparison clock signal DCLK to the third time by the delay selection operation of the delay selection unit 73 based on the delay control information DINF. The output point delayed by D3 is selected and outputted, the output point delayed by the period Dp of the clock signal CLK from the second output tap as the delayed signal T11 is selected and outputted, and the clock signal CLK becomes the period as the delayed signal T12. An output point delayed by the time obtained by adding twice the third time D3 to Dp is selected and output. In the window signal generation circuit 11e shown in FIG. 6B, the variable delay circuits 22, 25 and 26 can be replaced with the variable delay circuit 71 shown in FIG. 14B.
[0081]
Next, a second embodiment of the jitter test circuit according to the present invention will be described with reference to the drawings. FIG. 15 is a block diagram of a jitter test circuit 1b according to the second embodiment of the present invention.
[0082]
The jitter test circuit 1b includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13 as in the jitter test circuit 1a of the first embodiment, but further includes an encoding circuit 16. Then, after calibration, the jitter value of the clock signal CLK is measured by comparing the comparison clock signal DCLK and the window signal WS while changing the window width, and the measurement result is encoded and output to the outside.
[0083]
Also in the jitter test circuit 1b, the window signal generation circuit 11 and the comparison circuit 13 are the same as those in the jitter test circuit 1a of the first embodiment, and the window signal generation circuits 11a, 11b, and 11c in FIG. The comparator circuit 13a is used in combination, or the window signal generation circuits 11d, 11e, and 11f in FIG. 6 and the comparator circuit 13b in FIG. 7 are used in combination.
[0084]
The test control circuit 12 inputs the command CMD including the operation mode designation and the comparison result of the comparison circuit 13, and controls the generation of the delay control information DINF and the execution of the test operation. In the calibration mode, the second time D2 is searched for delay control information DINF equal to the time obtained by adding the period Dp of the clock signal CLK when there is no jitter to the first time D1, and in the jitter measurement mode, the calibration is performed. The second time D2 is set based on the delay control information searched for in the mode, and the jitter value is determined based on the result of comparison performed a plurality of times by changing the third time D3 by the comparison circuit 13.
[0085]
That is, in the calibration mode, the delay control information DINF is set by setting the second time D2 to an initial time larger than the time obtained by adding the first time D1 and the third time D3 to one cycle of the clock signal CLK. Thereafter, the delay control information DINF is operated to monitor the comparison result from the comparison circuit 13 while gradually decreasing the delay time of the second time D2 in increments of basic delay units, and the rising point of the comparison clock signal DCLK and Calibration is performed by searching for delay control information DINF corresponding to the second time D2 at which the falling point is located at the center of the window.
[0086]
In the jitter measurement mode, the second time D2 is set based on the delay control information DINF searched in the calibration mode, and the comparison is performed while changing the window width by controlling the third time D3 by the delay control information DINF. The jitter value JV is determined from the delay control information DINF corresponding to the third time D3 of the critical value, which is monitored in correspondence with the comparison result of the circuit 13 and the judgment is changed from a non-defective product to a defective product.
[0087]
The encoding circuit 16 generates and outputs encoded jitter information JINF from the jitter value JV determined by the test control circuit 12 and the delay control information DINF.
[0088]
FIG. 16 shows an example of encoding of the jitter value JV. The jitter value JV is sent to the encoding circuit 16 as the number of basic delay units corresponding to the measured actual jitter value, and the encoding circuit 16 encodes the number of basic delay units corresponding to the jitter value into a binary number representation. Output as encoded jitter information JINF. However, the encoding circuit is not limited to this. When the delay value of one basic delay unit is much smaller than the jitter value, for example, M (M is a positive integer) basic delay units. May be encoded as the same jitter value. Alternatively, the delay value Du of the basic delay unit is held in the encoding circuit 16 and the jitter value detected as the third basic delay unit number N3 corresponding to the jitter is multiplied by the delay value Du to obtain the jitter value in time. It may be encoded and output after conversion.
[0089]
Next, a jitter test method using the jitter test circuit 1b of the second embodiment shown in FIG. 15 will be described in detail. As shown in the flow chart of the jitter test in FIG. 17, the jitter test by the jitter test circuit 1b is performed by setting the jitter test circuit 1b to the calibration mode by an external command and setting the second time D2 to the first time D1. A calibration phase 81 for adjusting to a value obtained by adding the cycle Dp of the clock signal CLK when there is no signal, and the jitter test circuit 1b is set to the jitter measurement mode by an external command, and the second time D2 is obtained in the calibration phase. Set a delay value and compare the rising and falling points of the comparison clock signal DCLK and the window signal WS several times while changing the window width by changing the third time D3 that is half the window width. The jitter value is determined by detecting the third time D3 determined to be defective. It turned into it and a jitter measurement phase 82 to be output.
[0090]
The calibration phase 81 is the same as the calibration phase 41 in the first embodiment, and calibration is performed by the same method as the flow of FIG.
[0091]
A detailed flow of the jitter measurement phase will be described with reference to FIG. FIG. 18 is a flow when the window signal generation circuit 11a of FIG. 3A in which the first time D1 is 0 is used as in FIG. 10 of the calibration phase. When the first time D1 is extended so that it can be applied to a window signal generation circuit that is not 0, in step 91, instead of setting the basic delay unit number Np for one cycle of the clock signal CLK, the second calibrated second time is set. The second basic delay unit number N2p corresponding to the time may be changed.
[0092]
In the jitter measurement phase, first, in step 91, initial setting is performed. That is, the test control circuit 12 uses the third basic delay which is the number of basic delay units corresponding to Np obtained in the calibration phase based on the command CMD from the outside and the third time D3 which is half the window width. An initial value of the unit number N3 is set by the delay control information DINF, and a predetermined pass number PN, a predetermined fail number FN, and a predetermined repeated measurement number MN are set. Next, the process proceeds to step 92 where 1 is added to the number of times of measurement i and updated.
[0093]
Next, the routine proceeds to step 93, where it is determined whether or not the rising edge and falling edge of the comparison clock signal DCLK are within the window. In the operation timing chart of FIG. 19A, since the initial value of the third time D3 is set to be large, the window width of the window signal becomes much larger than the jitter of the comparison clock signal DCLK. Since the rising edge and the falling edge of the clock signal DCLK for use enter the window, the outputs C1 and C2 of the flip-flops are both at the low level and the pass / fail judgment signal NG is at the low level. If it is determined that the current position is within the window, the process proceeds to step 94 where the pass count value PCNT is incremented by 1 and updated, and then the process proceeds to step 95.
[0094]
In step 95, it is determined whether or not the pass count value PCNT is less than a predetermined pass count PN. If the pass count value PCNT is less than the predetermined pass count PN, the process returns to step 93, and if not less than the predetermined pass count PN, the process proceeds to step 96 and the basic delay corresponding to the third time D3 is determined by the delay control information DINF. The third basic delay unit number N3, which is the number of units, is updated by reducing it by one, and the pass count value PCNT and the fail count value FCNT are cleared to 0, and the process returns to step 93.
[0095]
For example, when PN is set to 5, in the state of FIG. 19A, if the path determination is repeated four times in step 93, the fifth path determination proceeds to step 96 and the third basic delay unit number N3. Is reduced by one. As a result, it is assumed that the state shown in FIG.
[0096]
Step 93 is performed in the state of FIG. 19B, but the window width of the window signal is still larger than the jitter of the comparison clock signal DCLK. Therefore, as shown by a point G2, the rising edge of the comparison clock signal DCLK and The falling edge enters the window, the outputs C1 and C2 of the flip-flops are both low level, and the pass / fail judgment signal NG is low level.
[0097]
In the state shown in FIG. 19B, when the path determination is repeated four times in step 93, the fifth path determination proceeds to step 96 where the third basic delay unit number N3 is decreased by one. As a result, the state shown in FIG.
[0098]
In step 93, when the jitter is large with respect to the window as shown in FIG. 13C, the rising edge and the falling edge are outside the window as shown at point G3, so that the outputs C1 and C2 of the flip-flops are at the high level. And the pass / fail judgment signal NG becomes high level. As described above, when it is determined in step 93 that it is not in the window, the process proceeds to step 97, the count value FCNT of the number of times of failure is increased by 1, and then the process proceeds to step 98.
[0099]
In step 98, it is determined whether or not the fail count value FCNT is less than a predetermined fail count FN. If the count value FCNT of the number of failures is less than the predetermined number of failures FN, the process returns to step 93, and if not less than the predetermined number of failures FN, the process proceeds to step 99.
[0100]
For example, when FN = 2 is set, FCNT is updated to 1 at the first fail determination when the high level of the pass / fail determination signal NG is read for the first time, and the process returns to step 93. Before the PCNT reaches 5 times, the high / low level of the pass / fail judgment signal NG is read, and if the second fail judgment occurs, the process proceeds to step 99.
[0101]
In step 99, the third basic delay unit number N3 at this time is stored in a predetermined storage area Z (i) as the basic delay number Nj (i) for jitter. In addition, the pass count value PCNT and the fail count value FCNT are cleared to zero.
[0102]
Next, the routine proceeds to step 100, where it is determined whether or not the number of measurements i is less than a predetermined number of repeated measurements MN. If it is less than the predetermined number of repeated measurements MN, the process returns to step 92 to continue the measurement. When the number of repeated measurements is MN or more, the process proceeds to step 101.
[0103]
In step 101, an average value of the basic delay numbers Nj (1) to Nj (MN) for the MN times stored in each of the storage areas Z (i) is calculated and output from the test control circuit 12 as a jitter value JV. .
[0104]
In step 102, the encoding circuit 16 encodes the jitter value as shown in FIG. 16, for example, and outputs it to the outside.
[0105]
As described above, in the second embodiment of the present invention, the calibration phase is provided before the jitter measurement phase, the jitter test circuit 1b is set to the calibration mode by the external command, and the positions of the comparison clock signal and the window signal are set. In an ideal case where there is no jitter, the relationship is calibrated so that the rising point and falling point of the comparison clock signal DCLK are in the center of the corresponding window, and then the jitter test circuit 1b is set to the jitter measurement mode. The jitter is measured by changing the third time D3 according to the delay control information DINF and comparing the comparison clock signal DCLK and the window signal WS, and the average value of a plurality of measurements is encoded as the jitter value. Outputs jitter accurately without being affected by manufacturing factors and environmental conditions Can be measured, the amount of jitter can be output to the outside of the semiconductor device mounted with a jitter test circuit 1b in serial or parallel as digital data encoding. This makes it possible to evaluate and analyze jitter such as evaluation of the distribution of jitter values by repeated measurement over a long period of time. Since the jitter test circuit 1b is composed of a digital circuit as in the first embodiment, it is easier to design than the second conventional example having an analog circuit portion and requires special noise countermeasures. Therefore, there is an advantage that it can be realized with a small occupied area.
[0106]
FIG. 20 is a block diagram of a jitter test circuit 1c according to the third embodiment of this invention. The jitter test circuit 1c includes a window signal generation circuit 11, a test control circuit 12, and a comparison circuit 13, as with the jitter test circuit 1a of the first embodiment shown in FIG. A detection circuit 17 is provided. Since the functions of the window signal generation circuit 11, the test control circuit 12, and the comparison circuit 13 are the same as those in the jitter test circuit 1a, description thereof is omitted.
[0107]
The same sign continuous data detection circuit 17 outputs the same sign continuous data detection signal CSS when it is detected in the data signal DATA inputted from the outside that the data of the same sign continues for a predetermined number of data DN or more.
[0108]
The same sign continuous data detection circuit 17 is set in advance with a same sign continuous data counter 18 that counts the number of times when the data with the same sign is continuous, that is, when 0 data is continuous or 1 data is continuous. Comparing the predetermined number of data DN with the count value CCN of the same sign continuous data counter 18 and, if the count value CCN is equal to or greater than the predetermined number of data DN, outputting the same sign continuous data detection signal CSS And a container 19.
The jitter test circuit 1c operates similarly to the jitter test circuit 1a in the calibration mode and the pass / fail judgment mode only by replacing the clock signal CLK with the recovery clock signal RCLK in the jitter test circuit 1a of FIG.
[0109]
The clock recovery PLL circuit 4 extracts and reproduces the recovery clock signal RCLK based on the change of the data signal DATA, and supplies it to the window signal generation circuit 11 and the internal circuit. Even when data of the same sign continues in the data signal DATA, the clock recovery PLL circuit 4 keeps generating the recovery clock signal RCLK while maintaining the period and phase of the recovery clock signal RCLK so far. Known examples of such a type of clock recovery PLL circuit include a phase synchronization circuit described in Japanese Patent Laid-Open No. 6-315024, a phase synchronization circuit described in Japanese Patent Laid-Open No. 10-285150, and the like.
[0110]
When both the same code continuous data detection signal CSS and the determination result signal JDG continue to be in an active signal level state, that is, data having the same code continues in the data signal DATA, and the jitter test circuit 1c has a jitter equal to or greater than the jitter specified value. Is continuously detected, there is a strong possibility that the lock frequency of the clock recovery PLL circuit has shifted for some reason. However, since the data signal DATA does not change during reception of the same-symbol continuous data, the clock recovery PLL circuit 4 itself cannot detect a phase shift, and thus the phase difference continues to expand beyond the phase that should be locked.
[0111]
FIG. 21 is a timing chart of an operation example when the data signal DATA changes from 1/0 repetition to 1 continuous data. The count value CCN of the same sign continuous data counter is incremented when the data signal DATA becomes 1 continuous data, and the recovery clock RCLK continues to maintain the signal even after the data signal DATA becomes 1 continuous data. When the predetermined number of data DN is set to 3, when the count value CCN becomes 3, the same sign continuous data detection signal CSS becomes active high level. When the period of the recovery clock RCLK changes and becomes large at time H, the pass / fail judgment signal NG becomes active high level, and when the pass / fail judgment signal NG continues high level, the judgment result signal JDG becomes active high level. . As described above, since the jitter test circuit 1c outputs the same sign continuous data detection signal CSS and the determination result signal JDG, there is an advantage that it can be detected when a shift occurs in the lock frequency of the clock recovery PLL circuit. Arise.
[0112]
FIG. 22 is a diagram showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 201, a frequency dividing circuit 111 is mounted instead of the PLL circuit 2 in the semiconductor device 200 of FIG. 1, and in the jitter test circuit 1, a jitter test of the divided clock signal DVCLK generated by dividing the input clock signal ICLK is performed. Perform a pass / fail judgment test or jitter measurement test.
[0113]
FIG. 23 is a diagram showing still another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 202, a multiplied PLL circuit 112 is mounted instead of the PLL circuit 2 in the semiconductor device 200 of FIG. 1, and the jitter test circuit 1 performs a jitter test of the multiplied clock signal NCLK generated by multiplying the input clock signal ICLK by N. Do.
[0114]
FIG. 24 is a diagram showing still another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 203, dedicated PLL circuits 121 and 122 are provided for the plurality of internal circuits A and B, respectively, and the clock signal CLKA and CLKB of the PLL circuits 121 and 122 are selected by the selector 123 using the selection signal SEL. The clock signal SCLK is supplied to the jitter test circuit 1. By configuring the semiconductor device 203 in this way, a plurality of clock signals used inside the device can be tested with one jitter test circuit.
[0115]
FIG. 25 is a diagram showing still another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 204, the clock signal CLK generated by the PLL circuit 2 and the high-quality clock FCLK supplied from the outside are input to the selector 131, and the selection clock SCLK that is an output from the selector is generated by the PLL circuit 2. The clock signal CLK is determined based on the test result of the jitter test circuit 1. When the jitter of the clock signal CLK generated by the PLL circuit 2 is large and is inconvenient as a clock signal for the operation test of the internal circuit, the internal circuit operates by supplying a high-quality clock FCLK with small jitter from the outside to the internal circuit. Test can be done.
[0116]
FIG. 26 is a diagram showing still another embodiment of the semiconductor device equipped with the jitter test circuit of the present invention. In the semiconductor device 205, either the input clock signal ICLK or the clock signal CLK generated by the PLL circuit 2 is selected and input by the selector 141, and the selected clock SCLK output from the selector 141 is jittered by the jitter test circuit 1. It is configured to test. In particular, in the jitter measurement test, the jitter measurement of the input clock signal ICLK and the jitter measurement of the clock signal CLK generated by the PLL circuit 2 are respectively performed, and the former is subtracted from the latter, thereby excluding the influence of the input jitter and resulting only from the PLL circuit 2. A jitter value can be obtained.
[0117]
FIG. 27 is a diagram showing still another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. The semiconductor device 206 includes a statistical circuit 151 in addition to the configuration of the semiconductor device 200 of FIG. The jitter signal of the clock signal CLK generated by the PLL circuit 2 is measured by the jitter test circuit 1, the encoded jitter information JINF is taken into the statistical circuit 151, and the jitter value distribution of the clock signal CLK is obtained by taking statistics of jitter for a certain period. Can be measured.
[0118]
FIG. 28 is a diagram showing still another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention. The semiconductor device 207 includes a plurality of clock recovery PLL circuits 161, 162, and 163 that generate recovery clocks from input data signals, and output clock signals CLKA, CLKB, and CLKC from the clock recovery PLL circuits 161, 162, and 163, respectively. Is selected as a clock signal to be tested by the selection signal SEL and supplied to the jitter test circuit 1, and one of CLKA, CLKB and CLKC is supplied to the internal circuit as the selection clock signal SCLK by the selection signal SEL. The selector 164 to be mounted is mounted. The jitter of the clock signals CLKA, CLKB, and CLKC can be measured by the jitter test circuit 1, and the clock signal with the least jitter can be supplied to the internal circuit as the selected clock signal SCLK.
[0119]
【The invention's effect】
As described above, according to the present invention, the jitter test circuit is set to the calibration mode before the pass / fail judgment or jitter measurement is performed, and the positional relationship between the comparison clock signal and the window signal is used for comparison in an ideal case where there is no jitter. Calibration is performed by adjusting the number of basic delay units constituting the variable delay circuit so that the rising point and falling point of the clock signal DCLK are in the center of the corresponding window, and then the jitter test circuit is set to pass / fail judgment mode. Alternatively, the jitter measurement mode is set, the comparison clock signal DCLK and the window signal WS are compared, and the rising point and the falling point of the comparison clock signal DCLK are in the corresponding window positions or outside the window. The jitter test circuit of the present invention. By using the semiconductor device equipped with this jitter test circuit and the test method using the jitter test circuit of the present invention, the amount of jitter can be accurately measured without being affected by manufacturing factors and environmental conditions as in the second conventional example. There is an effect that can be done.
[0120]
In addition, since the jitter test circuit of the present invention is constituted by a digital circuit, it is easier to design than the second conventional example having an analog circuit portion, and does not require special noise countermeasures, so that it can be realized with a small occupied area. There is an advantage that you can.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a semiconductor device equipped with a jitter test circuit of the present invention.
FIG. 2 is a block diagram of a first embodiment of a jitter test circuit of the present invention.
FIGS. 3A, 3B, and 3C are circuit diagrams of a window signal generation circuit. FIG.
FIG. 4 is a circuit diagram of a comparison circuit.
FIG. 5 is an operation timing chart of the jitter test circuit.
6A, 6B, and 6C are circuit diagrams of a window signal generation circuit.
FIG. 7 is a circuit diagram of a comparison circuit.
FIG. 8 is an operation timing chart of the jitter test circuit.
FIG. 9 is a flowchart of a pass / fail judgment test.
FIG. 10 is a detailed flowchart of the calibration phase.
FIGS. 11A, 11B, and 11C are timing diagrams showing the operation of the jitter test circuit in the calibration phase.
FIG. 12 is a detailed flowchart of the pass / fail judgment phase.
FIGS. 13A and 13B are timing charts showing the operation of the jitter test circuit in the pass / fail judgment phase.
FIG. 14 is a circuit diagram of a configuration example of a variable delay circuit.
FIG. 15 is a block diagram of a second embodiment of a jitter test circuit according to the present invention;
FIG. 16 is a diagram illustrating an example of encoding by an encoding circuit.
FIG. 17 is a flowchart of a jitter measurement test.
FIG. 18 is a detailed flowchart of the jitter measurement phase.
FIGS. 19A, 19B, and 19C are timing charts showing the operation of the jitter test circuit in the jitter measurement phase.
FIG. 20 is a block diagram of a third embodiment of a jitter test circuit according to the present invention.
FIG. 21 is an operation flowchart of the jitter test circuit according to the third embodiment;
FIG. 22 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 23 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 24 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 25 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 26 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 27 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 28 is a diagram schematically showing another embodiment of a semiconductor device equipped with the jitter test circuit of the present invention.
FIG. 29 is a block diagram of a jitter test circuit of a first conventional example.
FIG. 30 is a block diagram of a jitter test circuit of a second conventional example.
[Explanation of symbols]
1,1a, 1b, 1c Jitter test circuit
2 PLL circuit
11, 11a, 11b, 11c, 11d, 11e, 11f Window signal generation circuit
12 Test control circuit
13, 13a, 13b comparison circuit
16 Coding circuit
17 Same sign continuous data detection circuit
200, 201, 202, 203, 204, 205, 206, 207 Semiconductor device
CLK clock signal
CMD command
CSS Same sign continuous data detection signal
DCLK Comparison clock signal
DINF delay control information
JDG judgment result signal
JINF encoding jitter information
NG Pass / fail judgment signal
WS window signal

Claims (28)

A window signal generation circuit for generating a window signal having a window defined by the second hour ahead edges from the edge of the first time delay edges and the comparison clock from the comparison clock edge,
A jitter test circuit comprising: a comparison circuit that compares the window signal with an edge of the comparison clock signal and outputs a comparison result.   2. The jitter test circuit according to claim 1, wherein the comparison circuit outputs a defect determination signal as the comparison result when an edge of the input signal deviates from the window. The jitter test circuit according to claim 1, wherein the window signal generation circuit receives a clock and outputs the clock as the comparison clock. 2. The jitter test circuit according to claim 1, wherein the window signal generation circuit receives a clock and generates and outputs the comparison clock whose phase is delayed by a third time from the clock. The window signal generation circuit includes an exclusive OR of a first delay clock whose phase is delayed by a fourth time from the comparison clock and a second delay clock whose phase is delayed by a fifth time from the first delay clock, or 5. The jitter test circuit according to claim 3, wherein the window signal is generated by negation of exclusive OR. The window signal generation circuit includes a second delay circuit that delays the phase of the received signal for the fourth time period, a third delay circuit that delays the phase of the received signal for the fifth time period, and the exclusive logic of each of the received signals. 6. The jitter test circuit according to claim 5, further comprising an EX-OR gate that outputs a sum. The jitter test circuit according to claim 6, wherein the window signal generation circuit further includes a first delay circuit that delays a phase of the received signal for the third time period. The second delay circuit receives the clock and generates and outputs the first delay clock, and the third delay circuit and the EX-OR gate receive the first delay clock in common. The jitter test circuit according to claim 6. The first delay circuit and the second delay circuit commonly receive the clock, the second delay circuit generates and outputs the first delay clock based on the clock, and the third delay circuit and the EX 8. The jitter test circuit according to claim 7, wherein the -OR gate commonly receives the first delay clock output from the second delay circuit. The jitter test circuit according to claim 7, wherein the first delay circuit, the third delay circuit, and the EX-OR gate receive the clock in common. 8. The jitter test circuit according to claim 7, wherein each of the first to third delay circuits is formed by connecting a plurality of one basic delay unit in which two inverters are connected in series. The number of basic delay units of each of the first to third delay circuits is controlled by delay control information, and each of the first to third delay circuits receives the delay control information. Item 12. The jitter test circuit according to Item 11. In response to an external command, the first to third delay circuits output delay control information for controlling the phase delay amount of each of the first to third delay circuits to each of the first to third delay circuits, and the comparison circuit. A test control circuit that receives the defect determination signal from the signal and determines whether the clock state is good or bad;
The jitter test circuit according to claim 7, further comprising: The comparison circuit includes: a first flip-flop that receives the comparison clock and the window signal; a second flip-flop that receives the window signal and an inversion of the comparison clock; the first flip-flop; And a logic gate that receives an output signal from the second flip-flop and outputs a failure determination signal indicating whether or not jitter exceeding a jitter standard value is generated in the clock. The jitter test circuit according to 1. The test control circuit outputs the delay control information to the first to third delay circuits to control a phase delay amount of the first to third delay circuits, the command, and the defect The jitter test circuit according to claim 13, further comprising: a control unit that controls an operation of the arithmetic unit based on the determination signal. The test control circuit is a jitter test circuit that receives the defect determination signal and further calculates and outputs a jitter value generated in the clock based on the received defect determination signal. 14. The jitter test circuit according to claim 13, further comprising an encoding circuit that receives and encodes the jitter value output from the control circuit and outputs the encoded jitter value to the outside. Each of the first to third delay circuits includes a plurality of basic delay units each having two inverters connected in series, and the encoding circuit receives the jitter received from the test control circuit. 17. The jitter test circuit according to claim 16, wherein the value is encoded into a binary number based on the number of basic delay units and output. The data signal is checked when the sign of the data signal is inspected at a predetermined timing based on the clock, and in the inspection at each predetermined timing, it is confirmed that the sign of the data signal is the same sign a plurality of times. 4. The apparatus according to claim 3, further comprising a same sign continuous data detection circuit that counts the number of consecutive times of the same code and outputs a same sign continuous data detection signal when the counted value is equal to or greater than a reference value. 18. The jitter test circuit according to any one of items 17 to 17. The same sign continuous data detection circuit receives a value counted by the same sign continuous data counter that counts the number of times the data signal has the same sign, and compares it with the reference value. 19. The same sign continuous data determination unit that outputs the same sign continuous data detection signal when a value counted by the same sign continuous data counter becomes equal to or greater than the reference value. The jitter test circuit described in 1. 2. The jitter test circuit according to claim 1, wherein the window signal is defined by an edge delayed by a first time from an edge of the comparison clock and an edge advanced by a second time from the edge of the comparison clock. . For a clock having one period and a comparison clock having a phase difference between the first time, a first delay clock whose phase is delayed for a second time shorter than the period by a jitter standard value, and for the comparison clock Generating a window signal consisting of exclusive OR or negation of exclusive OR with a third time longer than the period by a jitter standard value and a second delayed clock whose phase is delayed;
Based on the positional relationship between the edge of the comparison clock and the edges located at both ends of a portion having a time width corresponding to the difference between the third time and the second time in the window signal, Evaluating the generated jitter; and
A jitter test method comprising: The step of generating the window signal comprises:
An exclusive OR or an exclusive OR of a clock obtained by delaying the phase of the comparison clock by a time longer than the sum of the second time and the time width and a clock obtained by delaying the phase of the clock by the time width A first step of generating a first temporary window signal consisting of negation;
The temporary window signal until a time when an edge located at an earlier time of edges located at both ends of the portion having the time width in the first temporary window signal coincides with one edge of the comparison clock. A second step of generating a second temporary window signal in which the phase of
A phase whose phase is advanced to a time point where an edge located at a later time point coincides with one edge of the comparison clock among edges located at both ends of the portion having the time width in the second temporary window signal. A third step of generating a temporary window signal;
The window signal is delayed by delaying the phase of the comparison clock for a time that is smaller than the phase difference between the comparison clock and the second temporary window signal and greater than the phase difference between the comparison clock and the third temporary window signal. A fourth step of generating,
The jitter test method according to claim 21, further comprising: The step of evaluating jitter generated in the clock comprises the steps of:
A fifth step of determining whether an edge of the comparison clock is located between edges at both ends of the portion having the time width in the window signal;
When the edge of the comparison clock is located between the edges at both ends of the portion having the time width in the window signal, it is determined that the state of the clock is good, and the edge of the comparison clock is And a sixth step of determining that the state of the clock is defective when it is not between edges at both ends of the portion having the time width in the window signal. The described jitter test method. In the sixth step, the state of the clock is good when the edge of the clock for comparison occurs a plurality of times when the edge of the window signal is located between the edges at both ends of the portion having the time width. If the edge of the comparison clock is not between the edges at both ends of the portion having the time width in the window signal, the state of the clock is determined to be defective. The jitter test method according to claim 23, wherein the determination is performed. The step of evaluating jitter generated in the clock comprises the steps of:
When the edge of the comparison clock is located between the edges at both ends of the portion having the time width in the window signal, one edge of the comparison clock coincides with one edge of the window signal A seventh step of reducing the time span until
An eighth step of calculating a jitter value generated in the clock based on the decrease in the time width;
The jitter test method according to claim 21, further comprising: 26. The jitter test method according to claim 25, further comprising a ninth step of encoding and outputting the jitter value. The jitter test method of claim 21, wherein the first time has a phase delay of zero. The jitter test method according to claim 21, wherein a value half the difference between the third time and the second time corresponds to the first time.

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