JP3913300B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which adverse effects due to pattern shifts associated with epitaxial layer formation are eliminated.
[0002]
[Prior art]
In a bipolar type semiconductor integrated circuit, an N + type buried layer is formed on the surface of a P type semiconductor substrate, an N type epitaxial layer is formed on the substrate, and the epitaxial layer is separated to form an island region, Each circuit element is formed in each of the island regions.
By the way, it is known that when an epitaxial layer is formed by an epitaxial growth method, a pattern shift occurs depending on the plane orientation of the substrate as described in, for example, Japanese Patent Laid-Open No. 04-307729.
[0003]
Referring to FIG. 4A, when antimony (Sb) is diffused on the surface of substrate 1 to form buried layer 2 and epitaxial layer 3 is grown thereon, step 4 of buried layer 2 on the surface of substrate 1 is formed. The pattern is shifted by a distance of X in the drawing between the step 5 of the buried layer 2 on the surface of the epitaxial layer 3. Usually, an alignment mark is formed in the blank portion of the chip simultaneously with the formation of the buried layer 2, and the next diffusion process is performed with reference to the mark. Depending on the amount of deviation, as shown in FIG. 4B, the element isolation diffusion regions 6 and 7 may be displaced to complete the element isolation, leading to a situation where the breakdown voltage is poor.
[0004]
The above pattern shift occurs when a wafer 10 offset with respect to the direction of the crystal axis [100] is used as shown in FIG. The offset direction 11 is inclined 3 to 5 degrees with respect to the crystal axis [100]. This is because the crystal of the epitaxial layer 3 grows vertically along the crystal axis exposed on the surface of the substrate 1. Accordingly, if the offset direction 11 is set to zero, the pattern shift does not occur, but inconveniences such as the step 5 on the surface of the epitaxial layer 3 not becoming clear and the epitaxial growth temperature being restricted occur.
[0005]
[Problems to be solved by the invention]
As described above, when the wafer 10 has the offset direction 11, the pattern shift amount increases, and in some cases, there is a disadvantage that the breakdown voltage is deteriorated or defective. Although there is a method of controlling the shift amount by controlling the epitaxial growth temperature with high accuracy, there are drawbacks in that process management becomes strict and restrictions on the apparatus arise. Although it is possible to provide a pattern with a margin, there is a drawback that the chip size is increased. It is also conceivable to perform a design that cancels the pattern shift in advance on the exposure apparatus or pattern design, but it is impossible to cancel it completely.
[0006]
[Means for Solving the Problems]
The present invention has been made in view of such a conventional problem. By forming the alignment mark formed simultaneously with the formation of the buried layer by a straight line inclined by about 45 ° with respect to the [001] axis, A semiconductor integrated circuit capable of accurate alignment even when a pattern shift occurs is provided.
[0007]
According to the present invention, the pattern shift amount is extremely small when the pattern is inclined by about 45 degrees with respect to the pattern having a horizontal and vertical shape on the [001] axis. Therefore, by performing alignment using an alignment film with a small amount of deviation, an integrated circuit free from defective breakdown voltage can be obtained.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view showing a peripheral portion of a chip of a semiconductor integrated circuit according to the present invention and showing a region where an alignment mark is formed for each process.
As shown in FIG. 5, the surface of the semiconductor wafer 10 is offset by 3 to 5 degrees with respect to the [100] axis, and an orientation flat (hereinafter referred to as orientation flat) 12 is provided in the [010] axis direction. The semiconductor chip 13 is drawn with a rectangular shape composed of straight lines in the vertical and horizontal directions with respect to the orientation flat 12, and the N + buried layer 2 drawn in the semiconductor chip 13 is also a straight line in the vertical and horizontal directions with respect to the orientation flat 12. It is drawn in a rectangular shape consisting of The alignment marks for each process are arranged in the margin of the periphery of the semiconductor chip 13.
[0009]
Referring to FIG. 1, one alignment mark 14 is added for each diffusion process, and a photoresist for performing a diffusion process immediately after the outer pattern 15 formed on the surface of the chip 13 in the previous process. The photomask is aligned by adjusting the inner pattern 16 to be positioned at the center of the outer pattern 15 in the process.
When the process is followed in order, first, the N + buried layer 2 is formed on the chip surface, and at the same time, the outer pattern 15a of the alignment mark 14 and the outer pattern 15b are formed next thereto, and the P + separation region 6 is formed in the outer pattern 15a. The alignment is performed so that the inner pattern 16a is at the center. When the epitaxial layer 3 is grown after the P + isolation region 6 is formed, the outer pattern 15b appears as it is on the surface of the epitaxial layer 3. In the next diffusion step, for example, when the P + diffusion region 7 is formed, alignment is performed by an MPA (mirror projection aligner) device so that the inner pattern 16b of the P + diffusion region 7 is positioned at the center with respect to the outer pattern 15b. At the same time, an outer pattern 15c is formed adjacently. Thereafter, the alignment mark 14 is formed for each process in the same manner.
[0010]
A feature of the present invention lies in that the outer pattern 15b serving as an alignment mark for forming the N + buried layer 2 is inclined by about 45 degrees with respect to the [010] axis or the [001] axis. That is, both the outer pattern 15b and the inner pattern 16b have a rhombus shape. FIG. 2 shows a conventional alignment pattern, in which the alignment patterns 15b and 16b of the buried layer 2 are formed as square patterns perpendicular to the [010] axis direction or the [001] direction.
[0011]
With reference to FIG. 3, as a method of measuring the pattern shift amount of the outer pattern 15b, the formation position of the upper separation region 7 is intentionally in the [010] direction with respect to the pattern of the lower separation region 6. A pattern shifted in stages from 10% to + 10% was prepared, and the isolation breakdown voltage of the isolation regions 6 and 7 formed by the pattern was measured. The offset amount of the P-type substrate 1 is 4 degrees. After the buried layer 2, the isolation region 6 and the alignment mark 14 are formed on the surface of the P-type substrate 1, growth is about 8 μm at a growth temperature of 1100 ° C. using silane (SiHCl 3). I let you. In the alignment method, as shown in FIG. 1, the inner pattern 16b is matched with the center of the outer pattern 15b.
[0012]
As is apparent from FIG. 3, it can be seen that the peak of the separation breakdown voltage is shifted to the minus side in the apparatus in which the alignment patterns 15b and 16b for the buried layer 2 are processed into the conventional square shape. This shift amount is the pattern shift amount, and specifically, it can be determined that the shift is about 5 μ in the [010] direction.
On the other hand, when the alignment is performed using the rhombus-shaped alignment pattern 14 of the present invention, the peak of the isolation breakdown voltage is located at the center, whereby the pattern position on the surface of the substrate 1 and the surface of the epitaxial layer 3 are obtained. It can be determined that there is almost no deviation from the pattern position at.
[0013]
Therefore, according to the present invention, it is possible to accurately perform alignment between the surface of the substrate 1 and the surface of the epitaxial layer 3 only by changing the shape of the alignment mark 14 and to prevent an accident such as a poor breakdown voltage. be able to. Further, unnecessary work conditions are not added to the exposure process and pattern design. Further, since there is no “sag” of the step 5 appearing on the surface of the epitaxial layer 3 and the shape becomes clear, the work is easy in the alignment step.
[0014]
【The invention's effect】
As described above, according to the present invention, it is possible to perform accurate alignment only by devising the shape of the alignment mark, and this has the advantage of preventing the occurrence of defects such as defective breakdown voltage.
In addition, there is an advantage that an extra burden is not applied to the exposure process and pattern design.
[Brief description of the drawings]
FIG. 1 is a plan view for explaining a semiconductor integrated circuit device of the present invention.
FIG. 2 is a plan view showing a conventional alignment pattern.
FIG. 3 is a cross-sectional view for explaining the present invention.
FIG. 4 is a cross-sectional view for explaining a conventional example.
FIG. 5 is a perspective view for explaining a conventional example.

Claims (3)

Forming a reverse-conductivity type high-concentration buried layer and an alignment mark for aligning the pattern of the buried layer on the surface of the one-conductivity-type single crystal semiconductor substrate whose wafer surface is offset with respect to the plane orientation 100; A semiconductor integrated circuit device having a reverse conductivity type epitaxial layer formed on a substrate,
The pattern of the buried layer is configured to be substantially parallel to the 001 axis, and the alignment mark of the buried layer is substantially 45 degrees or near the 001 axis . A semiconductor integrated circuit comprising such a pattern.   2. The semiconductor integrated circuit according to claim 1, wherein the alignment mark of the diffusion region other than the buried layer is formed in a pattern that is substantially parallel to the 001 axis.   2. The semiconductor integrated circuit according to claim 1, wherein the alignment mark is arranged in a peripheral area free area of the semiconductor chip.