JP3910889B2 - Semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring layout for weakening an electric field between wirings to which a high voltage is applied, and is particularly applied to a bit line of a nonvolatile semiconductor memory.
[0002]
[Prior art]
First, the prior art of the present invention will be described by taking a NAND flash memory as a kind of nonvolatile semiconductor memory as an example.
[0003]
FIG. 9 shows an example of a cell array portion of the NAND flash memory. In this example, only one NAND block (erase unit) is shown for simplicity of explanation.
[0004]
The NAND flash memory is a kind of electrically rewritable nonvolatile semiconductor memory. The NAND block represents an erase unit, and the data in the memory cells in the NAND block are erased simultaneously. The NAND block has a plurality of NAND cell units 1, and the plurality of NAND cell units 1 are arranged, for example, in one cell P well region CPWELL.
[0005]
The NAND cell unit includes a NAND string composed of a plurality of memory cells 2 connected in series, and select gate transistors 3 respectively connected to both ends of the NAND string. The select gate transistor 3 connected to one end of the NAND string is connected to the common source line CELSRC, and the select gate transistor 3 connected to the other end of the NAND string is bit lines BL1e,... BLne; • Connected to BLno.
[0006]
Word lines WL0, WL1,... WL15 are connected to the memory cell 2 in the NAND cell unit 1 and function as control gate electrodes of the memory cell 2. The select gate lines SGS and SGD are connected to the select gate transistor 3 in the NAND cell unit 1 and function as the gate electrode of the select gate transistor 3.
[0007]
In this example, a cell array in which two bit lines BLie, BLio (i = 1, 2,... N) are connected to one sense amplifier (S / A) 4 via a selection circuit 5A. The structure is adopted. Further, the two bit lines BLie and BLio are connected to the shield power supply line BLSHIELD via the selection circuit 5B. According to this structure, a so-called shield bit line reading method can be applied at the time of reading.
[0008]
That is, when the control signal BLSe is “H” and the control signal BLSo is “L”, the N-channel MOS transistor 6A is turned on, so that the even-numbered bit line BLie is electrically connected to the sense amplifier 4. At this time, since the control signal BIASe is “L” and the control signal BIASo is “H”, the N-channel MOS transistor 7B is in an on state, and the shield potential VSHIELD is applied to the odd-numbered bit line BLio. (For example, 0V) is supplied.
[0009]
When the control signal BLSe is “L” and the control signal BLSo is “H”, the N-channel MOS transistor 7A is turned on, so that the odd-numbered bit line BLio is electrically connected to the sense amplifier 4. At this time, since the control signal BIASe is “H” and the control signal BIASo is “L”, the N-channel MOS transistor 6B is in an on state, and the shield potential VSHIELD is applied to the even-numbered bit line BLie. (For example, 0V) is supplied.
[0010]
For even and odd numbers, the bit line order when starting from 0 is assumed, starting with the leftmost bit line.
[0011]
Here, the N-channel MOS transistors 6A, 6B, 7A, and 7B in the selection circuits 5A and 5B have all the bit lines BL1e,..., BLne, BL1o,. Therefore, it is composed of a high voltage MOS transistor.
[0012]
In the NAND flash memory, charge injection / discharge by the FN tunnel current is executed with respect to the floating gate electrode in the write operation and the erase operation.
[0013]
At the time of writing, for example, 20 V is applied to the selected word line WLj and 0 V is applied to the cell P well region (memory cell channel) CPWELL. At the time of erasing, for example, the word lines WL0 and WL1 in the selected NAND block ,..., WL15 is supplied with 0V, and the cell P well region (memory cell channel) CPWELL is supplied with 20V.
[0014]
At the time of erasing, in fact, all the bit lines BL1e,... BLne; BL1o,.
[0015]
However, when 20V is applied to the cell P well region CPWELL, a forward bias diode (cell P well region) is formed between the cell P well region CPWELL and the bit lines BL1e,... BLne; + N type diffusion layer) is connected. As a result, the bit lines BL1e,... BLne; BL1o,... BLno are also charged to about 20V.
[0016]
As described above, in the write operation or the erase operation, the selected word line WLj or all the bit lines BL1e,... BLne; BL1o,. Therefore, when the potential difference between these wirings and other wirings becomes large, dielectric breakdown occurs between the wirings, resulting in a problem of wiring short.
[0017]
In particular, in recent years, miniaturization of cell arrays has progressed, and design rules between wirings have become very narrow. Therefore, there is a high possibility that a wiring short-circuit due to a high electric field occurs in the cell array portion and the vicinity thereof, and this problem cannot be avoided in ensuring reliability.
[0018]
Hereinafter, this problem will be described in detail by taking a bit line of a nonvolatile semiconductor memory as an example.
[0019]
FIG. 10 shows a wiring layout of a portion indicated by a region B in FIG. FIG. 11 is a circuit diagram in which the layout of FIG. 10 is replaced with an image as it is.
The bit lines BL1e, BL1o, BL2e, and BL2o are laid out with a minimum width and a minimum space as the metal wiring M1 in the memory chip.
[0020]
Here, the minimum width is a minimum width determined by a lithography processing technique, and the minimum space is affected by the lithography processing technique, but in principle, a voltage (potential difference) V1 is generated between the wirings. Sometimes it is the smallest space S1 in which a wiring short circuit due to dielectric breakdown does not occur.
[0021]
Bit lines BL1e and BL2e are connected to an N-type drain diffusion layer of N-channel MOS transistor 6B via a V1 contact plug, a metal wiring M0, and a CS contact plug, respectively. The bit lines BL1o and BL2o are connected to the N-type drain diffusion layer of the N-channel MOS transistor 7B via the V1 contact plug, the metal wiring M0, and the CS contact plug, respectively.
[0022]
The shield power supply line BLSHIELD is connected to the N-type source diffusion layers of the N-channel MOS transistors 6B and 7B via the V1 contact plug, the metal wiring M0, and the CS contact plug.
[0023]
The metal wiring M0 is a lowermost metal wiring that is directly connected to a silicon substrate (N-type diffusion layer or the like) Si using a CS contact plug without passing through another metal wiring. The wiring M1 is a metal wiring that is one layer above the metal wiring M0.
[0024]
The gate electrodes of the N channel MOS transistors 6B and 7B are made of, for example, a conductive polysilicon film containing impurities.
[0025]
In the wiring layout of this example, since the bit lines BL1e, BL1o, BL2e, and BL2o are laid out with the minimum width and the minimum space, the bit lines BL1e, BL1o, BL2e, and BL2o are formed in the contact portion (above the V1 contact plug). The fringe is not attached. The size of the V1 contact plug is larger than the width of the bit lines BL1e, BL1o, BL2e, BL2o.
[0026]
Therefore, the space between the bit lines BL1e, BL1o, BL2e, BL2o and the V1 contact plug is further narrower than the minimum space where no dielectric breakdown occurs between the wirings.
[0027]
Specifically, in the example of FIGS. 10 and 11, in the region X1, the space between the bit line BL1o and the V1 contact plug is narrower than the minimum space. In the region X2, the space between the shield power supply line BLSHIELD and the V1 contact plug is narrower than the minimum space.
[0028]
As a result, dielectric breakdown due to electric field concentration occurs in the narrowed portion, and the reliability of the nonvolatile semiconductor memory cannot be ensured.
[0029]
In the wiring layout of this example, the bit lines BL1e, BL1o, BL2e, BL2o are laid out with the minimum width and the minimum space, and the space between the shield power supply line BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o. Is also set to the minimum space.
[0030]
However, this minimum space is determined based on the voltage V1 applied between the bit lines BL1e, BL1o, BL2e, and BL2o. That is, a voltage higher than the voltage V1 may be applied between the shield power supply line BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o.
[0031]
In this case, a wiring short circuit occurs due to electric field concentration between the shield power supply line BLSHIELD and the bit lines BL1e, BL1o, BL2e, and BL2o, and the reliability of the nonvolatile semiconductor memory cannot be ensured.
[0032]
FIG. 12 shows a signal waveform diagram at the time of erasing.
From time t1 to time t3, 20V is applied to the cell P well region CPWELL as an erase voltage.
[0033]
At this time, the bit lines BL1e, BL1o, BL2e, and BL2o are charged to about 20V, specifically, 20V-Vf (Vf is a forward bias voltage between the cell P well region and the N-type diffusion layer). . On the other hand, the shield power supply line BLSHIELD is charged to Vcc (for example, about 3 V) from time t1 to time t3.
[0034]
Therefore, at the time of erasing, for example, a potential difference of about 20 V-Vcc is generated between the bit line BL1o and the shield power supply line BLSHIELD in FIG.
[0035]
In particular, in the regions X1 and X2, the space between the bit line BL1o and the shield power supply line BLSHIELD is narrower than the minimum space. In consideration of misalignment of contact holes and wirings during lithography, and variations in processing shapes, the space between the bit line BL1o and the shield power supply line BLSHIELD cannot be denied.
[0036]
Therefore, there is a great possibility that a wiring short circuit will occur due to electric field concentration between the bit lines BL1e, BL1o, BL2e, BL2o and the shield power supply line BLSHIELD.
[0037]
When a wiring short occurs, for example, in the erase operation, charges leak from the cell P well region to the bit line BL1o and further to the shield power supply line BLSHIELD, and a sufficiently large erase voltage is applied to the cell P well. It cannot be applied to the region.
[0038]
As a result, an erasing operation failure occurs, which causes a decrease in the reliability of the nonvolatile semiconductor memory.
[0039]
[Problems to be solved by the invention]
Thus, conventionally, there has been a problem that if the design rule becomes very small with the miniaturization of elements, there is a high possibility that a short circuit will occur between wirings to which a high voltage is applied.
[0040]
The present invention has been made to solve such a problem, and the object thereof is to propose a wiring layout for weakening an electric field between wirings to which a high voltage is applied. The purpose is to improve reliability.
[0041]
[Means for Solving the Problems]
  The semiconductor memory of the present invention includes first and second bit lines extending in a first direction, a conductive line extending in the first direction, a first transistor connected between the first bit line and the conductive line, A second transistor connected between the two bit lines and the conductive line, wherein the first and second transistors are arranged side by side in the first direction, and the first bit line and the conductive line are in the first direction. In the second direction orthogonal to the first region, and the interval between the first bit line and the conductive line in the region is wider than the interval between the first and second bit lines.
[0064]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor device of the present invention will be described in detail with reference to the drawings.
[0065]
1. concept
(1) First concept
FIG. 1 is a diagram showing a first concept of the present invention.
The first and second wirings are formed in the same wiring layer, and a potential difference V1 is applied between them at the maximum. The space S1 of the first and second wirings is set to a value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V1 is applied at least between the first and second wirings.
[0066]
This value may be a minimum value at which no wiring short-circuit due to dielectric breakdown occurs when a potential difference V1 is applied between the first and second wirings, or may be limited by a processing technique using lithography.
[0067]
Here, this minimum value is assumed to be equal to the minimum processing dimension by lithography or the design rule (value less than 0.12 μm). That is, the space S1 is defined as the minimum value at which no wiring short-circuit due to dielectric breakdown occurs when the potential difference V1 is applied between the first and second wirings.
[0068]
On the other hand, the third and fourth wirings are formed in the same wiring layer, and a maximum potential difference V2 (> V1) is applied between them. The third and fourth wirings may be formed in the same wiring layer as the first and second wirings, or may be formed in different wiring layers.
[0069]
In this case, the space S2 of the third and fourth wirings is larger than the space S1, more specifically, when a potential difference V2 is applied between at least the third and fourth wirings, a wiring short circuit due to dielectric breakdown occurs. Set to a value that does not occur. Specifically, the space S <b> 2 is set to a minimum value or a value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V <b> 2 is applied between the third and fourth wirings.
[0070]
(2) Second concept
FIG. 2 is a diagram showing a second concept of the present invention.
The first and second wirings are formed in the same wiring layer, and a potential difference V1 is applied between them at the maximum. The space for the first and second wirings is set to a design rule (for example, a value less than 0.12 μm) or a minimum processing dimension by lithography.
[0071]
In the second concept, it is assumed that the size of the contact plug is larger than the width of the second wiring. In this case, the space Sa between the first wiring and the contact plug is narrower than the space (design rule or minimum processing dimension) between the first wiring and the second wiring.
[0072]
In the second concept, the space Sa between the first wiring and the contact plug is set to a value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V1 is applied between at least the first and second wirings. The Specifically, the space Sa is set to a minimum value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V1 is applied between the first and second wirings.
[0073]
On the other hand, the third and fourth wirings are formed in the same wiring layer, and a maximum potential difference V2 (> V1) is applied between them. The third and fourth wirings may be formed in the same wiring layer as the first and second wirings, or may be formed in different wiring layers.
[0074]
In this case, the space Sb between the third wiring and the contact plug has a larger value than the space Sa, that is, when a potential difference V2 is applied between at least the third and fourth wirings, a wiring short circuit due to dielectric breakdown occurs. Set to a value that does not occur. Specifically, the space Sb is set to a minimum value or a value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V2 is applied between the third and fourth wirings.
[0075]
(3) Third concept
FIG. 3 is a diagram showing a third concept of the present invention.
The first and second wirings are formed in the same wiring layer, and a potential difference V1 is applied between them at the maximum. The space S1 of the first and second wirings is set to a value that does not cause a wiring short circuit due to dielectric breakdown when a potential difference V1 is applied at least between the first and second wirings. This value is for example equal to the minimum processing dimension by lithography or a design rule (value less than 0.12 μm).
[0076]
On the other hand, the third wiring is formed in the same wiring layer as the first and second wirings, and a potential difference V2 (> V1) is applied between the first and third wirings at the maximum. In this case, the space S2 of the first and third wirings is larger than the space S1, more specifically, when a potential difference V2 is applied between at least the first and third wirings, a wiring short circuit due to dielectric breakdown occurs. It is set to a minimum value that does not occur or a value greater than that.
[0077]
The second wiring and the third wiring are connected to each other by a high voltage MOS transistor.
[0078]
(4) Numerical examples
The first concept relates to a layout method for determining the space S2 between the third and fourth wirings when the space S1 between the first and second wirings is determined. The third concept relates to a layout method for determining the space S2 between the first and third wirings when the space S1 between the first and second wirings is determined.
[0079]
In the first and third concepts, a relationship of E (electric field) = V1 / S1 = V2 / S2 is established between the space S1 and the space S2.
[0080]
The second concept relates to a layout method for determining the space Sb between the third wiring and the contact plug when the space Sa between the first wiring and the contact plug is determined.
[0081]
In the second concept, a relationship of E (electric field) = V1 / Sa = V2 / Sb is established between the space Sa and the space Sb.
[0082]
Based on this relationship, the values of S1, S2, Sa, and Sb can be simulated.
[0083]
For example, when V1 is fixed to 3.6V and V2 is fixed to 20V, when S1 is 0.1 μm, S2 is 0.56 μm. When S1 is 0.09 μm, S2 is 0.50 μm, when S1 is 0.05 μm, S2 is 0.28 μm, and when S1 is 0.03 μm, S2 is 0.00. When S1 is 0.025 μm, S2 is 0.14 μm.
[0084]
In addition, these numerical values S1, S2, Sa, and Sb actually mean a wiring interval after wiring processing. On the other hand, uncertain elements such as mask misalignment are mixed during wiring processing. That is, there is some space between the wiring interval on the design (design) before wiring processing (size at the time of layout pattern creation) S1 ′, S2 ′, Sa ′, Sb ′ and the wiring interval after wiring processing. There is a conversion difference.
[0085]
Accordingly, the designed wiring intervals S1 ', S2', Sa ', Sb' are determined in consideration of this conversion difference.
[0086]
(5) Summary
As described above, the maximum potential difference V1 generated between the first and second wirings that becomes the narrowest spaces S1 and Sa in the chip, and the maximum potential difference generated between the third and fourth wirings or between the first and third wirings. Based on the potential difference V2, the value of the space S2 between the third and fourth wirings or the space Sb between the first and third wirings is determined.
[0087]
Thereby, the layout of the third and fourth wirings or the first and third wirings to which the high voltage V2 is applied can be easily performed, and the reliability of the high voltage operation of the semiconductor device can be improved.
[0088]
2. Embodiment
The embodiment of the present invention will be specifically described below.
[0089]
  (1)Reference example
  FIG. 4 illustrates the present invention.Reference exampleThe wiring layout concerning is shown. FIG. 5 is a circuit diagram in which the layout of FIG.
  The layout in FIG. 4 corresponds to the area B in FIG. 9, and is an improved version of the conventional layout in FIG.
[0090]
The N-channel MOS transistors 6B and 7B as selection circuits have a function of selecting a bit line to which the shield potential VSHIELD is applied, and in the erase operation, the potentials of the bit lines BL1e, BL1o, BL2e, and BL2o (about 20V) are shield power supplies. It has a function of preventing transmission to the line BLSHIELD.
[0091]
In the erase operation, it is very difficult to prevent charges from being charged from the cell P well region CPWELL to the bit lines BL1e, BL1o, BL2e, BL2o. On the other hand, in the erase operation, the shield power supply line BLSHIELD is charged to about the power supply potential Vcc (for example, 3 V).
[0092]
Therefore, in order to weaken the electric field between the bit lines BL1e, BL1o, BL2e, BL2o (including the V1 contact plug) and the shield power supply line BLSHIELD (including the V1 contact plug) formed in the same wiring layer, It is only necessary to keep a sufficient distance. Ideally, the bit lines BL1e, BL1o, BL2e, and BL2o and the shield power supply line BLSHIELD should not be adjacent to each other in the width direction of the wiring.
[0093]
Therefore, in this example, the metal wiring M0 arranged immediately below the bit lines BL1e, BL1o, BL2e, and BL2o as the metal wiring M1 and the shield power supply line BLSHIELD is utilized.
[0094]
As is apparent from FIG. 9, all the selection circuits 5B (N-channel MOS transistors 6B and 7B) on the shield power supply line BLSHIELD side are commonly connected to the shield power supply line BLSHIELD.
[0095]
Therefore, in this example, the sources of the N-channel MOS transistors 6B and 7B in the plurality of (for example, two) selection circuits 5B are commonly connected by the metal wiring M0, and the metal wiring M0 is connected to the bit lines BL1e, BL1o, Stretching to a region where BL2e and BL2o do not exist.
[0096]
In the region where the bit lines BL1e, BL1o, BL2e, and BL2o do not exist, the metal wiring M0 and the shield power supply line BLSHIELD (metal wiring M1) are connected by the V1 contact plug.
[0097]
Accordingly, the bit lines BL1e, BL1o, BL2e, and BL2o (including the V1 contact plug) and the shield power supply line BLSHIELD (including the V1 contact plug) formed in the same wiring layer are not adjacent to each other in the wiring width direction. A wiring layout can be realized.
[0098]
Therefore, the bit lines BL1e, BL1o, BL2e, BL2o and the shield power supply line BLSHIELD are the same wiring layer and do not approach more than necessary, and the reliability can be improved with respect to the high voltage operation of the semiconductor device.
[0099]
A metal wiring M0 as an intermediate layer provided to connect bit lines BL1e, BL1o, BL2e, BL2o and N channel MOS transistors 6B, 7B, shield power supply line BLSHIELD, and N channel MOS transistors 6B, 7B are connected. The metal wiring M0 as an intermediate layer provided for connection also needs to be arranged with a sufficient distance to prevent a wiring short circuit due to dielectric breakdown.
[0100]
  (2)Example
  FIG. 6 illustrates the present invention.ExampleThe wiring layout concerning is shown. FIG. 7 is a circuit diagram in which the layout of FIG.
  The layout in FIG. 6 corresponds to the area A in FIG.
[0101]
The N-channel MOS transistors 6A and 7A as selection circuits have a function of selecting a bit line connected to the sense amplifier S / A, and in the erase operation, the potentials of the bit lines BL1e, BL1o, BL2e, and BL2o (about 20V) Is transmitted to the sense amplifier S / A.
[0102]
In the erase operation, it is very difficult to prevent charges from being charged from the cell P well region CPWELL to the bit lines BL1e, BL1o, BL2e, BL2o. On the other hand, in the erase operation, the gate potentials BLSe and BLSo of the N-channel MOS transistors 6A and 7A as selection circuits are set to the power supply potential Vcc (for example, 3 V), and the bit line BL1 before branching on the sense amplifier S / A side , BL2 is about Vcc-Vt (Vt is the threshold voltage of the MOS transistor).
[0103]
Therefore, in order to weaken the electric field between the bit lines BL1e, BL1o, BL2e, BL2o (including the V1 contact plug) and the bit lines BL1, BL2 (including the V1 contact plug) formed in the same wiring layer, both Should be sufficiently separated. For this purpose, in this example, the metal lines M1 are used as the metal lines M1. The bit lines BL1e, BL1o, BL2e, BL2o and the metal lines M0 arranged immediately below the bit lines BL1, BL2 are used.
[0104]
As is clear from FIG. 9, regarding the wiring layout on the bit lines BL1 and BL2 side, unlike the wiring layout on the shield power line BLSHIELD side, the selection circuit 5A (N-channel MOS transistors 6A and 7A) is individually sensed. Must be connected to amplifier S / A. Therefore, in this example, the sources of the N-channel MOS transistors 6A and 7A in the plurality of selection circuits 5A cannot be commonly connected by the metal wiring M0.
[0105]
Therefore, in this example, for each selection circuit 5A, the metal wiring M0 connected to the N-channel MOS transistors 6A and 7A is extended to a region where the bit lines BL1e, BL1o, BL2e, and BL2o as the metal wiring M1 are sparsely arranged. , Enlarge.
[0106]
In the region where the bit lines BL1e, BL1o, BL2e, BL2o are sparse, the metal wiring M0 and the bit lines BL1, BL2 (metal wiring M1) are connected by the V1 contact plug.
[0107]
It is even better if the metal wiring M0 connected to the N-channel MOS transistors 6A and 7A is extended to a region where the bit lines BL1e, BL1o, BL2e, and BL2o as the metal wiring M1 do not exist.
[0108]
Thereby, the bit lines BL1e, BL1o, BL2e, and BL2o (including the V1 contact plug) formed in the same wiring layer and the bit lines BL1 and BL2 (including the V1 contact plug) before branching are arranged in the width direction of the wiring. The wiring layout which is not adjacent to each other can be realized.
[0109]
Even when the bit lines BL1e, BL1o, BL2e, and BL2o and the bit lines BL1 and BL2 before branching are adjacent to each other in the width direction of the wiring, as shown in the region X4 in FIGS. The space between them is sufficiently larger than the space between the bit lines BL1e, BL1o, BL2e, and BL2o.
[0110]
Therefore, the bit lines BL1e, BL1o, BL2e, and BL2o and the bit lines BL1 and BL2 before branching are in the same wiring layer and do not approach more than necessary, and the electric field between the wirings is reduced with respect to the high voltage operation of the semiconductor device. In addition, the reliability can be improved.
[0111]
Further, since the bit lines BL1e, BL1o, BL2e, BL2o and the bit lines BL1, BL2 before branching are not short-circuited due to dielectric breakdown, no high voltage is applied to the MOS transistors in the sense amplifier S / A. The gate breakdown and junction breakdown of the MOS transistor can be prevented.
[0112]
Metal line M0 as an intermediate layer provided to connect bit lines BL1e, BL1o, BL2e, BL2o and N channel MOS transistors 6A, 7A, bit lines BL1, BL2 before branching and N channel MOS transistor 6A , 7A and the metal wiring M0 as an intermediate layer provided to connect to 7A must be arranged with a sufficient distance to prevent wiring short-circuit due to dielectric breakdown.
[0113]
  (3)Dummy pattern (reference example)
  FIG. 8 illustrates the present invention.Reference exampleThe wiring layout concerning is shown.
  This wiring layout is an improvement of the wiring layout of FIG.
[0114]
In the example of FIG. 4, in order to weaken the electric field between the bit lines BL1e, BL1o, BL2e, BL2o and the shield power supply line BLSHIELD formed in the same wiring layer M1, the wiring layer M0 is used to sufficiently The layout was separated. As a result, the object of eliminating the place where the wiring interval is extremely narrow and preventing the short circuit between the wirings due to the dielectric breakdown can be achieved.
[0115]
However, in the example of FIG. 4, since the degree of pattern density in a place where the wiring width and the wiring interval are narrow becomes severe, the lithography and processing surface of the wiring layer M1 cannot be optimal.
[0116]
Therefore, in this example, a dummy pattern (dummy wiring) DUMMY is arranged in an empty area around the bit lines BL1e, BL1o, BL2e, and BL2o formed in the wiring layer M1.
[0117]
The intervals between the bit lines BL1e, BL1o, BL2e, BL2o and the dummy pattern DUMMY may be the same as or wider than the intervals between the bit lines BL1e, BL1o, BL2e, BL2o.
[0118]
As described above, if the dummy pattern DUMMY is arranged in the empty area around the bit lines BL1e, BL1o, BL2e, and BL2o, good results can be obtained with respect to the lithography and processing of the wiring layer M1.
[0119]
In the example of FIG. 8, two dummy patterns DUMMY are arranged in empty areas around the bit lines BL1e, BL1o, BL2e, and BL2o. These dummy patterns DUMMY are in a floating state and are not supplied with a potential.
[0120]
As described above, according to this example, it is possible to realize a wiring layout having excellent processing accuracy in terms of wiring processing while achieving the original purpose of relaxing the electric field generated between the wirings.
[0121]
3. Other
Although the present invention has been described mainly using a NAND flash memory as an example, the present invention can also be applied to a nonvolatile semiconductor memory other than a NAND flash memory.
[0122]
In the embodiment, the bit line to which a high voltage is applied has been described as an example. However, the present invention can also be applied to wiring other than the bit line, such as a word line or a normal wiring.
[0123]
Furthermore, the present invention can also be applied to semiconductor memories other than nonvolatile semiconductor memories and semiconductor devices such as logic LSIs.
[0124]
【The invention's effect】
  As described above, the present inventionSemiconductor memoryAccording to the new wiring layout to weaken the electric field between high voltage wiring,Semiconductor memoryWith respect to the high voltage operation, the reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first concept of the present invention.
FIG. 2 is a diagram showing a second concept of the present invention.
FIG. 3 is a diagram showing a third concept of the present invention.
FIG. 4 of the present inventionReference exampleThe top view which shows the wiring layout in connection with.
5 is a circuit diagram in which the layout of FIG. 4 is replaced with an image as it is.
FIG. 6 of the present inventionExampleThe top view which shows the wiring layout in connection with.
7 is a circuit diagram in which the layout of FIG. 6 is replaced with an image as it is.
[Fig. 8] of the present inventionReference exampleThe top view which shows the wiring layout in connection with.
FIG. 9 is a circuit diagram showing a cell array portion of a NAND flash memory.
FIG. 10 is a plan view showing a conventional wiring layout.
11 is a circuit diagram in which the layout of FIG. 10 is replaced with an image as it is.
FIG. 12 is an operation waveform diagram showing the timing of the erase operation.
[Explanation of symbols]
1: NAND cell unit,
2: Memory cell
3: Select gate transistor,
4: Sense amplifier,
5A, 5B: selection circuit,
6A, 6B, 7A, 7B: N-channel MOS transistors.

Claims (2)

First and second bit lines extending in a first direction, a conductive line extending in the first direction, a first transistor connected between the first bit line and the conductive line, and the second bit line And a second transistor connected between the conductive line, the first and second transistors are MOS transistors whose channel length direction is the first direction, and the first and second transistors Are arranged side by side in the first direction, and the first and second bit lines and the conductive line are formed in the same wiring layer, and the first bit line and the conductive line are in the first direction. And an interval between the first bit line and the conductive line in the region is wider than an interval between the first and second bit lines. Semiconductor memory.   The semiconductor memory according to claim 1, wherein the conductive line is connected to a sense amplifier.

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