JP3996070B2 - Level shifter circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a level shifter circuit for converting the voltage level of a rectangular wave signal, and more particularly to a level shifter circuit including a field effect transistor having a relatively large threshold voltage.
[0002]
[Prior art]
In a semiconductor integrated circuit or the like, a level shifter circuit that converts a voltage level of a rectangular wave signal (pulse signal) is required to use a common signal among a plurality of functional blocks having different operating voltages. Generally, the level shifter circuit converts a low voltage amplitude input signal into a high voltage amplitude output signal. A conventional level shifter circuit generally has a configuration in which an output signal having a high voltage amplitude is obtained by a differential amplification operation using two field effect transistors each receiving a normal phase signal and a reverse phase signal of an input signal at the gate as input stages. (For example, Patent Document 1).
[0003]
[Patent Document 1]
JP 2000-315943 A (FIG. 1)
[0004]
[Problems to be solved by the invention]
However, such a conventional level shifter circuit requires two systems of circuits that input the positive phase and the negative phase of the input signal, and thus causes problems such as an increase in the number of signal lines and an increase in circuit scale.
[0005]
Also, for differential amplification, the field effect transistor in the input stage must be turned on and off in a complementary manner, so that the input signal has a voltage amplitude smaller than the threshold voltage of the field effect transistor in the input stage. Can not respond. Therefore, when a level shifter circuit is configured using a field effect transistor whose threshold voltage inevitably increases, such as a thin film transistor (TFT) element used in a liquid crystal panel or the like, a low voltage amplitude is required. It becomes difficult to level-convert the input signal.
[0006]
The present invention has been made to solve such problems, and the object of the present invention is to apply a field effect transistor having a small circuit scale and a relatively large threshold voltage. The present invention relates to a configuration of a level shifter circuit capable of level-converting an input signal having a low voltage amplitude.
[0007]
[Means for Solving the Problems]
In the level shifter circuit according to the present invention, the voltage of the input node that receives the rectangular wave input signal, the output node that outputs the output signal obtained by converting the voltage amplitude of the input signal, and the voltage of the first internal node are determined from the predetermined inversion voltage. When the output signal is high and low, a signal driver for driving the output signal with one of a different high voltage and low voltage, a voltage change of the input node are transmitted to the first internal node, and the first And a voltage adjusting unit that brings the voltage of the first internal node closer to the inverted voltage with a predetermined time constant when the internal node is different from the inverted voltage.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in the following shall show the same or an equivalent part.
[0009]
[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a level shifter circuit according to the first embodiment of the present invention.
[0010]
Referring to FIG. 1, a level shifter circuit 10 according to the first embodiment of the present invention includes an input node 11 to which a rectangular wave input signal SIN is input, and a rectangular wave output signal SOUT obtained by converting the level of the input signal SIN. An output node 12 to be output, a voltage adjusting unit 20 constituting an input stage, and an inverter 40 provided as a signal driving unit are provided.
[0011]
The logic low level (hereinafter also simply referred to as “L level”) of the input signal SIN is set to the voltage VIL, and the logic high level (hereinafter also simply referred to as “H level”) is set to the voltage VIH. .
[0012]
Voltage adjusting unit 20 includes capacitors 21 and 22, P-type transistor 31, N-type transistor 32, and resistors 33 and 34. Capacitor 21 is connected between input node 11 and node 16, and capacitor 22 is connected between input node 11 and node 17. Resistor 33 is electrically connected between nodes 15 and 16, and resistor 34 is electrically connected between nodes 15 and 17.
[0013]
P-type transistor 31 and N-type transistor 32 are each diode-connected and connected in series between voltage node 13 for supplying high voltage VH and voltage node 14 for supplying low voltage VL. The drains of P-type transistor 31 and N-type transistor 32 connected to each other are electrically connected to node 15.
[0014]
Specifically, P-type transistor 31 has a source electrically connected to voltage node 13, a drain electrically connected to node 15, and a gate electrically connected to node 16. N-type transistor 32 has a source electrically connected to voltage node 14, a drain electrically connected to node 15, and a gate electrically connected to node 17.
[0015]
Inverter 40 has a CMOS inverter configuration and includes a P-type transistor 41 and an N-type transistor 42 that are turned on and off in a complementary manner in accordance with the voltage at node 15. P-type transistor 41 has a source electrically connected to voltage node 13 and a gate electrically connected to node 15. N-type transistor 42 has a source electrically connected to voltage node 14, and a gate electrically connected to node 15. The drains of P-type transistor 41 and N-type transistor 42 are electrically connected to output node 12.
[0016]
P-type transistors 31 and 41 and N-type transistors 32 and 42 are field effect transistors, but a transistor having a relatively large threshold voltage, for example, a TFT element is applied.
[0017]
As is generally known, the output voltage of the inverter 40, that is, the voltage level of the output signal SOUT depends on whether the voltage at the node 15 is higher or lower than the inverted voltage VTL expressed by the following equation (1). Inverted.
[0018]
VTL = (VH−VTN + VTP + VL) / 2 (1)
In the equation (1), VTN represents the threshold voltage of the N-type transistor 41, and VTP represents the threshold voltage of the P-type transistor. Hereinafter, in this embodiment, it is assumed that | VTN | = | VTP | = VT. Under this condition, the inversion voltage VTL is given by the following equation (2).
[0019]
VTL = (VH + VL) / 2 (2)
Therefore, when the voltage of the node 15 is VIN, the inverter 40 drives the output signal SOUT with the high voltage VH when VIN <VTL, and as a signal driver that drives the output signal SOUT with the low voltage VL when VIN> VTL. Operate. The high voltage VH and the low voltage VL are determined corresponding to the voltage amplitude required for the output signal SOUT. The voltage amplitude (VH−VL) of the output signal is larger than the voltage amplitude (VIH−VIL) of the input signal SIN.
[0020]
Next, the operation of the level shifter circuit shown in FIG. 1 will be described. For example, in the following, the input signal has a voltage amplitude of 0 to 3 (V) (that is, VIL = 0 (V), VIH = 3 (V)), and the output signal SOUT has a voltage amplitude of −2 to 10 (V). (Ie, VH = 10 (V), VL = −2 (V)).
[0021]
When the voltage at the input node 11 is constant, that is, when a DC voltage is applied, the voltage at the node 15 is set to a constant voltage depending on the characteristics of the P-type transistor 31 and the N-type transistor 32, particularly the threshold voltage. Converge. The constant voltage is designed at the same level as the inverted voltage of the inverter 40. For example, by making the characteristics and transistor sizes of the P-type transistor 31 and the N-type transistor 32 equal, the voltage adjusting unit 20 changes the node 15 to (VH + VL) / 2, that is, the inverted voltage VTL shown in the equation (2). Can be converged to. Under the above voltage condition, VTL = 4 (V).
[0022]
When a rectangular wave input signal SIN is applied to the input node 11 from this state, the voltage variation of 3 (V) generated at the time of the level transition of the input signal SIN by the capacitors 21 and 22 as differential elements is caused by capacitive coupling. It is transmitted to the nodes 15-17.
[0023]
When the input signal SIN transitions from the L level to the H level, the voltage at the node 15 rises from the inverted voltage VTL. In response to this, the passing current of the P-type transistor 31 decreases and the passing current of the N-type transistor 32 increases. That is, the resistance value of the P-type transistor 31 decreases, and the resistance value of the transistor 32 increases.
[0024]
As a result, the voltage at node 15 that depends on the resistance ratio of diode-connected P-type transistor 31 and N-type transistor 32 rises significantly from inverted voltage VTL. As a result, in the inverter 40, the P-type transistor 41 is turned off, the N-type transistor 42 is turned on, and the output signal SOUT is driven to the low voltage VL (L level).
[0025]
Conversely, when the input signal SIN transitions from the H level to the L level, the voltage at the node 15 drops from the inverted voltage VTL. In response to this, the passing current of the N-type transistor 32 decreases and the passing current of the P-type transistor 31 increases. As a result, the voltage at the node 15 drops significantly from the inverted voltage VTL. As a result, in the inverter 40, the P-type transistor 41 is turned on, the N-type transistor 42 is turned off, and the output signal SOUT is driven to the high voltage VH (H level).
[0026]
Therefore, the voltage fluctuation (3 (V)) generated at the input node 11, that is, the voltage amplitude of the input signal SIN is the threshold voltage (3.5 (V)) of the transistors 31, 32, 41 and 42 in the level shifter circuit 10. ), The output signal SOUT having a high voltage amplitude can be driven.
[0027]
Thus, even if a field effect transistor having a relatively large threshold voltage, such as a thin film transistor (TFT) element, is used, a level shifter circuit having a wide range of voltage amplitude of input voltage that can be handled can be configured. The level shifter circuit according to the above is suitable for mounting on a liquid crystal panel or the like.
[0028]
In a period in which the input signal SIN is maintained at the L level or the H level, the voltage of the node 15 that has changed once changes so as to approach the original inverted voltage VTL according to a predetermined time constant of the voltage adjustment unit 20. The time constant depends on the RC product of all resistance components and all capacitance components connected to the node 15. A preferable design method for such a time constant will be described in detail later.
[0029]
As described above, the voltage adjusting unit 20 transmits the voltage change of the input node 11 to the node 15 by capacitive coupling, and when the voltage of the node 15 is different from the inverted voltage VTL, the voltage of the node 15 is set with a predetermined time constant. It approaches the inversion voltage VTL.
[0030]
2 and 3 are operation waveform diagrams for explaining the operation of the level shifter circuit of FIG.
[0031]
First, FIG. 2 shows an operation waveform diagram when the frequency of the input signal SIN is relatively low.
[0032]
Referring to FIG. 2, when the input signal SIN transitions from the L level (VIL = 0 (V)) to the H level (VIH = 3 (V)), the voltage at the node 15 becomes capacitive coupling by the capacitors 21 and 22 and Due to the change in the on-resistance of the transistors 31 and 32, the inverted voltage VTL (4 (V)) increases significantly. In response to this, the inverter 40 drives the output signal SOUT with the low voltage VL (−2 (V)) and sets it to the L level.
[0033]
Thereafter, during a period in which the input signal SIN is maintained at the H level, the voltage of the node 15 gradually attenuates according to the time constant described above and converges to the inverted voltage VTL. However, when the voltage at the node 15 reaches the inverted voltage VTL, a through current is generated in the P-type transistor 41 and the N-type transistor 42 in the inverter 40, and the level of the output signal SOUT becomes unstable.
[0034]
Next, when the input signal SIN transitions from the H level (VIH = 3 (V)) to the L level (VIL = 0 (V)), the voltage at the node 15 is capacitively coupled by the capacitors 21 and 22 and the transistors 31 and 32. Due to the change in the ON resistance, the voltage drops greatly from the inversion voltage VTL (4 (V)). In response to this, the inverter 40 drives the output signal SOUT with the high voltage VH (10 (V)) and sets it to the H level.
[0035]
On the other hand, FIG. 3 shows an operation when the frequency of the input signal SIN is relatively high.
[0036]
Referring to FIG. 3, when the frequency of input signal SIN is high, after the voltage at node 15 changes in response to the level transition of input signal SIN, before the voltage approaches the inverted voltage VTL, the input signal A new level transition will come. Therefore, the level of the input signal SIN can be converted to the output signal SOUT without causing the voltage at the node 15 to approach the inverted voltage VTL, that is, without causing the operation of the inverter 40 to become unstable.
[0037]
As understood from the description of FIGS. 2 and 3, in the level shifter circuit according to the present invention, it is necessary to design the time constant of the voltage change of the node 15 to a preferable value according to the cycle of the input signal SIN. The method will be described below.
[0038]
First, the resistance value of all resistance components connected to the node 15 is R, the capacitance value of all capacitance components is C, and the product of both is expressed as RC. Here, the resistance component R includes the on-resistances of the transistors 31 and 32 in addition to the resistance values of the resistors 33 and 34 shown in FIG. The capacitance value C includes the capacitance values of the capacitors 21 and 22 and other parasitic capacitances.
[0039]
Here, assuming that the elapsed time from the starting point is t, starting from the timing when the node 15 is set to the high voltage VH in response to the level transition (from the L level to the H level) of the input signal SIN, the time t has elapsed. The voltage VIN (t) at the later node 15 is expressed by the following equation (3).
[0040]
VIN (t) = VH− (VH−VL) · exp (−t / RC) (3)
On the other hand, the inverted voltage VTL is expressed by the following equation (4).
[0041]
VTL = (VH + VL) / 2 (4)
Therefore, in order for the output of the subsequent inverter 40 not to be inverted during the period when the voltage at the node 15 is attenuated, it is necessary to satisfy the condition of the following equation (5).
[0042]
VIN (t) ≧ VTL
(VH−VL) · exp (−t / RC) ≧ (VH−VL) / 2
exp (−t / RC) ≧ (1/2) (5)
Here, if the input signal SIN is an AC signal having a period T, the above equation (5) needs to be established during the half period (T / 2). Thus, the following formula (6) is obtained.
[0043]
exp [−T / (2 · RC)] ≧ (1/2) (6)
Taking the logarithm of both sides, the equation (7) is obtained from [−T / (2 · RC)] ≧ −ln2.
[0044]
(T / 2) ≦ RC · (ln2)
RC ≧ (T / 2) / (ln2) (7)
Therefore, the present application can stably convert the level of the input signal by designing the RC product of all the resistance components and all the capacitance components connected to the node 15 according to the equation (7) according to the period of the input signal. A level shifter circuit according to the invention can be realized.
[0045]
Alternatively, as in the level shifter circuit 51 shown in FIG. 4, the capacitors 21 and 22 and the resistors 33 and 34 in FIG.
[0046]
Specifically, in voltage adjustment unit 20 of level shifter circuit 51, the gates of P-type transistor 31 and N-type transistor 32, that is, nodes 16 and 17, are connected to each other. Further, capacitor 23 is connected between input node 11 and nodes 16 and 17. Nodes 16 and 17 are connected to node 15 via resistor 30.
[0047]
Since the configuration of other parts of level shifter circuit 51 is the same as that of level shifter circuit 10 shown in FIG. 1, detailed description will not be repeated. Even with such a configuration, a level conversion operation similar to that of the level shifter circuit 10 according to the first embodiment can be realized.
[0048]
[Embodiment 2]
FIG. 5 is a circuit diagram showing a configuration example of the level shifter circuit according to the second embodiment.
[0049]
Referring to FIG. 5, level shifter circuit 55 according to the second embodiment has a voltage adjustment unit 20 # in place of voltage adjustment unit 20 as compared with level shifter circuit 10 (FIG. 1) according to the first embodiment. Different.
[0050]
Voltage adjusting unit 20 # is connected between capacitor 23 connected between input node 11 and node 15, resistor 35 connected between voltage node 13 and node 15, and connected between voltage node 14 and node 15. And a resistor 36.
[0051]
The resistance values of the resistors 35 and 36 are designed so that the divided voltage levels of the high voltage VH and the low voltage VL at the node 15 coincide with the inverted voltage VTL of the inverter 40. In the configuration according to the present embodiment in which the threshold voltages of P-type transistor 41 and N-type transistor 42 constituting the inverter are made equal, resistors 35 and 36 are designed to have equal resistance values.
[0052]
Capacitor 23 transmits the voltage change caused by the level transition of input signal SIN generated at input node 11 to node 15 by capacitive coupling. In response to this, the voltage at the node 15 changes from the inverted voltage VTL to the high voltage VH side or the low voltage VL side, whereby the inverter 40 changes the output signal SOUT to the low voltage VL (L level) or the high voltage VH ( To H level).
[0053]
Therefore, even if the voltage amplitude of the input signal SIN is smaller than the absolute value of the threshold voltage of the P-type transistor 41 and the N-type transistor 42 constituting the inverter 40, the output voltage of the inverter 40 is inverted and the high voltage amplitude Output signal SOUT can be driven.
[0054]
In the configuration of FIG. 5, the time constant of the voltage of the node 15 is the resistance value and capacitance of the resistors 35 and 36 and the capacitor 23 according to the cycle of the input signal SIN, as in the description in the first embodiment. What is necessary is just to determine by a value.
[0055]
However, in the level shifter circuit 55 according to the second embodiment, while the circuit configuration of the voltage adjustment unit 20 is simplified, the level adjustment circuit 55 can be reduced by the resistance values of the resistors 35 and 36, but a through current is always generated at the node 15. . In other words, level shifter circuit 10 according to the first embodiment can reduce the through current generated at node 15 by connecting transistors 31 and 32 that are diode-connected between voltage nodes 13 and 14 in series.
[0056]
Therefore, in level shifter circuit 55 according to the second embodiment, through current is also likely to be generated in inverter 40 as compared with level shifter circuit 10 according to the first embodiment. Focusing on this point, preferable operating conditions of the level shifter circuit 55 will be described below.
[0057]
FIG. 6 shows an operation waveform diagram of a general CMOS inverter for explaining desirable operation conditions of the inverter 40.
[0058]
Referring to FIG. 6, input voltage VIN shown on the horizontal axis corresponds to the voltage at node 15 in FIG. The output voltage VOUT and the output current IOUT shown on the vertical axis respectively correspond to the voltage at the output node 12 (that is, the output signal SOUT) and the through current generated at the output node 12 in FIG.
[0059]
As described above, the output voltage VOUT is set to either the high voltage VH or the low voltage VL according to the level relationship between the input voltage VIN and the inverted voltage VTL. However, when the input voltage VIN is near the inversion voltage VTL, the output voltage VOUT becomes an intermediate voltage and the inverter operation becomes unstable.
[0060]
When the absolute value of the threshold voltage of the P-type transistor 41 and the N-type transistor 42 is VT, the output current IOUT is a P-type transistor and an N-type in the range of VIN <(VL + VT) and VIN> (VH−VT). It does not occur because the transistors are complementarily turned on and off.
[0061]
However, in the range of (VL + VT) <VIN <(VH−VT), a maximum through current is generated when VIN = VTL.
[0062]
Therefore, if the voltage amplitude of the input signal SIN is ΔVi, level conversion can be executed without causing the inverter 40 to generate a through current under the conditions of the following equations (8) and (9).
[0063]
VTL−ΔVi <VL + VT (8)
VTL + ΔVi> VH−VT (9)
Substituting VTL = (VH + VL) / 2 into the equations (8) and (9), the following equation (10) is obtained.
[0064]
ΔVi> VTL−VL−VT = (VH−VL) / 2−VT (10)
On the other hand, in the conventional level shifter circuit, since the voltage amplitude of the input signal needs to be larger than the threshold voltage VT of the transistor, if the required input voltage amplitude ΔVi ′ is assumed, ΔVi ′ is expressed by the following (11). It is shown by the formula.
[0065]
ΔVi ′> VT (11)
Therefore, the expression (11)-(10), that is, ΔVi′−ΔVi is an improvement in the voltage amplitude of the input signal that can be handled by the level shifter circuit of the present invention. Therefore, in order to satisfy ΔVi−ΔV> 0, it is necessary to satisfy the following expression (12).
[0066]
ΔVi′−ΔV = 2VT− (VH−VL) / 2> 0 (12)
Therefore, the following equation (13) is obtained as a preferable operating condition of the level shifter circuit according to the second embodiment.
[0067]
VT> (VH−VL) / 4 (13)
That is, the absolute value VT of the threshold voltage of the field effect transistor constituting the inverter is a voltage difference between the high voltage VH and the low voltage VL that are the operating voltages of the inverter, that is, ¼ of the voltage amplitude of the output signal SOUT. Is larger, the effect of applying the level shifter circuit according to the second embodiment is large.
[0068]
For example, when the voltage example shown in the first embodiment is substituted, in FIG. 6, VTL = 4 (V), (VL + VT) = 1.5 (V), and (VH−VT) = 6.5. (V). Therefore, even if the voltage amplitude of the input signal is 3 (V), which is smaller than the absolute value (3.5 (V)) of the threshold voltage, level conversion can be performed without generating a through current in the inverter 40. Can be executed.
[0069]
[Embodiment 3]
FIG. 7 is a circuit diagram showing a configuration example of the level shifter circuit according to the third embodiment.
[0070]
Referring to FIG. 7, level shifter circuit 10 # according to the third embodiment corresponds to voltage nodes 13 and 14 corresponding to voltage nodes 13 and 14, respectively, as compared with level shifter circuit 10 (FIG. 1) according to the first embodiment. The difference is that a P-type transistor 61 and an N-type transistor 62 for stopping the supply of the low voltage VL are further provided.
[0071]
P-type transistor 61 receives at its gate an enable signal / EN that is activated to L level during operation of level shifter circuit 10 #, receives supply of high voltage VH at its source, and has its drain electrically connected to voltage node 13. Connected. Similarly, N-type transistor 62 receives at its gate an enable signal EN that is activated to H level during operation of level shifter circuit 10 #, receives supply of low voltage VL at its source, and has its drain at voltage node 14 And electrically connected.
[0072]
By adopting such a configuration, voltage nodes 13 and 14 are electrically disconnected from high voltage VH and low voltage VL when level shifter circuit 10 # is not operating. Current can be prevented from being generated. As a result, power consumption during the non-operation period can be reduced.
[0073]
Similar voltage supply stopping transistors 61 and 62 are also arranged in the same manner with respect to voltage nodes 13 and 14 in level shifter circuits 51 and 55 shown in FIGS. 4 and 5, respectively, to reduce power consumption. Can be achieved.
[0074]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0075]
【The invention's effect】
As described above, in the level shifter circuit of the present invention, the voltage fluctuation of the low voltage amplitude input signal is input as a change from the inverted voltage in the input voltage to the signal driver (inverter). Even if the voltage amplitude is smaller than the threshold voltage of the field effect transistor in the level shifter circuit, an output signal having a high voltage amplitude can be driven. Therefore, even if a field effect transistor having a relatively large threshold voltage, such as a thin film transistor (TFT) element, is used, a level shifter circuit having a wide range of voltage amplitude of the input voltage that can be handled can be configured.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of a level shifter circuit according to a first embodiment of the present invention.
FIG. 2 is a first operation waveform diagram for explaining the operation of the level shifter circuit of FIG. 1;
FIG. 3 is a second operation waveform diagram for explaining the operation of the level shifter circuit of FIG. 1;
FIG. 4 is a circuit diagram illustrating another configuration example of the level shifter circuit according to the first embodiment;
FIG. 5 is a circuit diagram showing a configuration example of a level shifter circuit according to a second embodiment.
FIG. 6 is a diagram for explaining desirable operating conditions of the inverter unit 40;
7 is a circuit diagram showing a configuration example of a level shifter circuit according to a third embodiment. FIG.
[Explanation of symbols]
10, 51, 55 level shifter circuit, 11 input node, 12 output node, 13, 14 voltage node, 15, 16, 17 node, 20, 20 # voltage adjustment unit, 21, 22, 23 capacitor, 30, 33, 34, 35, 36 Resistance, 31, 41, 61 P-type transistor, 32, 42, 62 N-type transistor, EN, / EN enable signal, SIN input signal, SOUT output signal, VH high voltage, VL low voltage, VT threshold Voltage (absolute value), VTL Inversion voltage (inverter).

Claims (7)

An input node for receiving a rectangular wave input signal;
An output node that outputs an output signal obtained by converting the voltage amplitude of the input signal;
A signal driver for driving the output signal with a different one of a high voltage and a low voltage, respectively, when the voltage of the first internal node is higher and lower than a predetermined inversion voltage;
The voltage change of the input node is transmitted to the first internal node, and when the first internal node is different from the inverted voltage, the voltage of the first internal node is brought close to the inverted voltage with a predetermined time constant. A voltage regulator,
The signal driver is
A source electrically connected to the first voltage node receiving the supply of the high voltage; a drain electrically connected to the output node; and a gate electrically connected to the first internal node. A first P-type transistor;
A source electrically connected to a second voltage node receiving the low voltage supply; a drain electrically connected to the output node; and a gate electrically connected to the first internal node. A first N-type transistor,
The voltage regulator is
A first capacitor connected between the input node and a second internal node;
A second capacitor connected between the input node and a third internal node;
A second having a source electrically connected to the first voltage node; a drain electrically connected to the first internal node; and a gate electrically connected to the second internal node. P-type transistors of
A second source having a source electrically connected to the second voltage node, a drain electrically connected to the first internal node, and a gate electrically connected to the third internal node; N-type transistors of
A first resistor connected between the first and second internal nodes;
A level shifter circuit including a second resistor connected between the first and third internal nodes . An input node for receiving a rectangular wave input signal;
An output node that outputs an output signal obtained by converting the voltage amplitude of the input signal;
A signal driver for driving the output signal with a different one of a high voltage and a low voltage, respectively, when the voltage of the first internal node is higher and lower than a predetermined inversion voltage;
The voltage change of the input node is transmitted to the first internal node, and when the first internal node is different from the inverted voltage, the voltage of the first internal node is brought close to the inverted voltage with a predetermined time constant. A voltage regulator,
The signal driver is
A source electrically connected to the first voltage node receiving the supply of the high voltage; a drain electrically connected to the output node; and a gate electrically connected to the first internal node. A first P-type transistor;
A source electrically connected to a second voltage node receiving the low voltage supply; a drain electrically connected to the output node; and a gate electrically connected to the first internal node. A first N-type transistor,
The voltage regulator is
A capacitor connected between the input node and a second internal node;
A second source having a source electrically connected to the first voltage node, a drain electrically connected to the first internal node, and a gate electrically connected to the second internal node; A P-type transistor;
A second source having a source electrically connected to the second voltage node, a drain electrically connected to the first internal node, and a gate electrically connected to the second internal node; An N-type transistor;
Including a resistor and connected between said first and second internal nodes, Les Berushifuta circuit. 3. The level shifter circuit according to claim 1, wherein a voltage amplitude of the input signal is smaller than an absolute value of a threshold voltage of each of the second P-type and N-type transistors. And a voltage supply stop unit that stops the supply of the high voltage to the first voltage node and the supply of the low voltage to the second voltage node when the level shifter circuit is not operating. Item 3. The level shifter circuit according to Item 1 or 2 . In the voltage adjusting unit, the time constant is changed in response to the level transition of the input signal by designing the product RC of the resistance value of all resistance components connected to the internal node and the capacitance value of all capacitance components. 3. The level shifter circuit according to claim 1, wherein the voltage of the internal node is determined so as not to reach an inverted voltage of the signal driver until the level of the input signal is inverted. If the period until the level of the input signal is inverted is (T / 2), the product RC is
The level shifter circuit according to claim 5 , wherein the level shifter circuit is designed to satisfy RC ≧ (T / 2) · (1 / ln2). 3. The level shifter circuit according to claim 1, wherein the first and second P-type transistors and the N-type transistor are formed of thin film transistors. 4.

Images