JP3969776B2 - Transmission image decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video decoding apparatus for decompressing and displaying media such as compressed moving images that operate with a signal processing of moving images, particularly a clock independent of a clock of a transmission path.
[0002]
[Prior art]
Reference: "Practical MPEG Textbook" 1995 ASCII Publishing Bureau
Conventionally, there is the aforementioned document as a document relating to compressed moving image transmission. This document describes various technologies and problems related to compressed video transmission. For example, in the case of an application for entering a public network from a LAN, it is not always possible to expect the supply of the network clock, and there are the following problems when the supply of the network clock cannot be received. It has been pointed out. In other words, in the transmission of compressed moving images in the absence of a network clock supply, if the transmission side and reception side clocks operate independently, the data processing speed differs depending on the speed difference. It has been pointed out.
[0003]
However, when the data processing speed is different as described above, the amount of use of the buffer memory for temporarily storing the received data greatly varies depending on the relationship between the processing speed on the encoder side and the decoding side. For example, if the processing of the encoder is fast, the decoding processing does not catch up and increases, and vice versa. In addition, when the buffer is empty, there is no new image to be displayed, so “display twice” is necessary. Conversely, when the buffer is full, the input new image cannot be held. ”Occurs and visual deterioration becomes conspicuous.
[0004]
To prevent this, it is necessary to use a clock synchronized between transmission and reception.
[0005]
In this regard, in the MPEG2 system, time information called a program clock reference (hereinafter referred to as “PCR”) is defined to ensure clock synchronization. The literature also describes this method. Hereinafter, this method will be described.
[0006]
The encoder transmits the PCR created from the reference clock to the decode, and in the decode, counts its own clock and compares it with the value of the sent PCR. If they match, clock synchronization is ensured. By controlling the clock frequency so that the two values coincide with each other using a PLL circuit or the like, the transmission and reception clocks can be synchronized.
[0007]
FIG. 2 shows this configuration. A compressed image take to which a synchronization signal corresponding to PCR is added is input from the input terminal 201, and is separated into compressed image data and a synchronization signal by the synchronization separation unit 202. Image data is stored in the buffer memory 203 under the control of the synchronization separation unit 202. The PLL unit 204 regenerates a clock based on the synchronization signal from the synchronization separation unit 202. The image data is read from the buffer memory 203 by a read control signal based on this clock, and is decompressed by the video decoding unit 205 and transferred to the display memory 206. It is read from the display memory 206 at the timing of the display system, and a video signal is output from the output terminal 207.
[0008]
In this way, by using the PLL circuit, the clocks coincide with each other in transmission and reception, that is, the write amount to the buffer memory (control from the synchronization separation unit 202) and the read amount (read control from the video decoding unit 205) are the same. The amount of data stored in the buffer becomes constant and the above-described overflow does not occur.
[0009]
[Problems to be solved by the invention]
As described above, by adding a synchronization signal to the compressed image data and configuring a PLL circuit based on this, the clocks can be matched between transmission and reception. Thereby, it is possible to prevent “frame dropping” and “twice display” in the image display.
[0010]
However, in a network such as an ATM network where the transmission delay varies, jitter is added to the transmitted synchronization signal.
[0011]
When the delay variation becomes large, not only the PLL circuit cannot absorb the variation but also the PLL circuit may not be locked. In this case, since the clocks between the transmission and reception do not match, the accumulated amount of the reception buffer increases / decreases according to the speed difference, and “frame dropping” due to overflow or “twice display” of the same image due to underflow occurs. appear. In particular, when there is a large change in the image on the time axis, when “frame dropping” or “twice display”, that is, display disturbance occurs, image quality deterioration is noticeable.
[0012]
Further, in the conventional technique, there is a case where the PLL circuit is not used in order to avoid an increase in circuit scale due to the addition of the PLL circuit and a jitter remaining in the recovered clock. In this case, the display disorder problem remains unsolved.
[0013]
[Means for Solving the Problems]
In order to solve this problem, in the present invention, Compressed A transmission image decoding apparatus comprising: a reception buffer that temporarily stores received image data; and a decoding unit that decodes received image data read from the reception buffer using a clock different from a clock on the transmission side. It is characterized by that.
[0014]
That is, (1) the amount of change in the received image data on the time axis is Image 1 frame (2) When a part of the received image data needs to be discarded or redisplayed, on the time axis based on the detection result of the change amount monitoring means And a decoding control means for controlling the decoding means so as to selectively discard or redisplay received image data with a small change amount.
As described above, in the present invention, even when a part of the received image data needs to be discarded or redisplayed, the received image data with a small amount of change on the time axis can be selectively discarded or redisplayed. Even if such processing is performed on the display screen, visual degradation can be prevented from appearing on the corresponding screen.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
Hereinafter, a first embodiment of a decoding apparatus according to the present invention will be described.
[0016]
(A-1) Configuration of the first embodiment
Even with “Frame Drop” or “Twice Display”, still images that always display the same image will not be degraded even if the display is disturbed, but there will be a significant change in the displayed image on the time axis. In some cases, it is noticeable as image quality degradation.
[0017]
Therefore, in the video decoding according to this embodiment, when it is necessary to perform “frame dropping” or “display twice”, it is performed on an image with little change on the time axis, thereby overflowing the buffer. Etc., the degradation of visual image quality is minimized.
[0018]
FIG. 1 shows the overall configuration of a decoding apparatus according to the first embodiment of the present invention. Bro FIG.
[0019]
As shown in FIG. 1, the decoding apparatus includes an input terminal 101, a synchronization separation unit 102, a buffer memory 103, a PLL unit 104, a video decoding unit 105, a change amount detection unit 106, a buffer remaining amount calculation unit 107, and a decoding control unit 108. , A display memory 109, and a video signal output terminal 110.
[0020]
Here, the input terminal 101 is a terminal for inputting compressed image data to which a synchronization signal is added, and the input compressed moving image data is given to the synchronization separation unit 102 from the input terminal 101. The sync separator 102 is a means for separating the compressed image data and the sync signal. Of the separated signals, the compressed image data is input to the buffer memory 103, and the synchronization signal is input to the PLL unit 104. Note that the compressed image data is stored in the buffer memory 103. The PLL unit 104 regenerates the transmission side clock based on the synchronization signal.
[0021]
The video decoding unit 105 is a unit that expands the compressed image data read from the buffer memory 103. The change amount detection unit 106 is means for detecting a change in the image on the time axis. The buffer remaining amount calculation unit 107 is a means for obtaining the amount of data stored in the buffer memory 103. The decoding control unit 108 controls the decoding display timing of the video decoding unit 105 from the decoding end signal from the video decoding unit 105, the image change information from the change amount detection unit 106, and the buffer remaining amount from the buffer remaining amount calculation unit 107. It is means to do. The display memory 109 is a memory that holds the decoded image data and outputs it at the display system timing. The video output terminal 110 is an output terminal for video signals.
[0022]
The decoding device according to the embodiment includes the above-described means. Among these, unique means that are not included in the conventional decoding device shown in FIG. 2 are a change amount detection unit 106, a buffer remaining amount calculation unit 107, These are the three means of the decoding control unit 108. Hereinafter, means unique to the embodiment will be described.
[0023]
First, the configuration of the change amount detection unit 106 is shown in FIG. The change amount detection unit 106 is means for detecting the amount of data transferred from the buffer memory 103 to the video decoding unit 105. FIG. 3 shows a configuration for detecting a change in the image on the time axis from the amount of compressed data for one frame of the image.
[0024]
As shown in FIG. 3, the change amount detection unit 106 includes a read control signal (memory address) input terminal 301, a decoding end signal input terminal 302, registers 303 and 305, a subtractor 304, and a change amount output terminal 306.
[0025]
Here, the register 303 is a register that holds a read address using the decoding end signal as a trigger signal, and the subtractor 304 is for obtaining a difference between the read amount of the previous cycle and a new read amount. The register 305 is used to hold the output value of the subtracter 306 using the decoding end signal as a trigger signal.
[0026]
Next, the configuration of the buffer remaining amount calculation unit 107 will be described. This buffer remaining amount calculation unit 107 is a means used to monitor the remaining amount of the buffer memory 103, and inputs a write control signal (memory address) and a read control signal (memory address) to a subtracter, and the difference It is the composition which asks for.
[0027]
Next, the configuration of the decoding control unit 108 is shown in FIG. Note that FIG. 4 shows only the part that controls overflow. A similar circuit is separately required for underflow.
[0028]
As shown in FIG. 4, the decoding control unit 108 includes a plurality of input / output terminals (buffer remaining amount input terminal 401, change amount input terminal 402, decoding end signal input terminal 403, data output command terminal 415, decoding start command output terminal. 416), comparators 404 and 405, and a plurality of gate circuits (NAND gate 406, AND gates 407 and 410, registers 408, 409, 411 and 412, NOR gate 412 and OR gate 414).
[0029]
Here, the comparator 404 is a comparator that compares the remaining amount of the buffer with the threshold A, and the comparator 405 is a comparator that compares the amount of change with the threshold B. The NAND gate 406 is a means for obtaining the NAND of the two comparators 404 and 405. The register 408 is means for delaying the decoding end signal by one cycle of the clock. Further, the register 409 is means for holding the output of the NAND gate 406 with a decoding end signal. Further, the AND gate 410 is a means for obtaining the logical product of the outputs of the registers 408 and 409 as inputs. The shift register 411 is used to delay the output of the AND gate 410. Further, the register 412 is means for delaying the output of the NAND gate 406 by one clock cycle.
[0030]
(A-2) Operation of the first embodiment
(A-2-1) Basic operation
Next, the operation content of the decoding apparatus will be described. First, the basic operation content will be described.
[0031]
When the decoding apparatus inputs the compressed image data to which the synchronization signal is added to the input terminal 101, the decoding apparatus supplies the compressed image data to the synchronization separation unit 102 and separates the compressed image data and the synchronization signal. Next, the decoding device writes the separated compressed image data into the buffer memory 103 at the operation timing of the synchronization separation unit 102 and supplies the synchronization signal to the PLL unit 104, and reproduces the transmission side clock in the PLL unit 104. . This reproduction clock is given to the video decoding unit 105.
[0032]
The decoding device reads the data stored in the buffer memory 103 using the reproduction clock, and decompresses the data by the video decoding unit 105. When the expansion of one image is finished, a decoding end signal is output and the expanded image is transferred to the display memory 109 and output at the timing of the display system.
[0033]
The above is the basic operation of the decoding apparatus.
[0034]
(A-2-2) Operation at overflow
Next, the decoding control operation of the video decoding unit 105, which is a functional unit unique to the decoding device according to the present embodiment, will be described. Note that two circuits that are closely related to this control are a change amount detection unit 106 and a buffer remaining amount calculation unit 107. Among them, the change amount detection unit 106 is used to detect the change amount of the image on the time axis, and the remaining buffer amount calculation unit 107 locks the PLL unit 104 to the transmission side clock due to a transmission delay variation or the like. It is used to calculate the fluctuation of the remaining amount of the buffer that occurs when not.
[0035]
First, the operation contents of the change amount detection unit 106 and the buffer remaining amount calculation unit 107 will be described.
[0036]
The change amount detection unit 106 is a means for monitoring the amount of change in the image by obtaining the amount of compressed data per frame of the image. Each image frame processing end is performed in the register 303 of FIG. 3 using the decoding end signal as a trigger signal. The total read amount (memory address) at the time is held. Then, the subtracter 304 obtains a difference between the total read amount (memory address) obtained by adding data for one new frame and the previous total read amount held in the register 303, and compresses the image per frame. Get the data. Note that the output of the subtractor 304 is converted into a signal of one decoding cycle by the register 305 using the decoding end signal as a trigger signal, and is output from the output terminal 306 as a change amount of the image on the time axis.
[0037]
On the other hand, the remaining buffer capacity calculation unit 107 calculates the remaining buffer capacity by calculating the difference between the amount of data written (that is, the memory address on the writing side) and the amount of data read (that is, the memory address on the reading side). Calculate and output this.
[0038]
The decoding control unit 108 inputs the decoding end signal output from the video decoding unit 105 together with the change amount and the buffer remaining amount, and generates a decoding start command and a data output command. Here, the decoding start command is a command for fetching data from the buffer memory 103, and the data output command is a command for transferring the decoded image to the display memory 109 and displaying it.
[0039]
Hereinafter, the operation of the decoding control unit 108 executed at the time of buffer overflow will be described with reference to FIG.
[0040]
In the comparator 404, the decryption control unit 108 compares the output of the buffer remaining amount calculating unit 107 with a threshold A to determine whether or not the buffer remaining amount exceeds a threshold A. . Here, when the remaining amount of the buffer exceeds the threshold value A, the comparator 404 outputs an “H” level alarm signal to notify that the buffer overflow is near. For example, the decoding process period of the sixth to ninth frames in FIG. 5 corresponds to this state. Note that a fixed value obtained from the buffer capacity, the reception data rate, and the like is used as the threshold A.
[0041]
In addition, the decoding control unit 108 compares the output of the above-described change amount detection unit 106 with a certain threshold B in the comparator 405, so that the image quality degradation is small even if the currently processed image is “frame dropped”. It is determined whether or not it is an image. Again, the comparator 405 outputs an “H” level signal in the case of an image capable of “dropping frames”. For example, in FIG. 5, the decoding processing period of the fourth frame and the ninth frame represents this state. Note that a fixed value obtained from the display image size or the like is used as the threshold value B.
[0042]
Therefore, when the output of the comparator 404 is at the “H” level and the output of the comparator 405 is at the “H” level (that is, the remaining buffer capacity exceeds the threshold A and the image can be “dropped”). In this case, the output becomes “L” level, “frame dropping” is necessary, and the fact that “frame dropping” can actually be performed is notified to the subsequent circuit. Subsequent circuits start the “frame dropping” operation based on this “L” level signal.
[0043]
Actually, in order to perform “frame dropping”, cancel the data output command for the image to be “frame dropped” and advance the decoding start command to display the next image instead of the “frame dropping” image. It is necessary to output. Therefore, the AND gate 407 is used for the former purpose.
[0044]
The AND gate 407 masks (that is, ANDs) the signal obtained by delaying the decoding end signal by one cycle with the output of the NAND gate 406 so that the data output instruction is not transmitted. That is, when the remaining amount of the buffer exceeds the threshold value A and the change amount is equal to or less than the threshold value B, control is performed so that the decompressed image is not output from the video decoding unit 105 to the video decoding unit 105 from the AND gate 407. A signal is output.
[0045]
On the other hand, a shift register 411 is used for the latter purpose. The shift register 411 confirms whether the data transfer to the display memory 109 is completed. New It functions to delay the decoding end signal by the time required for data transfer so that simple decoding is started. If no “frame dropping” occurs, this signal becomes a decoding start command. In the register 412 and the NOR gate 413, the falling edge of the NAND gate 406 output is obtained and a decoding start instruction to be added is generated. In the OR gate 414, the pulse of the NOR gate 413 output is added to the normal decoding start instruction of the shift register 411 output. In this way, a decoding start instruction is generated to start the decoding ahead of schedule.
[0046]
By controlling as described above, when the remaining buffer capacity increases, one image with a small amount of received data is not written to the display memory 109. Instead, the next image is decoded and stored in the display memory. It will be transferred, and it will be “frame dropping” when displayed.
[0047]
(A-2-3) Operation during underflow
On the other hand, in the case of buffer underflow, the same circuit is used to mask the “H” pulse from being output to the decoding start instruction, and the data output instruction is output twice for one decoding process. It is realized by doing.
[0048]
(A-3) Effects of the first embodiment
In the transmission of compressed moving images, if the clocks on the transmission side and the reception side are independent, the remaining amount of the reception buffer increases or decreases according to the speed difference. The remaining amount of the buffer can be made constant by regenerating the clock with the PLL circuit, but the PLL may not lock depending on the delay variation of the transmission path. In this case, since the clocks are independent, the remaining buffer capacity increases or decreases. Here, when the buffer memory overflows or underflows, "frame dropping" or "display twice" occurs, resulting in display disturbance. Such disturbance of the display is noticeably deteriorated in an image having a large change on the time axis, but is not greatly deteriorated in an image having a small change.
[0049]
Therefore, the decoding device having the above-described configuration is used.
[0050]
FIG. 6 illustrates the effects brought about by the first embodiment. Here, the clock frequency on the reception side is lower than the clock frequency on the transmission side, and a buffer overflow state is shown. The upper row shows the state of the buffer. When the remaining amount of the buffer indicated by the broken line exceeds the overflow level, “frame dropping” occurs. The lower row shows the received image and the display image. Since the receiving side clock frequency is low, the number of display frames is lower than the number of received frames.
[0051]
In the conventional method, “frame dropping” occurs when a buffer overflow occurs. For this reason, “frame dropping” occurs between the received image “5” and the received image “10” in FIG. These images have a large difference from the immediately preceding received images “4” and “9”. For this reason, a discontinuous portion appears in the movement of the black circle in the display image (arrow portion), resulting in image quality degradation.
[0052]
Therefore, in the first embodiment, as described above, when an image whose change amount is smaller than the threshold value B is received in a state where the remaining amount of the buffer exceeds the threshold value A, control is performed so as to “drop frames”. . That is, in FIG. 6, the amount of change of the received image “4” with respect to the received image “3” and the amount of change of the received image “8” with respect to the received image “7” are smaller than the threshold B. Since it is larger, the received images “4” and “8” are “dropped”. As a result, a display image as shown in FIG. 6 is obtained, and unnaturalness does not appear in the movement of the black circle.
[0053]
As described above, according to the first embodiment, the change amount detection unit 106 monitors the change amount of the image on the time axis, the buffer remaining amount calculation unit 107 monitors the remaining amount of the buffer, and these signals are obtained. Originally, the decoding control unit 108 estimates the occurrence of overflow or underflow in the buffer memory 103 and the change of the image, and unavoidably disturbs the display on the image with little change on the time axis. Thereby, visual deterioration when display disturbance occurs can be suppressed.
[0054]
In the first embodiment, the fact that the compressed image data is normally created based on the difference data between the frames of the image is used to estimate the change of the image on the time axis from the amount of received data. Yes. Therefore, the above effect is obtained with a simple configuration as shown in FIG. Changes in the image on the time axis can be known from other than the amount of received data. For example, an actual inter-frame difference can be obtained using a motion vector value, a transform coefficient, and a decoded image obtained when decoding compressed image data. In the present embodiment, the received data amount is described as an object, but it is possible to estimate the change of the image by these other methods.
[0055]
(B) Second embodiment
Hereinafter, a second embodiment of the decoding apparatus according to the present invention will be described.
[0056]
(B-1) Configuration of the second embodiment
In the first embodiment, the image change information on the time axis and the remaining amount of the buffer are independently compared with the threshold value by the comparator, and control such as “frame dropping” is performed, but this second embodiment In the following, a case will be described in which these two types of information are handled in an integrated manner and control such as “frame dropping” is performed.
[0057]
The overall configuration of the second embodiment is the same as that of the first embodiment shown in FIG. 1, but among these, a different one is used as the decoding control unit 108.
[0058]
FIG. 7 shows the configuration of the decoding control unit 108 according to the second embodiment. FIG. 7 shows the corresponding parts in FIG. 4 with corresponding reference numerals, and is composed of the same circuit components except that the ROM 704 is used instead of the comparators 404 and 405 and the NAND 406. .
[0059]
Here, the ROM 704 stores control information determined according to the buffer remaining amount and the amount of change, and can implement adaptive “frame dropping” control according to the relationship between the two amounts. For example, if the amount of change in the buffer is large, “frame drop” is executed when the amount of change is relatively large. If the amount of change in the buffer is small, “frame drop” is executed even if the amount of change is very small. It has come to be. FIG. 7 shows only the control part for overflow as in the case of FIG. 4, and a similar circuit is separately required for underflow.
[0060]
Incidentally, the decoding control unit 108 shown in FIG. 7 receives a buffer remaining amount input terminal 701, an image change amount input terminal 702 on a time axis, a decoding end signal input terminal 703, a buffer remaining amount and a change amount as inputs. ROM 704, AND gate 707 that receives the output of register 708 and the output of ROM 704, register 708 that delays the decoding end signal by one clock cycle, register 709 that holds the output of ROM 704 with the decoding end signal, and registers 708 and 709 An AND gate 710 that receives the output, a shift register 711 that delays the output of the AND gate 710, a register 712 that delays the output of the ROM 704 by one clock cycle, and a NOR gate 713 that receives the output of the ROM 704 and the inverted output of the register 712. , The output of the NOR gate 713 OR gate 714 receives the output of the shift register 711, the output terminal 715 of the data output instruction, and an output terminal 716 of the decoding start command.
[0061]
(B-2) Operation of the second embodiment
The basic operation in the second embodiment is the same as that in the first embodiment. Therefore, only the operation of the decoding control unit 108 having a different circuit configuration will be described here.
[0062]
Also in the second embodiment, the decoding control unit 108 generates a decoding start command and a data output command from the change amount, the buffer remaining amount, and the decoding end signal. The ROM 704 is a circuit block specific to the second embodiment provided for this purpose, and the ROM 704 generates an original signal for generating “frame dropping” from the change amount and the remaining buffer capacity.
[0063]
When this signal is at “L” level, “frame dropping” occurs. The AND gate 707 masks (ANDs) the signal obtained by delaying the decoding end signal by one cycle with this signal, so that the data output command is not sent out. The AND gate 710 masks (ANDs) a signal obtained by delaying this signal by one decoding cycle and a signal obtained by delaying the decoding end signal by one cycle.
[0064]
The shift register 711 functions to delay a time decoding end signal for data transfer so that a new decoding starts after the data transfer to the display memory 109 is completed. The register 712 and the NOR gate 713 obtain the falling edge of the output of the ROM 704, and the OR gate 714 adds a new pulse to the output of the shift register 709 to generate a decoding start instruction.
[0065]
As described above, the second embodiment is characterized in that the “frame dropping” control is performed in the ROM 704 from the relationship between the change amount and the remaining buffer capacity. With this configuration, the “frame dropping” frame can be determined adaptively with respect to the remaining buffer capacity. For example, when the remaining amount of the buffer is relatively small, “frame dropping” is performed even if the amount of change is extremely small, and at the stage where the remaining amount of buffer is large, “frame dropping” is performed even if the amount of change is relatively large.
[0066]
(B-3) Effects of the second embodiment
As described above, according to the second embodiment, the decoding control unit 108 adaptively performs control such as “frame dropping” based on an arbitrary relationship between the buffer remaining amount and the change amount. It is also possible to set an execution criterion for “frame dropping” based on whether the image quality deterioration is a visually noticeable still image or a visually inconspicuous moving image. For example, in the case of an image close to a still image, the “frame dropping” is executed even when the change of the image is quite small, so that the visual deterioration can be made more inconspicuous.
[0067]
(C) Other embodiments
In the above-described embodiment, the case where the compressed image data is transmitted through the transmission path has been described.
[0068]
In the above-described embodiment, the case of transmitting a moving image has been described. However, the present invention can also be applied to the case of decoding an encoded still image.
[0069]
【The invention's effect】
As described above, according to the present invention, the reception buffer that temporarily stores the received image data and the decoding unit that decodes the received image data read from the reception buffer using a clock different from the clock on the transmission side are provided. In the transmission image decoding device, when a part of the received image data needs to be discarded or redisplayed, the received image data with a small amount of change on the time axis is selectively discarded or redisplayed. It is possible to prevent the visual characteristics of the display screen from being deteriorated when the processing is executed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of a transmission image decoding apparatus.
FIG. 2 is a block diagram showing a configuration of a transmission image decoding device used conventionally.
3 is a block diagram illustrating a configuration of a change amount detection unit in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a decoding control unit according to the first embodiment.
FIG. 5 is a time chart showing the operational relationship of each part in FIG. 1;
FIG. 6 is an explanatory diagram illustrating a relationship between a remaining buffer capacity and a display image.
FIG. 7 is a block diagram illustrating a configuration of a decoding control unit according to a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 102 ... Synchronous separation part, 103 ... Buffer memory, 104 ... PLL part, 105 ... Video decoding part, 106 ... Change amount detection part, 107 ... Buffer residual quantity calculation part, 108 ... Decoding control part, 109 ... Display memory, 404, 405 ... Comparator, 406 ... NAND gate, 704 ... ROM.

Claims (3)

In a transmission image decoding apparatus comprising: a reception buffer that temporarily stores received image data that has been compressed; and a decoding unit that decodes reception image data read from the reception buffer using a clock different from a clock on the transmission side.
Change amount monitoring means for monitoring the amount of change in the received image data on the time axis based on the amount of compressed data for one frame of the received image data;
When a part of the received image data needs to be discarded or redisplayed, the received image data with a small amount of change on the time axis is selectively discarded or redisplayed based on the detection result of the change amount monitoring means. A transmission image decoding apparatus comprising: a decoding control unit that controls the decoding unit. Data remaining amount monitoring means for monitoring the remaining amount of data in the reception buffer is provided, and the decoding control means discards or recycles the received image data based on the monitoring results of the change amount monitoring means and the data remaining amount monitoring means. The transmission image decoding apparatus according to claim 1, wherein the necessity of display is determined. The transmission image decoding apparatus according to claim 1 or 2, wherein the decoding control means stores control information for each arbitrary combination of the buffer remaining amount and the change amount in the control information storage means.

Images