JP3963071B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a power element formed on an SOI substrate or a power element and an LSI or other integrated circuit are monolithically formed, and a semiconductor device having a function of protecting the element from a transient abnormal voltage from the outside About.
[0002]
[Prior art]
Japanese Patent Laid-Open No. 9-266310 is known as a technique for protecting a power element formed on an SOI substrate from switching noise generated in conjunction with potential fluctuation of a connected load. FIG. 8 is a cross-sectional view corresponding to the main part of the semiconductor device. In the structure of FIG. 8, the LDMOS is isolated and formed in the element region by insulating films (oxide films) 122 and 123. In order to prevent the switching noise generated due to the abnormal voltage applied from the drain electrode or the source electrode from propagating to the isolated element region, the N + type is formed on the insulating film 122 on the support substrate. The buried layer 121b is formed, and a shield layer made of the deep N + diffusion layer 126 is provided so as to be in contact with the insulating film 123, and this shield layer is fixed to the ground or the power supply potential. When an abnormal voltage is applied from the outside, the noise current is allowed to escape to the power source or the ground via these potential fixing regions.
[0003]
[Problems to be solved by the invention]
However, in the above conventional example, it is necessary to provide an N + type buried layer 121b at the interface between the support substrate and the insulating film. This N + type buried layer does not contain N + type impurities when the SOI substrate is formed. Since diffusion formation is necessary, there is a problem that the cost of the SOI wafer is high and the chip cost is increased.
[0004]
The present invention has been made to solve the problems of the prior art as described above, and provides a semiconductor device having a function of protecting a semiconductor element from abnormal voltage and suppressing an increase in chip cost. Objective.
[0005]
In order to achieve the above object, the present invention is configured as described in the claims. That is, in claim 1, in the semiconductor device where the support substrate and the active layer substrate to form a first insulating electrically isolated S OI power element formed on a substrate by film and Integrated Circuit monolithically , the power element and the Integrated circuit forms islands which are electrically insulated and separated from each other, respective second island reaching said first insulating film provided on a main surface perpendicular direction of the active layer substrate A P-type layer exists in the active layer substrate in the vicinity of the interface between the active layer substrate and the first insulating film for each island, and a transient abnormal voltage is applied from the outside. A P-type region is provided between the second insulating film that is in contact with an island that may be in contact with the second insulating film that is in contact with another island , and the P-type region is provided on the active layer substrate. The main surface side is grounded, and the transient abnormal voltage is external The combined capacity of the current path from the island that may be applied from the part to the P-type region via the second insulating film is the island where the transient abnormal voltage may be applied from the outside. The second insulating film has a capacity greater than that of the first insulating film so that the combined capacity of the current path from the first insulating film to the P-type region through the first insulating film and the support substrate is larger. It was set as the structure formed large.
[0009]
In the invention according to claim 2 , the second insulating film in contact with the island to which a transient abnormal voltage may be applied from the outside is compared with the second insulating film in contact with another island. Thus, a thin insulating film is formed.
[0010]
In the invention according to claim 3 , the thin insulating film in contact with the island to which a transient abnormal voltage may be applied from the outside is compared with the second insulating film in contact with another island. A material using a high dielectric constant was used.
[0011]
【The invention's effect】
In claim 1, transient noise current due to the applied noise voltage flows through the P-type layer, but the second insulating film in contact with the island where the abnormal voltage may be applied from the outside and the other island A P-type region is provided between the surrounding second insulating film, the P-type region having a portion grounded on the first main surface side of the active layer substrate, and a second region from the island. The combined capacity of the current path from the island to the P-type region through the insulating film is larger than the combined capacity of the current path from the island to the P-type region through the first insulating film and the support substrate. Since the second insulating film has a larger capacity than the first insulating film, no noise current flows in the P-type layer of the other island, and the noise current is extracted to the surface through the P-type region and grounded. Can escape. That is, the island which is a “surge source” is shielded by the P-type region in contact with the second insulating film. Therefore, the circuit of other islands does not malfunction, and the semiconductor device can operate sufficiently safely. Since the P-type region is formed only around the limited island where a transient abnormal voltage may be applied from the outside, the area of the entire semiconductor device (chip) is small. There are few factors that increase the cost.
In addition, since the structure of the buried layer having a high concentration as in the prior art is not required, the manufacturing process can be simplified and the cost can be reduced. Further, since the high-concentration buried layer is not formed as in the prior art, there is very little possibility that the element characteristics change due to the formation of the high-concentration region. That is, when the high concentration layer is formed, the N + layer and the N (or N−) layer are not formed separately in a horizontal line, and a wave is generated in the concentration distribution, and this wave causes a partial variation in element characteristics. For this reason, for example, the breakdown voltage is not stable, and in some cases, the breakdown voltage is concentrated in one place. However, in the present invention, since the high concentration layer is not provided, these do not occur.
[0015]
In the second aspect, the insulating film in contact with the island transient abnormal voltage that may be applied from the outside, to the second insulating thin insulating film as compared to the film in contact with the other islands Since the configuration is adopted, the surge current can easily escape to the ground through the P-type region .
[0016]
According to a third aspect of the present invention, the thin insulating film in contact with the island to which a transient abnormal voltage may be applied from the outside has a higher dielectric constant than the second insulating film in contact with another island. Since the material is used, the surge current can be more easily escaped.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
(First reference example)
Figure 1 is a sectional view showing a configuration of a first exemplary embodiment of the present invention. Referring to FIG. 1, the P-type support substrate 1 is electrically insulated from the active layer substrate 3 through the buried insulating film 2. A P-type layer 20 is formed at the bottom of the active layer substrate 3 at the interface between the active layer substrate 3 and the buried insulating film 2. An N-type well region 25 is formed in the active layer substrate 3 above the P-type layer 20. Here, the P-type layer 20 may be the original active layer substrate 3 of P-type, or an N-type active layer substrate in which a P-type deep well is formed. On the surface portion of the active layer substrate 3, for example, a power element portion 6 such as an LDMOS is formed, and a control circuit portion 7 made of a bipolar device or the like electrically separated from the power element portion 6 is formed. . In FIG. 1, the power element unit 6 and the control circuit unit 7 are isolated from each other, and an isolation film 4 formed inside the trench and an isolation region by polysilicon 5 for embedding the trench therein are drawn. ing.
[0018]
In the power element portion 6, a drain N + contact region 15 and a P-type channel region 11 exist on the surface of the active layer substrate 3 as components thereof, and an N + -type source region is formed on the surface inside the P-type channel region 11. 12 is formed. A gate electrode 14 is formed on the active layer substrate 3 via a gate insulating film 13 so that a channel is formed in the P-type channel region 11 in contact with the N + -type source region 12.
[0019]
In the control circuit unit 7, for example, a lateral PNP transistor is formed. As components, a P + -type collector region 8, a P + -type emitter region 9, and an N + -type base contact region 10 are formed on the surface of the active layer substrate 3.
In this embodiment, these devices are listed as representative examples, and other bipolar elements and CMOS elements may be formed. By combining these elements, a circuit block is formed in the control circuit unit 7, but here, only one element is listed in the control circuit unit 7 for the purpose of making the explanation of the operation easy to understand. It was.
[0020]
Further, in this embodiment, the back surface of the support substrate 1 may or may not have a fixed potential. Since the N-type well region 25 of the power element unit 6 is the drain of the LDMOSFET, it fluctuates between the VDD potential or the VDD potential and the VSS potential. The P-type layer 20 is grounded on the surface side through the deep P-type diffusion region 21 and the P + -type diffusion region 22 in the power element unit 6.
[0021]
Next, the operation of this embodiment will be described.
It is assumed that a noise voltage as indicated by an arrow 16 in FIG. 1 is applied to the power element unit 6 as a transient abnormal voltage from the outside. In this case, the power element unit 6 can be a “surge source” and the control circuit unit 7 can be a “region that may be damaged”. The transient noise current due to the noise voltage applied to the power element unit 6 flows through the P-type layer 20. However, as described in the configuration, the P-type layer 20 is grounded on the surface. Can escape to the surface side. That is, the “surge source” is effectively shielded by the P-type layer 20. For this reason, the control circuit unit 7 does not malfunction, and the semiconductor device can operate sufficiently safely. In addition, although the arrow 16 of FIG. 1 illustrated the case of + surge, it is effective similarly in -surge.
[0022]
As described above, in the embodiment of FIG. 1, since it is not necessary to form a high-concentration buried diffusion layer as in the conventional example, the cost of the SOI substrate can be reduced, and the cost of the semiconductor device can be reduced.
Further, since the high concentration buried layer is not formed unlike the prior art, there is very little possibility that the element characteristics are changed by forming the high concentration region. That is, when a high concentration layer is formed, as shown in FIG. 1, the N + layer and the N (or N−) layer are not formed separately in a horizontal straight line, and a wave is generated in the concentration distribution. Variations occur. For this reason, for example, the breakdown voltage is not stable, and in some cases, the breakdown voltage may be concentrated in one place. However, in the present embodiment, since the high concentration layer is not provided, these do not occur. This operation is the same in all embodiments described later.
[0023]
Next, FIG. 2 is a diagram showing a manufacturing process for preparing an SOI substrate used in this embodiment. 2A, a P-type support substrate 40 whose periphery is covered with an insulating film 42 and a P-type active layer substrate 41 whose periphery is covered with an insulating film 43 are prepared. In (b), these substrates are bonded together. In (c), the thickness of the active layer substrate 41 is adjusted by etching. The insulating films 42 and 43 are bonded to form a buried insulating film 44, and this portion becomes the buried insulating film 2 in FIG. In (d), the well 45 necessary for the power element portion is formed at the concentration N1, and at the same time, the well 46 necessary for the control circuit portion is formed at the concentration N2. Here, the well concentrations N1 and N2 can be set to arbitrary concentrations. In (e), an insulating separation film 47 that separates the power element portion and the control circuit portion and a polysilicon 48 that fills the insulating separation film 47 are formed.
[0024]
As described above, in the preparation of the SOI wafer in this embodiment, since a complicated process for forming the N + type buried layer 121b as in the conventional method is not required, the cost can be reduced as compared with the conventional method. Further, since the deep P-type diffusion region 21 for grounding the P-type layer 20 is formed only on a limited island (here, an island to which a transient noise voltage may be applied from the outside), In the entire semiconductor device (chip), the increase in the area is small, and there are few factors that increase the cost.
[0025]
(Second reference example)
Figure 3 is a sectional view showing a configuration of a second exemplary embodiment of the present invention. The characteristic part of the configuration of FIG. 3 will be described. The P-type layer 20 is grounded on the surface side through the deep P-type diffusion region 23 and the P + -type diffusion region 24 in the control circuit unit 7. The manufacturing process for preparing the SOI substrate is the same as that shown in FIG.
[0026]
Next, the operation of this embodiment will be described.
It is assumed that a noise voltage as indicated by an arrow 16 in FIG. 3 is applied to the power element unit 6 as a transient abnormal voltage from the outside. In this case, the power element unit 6 can be a “surge source” and the control circuit unit 7 can be a “region that may be damaged”. A transient noise current due to a noise voltage applied to the power element portion 6 flows through the P-type layer 20, but due to capacitive coupling via the embedded insulating film 2 and the support substrate 1, the P-type layer 20 of the control circuit portion 7. Also flows. However, since the P-type layer 20 is grounded on the surface of the control circuit unit 7, the noise current can be released to the surface side by the control circuit unit 7. In other words, the “area that may be damaged” can be shielded by the P-type layer 20. Therefore, the control circuit unit 7 does not malfunction and the semiconductor device can operate sufficiently safely.
[0027]
As described above, in the embodiment of FIG. 3, since it is not necessary to form a high-concentration buried diffusion layer as in the conventional example, the cost of the SOI substrate can be reduced, so that the cost of the semiconductor device can be reduced. Further, the deep P-type diffusion region for grounding the P-type layer 20 is formed only on a limited island (here, a control circuit portion operating at a high impedance: a circuit portion that is likely to cause a malfunction at a low current). Therefore, the total increase in the area of the semiconductor device (chip) is small, and there are few factors that increase the cost.
[0028]
(First Embodiment)
FIG. 4 is a sectional view showing the configuration of the first embodiment of the present invention, and corresponds to claim 1 . In the configuration of FIG. 4, description of parts that are basically the same as the reference examples described so far is omitted.
Explaining the characteristic configuration of the present embodiment, the power element unit 6 and the control circuit unit 7 are formed with double separation regions (parts 4 and 5) for insulating and separating in the lateral direction. Yes. A region sandwiched between the double separation regions is a P-type region 26, and is grounded on the surface side through a P + -type diffusion region 27 at the surface portion. The lateral direction is a direction parallel to the main surface of the active layer substrate 3, and the isolation region is provided in a direction perpendicular to the main surface of the active layer substrate 3 in order to separate the direction. .
[0029]
In FIG. 4, the P-type region 26 sandwiched between such isolation regions is drawn only on the left side of the power element unit 6, but actually, the power element unit 6 (here, a noise voltage can be applied from the outside). It is assumed that it is formed in the periphery of a region having a characteristic.
[0030]
Next, the operation of this embodiment will be described.
It is assumed that a noise voltage as indicated by an arrow 16 in FIG. 4 is applied to the power element unit 6 as a transient abnormal voltage from the outside. In this case, the power element unit 6 can be a “surge source” and the control circuit unit 7 can be a “region that may be damaged”. A transient noise current due to the noise voltage applied to the power element unit 6 flows through the P-type layer 20. In the present embodiment, the effect of capacitive coupling through the insulating film 4 formed in the lateral direction is stronger than capacitive coupling through the buried insulating film 2, and the P-type layer 20 of the control circuit unit 7 has The noise current does not flow, and the noise current passes through the P-type region 26 and can be taken out to the surface and escape to the ground. That is, the power element portion 6 which is a “surge source” is shielded by the P-type region 26 in contact with the insulating film 4. For this reason, the control circuit unit 7 does not malfunction, and the semiconductor device can operate sufficiently safely.
[0031]
In the above configuration, the insulating film 4 is formed so that the capacity of the insulating film 4 is larger than the capacity of the buried insulating film 2. In other words, as shown in the equivalent circuit shown in FIG. 5, the combined capacity of the current path (1) is made larger than the combined capacity of the current path (2). By doing so, when a surge is applied, the surge is propagated through the current path (1), and the surge can be released via the P region 26 and the contact region 27. Therefore, the island B can be isolated from the surge input to the island A in FIG.
[0032]
As described above, in this embodiment, since a complicated process for forming a high-concentration buried diffusion layer is not required, the cost can be reduced as compared with the conventional case. In addition, since the P-type region 26 is formed only around the limited island, the area of the entire semiconductor device (chip) is slightly increased, and there are few factors that increase the cost.
[0033]
( Second embodiment)
FIG. 6 is a sectional view showing the construction of the second embodiment of the present invention, and corresponds to claim 2 . In the configuration shown in FIG. 6, the description of the parts that are basically the same as those of the embodiments described so far will be omitted. Explaining the configuration characteristic of the present embodiment, a double separation region is formed between the power element unit 6 and the control circuit unit 7 for insulating and separating the lateral direction. A region sandwiched between the double separation regions is a P-type region 26, and is grounded via a P + -type diffusion region 27 at the surface portion.
[0034]
The P-type region 26 sandwiched between the isolation regions as described above is drawn only on the left side of the power element unit 6, but in reality, the power element unit 6 (in this case, a possibility that a noise voltage is applied from the outside) It is assumed that it is formed around a certain area. The process so far is the same as that of the third embodiment, but the present embodiment is characterized in that the thickness of the insulating film 4 ′ in contact with the power element portion 6 is thinner than that of the other elements.
[0035]
Next, the operation of this embodiment will be described.
It is assumed that a noise voltage as indicated by an arrow 16 in FIG. 6 is applied to the power element unit 6 as a transient abnormal voltage from the outside. In this case, the power element unit 6 can be a “surge source” and the control circuit unit 7 can be a “region that may be damaged”. A transient noise current due to the noise voltage applied to the power element unit 6 flows through the P-type layer 20. In the present embodiment, the effect of capacitive coupling through the insulating film 4 ′ formed so as to be separated in the lateral direction is stronger than the capacitive coupling through the buried insulating film 2, and the control circuit unit 7. No noise current flows through the P-type layer 20, and the noise current passes through the P-type region 26 and is taken out to the surface and can be released to the ground.
[0036]
Here, as described in the configuration, since the insulating film 4 ′ in contact with the power element portion 6 is configured to be thin, the insulating capacitance of this portion is larger than the others, and the noise current is more effectively reduced. It can flow. Even when the insulating film 4 'is thin, the isolation voltage between the islands is sufficiently secured by other isolation regions, so that even if the insulation of this part is broken, the entire semiconductor chip is fatal. There will be no damage. Thus, there is an effect of shielding the power element portion 6 which is a “surge source” by the P-type region 26 in contact with the insulating film 4 ′. For this reason, the control circuit unit 7 does not malfunction, and the semiconductor device can operate sufficiently safely.
[0037]
In this embodiment, the basic operation principle is the same as that of the third embodiment. However, since the insulating film 4 ′ is thin and the insulating film 4 is thick, the capacity of the insulating film 4 ′ is larger. Is larger than the capacity of the insulating film 4, the surge propagated to the P region 26 is difficult to propagate from the insulating film 4 to the control circuit unit 7.
[0038]
( Third embodiment)
FIG. 7 is a cross-sectional view showing the configuration of the third embodiment of the present invention, and corresponds to claim 3 . The description of the configuration equivalent to that of the embodiment described so far in the configuration of FIG. 7 will be omitted. Explaining the configuration characteristic of the present embodiment, a double separation region is formed between the power element unit 6 and the control circuit unit 7 for insulating and separating the lateral direction. A material having a high dielectric constant is used for the insulating film 30 in contact with the power element portion 6. For example, it is obtained by depositing a material such as tantalum oxide inside the trench. The thickness is also reduced compared to others. In this configuration, since the dielectric constant is larger than that of the first embodiment, the capacity increases if the thickness is the same, and can be reduced if the same capacity is obtained.
[0039]
Next, the operation of this embodiment will be described.
It is assumed that a noise voltage as indicated by an arrow 16 in FIG. 7 is applied to the power element unit 6 as a transient abnormal voltage from the outside. In this case, the power element unit 6 can be a “surge source” and the control circuit unit 7 can be a “region that may be damaged”. A transient noise current due to the noise voltage applied to the power element unit 6 flows through the P-type layer 20. In the present embodiment, the effect of capacitive coupling via the insulating film 30 formed so as to be separated in the lateral direction is stronger than that of capacitive coupling via the buried insulating film 2. A noise current does not flow through the P-type layer 20, and the noise current passes through the P-type region 26 and is taken out to the surface and can be released to the ground.
[0040]
Here, as described in the configuration, since the insulating film 30 in contact with the power element portion 6 is thin (capacity can be increased if the thickness is the same), and is configured of a material with a high dielectric constant, The insulation capacity of this part becomes larger than the others, and a noise current can be flowed more effectively. Even when the insulating film 30 is thin, the isolation voltage between the islands is sufficiently secured by other isolation regions, so that even if the insulation of this part is broken, the entire semiconductor chip is seriously damaged. There is no such thing as receiving.
[0041]
As described above, in this embodiment, the power element portion 6 that is a “surge source” can be shielded by the P-type region 26 in contact with the insulating film. For this reason, the control circuit unit 7 does not malfunction, and the semiconductor device can operate sufficiently safely.
In addition, since the cost of the SOI substrate can be reduced as compared with the case where a high-concentration buried diffusion layer is formed as in the conventional example, the cost of the semiconductor device can be reduced. In addition, since such a P-type region 26 is formed only around a limited island, the area of the entire semiconductor device (chip) is slightly increased, and the cost is not increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a first reference example of the present invention.
FIG. 2 is a diagram showing a manufacturing process for preparing an SOI substrate used in a reference example.
FIG. 3 is a cross-sectional view showing a configuration of a second reference example of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a first example of the present invention.
FIG. 5 is an equivalent circuit diagram of the main part in FIG. 4;
FIG. 6 is a sectional view showing the configuration of a second embodiment of the present invention.
FIG. 7 is a sectional view showing a configuration of a third embodiment of the present invention.
FIG. 8 is a structural cross-sectional view of a conventional device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Support substrate 2 ... Embedded insulation film 3 ... Active layer board | substrate 4 ... Insulation separation film 5 ... Polysilicon 4 '... Thin insulation separation film 5' ... Thin polysilicon 6 ... Power element part 7 ... Control circuit part 8 ... P + Type collector region 9 P + type emitter region 10 N type base contact region 11 P type channel region 12 N type source region 13 Gate insulating film 14 Gate electrode 15 N + drain contact region 16 External transient noise (surge)
20 ... P-type layer 21 ... P-type deep diffusion region 22 ... P + -type diffusion region 23 ... P-type deep diffusion region 24 ... P + -type diffusion region 25 ... N-well region 26 ... P-type region 27 ... P + -type Diffusion region 30 ... Insulating film made of high dielectric constant material 40 ... P-type support substrate 41 ... P-type active layer substrate 42 ... Insulating film 43 ... Insulating film 44 ... Embedded insulating film 45 ... Concentration N1 well 46 ... Concentration N2 well 47 ... Insulation separation film 48 ... Polysilicon

Claims (3)

The supporting substrate and the active layer substrate said active layer substrate S OI type semiconductor substrate which are electrically isolated by the first insulating film, a monolithic electrically insulated isolated power element and Integrated Circuit each other A semiconductor device formed in
The power element and the Integrated Circuit forms islands which are electrically insulated and separated from each other, each island second reaching the first insulating film provided on a main surface perpendicular direction of the active layer substrate Surrounded by an insulating film, a P-type layer exists in the active layer substrate in the vicinity of the interface between the active layer substrate and the first insulating film for each island, and a transient abnormal voltage is applied from the outside. A P-type region is provided between the second insulating film in contact with a possible island and the second insulating film in contact with another island , and the P-type region is the first of the active layer substrate. A current path having a portion grounded on the main surface side and extending from the island where the transient abnormal voltage may be applied from the outside to the P-type region via the second insulating film; synthesis capacity, before said first insulating film from the island that might said transient abnormal voltage is externally applied The second insulating film is formed to have a larger capacity than the first insulating film so as to be larger than a combined capacity of a current path reaching the P-type region through a support substrate. Semiconductor device. The second insulating film in contact with an island to which a transient abnormal voltage may be applied from the outside is a thin insulating film as compared with the second insulating film in contact with another island. The semiconductor device according to claim 1 . As the thin insulating film in contact with an island to which a transient abnormal voltage may be applied from the outside, a material having a higher dielectric constant than that of the second insulating film in contact with another island is used. the semiconductor device according to claim 2 you.

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