JP3952383B2 - Compound field effect semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound field effect semiconductor device that can prevent collisional ionization caused by concentration of an electric field or current to prevent the element from being destroyed and improve reliability.
[0002]
[Prior art]
In a field effect transistor such as a HEMT (high electron mobility transistor) using a compound semiconductor as a material, a narrow energy band gap material such as InGaAs, InAs, or InSb is used as a channel material in order to achieve high speed operation. ing.
[0003]
The cap layer on which the ohmic contact electrode is formed is made of high-concentration doped InGaAs or InAlAs that has a lattice constant close to InGaAs, InAs, InSb, etc., and that provides a low contact resistance. In a semiconductor layer stacked structure for producing a field effect transistor containing a material in a semiconductor layer, it is difficult to perform element isolation by ion implantation. Is realized.
[0004]
FIGS. 13A and 13B are main part explanatory views showing a conventional field effect transistor in which elements are separated by a mesa. FIG. 13A shows a main part cutting side surface, and FIG. 13B shows a main part cutting plane. In addition, the principal part side surface of (A) is a side surface cut | disconnected along line XX seen in (B).
[0005]
In the figure, 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is an electron supply layer, 5 is a cap layer, 5G is a gate recess, 6S is a source-side non-alloy ohmic electrode, and 6D is a drain. Side non-alloy ohmic electrodes, 7 is a gate electrode, and 8A is an electric field concentration portion.
[0006]
The ohmic electrodes 6S and 6D in the illustrated field effect transistor are formed non-alloyed on the heavily doped cap layer 5 in order to achieve good contact resistance.
[0007]
Non-alloy ohmic electrode structures are described, for example, in Journal of Vac. Sci. Technol. B13 (5) 1995 p. 2092, JJAP Vol 35 (1996) p. 5642.
[0008]
In the illustrated field effect transistor, when a narrow energy band gap material such as InGaAs, InAs, InSb or the like is used as the material of the channel layer 3, the channel material has a high impact ionization rate, so that it flows into the channel during device operation. There is a problem that when ionization occurs due to impact current and excessive holes flow into the gate electrode, the device is destroyed.
[0009]
Since this impact ionization occurs at a location where the electric field or current is concentrated in the device, if the concentration of the electric field or current at that location can be mitigated, the impact ionization is suppressed and the reliability of the device is improved.
[0010]
In the element having a semiconductor layer made of a narrow energy band gap material such as InGaAs, InAs, or InSb and a heterojunction of a semiconductor layer such as InAlAs or InAlP, a non-alloy ohmic electrode structure is used. Forming a current-concentrated portion in the device, resulting in increased impact ionization.
[0011]
Therefore, it is conceivable to change the ohmic electrode structure to a different structure to alleviate the concentration of the electric field and current in the element and suppress the impact ionization. Among the conventionally known ohmic electrode structures, The alloy ohmic structure and the recess ohmic structure that are used for the purpose of reducing the source resistance of the transistor are expected as the impact ionization-suppressing effect.
[0012]
For the alloy ohmic structure, see, for example, Journal of Vac. Sci. Technol. B13 (1) 1995 p. 163, JP-A-10-107259, JP-A-10-107261, JP-A-5-29353, and the like.
[0013]
As a general ohmic electrode for GaAs, there is a method of obtaining an ohmic contact with a semiconductor by using an Au-based or AuGe-based material and alloying after forming the electrode, and this method is applied to the formation of an ohmic electrode for InGaAs. .
[0014]
FIGS. 14A and 14B are explanatory views of a main part of a field effect semiconductor device for explaining a conventional alloy ohmic electrode structure. FIG. 14A shows a main part cutting side surface, and FIG. 14B shows a main part cutting plane. The symbols used in FIG. 13 represent the same parts or have the same meaning.
[0015]
In the figure, 9S represents a source side alloy / ohmic electrode, and 9D represents a drain side alloy / ohmic electrode.
[0016]
The field effect semiconductor device shown in FIG. 14 is different in that the non-alloy ohmic electrode in the field effect semiconductor device described with reference to FIG. 13 is replaced with an alloy ohmic electrode.
[0017]
The recess ohmic structure is disclosed in, for example, Japanese Patent Laid-Open No. 6-124965.
[0018]
FIG. 15 is a cutaway side view showing a main part of a field effect semiconductor device for explaining a conventional recess ohmic electrode structure. The same reference numerals as those used in FIG. 13 and FIG. It shall have the same meaning.
[0019]
In the figure, 4S and 4D are ohmic electrode forming recesses that reach the surface of the channel layer 3 from the surface of the cap layer 5, and the source-side non-alloy ohmic electrode 6S is formed in the recess 4D. A drain-side non-alloy ohmic electrode 6D is formed.
[0020]
Also, an asymmetric recess structure is known as a structure for relaxing the electric field strength in order to reduce impact ionization in the device, and is disclosed in Japanese Patent Laid-Open No. 5-218090.
[0021]
FIG. 16 is a main part explanatory view showing a field effect semiconductor device for explaining a conventional asymmetric recess structure, (A) shows a main part cutting side surface, (B) shows a main part cutting plane, The symbols used in FIGS. 13 to 15 represent the same parts or have the same meaning.
[0022]
As is apparent from FIG. 16, the asymmetric recess structure is characterized in that the recess length between the gate and the drain is larger than that between the source and the gate. As a typical manufacturing method of the asymmetric recess structure, After the recess 5G is formed, the gate electrode 7 is formed by being shifted to the source side.
[0023]
Among the conventional field-effect semiconductor devices listed above, field-effect semiconductor devices having a non-alloy ohmic electrode structure have been analyzed because the phenomenon of element breakdown has been analyzed in detail.
[0024]
In the non-alloy ohmic electrode structure described with reference to FIG. 13, as shown as the electric field concentration portion 8A, the electric field and current are concentrated at the time of device operation at the end of the ohmic electrode in the gate width direction. There is a problem that element destruction occurs in a part.
[0025]
FIG. 17 is a cut-away side view of the principal part showing the field effect semiconductor device for explaining in detail the process in which element breakdown occurs in the field effect semiconductor device having a non-alloy ohmic electrode structure. The same symbols as those used in the above description represent the same parts or have the same meaning.
[0026]
The illustrated field effect semiconductor device has a heterojunction composed of a narrow energy band gap semiconductor layer such as InGaAs, InAs, or InSb and a semiconductor layer such as InAlAs or InAlP, and the internal resistance of the heterojunction interface is large.
[0027]
The current injected from the source-side non-alloy ohmic electrode 6S into the cap layer 5 flows through the cap layer 5 into the channel layer 3 at the source side of the gate recess 5G, and passes through the channel layer 3 to form the gate. -When reaching the drain side of the recess 5G, the path flowing out into the cap layer 5 is followed.
[0028]
When the current that follows such a path flows out from the channel layer 3 into the cap layer 5, that is, at the location where it flows in the vertical direction along the drain side of the gate recess 5G, a current concentration portion 8B is generated. Therefore, collision ionization occurs due to the current flowing through the channel during device operation, and the generated holes excessively flow into the gate electrode 7 to destroy the device. It is.
[0029]
Here, among the conventionally known electrode structures, an alloy ohmic electrode structure that is expected to be able to suppress the collision ions by relaxing the concentration of the electric field and current in the element as mentioned above, The recess ohmic electrode structure and the asymmetric recess structure will be described in more detail.
[0030]
The alloy ohmic electrode structure described with reference to FIG. 14 also has an electric field concentration portion 8A at the ends of the alloy ohmic electrodes 9S and 9D in the gate width direction. In order to alloy, the electrode material and the semiconductor are reacted by applying heat treatment from the cap layer 5 so that the tips of the alloy ohmic electrodes 9S and 9D reach the channel layer 3.
[0031]
However, during the heat treatment, if the semiconductor layer is InGaAs or InAlAs containing In, an Au-based material such as AuGe or Au excessively reacts with In to increase the contact resistance, so that an inconvenient current path Is generated.
[0032]
FIG. 18 is a cutaway side view showing a main part of a field effect semiconductor device for explaining a current path generated depending on the electrode structure. FIG. 18A shows an alloy ohmic electrode structure, and FIG. 18B shows a recess ohmic. Each of the electrode structures is shown, and the same symbols as those used in FIGS. 13 to 17 represent the same parts or have the same meaning.
[0033]
As shown in FIG. 18A, in the case of the alloy ohmic electrode structure, there is no path for the current in the element to flow from the alloy ohmic electrode 9S to the cap layer 5 or the electron supply layer 4, and the alloy ohmic contact. A path that directly flows from the electrode 9S to the channel layer 3 and flows directly to the opposing alloy ohmic electrode 9D is taken. At this time, a current concentration portion 8B is generated between the gate and drain of the channel layer 3.
[0034]
Therefore, also in this case, the current concentration portion 8B and the electric field concentration portion 8A shown in FIG. 14B coincide with each other. Therefore, collision ionization occurs due to the current flowing through the channel during the operation of the element, and the generated positive current is generated. A phenomenon occurs in which the holes excessively flow into the gate electrode 7 and the device is destroyed.
[0035]
As shown in FIG. 18B, in the case of the recess ohmic electrode structure, since the ohmic electrodes 6S and 6D are in direct contact with the channel layer 3, the current flows directly from the ohmic electrode 6S to the channel layer 3, A path that directly flows to the opposing ohmic electrode 6D is taken. At this time, a current concentration portion 8B is generated between the gate and drain of the channel layer 3.
[0036]
Accordingly, also in this case, the current concentrated portion 8B and the electric field concentrated portion 8A coincide with each other as in the case of the alloy ohmic electrode described with reference to FIG. Ionization occurs, causing a phenomenon that the generated holes excessively flow into the gate electrode 7 and the device is destroyed.
[0037]
FIG. 19 is a cutaway side view showing a main part of a field effect semiconductor device for explaining a current path generated in an asymmetric recess structure. The same symbols as those used in FIGS. Express or have the same meaning.
[0038]
As described with reference to FIG. 16, the electric field concentration portion 8A exists at the ends of the non-alloy ohmic electrodes 6S and 6D in the gate width direction even in the asymmetric recess structure, and the distance between the gate and the drain increases. However, since the internal resistance of the heterojunction interface is large, the current injected from the source-side non-alloy ohmic electrode 6S into the cap layer 5 through the cap layer 5 as shown in FIG. It flows into the channel layer 3 at the source side, and when it reaches the drain side of the gate recess 5G through the channel layer 3, it follows a path that flows out into the cap layer 5.
[0039]
When a current following such a path flows out from the channel layer 3 into the cap layer 5, that is, a current concentration portion 8B is generated at a position where the current flows in the vertical direction on the drain side of the gate recess 5G. Therefore, collision ionization occurs due to the current flowing through the channel during device operation, and the generated holes excessively flow into the gate electrode 7 to destroy the device. .
[0040]
[Problems to be solved by the invention]
In the present invention, by making a simple modification to the ohmic electrode and recess structure of the compound field effect semiconductor device, it is difficult to cause impact ionization due to the current flowing in the channel during the operation of the device, thereby improving the reliability of the device. .
[0041]
[Means for Solving the Problems]
In the compound field effect semiconductor device according to the present invention, in order to shift the current concentration portion from the electric field concentration portion generated at both ends in the gate width direction. Including the ohmic recess formed by completely removing the cap layer at the end in the gate width direction in the drain electrode region, the source-side ohmic electrode formed on the cap layer and alloyed, and the inside of the ohmic recess And a drain-side recessed ohmic electrode formed and alloyed That is the basis.
[0042]
By adopting the above means, collision ionization due to the current flowing in the channel during the operation of the device is less likely to occur, and the reliability of the device is improved.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a fragmentary plan view showing a compound field effect semiconductor device for explaining the first embodiment of the present invention, FIG. 2 is also a fragmentary cutaway side view, and FIG. 1 (A) is taken along line X1-X1 in FIG. A cross section along (B) shows a cross section along line X2-X2 in FIG. 1, and the same symbols as those used in FIGS. 13 to 19 represent the same parts or have the same meaning.
[0044]
In the figure, 11S represents a source-side ohmic electrode, 11D represents a drain-side ohmic electrode, and 12D represents a drain-side recessed ohmic electrode.
[0045]
In the first embodiment, as shown in FIG. 1 and FIG. 2A, the ohmic electrode forming recess in which the cap layer 5 is removed by etching at the end in the gate width direction in the drain side electrode region is provided. After that, the source-side ohmic electrode 11S and the drain-side ohmic electrode 11D are formed.
[0046]
Here, the heat treatment for alloying is performed. The alloying is performed to such an extent that the drain-side recess ohmic electrode 12D extends and contacts the channel layer 3. Therefore, the extension of the source side ohmic electrode 11 </ b> S and the drain side ohmic electrode 11 </ b> D remains in the cap layer 5.
[0047]
FIG. 3 is a fragmentary plan view showing a compound field effect semiconductor device for explaining the second embodiment of the present invention, FIG. 4 is a fragmentary sectional side view of the same, and FIG. 3A is a line X1-X1 in FIG. A cross section along (B) shows a cross section along line X2-X2 in FIG. 3, and the same symbols as those used in FIGS. 1 and 2 represent the same parts or have the same meaning.
[0048]
In the figure, 21S represents a source-side recessed ohmic electrode, 21D represents a drain-side recessed ohmic electrode, and 22D represents a drain-side ohmic electrode.
[0049]
In the second embodiment, as shown in FIGS. 3 and 4, the cap layer 5 is etched by etching in the entire region of the source side electrode region and in the entire region of the drain side electrode region except for the end in the gate width direction. The removed ohmic electrode forming recess is provided, and then the source-side recessed ohmic electrode 21S, the drain-side recessed ohmic electrode 21D, and the drain-side ohmic electrode 22D are formed.
[0050]
Here, a heat treatment for alloying is performed. The alloying is performed to such an extent that the source-side recess ohmic electrode 21S and the drain-side recess ohmic electrode 21D extend to contact the channel layer 3. Therefore, the extension of the drain side ohmic electrode 22 </ b> D remains in the cap layer 5.
[0051]
FIG. 5 is a fragmentary plan view showing a compound field effect semiconductor device for explaining the third embodiment of the present invention. Do the same symbols as those used in FIGS. 1 to 4 represent the same portions? Or it shall have the same meaning.
[0052]
In the figure, 23S indicates a source-side ohmic electrode, 23D indicates a drain-side ohmic electrode, 25G indicates a gate recess, and 26G indicates a gate recess whose length is increased in the gate length direction.
[0053]
In the third embodiment, the recess length in the gate length direction of the gate recess in the vicinity of the end of the ohmic electrode in the gate width direction is made larger than the recess length in the gate length direction of other portions. In this case, the ohmic electrode may be either a non-alloy electrode or an alloy electrode regardless of whether it is on the source side or on the drain side, and whether or not there is a recess for forming an ohmic electrode.
[0054]
By the way, when the contact resistance between the alloy ohmic electrode and the channel layer is larger than the resistance when overcoming the heterojunction, the structure of the first embodiment described with reference to FIGS. As seen in FIGS. 2A and 2B, the current path passes over the heterojunction and flows into the channel layer 3 to obtain a low source resistance.
[0055]
As shown in FIG. 2A, the drain-side current path flows into the drain-side recess ohmic electrode 12D through the channel layer 3 at the end in the gate width direction. Except at the end, as seen in FIG. 2B, the channel layer 3 crosses the heterojunction and flows into the drain side ohmic electrode 11D.
[0056]
Therefore, since the resistance of the current path in the element at the end in the gate width direction becomes larger, the amount of current is smaller than that in the current path in the element other than the end in the gate width direction. As a result, the electric field concentration portion at the end in the gate width direction does not coincide with the current concentration portion in the device, and the device is prevented from being destroyed.
[0057]
Further, when the contact resistance between the alloy ohmic electrode and the channel layer is smaller than the resistance when overcoming the heterojunction, the structure of the second embodiment described with reference to FIGS. Since the current path flows directly from the recess ohmic electrode 21S into the channel layer 3 as seen in FIGS. 4A and 4B, a low source resistance is obtained.
[0058]
As shown in FIG. 4A, the drain-side current path flows over the heterojunction from the channel layer 3 and flows into the drain-side ohmic electrode 22D at the end in the gate width direction. 4B, the current flows directly from the channel layer 3 to the drain-side recess ohmic electrode 21D, and therefore, the current path in the element at the end in the gate width direction. However, as the resistance increases, the amount of current is smaller than at the end other than the end in the gate width direction, and as a result, the electric field concentration portion at the end in the gate width direction does not match the current concentration portion in the element, The destruction of the element will be suppressed.
[0059]
In the third embodiment described with reference to FIG. 5, the recess length in the gate length direction of the gate recess is larger at the end in the gate width direction than the recess length in the gate length direction of other portions. The resistance value of the current path in the element at the end in the gate width direction is increased, and the amount of current is smaller than that at the end other than the end in the gate width direction. The electric field concentration portion and the current concentration portion in the element do not coincide with each other, and the destruction of the element is suppressed.
[0060]
Semiconductor device manufacturing process example 1
FIG. 6 to FIG. 9 are side sectional views showing a principal part of the semiconductor device at the main points for explaining the manufacturing process of the compound field effect semiconductor device according to the present invention. I will explain. The symbols used in FIGS. 1 to 5 represent the same parts or have the same meaning.
[0061]
Refer to FIG.
(1)
A buffer layer 2, a channel layer 3, an electron supply layer 4, and a cap layer 5 are grown on the substrate 1 by applying a MOCVD (Metalorganic Chemical Vapor Deposition) method. As a film forming method applied here, various known film forming methods can be adopted in addition to the MOCVD method. The electron supply layer 4 is actually a spacer layer, a supply layer, a barrier layer.
It consists of a laminate of layers.
[0062]
The main data regarding each semiconductor part is exemplified as follows.
▲ 1 ▼ Substrate 1
Material: InP
(2) Buffer layer 2
Material: InAlAs
Thickness: 200 [nm]
(3) Channel layer 3
Material: InGaAs
Thickness: 25 [nm]
(4) Electron supply layer 4
Spacer layer material: i-InAlAs
Thickness: 3 [nm]
Supply layer material: n-InAlAs
Impurity concentration: 5 × 10 ¹⁸ 〔cm ^-3 ]
Barrier layer material: i-InAlAs
▲ 5 ▼ Cap layer 5
Material: n-InGaAs
Thickness: 50 [nm]
[0063]
The wafer manufactured here can be used in common with each of the embodiments described above, and the thickness of the i-InAlAs spacer layer and the n-InAlAs supply layer constituting the electron supply layer 4 is 15 nm. When the thickness is 10 [nm], the resistance over the heterojunction described with reference to FIGS. 1 and 2 is 0.1 [Ω · mm], and the contact resistance between the alloy ohmic electrode and the channel layer is 0.2. If the thickness of the i-InAlAs spacer layer and the n-InAlAs supply layer is less than [Ω · mm] and is 10 [nm] and 5 [nm], the heterojunction overcoming described with reference to FIGS. The resistance is 0.35 [Ω · mm], which is larger than 0.2 [Ω · mm] which is the contact resistance between the alloy ohmic electrode and the channel layer.
[0064]
(2)
Using the wafer shown in FIG. 6A, the cap region 5 to the buffer layer 2 in the active region are mesa-etched to perform element isolation. Here, only the part where the elements are separated is taken out and illustrated.
[0065]
In the following process description, the case where the semiconductor device described with reference to FIGS. 1 and 2 is manufactured will be described. However, the present invention is easily applied to the case where another semiconductor device, for example, the semiconductor device described with reference to FIGS. be able to.
[0066]
Refer to FIG.
(3)
By applying a resist process in the lithography technique, a resist film 31 having an opening 31A is formed in the recess formation scheduled region in the drain side electrode formation planned region.
[0067]
Refer to FIG.
(4)
By applying a wet etching method using an etching solution selected from phosphoric acid, citric acid, and succinic acid, the cap layer 5 is etched using the resist film 31 as a mask to form an ohmic electrode recess 5A. .
[0068]
(5)
After removing the resist film 31, a resist film 32 having openings 32A is formed in the source-side electrode formation scheduled region and the drain-side electrode formation scheduled region by newly applying a resist process in lithography technology. .
[0069]
Refer to FIG.
(6)
By applying the vapor deposition method and the lift-off method, the source-side ohmic electrode 11S, the drain-side ohmic electrode 11D, and the drain-side recessed ohmic electrode 12D made of Ni / AuGe / Au are formed. In addition, since the figure referred here is a cut side surface along line X1-X1 in FIG. 1, the drain side ohmic electrode 11D is not represented.
[0070]
Refer to FIG.
(7)
By applying an electron beam lithography technique, a resist film having an opening in a region where a gate recess is to be formed is formed.
[0071]
(8)
By applying a wet etching method using an etching solution selected from phosphoric acid, citric acid, and succinic acid, the cap layer 5 is etched by using the resist film formed in step (7) as a mask. -Recess 5G is formed.
[0072]
Refer to FIG.
(9)
A heat treatment is performed at a temperature of 300 ° C. and a time of 5 minutes to alloy the source-side ohmic electrode 11S, the drain-side ohmic electrode 11D, the drain-side recessed ohmic electrode 12D, and the semiconductor.
[0073]
As described above, the reaction depth is 25 [nm] to 50 [nm] because the electrode uses the Ni layer as the reaction control layer as the lowermost layer and the heat treatment temperature is suppressed to 300 [° C.]. Therefore, the contact resistance does not increase due to an excessive reaction between the semiconductor material of the cap layer 5 and the Au-based ohmic electrode material.
[0074]
In this case, the material for the reaction control layer may be Pd or Ti in addition to Ni, and the heat treatment temperature may be selected in the range of 250 [° C.] to 300 [° C.].
[0075]
See FIG.
(10)
The gate electrode 7 made of Ti / Pt / Au is formed in the gate recess 5G by applying a resist process, a vacuum deposition method, and a lift-off method in the electron beam lithography technique.
[0076]
Semiconductor device manufacturing process example 2
10 and 11 are fragmentary plan views showing the semiconductor device at the main points of the process for explaining an example of the process for manufacturing the semiconductor device according to the third embodiment described with reference to FIG. This will be described with reference to the drawings. The symbols used in FIG. 1 to FIG. 9 represent the same parts or have the same meaning.
[0077]
When the semiconductor device shown in FIG. 5 is manufactured, the steps until the source-side ohmic electrode 23S and the drain-side ohmic electrode 23D are formed are the same as the manufacturing steps of the first specific example, and are omitted, and will be described from the next step. . It should be noted that the ohmic electrode in this case may be either a non-alloy electrode or an alloy electrode regardless of whether it is on the source side or on the drain side, and whether or not there is a recess for forming an ohmic electrode is described above. Street.
[0078]
Refer to FIG.
(1)
By applying a resist process in the electron beam lithography technique, an electron beam is drawn to form an opening corresponding to a gate recess formation scheduled portion in a formed resist film (not shown).
[0079]
At this time, it should be noted that the drawing region 33A for forming an opening with an enlarged recess length in the gate length direction such as double exposure or multiple dose exposure at the end in the gate width direction and normal drawing This is to perform electron beam drawing for the region 33.
[0080]
Refer to FIG.
(2)
When the resist film (not shown) exposed as described above is developed, an opening 34 and an opening 34A enlarged in the gate length direction are formed in the gate recess formation scheduled portion.
[0081]
(3)
The gate recesses 25G and 26G are formed by etching the cap layer 5 through the openings 34 and 34A by applying a wet etching method in which the etchant is based on phosphoric acid, citric acid or succinic acid. .
[0082]
See FIG.
(4)
When the source side ohmic electrode 23S and the drain side ohmic electrode 23D are alloy ohmic, an alloying heat treatment is performed at a temperature of 300 [° C.] for a time of 5 [min].
[0083]
(5)
Resist process, vacuum deposition method in electron beam lithography technology,
By applying the lift-off method, the gate electrode 8 made of Ti / Pt / Au is formed.
[0084]
FIG. 12 is a diagram comparing the emission intensities of electron-hole pairs from the recess surface along the gate width direction in the field effect semiconductor device according to the present invention and the field effect semiconductor device according to the prior art. The horizontal axis represents the length in the gate width direction, and the vertical axis represents the emission intensity.
[0085]
In the figure, the solid line shows the emission intensity obtained by the field effect semiconductor device of the present invention, and the broken line shows the emission intensity obtained by the conventional field effect semiconductor device. The field effect semiconductor device of the present invention was obtained by using the device described with reference to FIGS. 3 and 4, and the conventional field effect semiconductor device was obtained by using the device described with reference to FIG.
[0086]
According to the figure, in the data in the conventional field effect semiconductor device, it is recognized that strong light emission is seen at the end of the ohmic electrode in the gate width direction indicated by the arrow and the current is concentrated. According to the data in the field effect semiconductor device according to the above, it can be seen that the current concentration is relaxed at the end of the ohmic electrode in the gate width direction.
[0087]
【The invention's effect】
In the compound field effect semiconductor device according to the present invention, in order to shift the current concentration portion from the electric field concentration portion generated at both ends in the gate width direction. Including the ohmic recess formed by completely removing the cap layer at the end in the gate width direction in the drain electrode region, the source-side ohmic electrode formed on the cap layer and alloyed, and the inside of the ohmic recess And a drain-side recessed ohmic electrode formed and alloyed That is the basis.
[0088]
By adopting the above-described configuration, collision ionization due to the current flowing in the channel during device operation is less likely to occur, and the reliability of the device is improved.
[Brief description of the drawings]
FIG. 1 is a fragmentary plan view showing a compound field effect semiconductor device for explaining Embodiment 1 of the present invention;
FIG. 2 is a cutaway side view showing a main part of a compound field effect semiconductor device for explaining the first embodiment of the present invention;
FIG. 3 is a fragmentary plan view showing a compound field effect semiconductor device for explaining a second embodiment of the present invention;
FIG. 4 is a cutaway side view showing a main part of a compound field effect semiconductor device for explaining a second embodiment of the present invention.
FIG. 5 is a fragmentary plan view showing a compound field effect semiconductor device for explaining a third embodiment of the present invention;
FIG. 6 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a manufacturing process of a compound field effect semiconductor device according to the present invention.
FIG. 7 is a cut-away side view of the main part showing the semiconductor device in the process key for explaining the manufacturing process of the compound field effect semiconductor device according to the present invention.
FIG. 8 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a manufacturing process of a compound field effect semiconductor device according to the present invention.
FIG. 9 is a cut-away side view of the main part showing the semiconductor device in the process key for explaining the manufacturing process of the compound field effect semiconductor device according to the present invention.
FIG. 10 is a fragmentary plan view showing a semiconductor device in a process key point for explaining a process example of manufacturing the semiconductor device according to the third embodiment described with reference to FIG. 5;
FIG. 11 is a fragmentary plan view showing a semiconductor device in a process key point for explaining a process example of manufacturing the semiconductor device according to the third embodiment described with reference to FIG. 5;
FIG. 12 is a diagram comparing the emission intensity of electron-hole pairs from the recess surface along the gate width direction in the field effect semiconductor device according to the present invention and the field effect semiconductor device according to the prior art. It is.
FIG. 13 is a main part explanatory view showing a conventional field effect transistor in which elements are separated by mesa.
FIG. 14 is a main part explanatory view of a field effect semiconductor device for explaining a conventional alloy ohmic electrode structure;
FIG. 15 is a cutaway side view showing a main part of a field effect semiconductor device for explaining a conventional recess ohmic electrode structure;
FIG. 16 is a main part explanatory view showing a field effect semiconductor device for explaining a conventional asymmetric recess structure.
FIG. 17 is a cutaway side view showing a main part of a field effect semiconductor device for explaining in detail a process in which element breakdown occurs in a field effect semiconductor device having a non-alloy ohmic electrode structure.
FIG. 18 is a cutaway side view of a main part showing a field effect semiconductor device for explaining a current path generated depending on an electrode structure.
FIG. 19 is a cutaway side view showing a main part of a field effect semiconductor device for explaining a current path generated in an asymmetric recess structure.
[Explanation of symbols]
1 Substrate
2 Buffer layer
3 channel layer
4 Electron supply layer
5 Cap layer
5G Gate recess
6S Non-alloy ohmic electrode on source side
6D drain side non-alloy ohmic electrode
7 Gate electrode
8A Electric field concentration part
9S source side alloy ohmic electrode
9D drain side alloy ohmic electrode
11S Ohmic electrode on source side
11D drain side ohmic electrode
12D Drain side recess ohmic electrode
21S Recessed ohmic electrode
21D Drain-side recess ohmic electrode
22D Drain side ohmic electrode
23S Source-side ohmic electrode
23D Drain side ohmic electrode
25G Gate recess
26G Gate recess with increased length in the gate length direction

Claims (3)

An ohmic recess formed by completely removing the cap layer at the gate width direction end in the drain electrode region in order to shift the current concentration portion from the electric field concentration portion generated at both ends in the gate width direction ,
A compound field effect comprising: a source-side ohmic electrode formed on the cap layer and alloyed; and a drain-side recess ohmic electrode formed and alloyed including the inside of the ohmic recess. Semiconductor device. An ohmic structure formed by completely removing the cap layer at the end of the gate width direction in the entire source electrode region and the drain electrode region in order to shift the current concentration portion from the electric field concentration portion generated at both ends in the gate width direction. Recess and
A source-side recess ohmic electrode and a drain-side recess ohmic electrode formed and alloyed including the inside of the ohmic recess;
A compound field effect semiconductor device comprising: The ohmic recess formed by completely removing the cap layer at the end in the gate width direction in the drain electrode region is present at the end other than the end in the gate width direction.
The compound field effect semiconductor device according to claim 2 .

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