JP3945966B2 - Image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus that controls and modulates the light output of a semiconductor laser used as a light source in a laser printer, a digital copying machine, or the like.
[0002]
[Prior art]
As a conventional example of this type, for example, Japanese Patent Laid-Open Nos. 5-075199, 5-235446, and 9-321376 disclose a light receiving current and a light emission command of a light receiving element that monitors the light output of a semiconductor laser. A constant negative current feedback loop that controls the semiconductor laser at high speed is constructed by constantly comparing the current with the current, and a current proportional to the emission command current is added to the output current of the negative photoelectric feedback loop to flow through the semiconductor laser. Therefore, a method for modulating a semiconductor laser at high speed has been proposed. By doing so, temperature characteristics and droop characteristics of the semiconductor laser are suppressed, and high-speed modulation is realized.
[0003]
However, if the light output of the semiconductor laser decreases due to the characteristics of the light receiving element that monitors the light output of the semiconductor laser, the linearity of the light receiving current output characteristic with respect to the light input of the light receiving element is significantly deteriorated. For this reason, the control accuracy in the case of a low light output is deteriorated, and the light output may be larger than a predetermined light output. If such a situation occurs, the laser printer or the like will have an adverse effect such as soiling.
[0004]
In addition, since the light output is always controlled, the light output cannot be completely turned off even for the normal operation of the control system, which causes offset light. In addition, a circuit for setting a drive current for adding the drive current to the semiconductor laser is required, which entails circuit scale restrictions when improving the function of a light modulation IC such as a laser printer.
[0005]
Furthermore, since a light receiving element that detects only the light output of one semiconductor laser is required, when detecting the output of a plurality of lasers with a single light receiving element as in a semiconductor laser array, each light output is externally provided. It is necessary to provide a means for separately detecting the.
[0006]
As another conventional example, a pixel clock frequency setting method using a direct synthesizer as described in Japanese Patent Application Laid-Open No. 11-167081, can be performed at high speed by changing the frequency increment to LUT (lookup table) data. Although it is possible to change the frequency, the frequency variable increment and the output frequency change speed are closely intertwined with the control speed of the PLL-LOOP to be connected next and the low-pass filter, and become a constraint when designing the entire configuration. In addition, the frequency increment depends on the master clock frequency and the number of bits of the LUT, and it is necessary to increase the circuit scale or to increase the master clock speed in order to make fine settings. It is difficult to realize.
[0007]
In the method of adding a phase error to the PLL-LOOP as described in Japanese Patent Laid-Open No. 5-207234, a frequency error of the pixel clock occurs unless the additional signal of the phase error is made very stable. This is a major limitation when integrating a digital circuit and an analog circuit into a one-chip IC.
[0008]
[Problems to be solved by the invention]
This will be further described with reference to the conventional example shown in FIG. In the figure, the laser light emitted from the semiconductor laser unit 21 is scanned by the polygon mirror 22 as the polygon mirror 22 rotates, and a light spot is formed on the scanned medium (photosensitive member) 24 via the scanning lens 23. Then, the scanning medium 24 is exposed to form an electrostatic latent image. At this time, the semiconductor laser unit 21 controls the light emission time of the semiconductor laser in accordance with the image data generated by the image processing unit 26 and the image clock whose phase is set by the phase synchronization circuit 29, so that the on-scanned medium 24 To control the electrostatic latent image. The phase synchronization circuit 29 sets the phase of the clock generated by the clock generation circuit 28 to a phase synchronized with the photodetector 29 that detects the light of the semiconductor laser scanned by the polygon mirror 22.
[0009]
As described above, the laser drive circuit 27, the phase synchronization circuit 29, and the clock generation circuit 28 improve the positional accuracy and interval accuracy of the electrostatic latent image formed on the scanned medium 24 in the image forming apparatus using the laser scanning optical system. This is indispensable. For this reason, a number of paths are required in the image forming apparatus at the same frequency as the image clock, causing an EMI problem of the image forming apparatus. In addition, since the number of parts increases, the cost increases. Furthermore, it becomes very difficult to operate the image data transfer clock at the same timing in the entire system as the printing speed increases, and the image data must be transferred in parallel with a slow clock.
[0010]
In recent years, with the increase in the speed and density of laser printers, there are multi-beam optical systems that achieve high speed and high density by recording with light from a plurality of light sources as well as light from a single light source. It is being adopted. However, in this case, there are a case where a plurality of semiconductor lasers are used as a light source and a case where a semiconductor laser array in which a plurality of light emitting points are arrayed monolithically on one chip is used. It is desirable to select it from a viewpoint.
[0011]
However, since a light receiving element is conventionally common to all semiconductor lasers for a semiconductor laser array, it is described in JP-A-5-75199, JP-A-5-235446, JP-A-9-321376, and the like. As a result, when a semiconductor laser array is used, it is expensive.
[0012]
In addition, as described in Japanese Patent Laid-Open No. 5-75199, Japanese Patent Laid-Open No. 5-235446, Japanese Patent Laid-Open No. 9-321376, etc., in order to remove the influence of the temperature characteristics and the droop characteristics of the semiconductor laser, etc. Although constant control is required, offset light is generated because the control is always performed at the same time. In addition, a current setting circuit or the like is required, which increases the circuit scale. Further, when a semiconductor laser array is used, means for separately detecting each light output is required.
[0013]
Further, the beam profile of a semiconductor laser is usually approximated to a Gaussian distribution, and an electrostatic latent image in an electrophotographic system is formed according to the Gaussian distribution. For this reason, the electrostatic latent image is not binary, and an analog distribution occurs as the resolution increases. This is likely to be affected by external fluctuation factors such as development bias fluctuations, and is liable to cause image density fluctuations.
[0014]
Furthermore, the pixel clock frequency setting method using a direct synthesizer as described in Japanese Patent Laid-Open No. 11-167081 can change the frequency step at high speed by changing the LUT data. The output frequency change speed is closely entangled with the control speed of the PLL-LOOP to be connected next and the low-pass filter, and becomes a constraint on the overall configuration design. Further, since the frequency increment depends on the master clock frequency and the number of bits of the LUT, it is necessary to increase the circuit scale or to increase the master clock speed in order to make fine settings. Difficulty is involved in realizing this.
[0015]
Also, as described in Japanese Patent Laid-Open No. 5-207234, in the method of adding a phase error to the PLL-LOOP, a frequency error of the pixel clock occurs unless the additional signal of the phase error is made very stable. . This is a major limitation when integrating a digital circuit and an analog circuit into a one-chip IC.
[0016]
Also, in a deflector such as a polygon scanner, the variation in the distance from the rotation axis of the deflecting reflection surface (the variation in the inscribed circle radius) causes uneven scanning speed of the light spot (scanning beam) that scans the surface to be scanned. Let After detecting the synchronization light, a write signal is generated at a predetermined timing and the semiconductor laser starts to emit light, and data for each scan is sent to each light emitting source, and the repetition is repeated to cause a latent image on the scanned medium. An image is formed as an image.
[0017]
At this time, as shown in FIGS. 33A and 33B, due to the above factors in the deflector such as a polygon scanner, unevenness (variation) in the scanning length of each scanning line appears. At the end of the image, the writing end end variation appears as an image as a fluctuation at the end of the image (the image fluctuates not only at the end end but also at the middle image height. The influence of the deflector on the image is large, and the deterioration of the image quality is conspicuous. The deterioration of the image quality due to the fluctuation of the end portion needs to be corrected when a high quality image is required.
[0018]
Further, in the case of a multi-beam optical system, if there is a difference in the oscillation wavelength of each light source, an exposure position shift occurs in the case of an optical system in which the chromatic aberration of the scanning lens is not corrected, and a light spot corresponding to each light source. However, the scanning width when scanning the medium to be scanned varies depending on the light source, which causes deterioration in image quality. Therefore, it is necessary to correct the scanning width.
[0019]
In addition, the light emitting point interval of the semiconductor laser array has a limit that can be approached due to the influence of thermal crosstalk and electrical crosstalk. In addition, it is disadvantageous in terms of cost to make several kinds of light emitting point intervals of the semiconductor laser array. However, various scanning optical systems have been developed depending on the writing density and scanning width, and the magnification of the scanning optical system is also various. Therefore, in order to obtain an arbitrary scanning pitch on the surface to be scanned, the semiconductor laser array is used by tilting the semiconductor laser array so that the pitch of the light emitting points is apparently desired in the sub-scanning direction. However, when the semiconductor laser array is tilted, the scanning start position of the light beam emitted from each light emitting point on the surface to be scanned is shifted. Even in the case of not tilting, the scanning start position on the surface to be scanned is shifted in the same manner as described above due to the positional deviation of the light emitting point caused by the processing error in manufacturing the semiconductor laser array. Since this becomes a factor of image quality deterioration, it is necessary to correct the scanning start position.
[0020]
Further, when a light source unit of a multi-beam optical system is configured by combining a plurality of semiconductor lasers, there is a problem that the scanning start position is shifted in the same manner as described above, which also causes deterioration in image quality. It is necessary to correct the position.
[0021]
In the optical system design, in order to improve the quality of the output image, the performance of the optical system (reduction in curvature of field, reduction in magnification error, reduction in scanning line bending, etc.) has been achieved. There is a limit to the number of constituent elements of the optical system, the surface configuration, and the material. In order to achieve higher performance, it is necessary to increase the number of optical elements, introduce specially shaped surfaces, and use expensive optical materials, increasing the cost of optical systems, improving design difficulty, and improving processing difficulty. The problem arises.
[0022]
The present invention has been made in view of the above problems, and can obtain a high-quality image by correcting the variation in the scanning length due to the fluctuation of the image edge that appears due to a deflector such as a polygon scanner. An object is to provide an image forming apparatus.
[0023]
The present invention also provides a low-cost and small-sized configuration in an image forming apparatus in which a light source unit is configured by, for example, a multi-beam optical system, and an image is formed by scanning a scanned medium with modulated light of a semiconductor laser based on an image signal. An object of the present invention is to provide an image forming apparatus capable of performing image forming clock and image forming timing / semiconductor laser array modulation control.
[0024]
Another object of the present invention is to provide an image forming apparatus in which a circuit for generating an image writing clock and controlling a semiconductor laser array can be efficiently housed in a one-chip IC and can be reduced in size, speed and cost. With the goal.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, the first means scans the scanned medium by deflecting the light beam modulated according to the image data in the scanning direction by the plurality of deflecting surfaces of the deflector in synchronization with the output pixel clock. In the image forming apparatus, the output pixel clock of the output pixel clock is corrected so as to correct a variation in each scanning length when scanning by deflecting in the scanning direction by the plurality of deflecting surfaces of the deflector. The time width of one pixel by controlling the phase For each predetermined pixel interval System And a clock phase frequency control means for controlling the frequency of the output pixel clock for each of the deflection surfaces.
[0026]
The second means is the first means The clock phase frequency control means divides the high-frequency clock output from the high-frequency clock generation means and the high-frequency clock generation means to generate the output pixel clock, and controls the phase of the output pixel clock. A first frequency dividing unit capable of changing a time width of one pixel, and a high frequency clock output from the high frequency clock generating unit, and the same frequency as the output pixel clock generated by the first frequency dividing unit And a second frequency dividing means for generating an image data capturing clock having a different phase, and a phase changing means for changing the phase of the image data capturing clock generated by the second frequency dividing means. It is characterized by that.
[0027]
The third means is the second means. The high-frequency clock generation means includes a voltage-controlled oscillation circuit, a programmable counter that divides the output of the voltage-controlled oscillation circuit, and a phase comparison circuit that compares the phase of the output of the programmable counter and a reference frequency. A PLL circuit is configured, and the first frequency divider divides the output of the voltage controlled oscillation circuit to generate the output pixel clock and synchronizes the phase of the output pixel clock with a phase synchronization signal. It is characterized by that.
[0028]
The fourth means is The third means further includes a modulation pattern generation circuit that generates a modulation pattern that obtains an optimal exposure energy distribution based on image data in synchronization with the output pixel clock. It is characterized by that.
[0029]
The fifth means is The first frequency dividing means and phase changing means in the second means, the PLL circuit in the third means, and the modulation pattern generating circuit in the fourth means are configured in a common IC. It is characterized by that.
[0030]
The sixth means In the fifth means, the semiconductor laser modulation driving circuit is further configured in the common IC. It is characterized by that.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0033]
Here, the following description is based on a multi-beam optical system, but the present invention can obtain the same effect even when there is one light source, and is not particularly limited to the number of light sources. However, in the case of a multi-beam optical system using a plurality of light sources, since a plurality of light beams simultaneously scan the scanned medium, variations at the scanning end are easily noticeable, and the present invention is more effective.
[0034]
FIG. 1 shows an embodiment of a multiple beam scanning device. A light source device 10 shown in FIG. 1A has a light source unit having a plurality (two in this example) of light emitting units 11a and 12a and an emission from each of the light emitting units 11 and 12, as shown in detail in FIG. Coupling lenses 13 and 14 for coupling the divergent light flux. The coupling lenses 13 and 14 convert the divergent light beam into a “light beam form suitable for the subsequent optical system (for example, a parallel light beam, a weak divergent light beam, a convergent light beam, etc.)”. In this embodiment, as shown in FIG. 1A, the coupled light beams are emitted from the light source device 10 as “parallel light beams B1 and B2,” and deflected by a cylindrical lens 3 as a line image imaging system. In the vicinity of the deflecting and reflecting surface of the rotary polygon mirror 4 serving as a mirror, an image is formed in a substantially linear shape in the main scanning direction.
[0035]
The two light beams deflected by the deflecting reflecting surface pass through the imaging lenses 5 and 6 while being deflected at a constant angular velocity as the rotary polygon mirror 4 rotates at a constant speed, and then the optical path is bent by the optical path bending mirror 7. By the action of 5 and 6, the light is condensed as a light spot on the photosensitive surface of the photosensitive member 8 which is the surface to be scanned, and two scanning lines on the surface to be scanned are scanned. The two light spots are formed at a desired interval (scanning pitch) in the sub-scanning direction.
[0036]
The relative positional relationship between the light emitting units of the light source unit is an imaging system between the light source unit and the surface to be scanned (in this embodiment, the coupling lenses 13 and 14, the cylindrical lens 4, the imaging lens 5, The “desired scanning line pitch” is determined according to the composite magnification M in the sub-scanning direction 6).
[0037]
Here, as shown in FIG. 1B, the light source device 10 separately couples the divergent light beams from the two semiconductor lasers 11 and 12 by the coupling lenses 13 and 14 corresponding to the respective semiconductor lasers. The beam is combined using a beam combining prism 15. The beam combining prism 15 has a polarization separation film 15A, and the light beam from the coupling lens 13 is transmitted through the polarization separation film 15A. The light beam from the coupling lens 14 is rotated 90 degrees from the initial state by the half-wave plate 16, and is sequentially reflected by the prism surface and the polarization separation film 15 </ b> A and emitted from the beam combining prism 15.
[0038]
The optical axes (indicated by chain lines) of the coupling lenses 13 and 14 are parallel to each other, and after the beam combining prism 15, they are combined into a single combined optical axis AX as shown in the figure. In FIG. 1B, the vertical direction is the sub-scanning direction. The light emitting portions 11a and 12a of the semiconductor lasers 11 and 12 are displaced in the sub-scanning direction (in opposite directions) with respect to the optical axes of the corresponding coupling lenses 13 and 14, respectively. The combined light beams B1 and B2 form an angle with each other in the sub-scanning direction.
[0039]
The light source unit is not limited to the one shown in FIG. For example, a “semiconductor laser array in which a plurality of light emitting portions are monolithically arrayed” may be used, and a plurality of divergent light beams emitted from the light emitting portions may be coupled by a common coupling lens.
[0040]
The light emitting point interval of the semiconductor laser array has a limit (˜14 μm) that can be approached due to the influence of thermal crosstalk and electrical crosstalk. In addition, it is disadvantageous in terms of cost to make several kinds of light emitting point intervals of the semiconductor laser array. However, various scanning optical systems have been developed depending on the writing density and scanning width, and the magnification of the scanning optical system is also various. Therefore, in order to obtain an arbitrary scanning pitch on the surface to be scanned, the sub-scanning direction is obtained by tilting the semiconductor laser array. of The pitch is used in such a manner that it appears to be a desired pitch. As shown in FIG. 2 (this example is an example of a semiconductor laser array with four emission points), by tilting the semiconductor laser array with the emission point interval P by an angle θ, as shown in FIG. The pitch is equal to Pcosθ in the scanning direction. By doing so, the scanning pitch in the sub-scanning direction can be set to any desired pitch.
[0041]
However, when the semiconductor laser array is tilted, as shown in FIG. 2B, the position of the light emitting point in the main scanning direction is shifted by the distance d, thereby causing the light beam emitted from each light emitting point on the surface to be scanned. The scanning start position is also shifted. In that case, the amount to be multiplied by the magnification of the entire optical system in the main scanning direction is shifted on the surface to be scanned. Even in the case of not tilting, the scanning start position on the surface to be scanned is shifted in the same manner as described above due to the positional deviation of the light emitting point caused by the processing error in manufacturing the semiconductor laser array. As described above, the deviation of the position of the light emitting point in the main scanning direction causes the final deterioration of the image quality. Therefore, it is necessary to correct the scanning start position.
[0042]
Next, FIG. 3 shows a specific perspective view of a four-beam light source unit using a total of four general-purpose semiconductor lasers. In FIG. 3, the semiconductor lasers 101 and 102 are respectively press-fitted and supported in fitting holes (not shown) formed in parallel on the back side of the aluminum die-cast support member 103 at intervals of about 8 mm in the main scanning direction. They are arranged in a row symmetrically with respect to the injection axis. The collimating lenses 104 and 105 are paired with the semiconductor lasers 101 and 102 by aligning the X position so that the divergent light beams of the respective semiconductor lasers become parallel light beams and the Y and Z positions so as to be in a predetermined beam emission direction. The first light source unit is configured by filling and fixing the UV curing adhesive in the gap between the U-shaped support units 103-1 and 103-2 formed in the above. Similarly, the second light source unit is configured by pressing the semiconductor lasers 106 and 107 into the support member 108 and fixing the collimating lenses 119 and 109.
[0043]
The first and second light source portions are arranged symmetrically with respect to the x-axis, and cylindrical portions 103-6 and 108-6 whose centers coincide with the respective emission axes (first and second emission axes) are base members. The cylindrical part is engaged with the fitting holes 110-1 and 110-2 from the back side of 110, and each of the positioning parts 103-3, 103-4, 103-5 and 108-3, 108-4, 108-5 The three points are brought into contact with each other as a reference, and the positioning portions 103-3, 103-4, 108-3, and 108-4 are fixed through screws from the front side of the base member.
[0044]
The base member supports a plate 111 provided with an aperture corresponding to each semiconductor laser, and a beam combining prism 112 that emits the beams of the semiconductor lasers 106 and 107 close to the optical axes of the semiconductor lasers 101 and 102. The base member configured as described above is held by the holder member 113 and attached to an optical housing (not shown) that houses the scanning optical means with the center of the cylindrical portion 113-1 being aligned with the optical axis of the scanning optical means. Then, a plurality of beams are made incident on the scanning optical means. Further, the lever 113-3 is moved up and down with the adjusting screw 115 so as to be rotatable about the cylindrical portion 113-1.
[0045]
As a result, the scanning line is tilted due to an arrangement error of the scanning optical system, and the beam array can be tilted in accordance with the scanning line. The substrate 114 on which the drive circuit of each semiconductor laser is formed is fixed to the support 113-2, and the circuit connection is made by soldering the lead of the semiconductor laser.
[0046]
In the light source device having a plurality of light emitting units as described above, the oscillation wavelength of each light emitting unit is different, so that each of the surfaces to be scanned is scanned by the chromatic aberration of the imaging lenses 5 and 6 shown in FIG. This causes a phenomenon that the magnification of the scanning light is different and the exposure width is different. Similarly to the case where the semiconductor laser array is tilted, as is apparent from FIG. 3, the light emitting point position in the main scanning direction is shifted so that the scanned surface of the light beam emitted from each light emitting point. The scanning start position above is also shifted. Since the deviation of the scanning start position in the main scanning direction becomes a factor of final image quality degradation as in the case where the semiconductor laser array is tilted, it is necessary to correct the scanning start position.
[0047]
In other words, the displacement of the position of the light emitting point can be rephrased as “when the relative position of each light emitting point of the semiconductor laser is different with respect to an axis orthogonal to the deflection scanning plane (main scanning plane)”. In such a state, that is, when there is no relative position of each light emitting point on an axis orthogonal to the deflection scanning plane, the scanning start position of the light spot on the scanned surface is shifted in the main scanning direction, The writing end portion becomes an “unsteady” image.
[0048]
In FIG. 4, waveform (4) is an example of a conventional light modulation pulse. Further, exposure is performed when the beam profile has a Gaussian distribution in an optical system in which the semiconductor laser beam of the light modulation pulse (4) is collimated by a collimator lens and then imaged on the surface of the photosensitive body through a scanning optical system. The energy distribution is shown in (2). On the other hand, in the case of the present invention, the light pulse has a pattern as shown in (3), and the exposure energy distribution by the same optical system when exposed with the pattern (3) is shown in (1). FIG. 5 shows an example in which the conventional modulated light pulse width is narrowed, and shows the exposure energy distribution in which the light modulation pattern of the present invention is changed to correspond to this.
[0049]
FIG. 6 shows a conventional example when the above pulse widths are sequentially changed, and FIG. 7 shows an exposure energy distribution when the pulse width is changed by the modulation pattern of the present invention. The light modulation pattern shown in FIG. 7 is a combination of the light pattern shown in FIG. 4, the thin first optical pulse train (3) symmetrical in right and left as shown in FIG. 5, and the second pulse (4) emitted at the center. It is. The interval between the first pulses {circle around (3)} is narrowed when the exposure energy distribution is narrowed, thickened when thickened, and in this case the second pulse {circle around (4)} is set at the center of the exposure energy distribution. Is to suppress the decrease of.
[0050]
As can be seen from the above figures, a steep exposure energy distribution close to when the light beam diameter is reduced by about 20% can be obtained by exposure with the light pulse of the present invention. By doing so, a surface potential distribution similar to that obtained when the beam surface diameter of the photoreceptor surface potential distribution is made narrower can be obtained, so that an image having a good granularity (S / N ratio) can be obtained. .
[0051]
Further, although the scanning optical system has been described for the modulation of the laser beam, it is an effective method even when the object irradiated with the laser light is rotating (for example, an optical disc or the like).
[0052]
FIG. 8 shows a pulse modulation unit (Pulse-Modulation-Unit) 300 for generating the optical modulation pulse train. In FIG. 8, Clock is a clock for transferring image data. Input image data is converted into data corresponding to a modulated pulse train by a LUT (Look-up-table) 301, and this modulated data is loaded into a shift register (Shift-Register) 302 in response to a Load signal. On the other hand, a high-frequency clock VCLK that multiplies the frequency of the clock clock by eight is converted into a phase comparator (Phase-Detector) 303, a loop filter (Loop-Filter) 304, a voltage controlled oscillator (VCO) 305, 1 / The frequency divider 306 generates the data and outputs modulation data (Modulation Data) of the shift register 302 in accordance with the VCLK signal.
[0053]
In this way, the optical pulse (3) shown in FIG. 5 is generated from the data shown in FIG. 9, and the optical pulse (3) shown in FIG. 4 is generated from the data shown in FIG. . Further, here, by adopting a configuration in which the image data is converted by the LUT 301, even when the laser scanning optical system is changed, only the contents of the LUT 301 are changed, and an optical pulse as shown in FIGS. (3) can be freely selected. With such a configuration, a light modulation pulse with a high degree of freedom can be generated, and an image with good graininess can be obtained by the light pulse generation according to this configuration.
[0054]
FIG. 11 shows an LD control unit 310 and an LD peripheral circuit for controlling and modulating the semiconductor laser in accordance with the modulation data from the pulse modulation unit 300 shown in FIG. The operation will be described below with reference to FIG. In the case of the optical output P0 by the control circuit 311, the voltage generated by the output current of the light receiving element PD that receives the light of the semiconductor laser LD (the photoelectromotive current is converted into a voltage via the variable resistor REXT) is supplied to the XPD terminal. This is detected and compared with the VCONT voltage, and the control result is held by a capacitor (Hold-Capacitor 1) connected to the XCH terminal.
[0055]
On the other hand, when the optical output is P1, it is controlled in the same manner and is held by the capacitor (Hold-Capacitor 2). Assuming that the optical output is a straight line with respect to the voltage between P1 and P0 (in fact, this linearity is accurately established by the IL characteristic of the semiconductor laser), it is modulated in multiple stages.
[0056]
The modulation data from the pulse modulation unit (Pulse-Modulation-Unit) 300 is Dn (data that changes at the speed of the pixel clock VCLK), the semiconductor laser drive current is In, and the capacitors (Hold-Capacitor1) and (Hold-Capacitor2). When V1 is V1, V2, and P1 = P0 / 2
In = {(V0−V1) × Dn + V1} / RE
Where Dn = −1 to 1
Is set by the control circuit 311 and the modulation signal generation circuit 312.
[0057]
In this manner, the optical pulse pattern of the semiconductor laser LD can be generated according to the output data from the pulse modulation unit 300, and the exposure energy distribution in FIGS. 4 and 5 can be generated relatively easily. An image with good graininess can be obtained.
[0058]
Here, in the pulse modulation unit 300 shown in FIG. 8, the configuration is shown in which the high-frequency clock VCLK having a frequency that is eight times the pixel clock CLK is generated from the pixel clock CLK. Generated. When the semiconductor laser LD is used as a light source, an exposure (scanning) position shift due to chromatic aberration (so-called magnification chromatic aberration) of the scanning optical system occurs due to laser oscillation wavelength jumping or differences in oscillation wavelengths of a plurality of light emitting portions. Therefore, a pixel clock generation circuit that can finely adjust the pixel clock is required.
[0059]
For example, when the number of pixels for one scan is 14,000, the pixel clock frequency is 60 MHz, and the pixel position accuracy at both ends of the scan is 1/4 pixel width, this frequency can be set with a single PLL.
60 MHz / (14000 × 4) = 1.07 kHz
Therefore, the PLL must be controlled with a reference clock of about 1 kHz. As a result, the phase variation amount of the PLL can be detected only every 1 kHz, and the control bandwidth as the PLL decreases. Furthermore, it becomes vulnerable to disturbances and the like, and in order to improve the pixel position accuracy, the demand for the stability of the VCO 305 constituting the PLL becomes very high. In order to avoid this, there is a method using a double PLL or the like. However, by having such a circuit separately, the jitter of the PLL circuit is accumulated twice, causing an increase in jitter. In addition, the cost is high.
[0060]
FIG. 12 shows an embodiment in which VCLK signal generation and pixel clock generation are realized while solving this problem. The operation will be described below with reference to FIG. In the circuit shown in FIG. 12, the phase frequency comparison circuit 322 that compares the reference clock and the result obtained by dividing the VCLK signal by N by a programmable counter (Programmable-Counter) 321 and the result of the phase frequency comparison circuit 322 are filtered. A VCLK signal is generated by a PLL loop including a loop filter (Loop-Filter) 323 and a VCO 324 whose oscillation frequency changes according to the output voltage of the loop filter 323. Further, the frequency division ratio N of the programmable counter 321 is set by the frequency division ratio setting from the outside.
[0061]
In this way, the VCLK signal is generated, and by loading the data = 0 from the load pulse generator 325 to the 1/8 frequency divider 326 by the VCLK signal and the phase synchronization pulse, the pixel clock phase-synchronized with the phase synchronization pulse. Is generated at a frequency 1/8 of the VCLK signal.
[0062]
This circuit also uses preset phase data at similar timing. Load from load pulse generator 325 Then, the 1/8 frequency divider 327 for generating an internal clock having a phase difference from the pixel clock is provided. The 1/8 frequency divider 327 is not necessary when the pixel clock is slow. Further, it is not necessary if the time delay until image data is transferred is not a problem.
[0063]
However, when the frequency of the pixel clock is high, when capturing image data from the outside synchronized with this output, the delay time from the output of this pixel clock to the input of image data becomes a problem, and data can be captured correctly. Disappear. Such a case can be avoided by making the phase of the image data capturing clock variable with respect to the output pixel clock based on the preset phase data as in this embodiment.
[0064]
Further, in this embodiment, the count (frequency division) of the 1/8 frequency dividing circuits 326 and 327 can be enabled / disabled by the Phase-Set signal. In this embodiment, the rising edge of the Phase-Set signal is captured by VCLK, and the count (frequency division) operation for one clock cycle of VCLK is stopped. By doing so, the phase of the pixel clock and the internal clock can be delayed in 1/8 clock steps. By executing the phase delay amount of 1/8 clock cycle at a predetermined interval (or close to a predetermined interval) during one scanning period, the frequency of the pixel clock in one scanning period can be finely adjusted equivalently. become. This is equivalent to the fact that the frequency variable step that can be set by PLL-LOOP can be set more finely.
[0065]
On the contrary, in the fine adjustment, when 1/8 clock is advanced, as shown in FIG. 13, instead of loading data = 0, data = 1 is loaded and the frequency division number is changed from 8 → 7. The clock can be shortened. At this time, when the load data is set, the data is output from the register 329 to the frequency dividing circuit 326-1. However, when the frequency dividing number = 7 is output, the data is shortened and the frequency dividing number = 9 is output. If it happens, it will be extended.
[0066]
As another method, the original pixel clock is shortened and set short, and the phase of the pixel clock and the internal clock is gradually increased at a predetermined interval (or an interval close to the predetermined interval) in one scanning period. Is delayed in 1/8 clock increments to obtain a desired image with fine adjustment.
[0067]
Here, when the light emitting part of the semiconductor laser LD, which is a light source part, is a multi-beam optical system composed of a plurality of light emitting parts, if the emission wavelength of each light emitting part is different, the scanning surface is scanned and imaged Due to the chromatic aberration of the scanning optical system, a difference occurs in the scanning width of the scanning light from each light emitting section, causing image position deviation for each scanning line and density unevenness in the highlight section, which causes image degradation.
[0068]
This difference in scanning width can be corrected by using the above-described phase shift, and writing can be performed at a desired target writing position. The light emitting portion whose scanning width is extended may be shifted so as to be shortened, and the light emitting portion whose scanning width is reduced may be shifted so as to be long. On the other hand, in the case where the original image clock is shortened in advance and set to be short, it is only necessary to cope with this by changing the shift amount between the light emitting portion where the scanning width is extended and the light emitting portion where the scanning width is reduced.
[0069]
Here, when the semiconductor laser array is tilted, as described above, as shown in FIG. 2B, the light emitting point positions in the main scanning direction are shifted by the distance d, so that the light is emitted from each light emitting point. The scanning start position on the surface to be scanned of the emitted light beam is also shifted. In that case, the amount to be multiplied by the magnification of the entire optical system in the main scanning direction is shifted on the surface to be scanned.
[0070]
This is shown in FIG. 14, which shows the relationship between the intervals between the plurality of light emitting points and the intervals between the plurality of light spots on the surface to be scanned in the main scanning section. In FIG. 14, the light beam emitted at the interval d scans the surface to be scanned at the interval d ′ due to the magnification relationship according to the ratio of the focal lengths of the coupling lenses 13 and 14 and the imaging lenses 5 and 6. It is the figure which expressed typically. The scanning light beam scans the surface to be scanned as a light spot by the focusing action of the imaging lenses 5 and 6. As described above, when each light spot is scanned with d ′ shifted in the main scanning direction, and the magnification of the entire optical system in the main scanning direction is βm
| D '| = | βm · d |
The relationship holds.
[0071]
On the other hand, even if it is not tilted, the scanning position on the surface to be scanned is shifted in the same manner as described above due to the positional deviation of the light emitting point caused by the processing error in manufacturing the semiconductor laser array.
[0072]
Similarly to the case where the semiconductor laser array is tilted, the light source portion is configured by a plurality of semiconductor lasers, and the light emission point position is shifted in the main scanning direction. The scanning start position on the surface to be scanned is also shifted. Since the deviation of the scanning start position in the main scanning direction becomes a factor of final image quality degradation as in the case where the semiconductor laser array is tilted, it is necessary to correct the scanning start position.
[0073]
In other words, the deviation of the position of the light emitting point can be changed to the case where the relative position of each light emitting point of the semiconductor laser with respect to the axis orthogonal to the deflection scanning plane (main scanning plane) is different. In such a state, that is, when there is no relative position of each light emitting point on the axis orthogonal to the changed scanning plane, the scanning start position of the light spot on the scanned surface is shifted in the main scanning direction, The writing end part becomes a rattling image.
[0074]
FIG. 15 schematically shows scanning of a light spot on the surface to be scanned. By tilting the semiconductor laser array, the light spot that scans the surface to be scanned is scanned at intervals of d ′. At this time, light is oscillated from the semiconductor laser array in accordance with the image modulation signal after a predetermined timing based on the detection signal from the synchronization detection optical system (scanning light detection means) disposed in front of the image area, An electrostatic latent image is formed on the scanning surface. At this time, the semiconductor laser array takes other light emitting points and oscillation timing based on the light beam that first traverses the synchronous detection optical system. For this reason, in this state, the writing start position of the light spot by each light emitting point is deviated in the image area, which causes image deterioration.
[0075]
Therefore, by the method described above, the phase is shifted and delayed so that the image information is started to be written at the timing when the light beam for writing the image area at the end reaches the image area. The start position of the electrostatic latent image can be adjusted. Assuming that d ′ is N / 8 clock length, in the case of a semiconductor laser array having four light emitting points as shown in FIG. 15, the control signal for the most advanced scanning light is 3 * N / 8 clock shift. If you do, you can match the last. Similarly, the second may be shifted by 2 * N / 8 clock, and the third may be shifted by N / 8 clock.
[0076]
In the above example, the last scanning light is used as a reference, but any reference may be used. In that case, it may be shifted so as to be arbitrarily short, or shifted so as to be long. As described above, even when the semiconductor laser array is tilted, it is possible to align the image writing end portions.
[0077]
When it is actually desired to set the PLL-LOOP frequency variable step in detail, the frequency division setting range of the programmable counter 321 shown in FIG. 13 is widened, and the reference clock is lowered or the VCLK signal is increased. However, if the reference clock is lowered, frequency fluctuations of the VCLK signal can be detected only in the reference clock cycle, and stabilization of the oscillation frequency of the VCO 324 becomes a major technical problem.
[0078]
For example, when the number of pixels for one scan is 14,000, the pixel clock frequency is 60 MHz, and the pixel position accuracy at both ends of the scan is 1/4 pixel width, this frequency can be set with a single PLL.
60 MHz / (14000 × 4) = 1.07 kHz
Therefore, the PLL must be controlled with a reference clock of about 1 kHz. As a result, the phase variation amount of the PLL can be detected only every 1 kHz, and the control bandwidth as the PLL decreases. Furthermore, it becomes vulnerable to disturbances and the like, and in order to improve the pixel position accuracy, the demand for the stability of the VCO 324 constituting the PLL becomes very high. In order to avoid this, there is a method using a double PLL or the like. However, by having such a circuit separately, the jitter of the PLL circuit is accumulated twice, causing an increase in jitter. In addition, the cost is high. On the other hand, increasing the VCLK has to increase the oscillation frequency of the VCO 324, which is also a technical problem.
[0079]
However, according to the present invention, if the oscillation frequency of the VCO 324 can be increased, the frequency can be set in a step exceeding that, and if the VCO 324 can be stabilized, the frequency can be set in a step exceeding that. Further, the discontinuity of the exposure energy amount can be eliminated by preventing the semiconductor laser from emitting light for 1/8 clock cycle in which the phase delay due to the Phase-Set signal is generated.
[0080]
Further, the Phase-Set signal may be set when the semiconductor laser does not emit light. You may set in the position shifted a little for every scanning. It may be set only on the first line of the page. Further, it may be set at a preset time interval while the apparatus is powered on. The time interval may be measured by incorporating an internal clock of the apparatus, or may be measured by a method such as a time counter.
[0081]
By changing the phase delay amount at such timing, the pixel clock phase can be changed without affecting the output image. In addition, the Phase-Set signal is increased or decreased only at the scanning start timing for each scanning (for example, 1/8 → 2/8 → 3/8 → 4/8 → 5/8 → 6/8). → 7/8 → 0) By changing the position, the position of each pixel can be controlled every 1/8 clock cycle.
[0082]
By doing so, a high-quality image can be obtained by finely adjusting the screen angle of image output. Further, by making it possible to arbitrarily change the setting timing of the phase change circuit, various cases can be dealt with.
[0083]
In the configuration shown in FIG. 16, an N-ary counter (N-Counter) 330 is added to the configuration shown in FIG. 12, and the N-ary counter 330 automatically generates a phase-set signal every N-counts with an internal clock. In addition, the 1/8 pixel clock phase is delayed. In this embodiment, the optical pulse is not output for a time of 1/8 clock. Even in this case, the exposure energy distribution does not become discontinuous as shown in FIG. 4 (because the light is extinguished only for a sufficiently short time with respect to the beam diameter of the semiconductor laser LD, and at the timing of pixel separation. Because there is).
[0084]
Note that the count value N of the N-ary counter 330 can be set by serial data from the outside. By doing in this way, since the frequency of the step which cannot be set by PLL-LOOP can be set by serial data, the frequency step can be set finely equivalently.
[0085]
Variation in the distance from the rotation axis (center) of the deflecting and reflecting surface of a deflector such as a polygon scanner (inscribed circle radius variation) is a variation in the scanning width of the light spot (scanning beam) that scans the surface to be scanned. Is generated. After detecting the synchronous light, a writing signal is emitted at a predetermined timing, the semiconductor laser starts to emit light, and data for one scan is sent to each light emitting source, and the latent image is formed on the scanned medium by repeating the process. As shown in FIG. At this time, due to the above factors in the deflector such as a polygon scanner, the unevenness (variation) of the scanning length of each scanning line appears, and as with the writing magnification error, it stands out mainly at the edge of the image, and the variation of the writing end point Appears as a fluctuation at the edge of the image.
[0086]
According to the present invention, this variation in scanning width is also corrected by shifting the phase of the pixel clock and the internal clock. Do (Adjust the writing end). Variations in scanning width caused by the deflector occur when the deflecting / reflecting surface changes, and periodically occur in accordance with the period of the deflecting / reflecting surface. Therefore, it is necessary to determine which surface of the deflecting reflecting surface is deflected and scanned. As an example of the method, marking is performed on the upper surface of the deflector, and it can be recognized that the rotation is performed once every time the mark is read. In addition, an input signal is obtained by the synchronous detection system before the start of each scan, and it can be determined which surface is currently scanned by these two types of information.
[0087]
Referring to FIG. 17, the 1 / n counter (1 / n Counter) 331 is reset by a mark detection signal from the deflector, starts counting the synchronization pulse signal again after the reset, 3..., The n-plane is counted and reset again by the mark detection signal from the deflector. By repeating this, it is possible to determine on which surface of the deflector the deflection scanning is performed.
[0088]
In FIG. 18, a line counter 333 and a count value setting unit 334 are added to the configuration shown in FIG. Since the scanning width is expanded and contracted by the deflecting / reflecting surface, information for each surface is stored in the count value setting unit 334 as line information, and an identification signal indicating which surface the line counter 333 scans the surface to be scanned next. Accordingly, this line information is loaded into the N-ary counter 330, and it is determined how to shift the phase of the pixel clock and the internal clock based on the information. That is, the number of reflection surfaces of the identified deflector is loaded with line information into the N-ary counter 330 based on the data from the line counter 333, the count value is set, and the Phase-Set signal is generated by the N-ary counter 330. Shift. The above operation is not limited to the number of light sources, and is the same, and has the same effect even when the number of light sources is one or a plurality of light sources.
[0089]
FIG. 19 is a timing chart for controlling the phase of the internal clock with respect to the pixel clock in accordance with the phase data. From the top, the VCLK signal, the synchronization pulse, the reset signal, the pixel clock, the image data, the Reset2 signal, and the internal clock. Indicates. Further, the operation of FIG. 19 is configured to operate only when the phase detection set signal = L. By doing so, the synchronization pulse is always valid when the phase detection Set signal = L, and the phase relationship between the internal clock and the image data is controlled. On the other hand, by setting the phase detection Set signal = L only at the first timing of power-on, the initially set phase difference can be maintained.
[0090]
FIG. 20 shows a method in which the number of bits of the LUT 301 is reduced as compared with the case of FIG. 8, and the left and right independent pulses can be selected based on the center of one pixel. In addition, a generation method for generating a pulse at an arbitrary position by setting a selection table for selecting an 8-phase pulse (shown in FIG. 21) when the VCLK signal is divided by 8 instead of the shift register 302 is shown. Is. By doing so, the selectable pulse train range is narrower than in FIG. 8, but the circuit scale of the LUT 301 is reduced, and an effective method is obtained at a low cost when obtaining optical pulses as shown in FIGS. Can be realized.
[0091]
FIG. 22 shows a configuration for a semiconductor laser having a common cathode in an LD drive circuit that controls the peak value of the light output intensity and the bias current of the semiconductor laser. In the figure, the light output of the semiconductor laser LD is detected by the light receiving element PD, and the detected result is converted into a voltage by an error amplifier (Error-Amp1) 341 and compared with a reference voltage (Refference Voltage). Control is held in (Hold-Capacitor1). In this embodiment, the control result of the error amplifier (Error-Amp2) 342 is held in the capacitor (Hold-Capacitor2) so that the voltage at the RE terminal is controlled so that VCC = 80 mV.
[0092]
The control timing of the error amplifier 341 is controlled with a delay of a certain time when the LDON signal for emitting the semiconductor laser LD is active. Further, the error amplifier 342 is controlled to be delayed by a certain time when the LDON signal is inactive so that the bias current when the semiconductor laser LD is turned off becomes a constant value.
[0093]
In this way, by starting the control with a certain time delay from the LDON signal, the light receiving current of the light receiving element and the light receiving current are converted into voltage from the light output of the semiconductor laser LD, and the delay in signal transmission to the error amplifier 341 is achieved. An error due to time is avoided.
[0094]
The same applies to the bias current control timing. Further, by connecting the semiconductor laser LD to the emitter of the bipolar transistor 343, the base voltage of the bipolar transistor 343 is transmitted to the semiconductor laser LD so as not to cause a delay as much as possible. Therefore, in this configuration example, a predetermined optical output is obtained by setting the voltage between the terminals of the semiconductor laser LD to a predetermined voltage. By doing so, the semiconductor laser LD can be modulated at high speed.
[0095]
FIG. 23 shows an LD driving circuit when a common anode semiconductor laser LD is used as a modification of FIG. In this embodiment, as compared with FIG. 22, the semiconductor laser LD is connected to the collector of the transistor 343. In this way, it can be realized with a circuit similar to that of the semiconductor laser LD having a cathode common. As a result, it is possible to make the anode common and cathode common semiconductor lasers LD usable on the same IC.
[0096]
In FIG. 24, in order to generate the timing for controlling the semiconductor laser LD, the capacitor C1 is rapidly charged when the LDON signal = H, and the charge of the capacitor C1 is discharged with a constant current when the LDON signal = L. When it comes, control is lost. By doing so, compared to a simple delay circuit + logic circuit configuration, the control value is held for a narrow pulse train, and the control accuracy is improved.
[0097]
25, when the semiconductor laser LD is connected as shown in FIG. 22 and FIG. 23, the terminal voltage of the light receiving element PD for detecting the light of the semiconductor laser LD changes with reference to GND when the anode common is used. In the case of the cathode common, the semiconductor laser LD of the anode common is connected when the terminal voltage of the light receiving element PD is equal to or less than VCC / 2, using the property of changing with respect to VCC. It can be seen that the common semiconductor laser LD is connected.
[0098]
FIG. 25 shows a circuit that realizes this. By doing so, it is possible to automatically determine whether it is the anode common semiconductor laser LD or the cathode common semiconductor laser LD, and to change the control direction according to FIGS. 22 and 23. The same circuit (IC) can be used for both the cathode common semiconductor laser LD.
[0099]
FIG. 26 summarizes the above-described matters and is an embodiment in the case where it is realized as a one-chip IC. In this embodiment, the pixel clock frequency is the same, the synchronization signal can be controlled independently by two types, and the circuit portion for controlling and modulating the semiconductor laser has two channels. In the figure, a reference power supply circuit (Voltage-Reference) 350 is the whole of the present IC, and supplies reference power supplies VREF and IREF to other circuit blocks. A phase detector (Phase-Detector) 351, a VCO 352, a clock driver (Clock-Driver) 353, and an 11-bit programmable counter (11BIT-Programmable-Counter) 354 constitute a PLL-LOOP circuit. Of the set 12-bit data, the lower 1 bit is set so as to delay the phase of the output clock VCLK of the clock driver by π, and the upper 11 bits set the division ratio of the programmable counter 354. Thus, the frequency of CLK is F-REF × N / 2 (N: 12-bit data).
[0100]
Further, the X reset pulse generator (XResetPulse-Generator) 356X and the Y reset pulse generator (YResetPulse-Generator) 356Y respectively detect the main scanning synchronization from the detect pulse selector 358 (DETP1 signal, DETP2 signal). The Xreset signal, the Yreset signal, and the XCLK signal and the YCLK signal, which are selected to be normal or inverted, are sent to the X divider driver (XDivider-Drive) 357X and the Y divider driver (YDivider-Driver) 357Y. Output to.
[0101]
The drivers 357X and 357Y respectively divide the frequency by four in accordance with the Xreset signal, the Yreset signal, the XCLK signal, and the YCLK signal, and output pixel clocks XPCLK and YPCLK synchronized with the XDETP signal and the YDETP signal from the selector 358, respectively.
[0102]
Further, according to the timing chart as shown in FIG. 27, the pixel clock can be delayed by 1/8 phase according to the rising edge of the ADPphase signal and the BDPphase. As a result, the start position of the pixel clock can be delayed and controlled every 1/8 clock cycle for each line scan.
[0103]
In addition, the pixel clock frequency can be equivalently changed to FCLK × N / (N + M / 8) by providing M rising edges during the scanning period of one line. Further, as shown in the timing chart of FIG. 27, by generating the ALDMASK and BLDMASK signals, the pixel clock is delayed by 1/8 clock cycle, and the semiconductor laser is forcibly turned off at the timing. The concentration is kept from changing suddenly.
[0104]
In this case, the semiconductor laser LD is automatically turned off, but it is not necessary to forcibly turn off the light by previously reducing the density by 1/8 from the image data. As described above, when the image data is previously reduced by あ ら か じ め, the LDMASK signal is invalidated by setting the MaskEN signal to high.
[0105]
FIG. 28 shows an embodiment in the case where the optical modulation pulse is generated according to a predetermined rule.
[0106]
In FIG. 29, by writing a program code to the code area program counter 402 by the serial interface 401, the effective writing period of image data, density pattern generation for electrophotographic process control, detection of isolated dot, and correspondingly This is an embodiment in which a unit that performs image data conversion processing is configured to realize the above described items.
[0107]
In FIG. 29, the ALU 403 operates with the output clock of the clock generator 404 (eight times the pixel clock). The program code is controlled so as to have a predetermined program count value for each synchronization signal. As described above, the ALU 403 processes the image data transferred from the speed conversion RAM 405 and sends the processing result to the LD controller 406. The LD controller 406 modulates the semiconductor laser LD according to this data. In FIG. 29, the speed conversion RAM 405 is a buffer memory for absorbing the speed difference between the clock transferred to the IC and the write clock.
[0108]
FIG. 30 shows a modification of FIG. 29, in which a register 408 and a shift register 409 are added to the front and rear stages of the ALU 403, respectively. In FIG. 30, the ALU 403 writes the operation result to the shift register 409 and writes a data pattern corresponding to the light modulation pattern for one pixel once in 8 clock cycles of the clock generator 404. The modulation data is transferred to the LD controller 406 according to the clock.
[0109]
In FIG. 31, a configuration for adding shading data is added to the configuration shown in FIG.
[0110]
【The invention's effect】
As described above, according to the first aspect of the present invention, the variation in scanning length (difference in the optical scanning width of each scanning line) caused by a deflector such as a polygon scanner, and the accompanying image end portion appear. Image fluctuation can be corrected.
[0111]
According to the second aspect of the present invention, in the image forming apparatus constituting the light source unit by the multi-beam optical system, the phase difference between the output image (pixel) clock and the internal clock can be set. The image data transfer delay time with the connected image data transfer circuit block can be set to be appropriate, so that the semiconductor laser can be controlled simultaneously with high-speed image (pixel) clock generation, and the IC is provided. it can.
[0112]
According to the invention described in claim 3, the degree of freedom in setting the frequency of the high-frequency clock is improved, the image (pixel) clock can be synchronized with the writing position, and the semiconductor laser is controlled simultaneously with the high-speed image (pixel) clock generation. And the IC can be provided.
[0113]
According to the fourth aspect of the present invention, the degree of freedom in setting the frequency of the high-frequency clock is improved, and a high-speed light modulation pattern that can obtain an optimum exposure energy distribution from the image data can be generated, and a high-speed image (pixel) clock can be generated. The semiconductor laser can be controlled simultaneously with the generation, and the IC can be provided.
[0114]
According to the invention of claim 5, it is possible to realize high speed, further finely adjust the writing position of a plurality of light emitting points, to control the semiconductor laser simultaneously with high-speed image (pixel) clock generation, The IC can be provided.
[0115]
According to the sixth aspect of the present invention, since the semiconductor laser modulation drive circuit can be installed in another place, the layout around the light source section is facilitated, and the IC that controls the semiconductor laser simultaneously with the generation of a high-speed image (pixel) clock. Can provide.
[0116]
According to the seventh aspect of the present invention, it is possible to realize a high speed operation by integrating circuit portions having a high transmission speed, and according to the present invention, it is possible to provide an IC that controls a semiconductor laser simultaneously with high-speed image (pixel) clock generation.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an image forming apparatus according to the present invention.
FIG. 2 is an explanatory diagram showing light emitting points of another example of the light source unit of FIG.
3 is an exploded perspective view showing an example of a light source unit in FIG. 2. FIG.
FIG. 4 is an explanatory diagram showing a conventional light modulation pulse and exposure energy distribution.
FIG. 5 is an explanatory diagram showing a light modulation pulse and an exposure energy distribution according to the present invention.
6 is an explanatory diagram showing an exposure energy distribution when the light modulation pulse in FIG. 4 is changed. FIG.
7 is an explanatory diagram showing an exposure energy distribution when the light modulation pulse in FIG. 5 is changed. FIG.
FIG. 8 is a block diagram showing a pulse modulation unit of the present invention.
FIG. 9 is an explanatory diagram showing an optical modulation pulse of the pulse modulation unit of FIG.
10 is an explanatory diagram showing an optical modulation pulse of the pulse modulation unit in FIG. 8. FIG.
FIG. 11 is a block diagram showing an LD control unit of the present invention.
FIG. 12 is a block diagram showing a high-frequency clock generation / pixel clock generation circuit.
FIG. 13 is a block diagram showing a high-frequency clock generation / pixel clock generation circuit of the present invention.
FIG. 14 is an explanatory diagram showing scanning by a plurality of light emitting points.
FIG. 15 is an explanatory diagram showing a plurality of light emitting points and their writing positions.
FIG. 16 is a block diagram showing a high-frequency clock generation / pixel clock generation circuit;
FIG. 17 is a block diagram showing a deflection surface detection circuit;
FIG. 18 is a block diagram showing a high-frequency clock generation / pixel clock generation circuit of the present invention.
FIG. 19 is a timing chart showing main signals in FIG. 18;
20 is an explanatory diagram showing an optical modulation pulse when the number of bits of the LUT is reduced in FIG.
FIG. 21 is an explanatory diagram showing eight-phase pulses in FIG. 20;
FIG. 22 is a block diagram illustrating an example of an LD drive circuit.
FIG. 23 is a block diagram illustrating another example of an LD drive circuit.
FIG. 24 is a block diagram showing in detail an LD driving circuit.
FIG. 25 is a block diagram illustrating another LD driving circuit in detail.
FIG. 26 is a block diagram showing an example in which the present invention is integrated into an IC.
FIG. 27 is a timing chart showing main signals in FIG. 26;
FIG. 28 is a block diagram showing another example in which the present invention is made into an IC.
FIG. 29 is a block diagram showing an example of the overall configuration of the present invention.
FIG. 30 is a block diagram showing another example of the overall configuration of the present invention.
31 is a block diagram showing a modification of the LD drive circuit of FIG. 22;
FIG. 32 is a configuration diagram illustrating a conventional image forming apparatus.
FIG. 33 is an explanatory diagram showing variations in image edges due to a deflector.
[Explanation of symbols]
321 Programmable counter
322 Phase comparison circuit
323 Loop filter
324 VCO
326-1, 327-2 Frequency divider circuit
328,329 registers
328a, 329a phase detection circuit
333 line register
334 Count value setting section

Claims (6)

In an image forming apparatus that scans a scanned medium by deflecting a light beam modulated in accordance with image data in a scanning direction by a plurality of deflecting surfaces of a deflector in synchronization with an output pixel clock.
So as to correct the variation in the scanning length obtained by scanning by deflecting the scanning direction by a plurality of the deflecting surface of the deflector, the time width of one pixel of the output pixel clock, control at predetermined pixel intervals Clock phase frequency control means for controlling the frequency of the output pixel clock for each of the deflection surfaces;
An image forming apparatus comprising: The clock phase frequency control means includes
High-frequency clock generation means;
First frequency dividing means capable of generating the output pixel clock by dividing the high frequency clock output from the high frequency clock generating means, and capable of changing a time width of one pixel of the output pixel clock;
Second frequency dividing means for frequency-dividing the high-frequency clock output from the high-frequency clock generating means and generating an image data capturing clock having the same frequency as that of the output pixel clock generated by the first frequency dividing means. When,
Phase changing means for changing the phase of the image data capturing clock generated by the second frequency dividing means;
The image forming apparatus according to claim 1, further comprising a. The high-frequency clock generation means includes a voltage-controlled oscillation circuit, a programmable counter that divides the output of the voltage-controlled oscillation circuit, and a PLL that compares the phase of the output of the programmable counter and a reference frequency. And a first frequency divider that divides the output of the voltage-controlled oscillation circuit to generate the output pixel clock and synchronizes the phase of the output pixel clock with a phase synchronization signal. The image forming apparatus according to claim 2 . 4. The image forming apparatus according to claim 3, further comprising a modulation pattern generation circuit that generates a modulation pattern that obtains an optimal exposure energy distribution based on image data in synchronization with the output pixel clock . An image characterized in that the first frequency dividing means and phase changing means according to claim 2, the PLL circuit according to claim 3, and the modulation pattern generating circuit according to claim 4 are configured in a common IC. Forming equipment. 6. The image forming apparatus according to claim 5, further comprising a semiconductor laser modulation drive circuit in the common IC .

Images