JP3835666B2 - Phase synchronization circuit and clock generation circuit - Google Patents

Description

【００１０】
【数２】

【００１１】
また、数１、数２より、ボード線図は図８のようになる。位相同期回路が安定な収束をするためには、ゲイン曲線が０ｄＢとなる点（ループ帯域ωｕ）よりも低い位置に零点が存在し、かつループ帯域ωｕにおける位相と１８０°との差（以下、位相余裕とする）が十分大きくなる必要がある。
【００１２】
つぎに、上述した開ループ伝達関数において、温度変化による素子変動が生じた場合を考える。電圧制御発振器は高温時において、常温時に対し電圧制御発振器の電圧周波数変換利得が減少する。したがって、位相曲線は変化しないのに対し、ループゲインが減少するため位相余裕が降下する。
【００１３】
そこで高温時のループゲインを補うため、図９のバイアス電流供給回路を適用している。このバイアス電流供給回路は、トランジスタ４４，４５により構成されるカレントミラー回路が電流Ｉ３，Ｉ４を等しくし、トランジスタ４２，４３とダイオード４８，４９により数３で与えられるバイアス電流を発生する。
【００１４】
【数３】

【００１５】
ここで、Ａ（４８），Ａ（４９）は、それぞれダイオード４８，４９のサイズであり、Ｗ（４２），Ｗ（４３），Ｌ（４２），Ｌ（４３）はそれぞれトランジスタ４２，４３のゲート幅およびゲート長である。また、βはＮＭＯＳトランジスタのコンダクタンス係数であり、ｋはボルツマン定数、ｑは電子電荷、Ｔは温度である。
【００１６】
上記バイアス電流はトランジスタ４５と４６により構成されるカレントミラー回路によりトランジスタ４７に伝達され、Ｖｂｐ，Ｖｂｎ端子とチャージポンプを接続することによりチャージポンプ電流を決定する。
【００１７】
数３より、バイアス電流が正の温度特性を有するため、チャージポンプ電流も同様に正の温度特性を有する。したがって、（位相比較器＋チャージポンプ）２４の温度特性も正となり、高温時の電圧制御発振器利得の減少を打ち消してループゲインの降下による、位相余裕の劣化を防止することができる。
【００１８】
【発明が解決しようとする課題】
上述した従来技術では、温度変化に対する位相余裕劣化を抑えることが可能であるが、ループフィルタには抵抗を用いており、温度やプロセスの変動により抵抗値が変動した場合における位相余裕の劣化に関しては考慮されていなかった。
【００１９】
本発明は、温度やプロセスの変動による抵抗値の変動に対しても一定の位相余裕を保ち、かつトランジスタ特性の変動に対する位相余裕の変動を抑えることができる位相同期回路の提供を目的としてなされたものである。
【００２０】
【課題を解決するための手段】
上記目的を達成するため、本発明では抵抗値の変動に対する位相同期回路のゲイン曲線と位相曲線の変動を等しくするものであり、その手法として互いの抵抗値の変動に対する依存性を打ち消し合うことができるバイアス電流供給回路と電圧電流変換回路を適用するものである。
【００２１】
本発明の位相同期回路およびクロック発生回路は、より具体的かつ代表的には以下のように構成される。
【００２２】
（１）位相比較器とチャージポンプとループフィルタと電圧制御発振器と分周器により構成され、基準信号と分周器の出力信号を位相比較器において検出し、位相差信号をチャージポンプとループフィルタを通して電圧制御発振器に入力することにより発振周波数が制御される位相同期回路を、チャージポンプの電流が抵抗値の２乗に反比例するバイアス回路と、極および零点の位置が抵抗値に反比例するループフィルタにより構成したことを特徴とする位相同期回路。
【００２３】
（２）位相比較器とチャージポンプとループフィルタと電圧制御発振器と分周器により構成され、基準信号と分周器の出力信号を位相比較器において検出し、位相差信号をチャージポンプとループフィルタを通して電圧制御発振器に入力することにより発振周波数が制御される位相同期回路を、チャージポンプの電流が抵抗値に反比例するバイアス回路と、極および零点の位置が抵抗値に反比例するループフィルタと、電圧制御発振器の電圧−周波数変換利得が抵抗値に反比例する電圧電流変換器により構成したことを特徴とする位相同期回路。
【００２４】
（３）上記（１）において、チャージポンプ電流を決定するバイアス回路が第１から第４の４つのトランジスタと１つの抵抗により構成され、抵抗が第１のトランジスタのソース端子とグランドとの間に接続され、第１のトランジスタのゲート端子が第２のトランジスタのゲート端子およびドレイン端子に接続され、第２のトランジスタのソース端子がグランドに接続され、さらに、第３および第４のトランジスタから構成されるカレントミラー回路を上記第１および第２のトランジスタと正電源の間に挿入することにより、上記バイアス回路の電流が抵抗の２乗に反比例することを特徴とした位相同期回路。
【００２５】
（４）上記（１）において、電圧制御発振器が電圧電流変換器と電流制御発振器により構成され、電圧電流変換器が少なくとも１つ以上のトランジスタにより構成され、同トランジスタのゲート端子をループフィルタの出力に、また、ソース端子をグランドに接続することにより上記ループフィルタの出力を電流信号に変換し、さらに同電流信号が電流制御発振器に入力されることを特徴とする位相同期回路。
【００２６】
（５）上記（２）において、チャージポンプ電流を決定するバイアス回路が、１つの抵抗と第１から第４の４つのトランジスタにより構成され、第１のトランジスタのソース端子をグランドに接続し、第１のトランジスタのゲート端子とグランドの間に抵抗を挿入し、第２のトランジスタのソース端子と第１のトランジスタのゲート端子を接続し、第２のトランジスタのゲート端子と第１のトランジスタのドレイン端子に接続し、さらに第１および第２のトランジスタと正電源との間に第３および第４のトランジスタにより構成されるカレントミラー回路を挿入し、上記カレントミラー回路により抵抗および第２のトランジスタのドレインを通過する電流を第１のトランジスタのドレインに折り返すことにより、第１から第４のトランジスタと抵抗に流れる電流が抵抗値に反比例することを特徴とする位相同期回路。
【００２７】
（６）上記（２）において、電圧制御発振器が電圧電流変換器と電流制御発振器により構成され、さらに、電圧電流変換器が少なくとも１つ以上のトランジスタと抵抗により構成され、同トランジスタのゲート端子をループフィルタの出力に接続し、また、ソース端子とグランドの間に抵抗を挿入し、抵抗に反比例した電圧電流変換を行なうことにより、電圧制御発振器の電圧−周波数変換利得が抵抗に反比例することを特徴とする位相同期回路。
【００２８】
（７）クロック信号により動作する集積回路に対し、上記集積回路の外部より供給される基準信号の周波数を定数倍して同半導体内部に供給するクロック発生回路が、上記（１）から（６）のいずれか記載の位相同期回路により構成されることを特徴とするクロック発生回路。
【００２９】
（８）データ送信を行なう第１の集積回路と、第１の集積回路とは別の基板上に構成されデータ受信を行なう第２の集積回路とのデータ送受信に時において、第１の集積回路の内部クロックと第２の集積回路の内部クロックの位相を合わせる位相調整回路が上記（１）から（６）のいずれか記載の位相同期回路により構成されることを特徴とした位相調整回路。
【００３０】
【発明の実施の形態】
図１は本発明による第１の実施例の位相同期回路を示した図である。位相同期回路は位相比較器１、第１のバイアス電流供給回路２、チャージポンプ３、ループフィルタ４、第１の電圧電流変換器５、電流制御発振器６および分周器７により構成される。
【００３１】
位相比較器１は、基準信号（ｆref）と分周器７の出力（ｆosc）の位相差を検出し、位相差に応じたＵＰ，ＤＮ信号をチャージポンプ２に出力する。チャージポンプ３は位相比較器１の出力信号に応じて、ループフィルタ４の容量から電荷を充放電する。このときチャージポンプ３の充放電電流はバイアス電流供給回路２により決定される。ループフィルタ４はチャージポンプ３の出力信号を平滑化し、電圧電流変換器５に電圧信号を出力する。
【００３２】
電圧電流変換器５はループフィルタ４の出力信号を電流に変換し、電流制御発振器６の周波数（ｆvco）を調整する。その出力は分周器７によりＮ分周され、位相比較１に帰還される。このような帰還構成をとることにより、電圧制御発振器４の出力は基準信号のＮ倍の周波数となる。
【００３３】
つぎに、位相同期回路を構成する個別構成要素について説明する。位相比較器１は２つの信号の位相差を検出し、位相差に応じた幅のＵＰ，ＤＮ信号をチャージポンプ３に出力する。このＵＰ，ＤＮ信号のパルス幅の差は位相差をパルス変調した信号となる。
【００３４】
バイアス電流供給回路２は４つのトランジスタ（８，９，１０，１１）および抵抗１２（抵抗値Ｒ１）により構成される。このような構成のバイアス電流供給回路については、「CMOS Analog Integrated Circuits Based on Weak Inversion Operation」（IEEE Journal of Solid-State Circuits,Vol.SC-12,No.3,pp224-231,June 1977）などに記載されている。
【００３５】
電流Ｉ１，Ｉ２は２つのトランジスタ８、９により構成されるカレントミラー回路により等しくなり、その電流値は２つのトランジスタ１０、１１のサイズの比と、ＮＭＯＳトランジスタのコンダクタンス係数βと、抵抗１２の値Ｒ１により決定される。具体的には、トランジスタ１０に対しトランジスタ１１のサイズをＫ倍に設定すると数４となり、抵抗１２の２乗に反比例した電流となる。
【００３６】
【数４】

【００３７】
この電流Ｉ１，Ｉ２は、トランジスタ９，１０とチャージポンプ３の電流源トランジスタ１３，１４の間に形成されるカレントミラー回路によりチャージポンプ２に伝達され、チャージポンプ２の電流値を決定する。
【００３８】
チャージポンプ３は電流源トランジスタ１３，１４とスイッチトランジスタ１５，１６により構成される。スイッチトランジスタ１５，１６のゲート端子（ＵＰ，ＤＮ）は位相比較器１より出力された信号に駆動され、ＵＰ，ＤＮ信号に応じてスイッチオン・オフを繰り返す。これにより、ループフィルタ４の容量から電流源トランジスタ１３，１４の出力する電流値およびスイッチのオン時間に応じた電荷を充放電する。
【００３９】
ループフィルタ４は抵抗１７（抵抗値Ｒｓ）、容量１８（容量値Ｃｓ），容量１９（容量値Ｃｐ）により構成される。ループフィルタ４ではチャージポンプ３により容量１８，１９の電荷が充放電され、それに応じた電圧信号Ｖlpfを電圧電流変換器５に出力する。このとき、Ｒｓ，Ｃｓ，Ｃｐの時定数に応じた極零点が周波数軸上に生成される。
【００４０】
電圧電流変換回路５はトランジスタ２０，２１，２２，２３により構成される。ループフィルタ４から出力される電圧信号Ｖlpfはトランジスタ２０のゲート端子に接続され、電流Ｉvicに変換される。ＩvicはＶlpfを用いて、数５で表すことができる。
【００４１】
【数５】

【００４２】
ここで、Ｖthはトランジスタの閾値電圧である。Ｉvicはトランジスタ２１と２２により構成されるカレントミラー回路によりトランジスタ２３に折り返され、端子Ｉｐおよび端子Ｉｎから電流制御発振器６に伝達される。
【００４３】
電流制御発振器６は電圧電流変換器５の電流に応じた周波数で発振する。ここで適用する電流制御発振器６の詳細については特開平１１−２９８３０２に記載されている。
【００４４】
つぎに、図２の線形モデルを用いて位相同期回路の位相余裕と抵抗値の関係について述べる。ここで、位相同期回路の構成要素をそれぞれ、（位相比較器＋チャージポンプ）２４、ループフィルタ２５、（電圧電流変換器＋電流制御発振器）２６、分周器２７に分割している。また、φREFは基準信号の位相、φOSCはフィードバック信号の位相である。同図から開ループ伝達関数を求めると、数６となる。
【００４５】
【数６】

【００４６】
ここで、Ｉcpはチャージポンプ電流、Ｋvcoは電圧電流変換器５と電流制御発振器６により構成される電圧制御発振器の電圧電流変換利得である。
【００４７】
上述したように、位相同期回路は３つの極と１つの零点を周波数軸上に有する。直流に存在する２個つの極をＰ１，Ｐ２、その他の極をＰ３、零点をＺ１とおくと、Ｐ３およびＺ１は開ループ伝達関数から、数７および数８となる。
【００４８】
【数７】

【００４９】
【数８】

【００５０】
位相同期回路の安定性を確保するためには、開ループ伝達関数の利得が１となる周波数（以下、ループ帯域ωｕとする）よりも低い位置に零点Ｚ１が存在し、ループ帯域ωｕよりも周波数が高い位置にＰ３が存在し、さらに位相余裕が十分大きくなるようＰ３，Ｚ１および各ブロックの伝達関数を設定する必要がある。マイクロプロセッサ等の用途では、通常３０°から４０°の位相余裕が確保できるよう設計される。
【００５１】
抵抗値が変動した場合、バイアス電流供給回路２の電流値は数４で示したように抵抗１２の２乗に反比例して変化する。したがって、位相比較器１とチャージポンプ３の伝達関数は抵抗１２の２乗に反比例して変化する。また、極Ｐ３および零点Ｚ１の位置は抵抗１７に反比例して変化する。さらに、電圧電流変換器５と電流制御発振器６により構成される電圧制御発振器の電圧−周波数変換利得は抵抗値に依存しない。
【００５２】
集積回路上では素子間の相対的な精度が十分高く、プロセス変動や温度変化に起因する抵抗１２，１７の変化率が等しいため、抵抗値の変動に対するゲイン曲線および位相曲線の変動は図３のようになる。ここで、図中の実線は抵抗値変動前、破線は抵抗値変動後を示している。同図より、ゲイン曲線および位相曲線ともに抵抗値に反比例して変動する。したがって、位相曲線とループ帯域ωｕの位置関係は、温度やプロセス等の変動により抵抗値が変動したとしても一定であり、位相余裕は変化しない。
【００５３】
上述した位相同期回路では、バイアス電流供給回路２と、電圧電流変換回路５および電流制御発振器６により構成される電圧制御発振器を適用したが、チャージポンプ電流が抵抗の２乗に依存して変化し、電圧制御発振器の電圧−周波数変換利得が抵抗に依存しない回路構成であれば、どのような回路でも抵抗値の変動に対し位相余裕を一定に保つことができる。
【００５４】
また、バイアス電流供給回路２と電圧電流変換回路５を用いた場合、バイアス電流供給回路２の電流はＮＭＯＳトランジスタのコンダクタンス係数βに反比例し、電圧電流変換回路５の電流はβに正比例する。したがって、トランジスタ特性の変動に対する位相余裕の変動を、電流制御発振器６の電流周波数変換利得の変動のみに抑えることが可能である。
【００５５】
つぎに、位相余裕の抵抗値変動に対する依存性を打ち消すことができる位相同期回路の第２の実施例として、図１のバイアス電流供給回路２と電圧電流変換器５を、それぞれ、第２のバイアス電流供給回路（図４）と第２の電圧電流変換回路（図５）に変更した構成を挙げる。
【００５６】
図４のバイアス電流供給回路はトランジスタ２９，３０，３１，３２，３３，３４と抵抗３５（抵抗値Ｒ２）により構成される。トランジスタ３１，３２はカレントミラー回路を構成し、トランジスタ２９，３０および抵抗３５の電流が等しくなるよう動作する。トランジスタ２９の電流はゲート・ソース間電位Ｖgs２９で決定され、Ｖgs２９と抵抗値Ｒ２によりトランジスタ３０の電流が決定される。その結果、バイアス電流供給回路の電流は、数９となり、抵抗３５に反比例する。
【００５７】
【数９】

【００５８】
同電流はトランジスタ３２，３３からなるカレントミラー回路によりトランジスタ３４に伝搬され、さらにＶbp，Ｖbn端子をチャージポンプ３の電流制御トランジスタ１３，１４のゲート端子に接続することによりチャージポンプ電流を決定する。
【００５９】
図５の電圧電流変換器はトランジスタ３７，３８，３９，４０と抵抗４１（抵抗値Ｒ３）により構成される。トランジスタ３７および抵抗４１に流れる電流と、抵抗４１の両端の電位差と、トランジスタ３７のゲート・ソース間電位に対しキルヒホッフの法則を適用すると、トランジスタ３７の電流は、数１０で与えられる。ここで、数１１が成立するよう各パラメータを選択している。
【００６０】
【数１０】

【００６１】
【数１１】

【００６２】
したがって、電圧電流変換器３７の電圧−電流変換利得は抵抗値に反比例し、電流制御発振器６と組み合わせて構成した電圧制御発振器の電圧−周波数変換利得も同様に抵抗値に反比例する。
【００６３】
上述した第２の実施例による位相同期回路では、位相比較器１とチャージポンプ２の伝達関数は抵抗値に反比例し、極Ｐ３および零点Ｚ１の位置は抵抗値に反比例し、電圧制御発振器４の電圧−周波数変換利得は抵抗値に反比例する。したがって、抵抗値の変動に対するボード線図の変動は第１の実施例に示した位相同期回路と同様に図３のようになる。同図より、ループ帯域ωｕと位相曲線の抵抗値に対する依存性が等しいため位相余裕は変化しない。
【００６４】
以上の実施例では、図４のバイアス電流供給回路と図５の電圧電流変換回路を適用したが、電流が抵抗値に反比例するチャージポンプと電圧−周波数変換利得が抵抗値に反比例する電圧制御発振器であれば、どのような回路構成でも抵抗値の変動に対して位相余裕が変動しない位相同期回路を構成することが可能である。
【００６５】
以上のように位相同期回路を構成する個別構成要素が、互いの抵抗値に対する依存性を打ち消すことによって、抵抗値の変動に対するゲイン曲線および位相曲線の依存性が等しくなり、抵抗値の変動に対して位相余裕が変動しない位相同期回路が構成可能である。
【００６６】
【発明の効果】
本発明により、抵抗変動に対する位相余裕の変動がなくなるため、半導体上に回路を構成した場合のように抵抗値の絶対値精度が低い場合においても、安定な位相同期回路を構成することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例になる位相同期回路の回路図。
【図２】第１の実施例の位相同期回路の線形モデルの説明図。
【図３】本発明の実施例による抵抗変動に対するボード線図の変動の説明図。
【図４】本発明の第２の実施例のバイアス電流供給回路の回路図。
【図５】本発明の第２の実施例の電圧電流変換器の回路図。
【図６】従来例の位相同期回路の構成を示すブロック図。
【図７】従来例の位相同期回路の線形モデルの説明図。
【図８】従来例の位相同期回路のボード線図の説明図。
【図９】従来例の位相同期回路のバイアス電流供給回路の回路図。
【符号の説明】
１…位相比較器、２…バイアス電流供給回路、３…チャージポンプ、４…ループフィルタ、５…電圧電流変換器、６…電流制御発振器、７…分周器、８，９，１０，１１，１２，１３，１４，１５，１６，２０，２１，２２，２３，２９，３０，３１，３２，３３，３４，３７，３８，３９，４０，４２，４３，４４，４５，４６，４７…トランジスタ、１７，３５，４１…抵抗、１８，１９…容量、２４…位相比較器＋チャージポンプの伝達関数、２５…ループフィルタの伝達関数、２６…電圧制御発振器の伝達関数、２７…分周器の伝達関数、４８，４９…ダイオード。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase synchronization circuit capable of maintaining stability even when the absolute value accuracy of a resistance element is low, such as a circuit configured on a semiconductor, and a clock generation circuit using the same.
[0002]
[Prior art]
A phase synchronization circuit that performs clock synchronization, clock multiplication, and the like is used for the purpose of generating a high-speed clock inside a logic LSI and adjusting the phase with a RAM module connected outside the LSI. In particular, the charge pump type phase locked loop circuit has a small steady phase error and has a wide capture range, so that it is suitable for applications such as a microprocessor and is widely used. For a phase-locked loop with this configuration, see “A PLL Clock Generator with 5to110 MHz of Lock Range for Microprocessor” by I. Young (IEEE Journal of solid-state circuits, vol.SC-27, pp.1599-1607, November. 1992).
[0003]
First, the operation of the phase synchronization circuit will be described with reference to FIG. The phase synchronization circuit includes a phase comparator 1, a bias current supply circuit 2, a charge pump 3, a loop filter 4, a voltage / current converter 5, a current control oscillator 6, and a frequency divider 7.
[0004]
The phase comparator 1 detects a phase difference between the reference signal (fref) and the feedback signal (fosc), and outputs a pulse signal (UP, DN) corresponding to the phase difference. The charge pump 3 charges and discharges the capacitor 57 (capacitance value C) of the loop filter 4 according to the pulse signal (UP, DN) output from the phase comparator 1. The charge / discharge current at this time is determined by the bias current supply circuit 2. The loop filter 4 smoothes the signal output from the charge pump 3 and outputs the control voltage signal of the voltage / current converter 5. The voltage-current converter 5 converts the control voltage signal output from the loop filter 4 into a current signal, and controls the oscillation frequency of the current-controlled oscillator 6.
[0005]
Finally, a frequency divider 7 is provided between the output of the current control oscillator 6 and one input of the phase comparator 1 to constitute a feedback loop. Here, an arbitrary positive integer can be selected as the frequency division number N of the frequency divider 7. The frequency of the signal (fvco) output from the current control oscillator 6 is N times that of the reference signal.
[0006]
By taking such a feedback configuration, the loop filter 4 generates poles and zeros on the frequency axis. Therefore, when designing the phase synchronization circuit, it is necessary to set various constants so as to achieve stable convergence. In addition, since stability changes due to process fluctuations during semiconductor manufacturing and element fluctuations due to temperature changes, a design that can maintain the stability in consideration of the fluctuations is required. However, when the fluctuation of the passive element and the active element becomes large, the fluctuation range of the elements constituting the phase synchronization circuit becomes large, and it becomes difficult to maintain stability.
[0007]
Therefore, a technique is required in which the components of the phase-locked loop cancel each other's dependence on element variations. The following is a phase synchronization circuit using the "A Wide-Bandwidth Low-Voltage PLL for PowerPc (TM) Microprocessors" (IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, pp383-391, April 1995) as an example. A conventional technique for canceling the dependence of stability on element variation will be described.
[0008]
FIG. 7 shows a linear model of the phase locked loop. The linear model divides the phase-locked loop into blocks of (phase comparator + charge pump) 24, (loop filter) 25, (voltage-current converter + current-controlled oscillator) 26, and (frequency divider) 27. It can be represented by a block transfer function. Here, Icp is a charge pump current, and Kvco is a voltage frequency conversion gain of a voltage controlled oscillator constituted by the voltage current converter 5 and the current controlled oscillator 6. ΦREF is the phase of the reference signal, and φOSC is the phase of the feedback signal. From the linear model, the open-loop transfer function is given by Equation 1, and the zero position Z ₁ is given by Equation 2.
[0009]
[Expression 1]

[0010]
[Expression 2]

[0011]
Also, from Equations 1 and 2, the Bode diagram is as shown in FIG. In order for the phase-locked loop to stably converge, a zero point exists at a position lower than the point where the gain curve becomes 0 dB (loop band ωu), and the difference between the phase in the loop band ωu and 180 ° (hereinafter, (The phase margin) must be sufficiently large.
[0012]
Next, let us consider a case where element variation due to temperature change occurs in the above-described open loop transfer function. When the voltage controlled oscillator is at a high temperature, the voltage frequency conversion gain of the voltage controlled oscillator is reduced as compared with the room temperature. Therefore, while the phase curve does not change, the loop margin decreases and the phase margin decreases.
[0013]
In order to compensate for the loop gain at high temperatures, the bias current supply circuit of FIG. 9 is applied. In this bias current supply circuit, the current mirror circuit constituted by the transistors 44 and 45 equalizes the currents I3 and I4, and generates a bias current given by the equation 3 by the transistors 42 and 43 and the diodes 48 and 49.
[0014]
[Equation 3]

[0015]
Here, A (48) and A (49) are the sizes of the diodes 48 and 49, respectively, and W (42), W (43), L (42), and L (43) are the transistors 42 and 43, respectively. Gate width and gate length. Β is a conductance coefficient of the NMOS transistor, k is a Boltzmann constant, q is an electronic charge, and T is a temperature.
[0016]
The bias current is transmitted to the transistor 47 by a current mirror circuit constituted by the transistors 45 and 46, and the charge pump current is determined by connecting the Vbp and Vbn terminals and the charge pump.
[0017]
From Equation 3, since the bias current has a positive temperature characteristic, the charge pump current similarly has a positive temperature characteristic. Therefore, the temperature characteristic of the (phase comparator + charge pump) 24 is also positive, and the decrease in the voltage control oscillator gain at a high temperature can be canceled to prevent the phase margin from being deteriorated due to the drop in the loop gain.
[0018]
[Problems to be solved by the invention]
In the above-described prior art, it is possible to suppress the phase margin deterioration due to temperature change, but the loop filter uses a resistor, and regarding the phase margin deterioration when the resistance value fluctuates due to temperature and process fluctuations. It was not considered.
[0019]
The present invention has been made for the purpose of providing a phase locked loop circuit that can maintain a constant phase margin against resistance fluctuations due to temperature and process fluctuations, and can suppress fluctuations in phase margin relative to transistor characteristic fluctuations. Is.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, the present invention equalizes the fluctuations of the gain curve and the phase curve of the phase synchronization circuit with respect to the resistance value fluctuation, and as a method thereof, cancels the dependence on the mutual resistance value fluctuations. A bias current supply circuit and a voltage-current conversion circuit that can be applied are applied.
[0021]
The phase synchronization circuit and clock generation circuit of the present invention are more specifically and typically configured as follows.
[0022]
(1) Consists of a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase comparator detects the reference signal and the output signal of the frequency divider, and the phase difference signal is detected by the charge pump and the loop filter. A phase-locked loop whose oscillation frequency is controlled by inputting to a voltage-controlled oscillator through a bias circuit in which the charge pump current is inversely proportional to the square of the resistance value, and a loop filter in which the positions of the poles and zeros are inversely proportional to the resistance value A phase locked loop circuit comprising:
[0023]
(2) Consists of a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase comparator detects the reference signal and the output signal of the frequency divider, and the phase difference signal is detected by the charge pump and the loop filter. A phase-locked loop whose oscillation frequency is controlled by inputting to a voltage-controlled oscillator through a bias circuit in which the charge pump current is inversely proportional to the resistance value, a loop filter in which the position of the pole and zero is inversely proportional to the resistance value, and a voltage A phase locked loop circuit comprising a voltage-current converter in which a voltage-frequency conversion gain of a controlled oscillator is inversely proportional to a resistance value.
[0024]
(3) In the above (1), the bias circuit for determining the charge pump current is composed of the first to fourth transistors and one resistor, and the resistor is between the source terminal of the first transistor and the ground. Connected, the gate terminal of the first transistor is connected to the gate terminal and the drain terminal of the second transistor, the source terminal of the second transistor is connected to the ground, and further comprises third and fourth transistors. A phase-locked loop circuit in which a current of the bias circuit is inversely proportional to the square of the resistance by inserting a current mirror circuit between the first and second transistors and a positive power source.
[0025]
(4) In the above (1), the voltage controlled oscillator is composed of a voltage current converter and a current controlled oscillator, the voltage current converter is composed of at least one transistor, and the gate terminal of the transistor is connected to the output of the loop filter. In addition, the output of the loop filter is converted into a current signal by connecting the source terminal to the ground, and the current signal is further input to the current controlled oscillator.
[0026]
(5) In the above (2), the bias circuit for determining the charge pump current is composed of one resistor and the first to fourth transistors, the source terminal of the first transistor is connected to the ground, A resistor is inserted between the gate terminal of the first transistor and the ground, the source terminal of the second transistor is connected to the gate terminal of the first transistor, the gate terminal of the second transistor and the drain terminal of the first transistor And a current mirror circuit constituted by the third and fourth transistors is inserted between the first and second transistors and the positive power supply, and the current mirror circuit provides a resistor and a drain of the second transistor. By folding the current passing through the first transistor to the drain of the first transistor. Phase locked loop circuit and a current flowing through the resistor is inversely proportional to the resistance value.
[0027]
(6) In the above (2), the voltage-controlled oscillator is constituted by a voltage-current converter and a current-controlled oscillator, and the voltage-current converter is constituted by at least one transistor and a resistor, and the gate terminal of the transistor is The voltage-frequency conversion gain of the voltage controlled oscillator is inversely proportional to the resistance by connecting the output of the loop filter and inserting a resistance between the source terminal and the ground and performing voltage-current conversion inversely proportional to the resistance. A characteristic phase synchronization circuit.
[0028]
(7) A clock generation circuit that supplies an internal frequency of a reference signal supplied from the outside of the integrated circuit by a constant to an integrated circuit that operates by a clock signal and supplies the same inside the semiconductor circuit. A clock generation circuit comprising the phase synchronization circuit according to any one of the above.
[0029]
(8) At the time of data transmission / reception between a first integrated circuit that performs data transmission and a second integrated circuit that is configured on a substrate different from the first integrated circuit and that receives data, the first integrated circuit A phase adjustment circuit comprising the phase synchronization circuit according to any one of (1) to (6) above, wherein the phase adjustment circuit for synchronizing the phases of the internal clock and the internal clock of the second integrated circuit.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a phase locked loop circuit according to a first embodiment of the present invention. The phase synchronization circuit includes a phase comparator 1, a first bias current supply circuit 2, a charge pump 3, a loop filter 4, a first voltage / current converter 5, a current control oscillator 6 and a frequency divider 7.
[0031]
The phase comparator 1 detects the phase difference between the reference signal (fref) and the output (fosc) of the frequency divider 7, and outputs UP and DN signals corresponding to the phase difference to the charge pump 2. The charge pump 3 charges and discharges charges from the capacity of the loop filter 4 according to the output signal of the phase comparator 1. At this time, the charge / discharge current of the charge pump 3 is determined by the bias current supply circuit 2. The loop filter 4 smoothes the output signal of the charge pump 3 and outputs a voltage signal to the voltage / current converter 5.
[0032]
The voltage / current converter 5 converts the output signal of the loop filter 4 into a current, and adjusts the frequency (fvco) of the current control oscillator 6. The output is divided by N by the frequency divider 7 and fed back to the phase comparison 1. By adopting such a feedback configuration, the output of the voltage controlled oscillator 4 has a frequency N times that of the reference signal.
[0033]
Next, individual components constituting the phase synchronization circuit will be described. The phase comparator 1 detects the phase difference between the two signals and outputs UP and DN signals having a width corresponding to the phase difference to the charge pump 3. The difference between the pulse widths of the UP and DN signals is a signal obtained by pulse-modulating the phase difference.
[0034]
The bias current supply circuit 2 includes four transistors (8, 9, 10, 11) and a resistor 12 (resistance value R1). Regarding the bias current supply circuit having such a configuration, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation” (IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 3, pp224-231, June 1977), etc. It is described in.
[0035]
The currents I1 and I2 are equalized by the current mirror circuit formed by the two transistors 8 and 9, and the current value is the ratio of the sizes of the two transistors 10 and 11, the conductance coefficient β of the NMOS transistor, and the value of the resistor 12 Determined by R1. Specifically, when the size of the transistor 11 is set to K times the transistor 10, Equation 4 is obtained, and the current is in inverse proportion to the square of the resistor 12.
[0036]
[Expression 4]

[0037]
The currents I1 and I2 are transmitted to the charge pump 2 by a current mirror circuit formed between the transistors 9 and 10 and the current source transistors 13 and 14 of the charge pump 3, and determine the current value of the charge pump 2.
[0038]
The charge pump 3 includes current source transistors 13 and 14 and switch transistors 15 and 16. The gate terminals (UP, DN) of the switch transistors 15 and 16 are driven by the signal output from the phase comparator 1 and repeatedly switch on and off in accordance with the UP and DN signals. Thereby, the electric charge according to the current value output from the current source transistors 13 and 14 and the on-time of the switch is charged and discharged from the capacity of the loop filter 4.
[0039]
The loop filter 4 includes a resistor 17 (resistance value Rs), a capacitor 18 (capacitance value Cs), and a capacitor 19 (capacitance value Cp). In the loop filter 4, charges of the capacitors 18 and 19 are charged / discharged by the charge pump 3, and a voltage signal Vlpf corresponding to the charges is output to the voltage / current converter 5. At this time, pole zeros corresponding to the time constants of Rs, Cs, and Cp are generated on the frequency axis.
[0040]
The voltage / current conversion circuit 5 includes transistors 20, 21, 22 and 23. The voltage signal Vlpf output from the loop filter 4 is connected to the gate terminal of the transistor 20 and converted into a current Ivic. Ivic can be expressed by Equation 5 using Vlpf.
[0041]
[Equation 5]

[0042]
Here, Vth is a threshold voltage of the transistor. Ivic is folded back to the transistor 23 by a current mirror circuit composed of the transistors 21 and 22 and transmitted to the current control oscillator 6 from the terminal Ip and the terminal In.
[0043]
The current controlled oscillator 6 oscillates at a frequency corresponding to the current of the voltage / current converter 5. Details of the current-controlled oscillator 6 applied here are described in JP-A-11-298302.
[0044]
Next, the relationship between the phase margin of the phase locked loop and the resistance value will be described using the linear model of FIG. Here, the components of the phase-locked loop are divided into (phase comparator + charge pump) 24, loop filter 25, (voltage-current converter + current-controlled oscillator) 26, and frequency divider 27, respectively. ΦREF is the phase of the reference signal, and φOSC is the phase of the feedback signal. When the open-loop transfer function is obtained from FIG.
[0045]
[Formula 6]

[0046]
Here, Icp is a charge pump current, and Kvco is a voltage-current conversion gain of a voltage-controlled oscillator constituted by the voltage-current converter 5 and the current-controlled oscillator 6.
[0047]
As described above, the phase locked loop circuit has three poles and one zero on the frequency axis. Assuming that two poles existing in the direct current are P1 and P2, the other poles are P3, and a zero point is Z1, P3 and Z1 are expressed by Equations 7 and 8 from an open loop transfer function.
[0048]
[Expression 7]

[0049]
[Equation 8]

[0050]
In order to ensure the stability of the phase locked loop, the zero point Z1 exists at a position lower than the frequency at which the gain of the open-loop transfer function is 1 (hereinafter referred to as the loop band ωu), and the frequency is higher than the loop band ωu. It is necessary to set P3, Z1 and the transfer function of each block so that P3 exists at a position where is high and the phase margin is sufficiently large. For applications such as microprocessors, it is usually designed to ensure a phase margin of 30 ° to 40 °.
[0051]
When the resistance value fluctuates, the current value of the bias current supply circuit 2 changes in inverse proportion to the square of the resistor 12 as shown in Equation 4. Therefore, the transfer function of the phase comparator 1 and the charge pump 3 changes in inverse proportion to the square of the resistor 12. The positions of the pole P3 and the zero point Z1 change in inverse proportion to the resistor 17. Furthermore, the voltage-frequency conversion gain of the voltage controlled oscillator constituted by the voltage / current converter 5 and the current controlled oscillator 6 does not depend on the resistance value.
[0052]
On the integrated circuit, the relative accuracy between the elements is sufficiently high, and the rate of change of the resistors 12 and 17 due to process fluctuations and temperature changes is equal. It becomes like this. Here, the solid line in the figure indicates the state before the resistance value change, and the broken line indicates the state after the resistance value change. From the figure, both the gain curve and the phase curve fluctuate in inverse proportion to the resistance value. Therefore, the positional relationship between the phase curve and the loop band ωu is constant even if the resistance value fluctuates due to fluctuations in temperature, process, etc., and the phase margin does not change.
[0053]
In the phase-locked loop circuit described above, the voltage-controlled oscillator composed of the bias current supply circuit 2, the voltage-current converter circuit 5 and the current-controlled oscillator 6 is applied. However, the charge pump current changes depending on the square of the resistance. As long as the circuit configuration is such that the voltage-frequency conversion gain of the voltage controlled oscillator does not depend on the resistance, the phase margin can be kept constant with respect to the fluctuation of the resistance value in any circuit.
[0054]
When the bias current supply circuit 2 and the voltage / current conversion circuit 5 are used, the current of the bias current supply circuit 2 is inversely proportional to the conductance coefficient β of the NMOS transistor, and the current of the voltage / current conversion circuit 5 is directly proportional to β. Therefore, the fluctuation of the phase margin with respect to the fluctuation of the transistor characteristics can be suppressed only to the fluctuation of the current frequency conversion gain of the current control oscillator 6.
[0055]
Next, as a second embodiment of the phase locked loop that can cancel the dependence of the phase margin on the resistance value fluctuation, the bias current supply circuit 2 and the voltage / current converter 5 shown in FIG. The configuration is changed to a current supply circuit (FIG. 4) and a second voltage-current conversion circuit (FIG. 5).
[0056]
The bias current supply circuit shown in FIG. 4 includes transistors 29, 30, 31, 32, 33, and 34 and a resistor 35 (resistance value R2). The transistors 31 and 32 constitute a current mirror circuit, and operate so that the currents of the transistors 29 and 30 and the resistor 35 become equal. The current of the transistor 29 is determined by the gate-source potential Vgs29, and the current of the transistor 30 is determined by Vgs29 and the resistance value R2. As a result, the current of the bias current supply circuit is expressed by Equation 9 and is inversely proportional to the resistor 35.
[0057]
[Equation 9]

[0058]
The current is propagated to the transistor 34 by a current mirror circuit composed of transistors 32 and 33, and the charge pump current is determined by connecting the Vbp and Vbn terminals to the gate terminals of the current control transistors 13 and 14 of the charge pump 3.
[0059]
The voltage-current converter shown in FIG. 5 includes transistors 37, 38, 39, and 40 and a resistor 41 (resistance value R3). When Kirchhoff's law is applied to the current flowing through the transistor 37 and the resistor 41, the potential difference between both ends of the resistor 41, and the gate-source potential of the transistor 37, the current of the transistor 37 is given by the following equation (10). Here, each parameter is selected so that Formula 11 is satisfied.
[0060]
[Expression 10]

[0061]
[Expression 11]

[0062]
Therefore, the voltage-current conversion gain of the voltage-current converter 37 is inversely proportional to the resistance value, and the voltage-frequency conversion gain of the voltage-controlled oscillator configured in combination with the current-controlled oscillator 6 is also inversely proportional to the resistance value.
[0063]
In the phase locked loop according to the second embodiment described above, the transfer functions of the phase comparator 1 and the charge pump 2 are inversely proportional to the resistance value, and the positions of the pole P3 and the zero point Z1 are inversely proportional to the resistance value. The voltage-frequency conversion gain is inversely proportional to the resistance value. Therefore, the variation of the Bode diagram with respect to the variation of the resistance value is as shown in FIG. 3 like the phase synchronization circuit shown in the first embodiment. From the figure, the phase margin does not change because the dependence of the loop bandwidth ωu and the resistance value of the phase curve on the resistance is equal.
[0064]
In the above embodiment, the bias current supply circuit of FIG. 4 and the voltage-current conversion circuit of FIG. 5 are applied. However, a charge pump whose current is inversely proportional to the resistance value and a voltage-controlled oscillator whose voltage-frequency conversion gain is inversely proportional to the resistance value. As long as the circuit has any circuit configuration, it is possible to configure a phase synchronization circuit in which the phase margin does not vary with respect to the resistance value variation.
[0065]
As described above, the individual components constituting the phase locked loop cancel out the dependency on the resistance value of each other, so that the dependency of the gain curve and the phase curve on the variation of the resistance value becomes equal, and the variation of the resistance value Thus, it is possible to configure a phase synchronization circuit in which the phase margin does not vary.
[0066]
【The invention's effect】
According to the present invention, since there is no phase margin variation with respect to resistance variation, a stable phase synchronization circuit can be configured even when the absolute value accuracy of the resistance value is low, such as when a circuit is configured on a semiconductor.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a phase locked loop circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a linear model of the phase locked loop of the first embodiment.
FIG. 3 is an explanatory diagram of Bode diagram fluctuations with respect to resistance fluctuations according to an embodiment of the present invention.
FIG. 4 is a circuit diagram of a bias current supply circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram of a voltage-current converter according to a second embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a conventional phase synchronization circuit.
FIG. 7 is an explanatory diagram of a linear model of a conventional phase locked loop circuit.
FIG. 8 is an explanatory diagram of a Bode diagram of a conventional phase synchronization circuit.
FIG. 9 is a circuit diagram of a bias current supply circuit of a conventional phase locked loop.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Phase comparator, 2 ... Bias current supply circuit, 3 ... Charge pump, 4 ... Loop filter, 5 ... Voltage-current converter, 6 ... Current control oscillator, 7 ... Divider, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 21, 22, 23, 29, 30, 31, 32, 33, 34, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47 ... Transistors 17, 35, 41 ... resistors, 18, 19 ... capacitors, 24 ... phase comparator + charge pump transfer function, 25 ... loop filter transfer function, 26 ... voltage controlled oscillator transfer function, 27 ... frequency divider Transfer function of 48, 49 ... diode.

Claims (8)

A phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, and a bias circuit for providing a bias for determining a value of the current of the charge pump, and a phase comparator which outputs a reference signal and an output signal of the frequency divider And a phase-locked loop whose oscillation frequency is controlled by inputting a phase difference signal to a voltage controlled oscillator through a charge pump and a loop filter, wherein the bias circuit has a first resistor and has a current of the charge pump. Gives a bias that is inversely proportional to the square of the resistance value of the first resistor, the loop filter has a second resistance, and the position of the pole and zero on the frequency axis is inversely proportional to the resistance value of the second resistor. phase locked loop circuit characterized by being configured to vary. A phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, and a bias circuit for providing a bias for determining a value of the current of the charge pump, and a phase comparator which outputs a reference signal and an output signal of the frequency divider And a phase-locked loop whose oscillation frequency is controlled by inputting a phase difference signal to a voltage controlled oscillator through a charge pump and a loop filter, wherein the bias circuit has a first resistor and has a current of the charge pump. Gives a bias that is inversely proportional to the resistance value of the first resistor, and the loop filter has a second resistance, and the position of the pole and zero on the frequency axis varies inversely proportional to the resistance value of the second resistor. The voltage controlled oscillator has a third resistor, and the voltage-frequency conversion gain is configured to be inversely proportional to the resistance value of the third resistor. Synchronization circuit. 2. The bias circuit according to claim 1, wherein the bias circuit for determining a charge pump current includes first to fourth transistors and the first resistor, and the first resistor is connected between the source terminal of the first transistor and the ground. , A gate terminal of the first transistor is connected to a gate terminal and a drain terminal of the second transistor, a source terminal of the second transistor is connected to the ground, and further includes third and fourth transistors A phase of the current circuit of the bias circuit being inversely proportional to the square of the resistance value of the first resistor by inserting a current mirror circuit between the first and second transistors and a positive power source. Synchronous circuit. According to claim 1, said voltage controlled oscillator is constituted by a voltage-current converter and a current controlled oscillator, the voltage-current converter is constituted by at least one or more transistors, the one gate terminal of the transistor the output of the loop filter, also, the output of the loop filter into a current signal by connecting the source terminal to ground, further the current signal and wherein the input to the current-controlled oscillator phase locked loop . 3. The bias circuit according to claim 2, wherein the bias circuit for determining a charge pump current includes the first resistor and first to fourth transistors, and a source terminal of the first transistor is connected to the ground. The first resistor is inserted between the gate terminal of the transistor and the ground, the source terminal of the second transistor and the gate terminal of the first transistor are connected, and the gate terminal of the second transistor is connected to the drain of the first transistor. A current mirror circuit connected to the terminal and further comprising a third and a fourth transistor between the first and second transistors and the positive power supply, and the first mirror and the second resistor are inserted by the current mirror circuit. by folding back the current through the drain of the transistor to the drain of the first transistor, from the first Phase locked loop circuit 4 of the transistor and the current flowing through the first resistor is equal to or inversely proportional to the resistance of the first resistor. In claim 2, the voltage controlled oscillator is constituted by a voltage-current converter and a current controlled oscillator further voltage-current converter is constituted by a third resistor above and at least one transistor, one of the transistor 1 Voltage control is performed by connecting one gate terminal to the output of the loop filter and inserting the third resistor between the source terminal and the ground and performing voltage-current conversion inversely proportional to the resistance value of the third resistor. A phase-locked loop characterized in that the voltage-frequency conversion gain of the oscillator is inversely proportional to the resistance.   7. The clock generation circuit according to claim 1, wherein a clock generation circuit for multiplying a frequency of a reference signal supplied from the outside of the integrated circuit by a constant with respect to the integrated circuit operated by a clock signal and supplying the same into the semiconductor is provided. A clock generation circuit comprising a synchronization circuit. A first integrated circuit for performing data transmission, at the time of data transmission and reception between the second integrated circuit includes a first integrated circuit which performs the configured data received on a separate substrate, the internal clock of the first integrated circuit 7. A phase adjustment circuit, wherein the phase adjustment circuit for adjusting the phase of the internal clock of the second integrated circuit comprises the phase synchronization circuit according to claim 1.

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