JP3833854B2 - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, a stack gate type memory cell having a control gate and a floating gate and its peripheral circuit are integrated on the same chip. Method for manufacturing nonvolatile semiconductor memory device In particular, the trench element isolation is formed in a self-aligned manner with the polycrystalline silicon layer for the floating gate, and the occurrence of kink characteristics is suppressed in the peripheral circuit transistor. Method for manufacturing nonvolatile semiconductor memory device About.
[0002]
[Prior art]
2. Description of the Related Art Non-volatile semiconductor memory devices in which a stack gate type memory cell having a control gate and a floating gate and a peripheral circuit for driving the memory cell are integrated on the same chip are widely known. In general, in this type of semiconductor memory device, trench element isolation (STI) is formed in a self-aligned manner with the polycrystalline silicon layer for floating gates. After removing the silicon, gate oxidation and electrode formation are performed again.
[0003]
When removing the floating gate polycrystalline silicon, the end portion of the peripheral circuit element region is exposed, and a gate electrode formed on the element region may be formed in the upper side surface of the element region. When the gate electrode falls, a parasitic transistor is formed on the side surface of the element region, and a so-called kink characteristic in which a low-threshold characteristic curve caused by the parasitic transistor is superimposed on the drain voltage-current characteristic curve of the MOSFET. Occurs. When this kink characteristic occurs, problems such as an increase in the standby current of the memory are caused.
[0004]
In order to prevent this kink characteristic, it is necessary to form a large amount of bird's beaks in advance between the element region and the polycrystalline silicon layer. In particular, when the operation of extracting electrons from the floating gate to the silicon substrate is performed, electric field concentration occurs in the portion where the shape has changed, leading to variations in the erasing speed of each cell. This variation in the erasure speed causes an expansion of the erasure Vth distribution width, and causes a problem of over-erasure in the NOR type flash memory. However, if oxidation is performed only to such an extent that a bird's beak does not occur in the memory cell, the gate electrode falls into STI in the peripheral circuit portion, and a kink characteristic occurs. This leads to an increase in subthreshold leakage in the peripheral circuit, and the standby current consumption of the semiconductor memory device increases.
[0005]
The above problem will be described in detail with reference to FIGS.
[0006]
After forming the tunnel oxide film 102 on the silicon substrate 101, the first polycrystalline silicon 103 which is the lower layer portion of the floating gate is deposited (FIG. 18A). Next, a shallow trench (STI region) 104 is formed to form an element isolation region (FIG. 18B). At this time, the end portion of the floating gate and the STI are formed in a self-aligned manner, the floating gate does not fall into the STI trench, and the operation variation of the memory cell hardly occurs. The STI region is filled with an insulating film 105, and then a second polycrystalline silicon layer 106 which is an upper layer portion of the floating gate is deposited, and then separated for each cell (FIG. 18C).
[0007]
Next, an insulating film 107 between the floating gate and a control gate formed later is formed. Usually, it is a three-layer structure film of oxide film / nitride film / oxide film (FIG. 18D). From this next figure, the process of forming the peripheral circuit portion is shown.
[0008]
The insulating film 107, the floating gates 103 and 106, and the tunnel oxide film 102 in the peripheral circuit portion are removed. In the wet etching process for removing the tunnel oxide film, the buried insulating film 105 at the end of the STI may recede and a depression may occur. In this case, as shown in FIG. 19, the gate electrode 108 of the peripheral circuit is applied to the side surface of the AA (Active Area) region, and at the same time, the gate electrode overlaps the AA edge where electric field concentration occurs, thereby forming a parasitic transistor. Is done. This parasitic transistor has a low threshold characteristic, which is superimposed on the drain voltage / current characteristic of the main transistor to generate a kink characteristic.
[0009]
As a method for preventing this, before forming the buried insulating film 105 in the STI, it is sufficiently oxidized to form bird's beaks at the interface between the first polycrystalline silicon and the silicon substrate, as shown in FIG. There is a way to keep it. In this way, even after the polycrystalline silicon and the tunnel oxide film are removed from the peripheral circuit portion, as shown in FIG. 20B, the insulating film can be prevented from receding at the end of the STI.
[0010]
However, it has been found that if such sufficient oxidation is performed, a great problem occurs. In other words, if a bird's beak is greatly penetrated between the floating gate and the silicon substrate in the memory cell region, the shape of the polycrystalline silicon will vary, and the shape will vary. Concentrate. When such variation in shape occurs, for example, a difference in extraction speed occurs when an operation of extracting electrons from the floating gate is performed, causing a problem that the erase Vth distribution is widened. The wide erase distribution leads to an operation failure such as over-erasure in the NOR type flash memory.
[0011]
[Problems to be solved by the invention]
As described above, in the conventional STI type nonvolatile semiconductor memory device, in order to suppress the kink characteristics of the peripheral circuit transistor, a large bird's beak is sometimes formed at the interface between the polycrystalline silicon and the silicon substrate. However, bird's beaks also invade between the floating gate of the memory cell portion and the silicon substrate. This causes a difference in extraction speed when an operation of extracting electrons from the floating gate is performed, and the erase Vth distribution is widened. Problem arises.
[0012]
The present invention has been made in view of the above circumstances, and there is little variation in the characteristics of the memory cell section, and there is no occurrence of kink characteristics in the peripheral circuit section, and therefore there is no increase in standby current consumption. Method for manufacturing nonvolatile semiconductor memory device Is to provide.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention (claim 1) includes a memory cell portion having an element region formed by trench-type element isolation and a floating gate, and its peripheral circuit portion. A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a polycrystalline silicon layer on a silicon substrate via an insulating film, and forming the device region by using the polycrystalline silicon layer and the insulating film, Etching the silicon substrate in a self-aligned manner to form a plurality of element isolation trenches having a bottom and surrounding the element region in the silicon substrate; and each end of the surface where the element region and the polycrystalline silicon layer face each other A step of rounding the portion by oxidation, a step of covering only the memory cell portion with an oxidation-resistant film, and an oxidation after the formation of the oxidation-resistant film, and in the element region of the peripheral circuit portion, a silicon substrate Between the ends of the polycrystalline silicon layer is opposed surfaces, characterized by a step of forming a thick bird's beak-shaped oxide film than the memory cell portion.
[0014]
In the above manufacturing method, after the deposition of the oxidation resistant film, before the oxidation of the peripheral circuit portion, in the memory cell portion, the oxidation resistant film is left only on the side surface of the floating gate. Can be further removed.
[0015]
Further, the oxidation resistant film covering the memory cell portion may be removed after the peripheral circuit portion is oxidized.
[0016]
In order to achieve the above object, a method for manufacturing a semiconductor memory device according to the present invention (claim 4) includes a memory cell portion having an element region formed by trench-type element isolation and having a floating gate and its peripheral circuit portion. A method for manufacturing a nonvolatile semiconductor memory device, in which a polycrystalline silicon layer is formed on a silicon substrate through an insulating film, and only the peripheral circuit portion is self-aligned with the polycrystalline silicon layer, the insulating film, and the silicon substrate. Etching to form a first element isolation groove, and in the peripheral circuit portion, each end of the surface where the element region and the polycrystalline silicon layer face each other is oxidized to form a bird's beak-like oxide film A step of etching the polycrystalline silicon layer, the insulating film, and the silicon substrate in the memory cell portion in a self-aligned manner to form a second element isolation groove; and after forming the second element isolation groove, Forming a bird's beak-like oxide film that is thinner than the bird's beak-like oxide film formed in the peripheral circuit portion by oxidizing each end of the surface where the element region and the polycrystalline silicon layer face each other. Features.
[0017]
In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention (claim 5) includes a memory cell portion having an element region formed by trench-type element isolation and a floating gate, and a peripheral circuit portion thereof. A method for manufacturing a nonvolatile semiconductor memory having a step of stacking an oxidation resistant film on a silicon substrate via an insulating film, and selectively removing the oxidation resistant film and the insulating film of the memory cell portion A step of forming a tunnel oxide film in the memory cell portion and nitriding the tunnel oxide film to convert the tunnel film into an oxynitride film; and an oxidation resistance of the upper portion of the tunnel oxynitride film in the memory cell portion and the peripheral circuit portion A step of forming a polycrystalline silicon layer on the top of the film, a step of etching the polycrystalline silicon and the silicon substrate in a self-aligned manner to form a groove for element isolation, and an oxidation after forming the groove for element isolation, Device area and multiple connection Silicon layer to form a bird's beak-shaped oxide film between the ends of opposing surfaces, characterized by a step of forming a thick bird's beak-shaped oxide film from the memory cell portion in the peripheral circuit portion.
[0018]
In order to solve the above problems, a method for manufacturing a non-volatile semiconductor device according to the present invention (claim 6) includes a memory cell section having an element region formed by trench-type element isolation and having a floating gate and its peripheral circuit. A method of manufacturing a non-volatile semiconductor memory device having a portion comprising: a step of forming a polycrystalline silicon layer on a silicon substrate via an insulating film; and etching the polycrystalline silicon layer and the silicon substrate in a self-aligning manner. A step of forming a trench for element isolation to form an element region, a step of rounding edges of the opposing surfaces of the element region and the polycrystalline silicon by oxidation, and a step of forming only a memory cell portion with a silicon film Adding a step of coating with silicon and post-coating oxidation of the silicon film, While making the silicon film covering the memory cell part into an oxide film, And a step of forming a bird's beak-like oxide film thicker than the memory cell portion between end portions of opposing surfaces of the silicon substrate and the polycrystalline silicon layer of the peripheral circuit portion.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
(First embodiment)
1 to 5 are sectional views of a peripheral circuit section showing steps of a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention.
[0024]
First, a tunnel oxide film 302 of a memory cell is formed on the entire surface of the silicon substrate 301, for example, 10 nm. Next, a 70 nm thick first polycrystalline silicon layer 303 serving as a lower layer of the floating gate is formed thereon (FIG. 1A). Further, a silicon nitride film 304 is usually deposited thereon, for example, 200 nm. Thereafter, a resist pattern in which a portion for forming the STI trench is opened is formed by a photolithography process, and the silicon nitride film 304 is processed based on the resist pattern (FIG. 1B).
[0025]
Next, using the nitride film 304 as a mask, the first floating gate polycrystalline silicon 303, the tunnel oxide film 302, and the silicon substrate 301 are sequentially etched vertically by the RIE method. A shallow trench 305 dug in the silicon substrate 301 is a trench for element isolation (Shallow Trench Isolation: STI).
[0026]
Next, an oxidation process, for example, a thermal oxidation process of 10 nm, is performed with the amount of oxidation suppressed as little as possible so that a bird's beak does not enter so much at the interface between the first polycrystalline silicon 303 serving as a floating gate and the silicon substrate 301. Thereby, a thermal oxide film 306 is formed (FIG. 1C).
[0027]
Next, an oxide film 307 is thinly deposited thereon by a CVD method. Further, an oxidation-resistant film, specifically, a silicon nitride film 308 is deposited thereon, for example, 6 nm (FIG. 1 (d)).
[0028]
Next, a resist pattern 309 having openings only in the peripheral circuit portion is formed on the substrate by a photolithography process (FIG. 2A). Using this resist pattern 309 as a mask, the oxidation resistant film 308 in the peripheral circuit portion is removed (FIG. 2B). For example, a silicon nitride film can be removed by a method such as CDE (Chemical Dry Etching). The CVD oxide film 307 formed under the oxidation resistant film plays a role of reducing damage entering the silicon substrate when a buried insulating film is deposited inside the STI later.
[0029]
Next, oxidation is performed to insert bird's beaks into the opposing surface end portions of the element region (silicon substrate 301) and the first polycrystalline silicon layer 303 in the peripheral circuit portion (FIG. 2 (c)). The bird's beak 310 formed by this oxidation reduces the drop of the gate electrode when the peripheral circuit is formed later. Therefore, this oxidation is performed under a sufficient amount, for example, a condition for forming a 30 nm oxide film on the silicon substrate.
[0030]
At this time, the memory cell portion is covered with the oxidation resistant film 308 and is not oxidized. If necessary, the oxidation resistant film may be removed thereafter. If a silicon nitride film exists in the vicinity of the memory cell, the tunnel oxide film may be damaged by hydrogen diffused from the silicon cell. Therefore, it may be removed if necessary, but this example shows a case where it is not removed. When the silicon nitride film is removed, it may be removed by hot phosphoric acid etching or CDE after the step of FIG.
[0031]
Next, for example, a plasma oxide film 311 is deposited in order to fill the inside of the STI (FIG. 3A). When the aspect ratio is high, the film may be deposited using a high density plasma (HDP) CVD method. Next, the plasma oxide film 311 is planarized by, for example, CMP (Chemical Mechanical Polishing) (FIG. 3B).
[0032]
Next, the silicon nitride film 304 on the first floating gate polycrystalline silicon 303 is removed by wet etching. In some cases, in order to adjust the height of the insulating film 311 embedded in the STI, the insulating film 311 may be slightly etched before the nitride film is removed. Thereafter, a second floating gate polycrystalline silicon layer 312 is formed thereon. Further, a lithography process and etching of the floating gate isolation region 313 are performed on the STI region, and processing for separating the floating gate for each cell is performed (FIG. 3C).
[0033]
Next, a laminated insulating film 314 of, for example, an oxide film / nitride film / oxide film (ONO), which becomes an insulating film between the floating gate and the control gate, is formed on the floating gate (FIG. 4A). After this, the figure shows only the peripheral circuit section.
[0034]
Next, the memory cell region is covered with a resist by a photolithography process, the ONO film 314 in the peripheral circuit region, the first and second polycrystalline silicons 303 and 312 for the floating gate are dry-etched, and the tunnel oxide film 312 is wet. It is removed by etching (FIG. 4B). By sufficiently forming the gate bird's beak, the upper end portion of the element region is protected during the wet etching, and the oxide film can be prevented from dropping at the upper end portion.
[0035]
Next, a gate oxide film 315 having a thickness of, for example, 15 nm required for the peripheral circuit is formed (FIG. 4C), and a polycrystalline silicon layer 316 is formed thereon (FIG. 5). This polycrystalline silicon layer 316 becomes a gate electrode in the peripheral circuit portion and a control gate electrode in the memory cell portion.
[0036]
Next, although not shown in the figure, the peripheral transistors and the memory cell transistors are processed with gates, and then a diffusion layer is formed in the memory cell portion and the peripheral circuit portion as usual, and then a wiring process is performed, whereby The cell array is completed.
[0037]
By adopting the process as described above, a semiconductor memory device is realized in which a bird's beak is greatly invaded only in the peripheral circuit portion.
[0038]
(Second Embodiment)
In the first embodiment, the entire memory cell region is covered with the silicon nitride film. However, if the entire surface is covered with the silicon nitride film and heat treatment is applied, the tunnel oxide film of the memory cell may be deteriorated. In order to minimize this phenomenon, the oxidation resistant film may be formed in a sidewall shape on the side surface of the floating gate of the memory cell. The second embodiment provides such a method.
[0039]
First, the steps of FIGS. 1A to 1D in the first embodiment are performed. After the oxidation resistant film 308 is deposited in FIG. 1D, the entire surface is etched back by RIE to leave the oxidation resistant film only on the side walls. Thereby, a structure as shown in FIG. 6 is obtained. Thereafter, the same steps as those in FIG. 2 and subsequent steps of the first embodiment are performed to complete the structure in which the oxidation resistant film is left only on the floating gate side wall and the STI inner wall.
[0040]
(Third embodiment)
7 and 8 are cross-sectional views showing the method of manufacturing the semiconductor memory device according to the third embodiment of the present invention step by step.
[0041]
First, a tunnel oxide film 502 of a memory cell is formed, for example, 10 nm on the entire surface of the silicon substrate 501. Next, a first polycrystalline silicon layer 503 that becomes a part of the floating gate is formed to 70 nm thereon (FIG. 7A). Further, a silicon nitride film 504 is deposited thereon, for example, 200 nm. Thereafter, by a photolithography process, a resist pattern (not shown) having an opening for forming an STI trench only in the peripheral circuit portion is formed, and the silicon nitride film 504 is processed. Next, using the nitride film 304 as a mask, the first floating gate polycrystalline silicon layer 503, the tunnel oxide film 502, and the silicon substrate 501 are sequentially etched vertically by the RIE method to form an STI 505.
[0042]
Subsequently, in order to form a sufficient bird's beak oxide film 506 at the interface between the polycrystalline silicon layer 503 and the silicon substrate 501 in the peripheral circuit portion, for example, oxidation of 30 nm is performed (FIG. 7C). At this time, the memory cell portion is covered with the silicon nitride film and is not oxidized.
[0043]
Next, the STI trench 507 in the memory cell portion is formed (FIG. 8A). Subsequently, the minimum necessary oxidation for the memory cell, for example, oxidation of 6 to 10 nm is performed to form an oxide film 508 (FIG. 8B). Thereafter, a buried insulating film forming step in the STI corresponding to FIG. 3 of the first embodiment is performed.
[0044]
The semiconductor memory device in which the bird's beak is greatly invaded only in the peripheral circuit portion is also realized by the process as described above.
[0045]
(Fourth embodiment)
9 and 10 are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the fourth embodiment of the present invention step by step.
[0046]
First, a first thick oxide film, for example, an oxide film 602 of about 20 nm is formed on a silicon substrate 601 (FIG. 9A). Next, an oxidation-resistant film, for example, a silicon nitride film 603 is deposited on the upper portion thereof to 8 nm (FIG. 9B).
[0047]
Next, the resist 604 is left in the peripheral circuit portion by the lithography process, the silicon nitride film 603 in the memory cell portion is removed (FIG. 9C), and the 20 nm silicon oxide film in the memory cell portion is etched after further removing the resist. Remove.
[0048]
Next, a tunnel oxide film 605 is formed in the memory cell portion with a thickness of 9 nm, for example. Since there is an oxidation resistant film (silicon nitride film) 603 in the peripheral circuit portion, there is no change. Subsequently, nitrogen is introduced between the tunnel oxide film 605 and the silicon substrate 601 by nitriding treatment (FIG. 9D). This nitriding prevents the bird's beak from entering in a later step and generally improves the reliability of the cell because the tunnel oxide film becomes oxynitride. At this time, since the peripheral circuit portion is covered with the nitride film, the interface between the first oxide film 602 and the silicon substrate 601 is not nitrided. Nitriding is generally performed using ammonia or N ₂ The heat treatment can be performed in a gas such as O or NO.
[0049]
Next, a first polycrystalline silicon layer 606 that forms a lower layer of the floating gate is formed to 70 nm thereon (FIG. 10A). Further, a silicon nitride film 607 is usually deposited thereon with a thickness of 200 nm, for example. Thereafter, a resist pattern in which a portion for forming an STI trench is opened is formed by a lithography process, and the silicon nitride film 607 is processed.
[0050]
Next, using the nitride film 607 as a mask, in the peripheral circuit portion, the first floating gate polycrystalline silicon layer 606, the silicon nitride film 603, the underlying first oxide film 602, and the silicon substrate 601 are connected to the memory cell portion. Then, the first floating gate polycrystalline silicon layer 606, the tunnel oxide film 605, and the silicon substrate 601 are sequentially etched vertically by the RIE method. This shallow groove dug in the silicon substrate is an element isolation groove (STI) (FIG. 10B).
[0051]
Next, oxidation is performed to insert bird's beaks at the interface edge between the element region of the peripheral circuit portion and the silicon nitride film 603 (FIG. 10C). Oxidation films 609 and 610 are formed by this oxidation. The peripheral circuit bird's beak 610 formed thereby can reduce the drop of the gate electrode when the peripheral circuit is formed later. Therefore, a sufficient amount of this oxidation is performed. At this time, the tunnel oxide film is nitrided in the memory cell portion, and the oxide film thickness is smaller than that of the peripheral circuit portion.
[0052]
On the other hand, in the peripheral circuit portion, since there is a thick silicon oxide film 602 that is not nitrided on the element region, a bird's beak 610 that is thicker than the memory cell portion can be inserted at the interface between the silicon substrate 601 and the silicon oxide film 602. . The thick silicon oxide film 602 in the peripheral circuit portion and the silicon nitride film 603 thereabove are completely removed before forming the gate oxide film in the peripheral circuit portion (step of FIG. 4B in the first embodiment). Equivalent).
[0053]
The semiconductor memory device in which the bird's beak is greatly invaded only in the peripheral circuit portion is also realized by the process as described above.
[0054]
(Fifth embodiment)
FIG. 11 to FIG. 14 are cross-sectional views showing stepwise a method of manufacturing a semiconductor memory device according to the fifth embodiment of the present invention.
[0055]
First, a tunnel oxide film 702 of a memory cell is formed on the entire surface of the silicon substrate 701, for example, 10 nm. Next, a first polycrystalline silicon layer 703 serving as a lower layer portion of the floating gate is formed thereon to a thickness of 70 nm (FIG. 11A).
[0056]
Further, usually, a silicon nitride film 704 is deposited to 200 nm, for example. Thereafter, a pattern in which a portion for forming the STI trench is opened is formed by a photolithography process, and the silicon nitride film is processed. Next, using this nitride film as a mask, the first floating gate polycrystalline silicon layer, the tunnel oxide film, and the silicon substrate are sequentially processed by the RIE method. A shallow groove dug in the silicon substrate is an element isolation groove (STI) (FIG. 11B).
[0057]
Next, oxidation is performed while suppressing the amount of oxidation as small as possible so that there is not much bird's beak at the interface between the first polycrystalline silicon serving as the floating gate and the silicon substrate. For example, a thermal oxidation process of 10 nm is performed. Thereby, a thermal oxide film 706 is formed (FIG. 11C).
[0058]
Next, an oxide film 707 is deposited thereon by a CVD method. Further, a silicon film is formed thereon. Specifically, an amorphous silicon film 708 is deposited by 10 nm, for example, by a low pressure CVD (LPCVD) method (FIG. 11D).
[0059]
Next, a resist pattern 709 having an opening only in the periphery is formed by a photolithography process (FIG. 12A). Using this resist material as a mask, the silicon film 708 in the peripheral circuit portion is removed (FIG. 12B). For example, an amorphous silicon film can be removed by a method such as CDE. The CVD oxide film 707 formed under the silicon film plays a role of reducing damage entering the silicon substrate when a buried insulating film is deposited later in the STI.
[0060]
Next, oxidation is performed to introduce bird's beaks into the STI edge of the peripheral circuit section (FIG. 12C). The bird's beak 710 formed by this oxidation can reduce the fall of the gate electrode when the peripheral circuit portion is formed later. Therefore, this oxidation is carried out in a sufficient amount. For example, it is performed under conditions for forming an oxide film of 30 nm on a silicon substrate.
[0061]
On the other hand, the memory cell portion is covered with an amorphous silicon film 708, and is completely oxidized during bird's beak oxidation at the upper end of the element region of the peripheral circuit portion. Double 20 nm.
[0062]
In the memory cell portion, after the amorphous silicon film 708 becomes the silicon oxide film 711 completely, the oxidant diffuses the silicon oxide film 711 and the first polycrystalline silicon film 703 which is the lower layer portion of the silicon substrate 701 and the floating gate. Is also oxidized.
[0063]
However, since the oxidant diffuses the silicon oxide film 711 and further diffuses the silicon oxide film 706 formed by the CVD method to reach the silicon substrate 701 or the polycrystalline silicon film 703, the lower layer of the silicon substrate 701 and the floating gate is used. The oxidation rate of the first polycrystalline silicon film 703 which is the portion is greatly suppressed. Therefore, in this process, the bird's beak hardly enters the upper end portion of the element region of the memory cell portion.
[0064]
The amount of oxidation for placing a bird's beak at the upper end of the element region of the peripheral circuit portion needs to be equal to the amount of oxidation required for the silicon film 708 deposited in the memory cell portion to completely become the silicon oxide film 711, and the memory. In the cell portion, it is necessary that almost no bird's beak enters the upper end portion of the element region, and the deposited film thickness of the silicon oxide film 708 is set taking this into consideration.
[0065]
Next, for example, a plasma oxide film 712 is deposited to fill the STI (FIG. 13A). If the aspect ratio is high, it may be deposited using high density plasma (HDP) CVD. Next, the plasma oxide film is planarized by, eg, CMP (FIG. 13B).
[0066]
Next, the silicon nitride film 704 on the first floating gate polycrystalline silicon 703 is removed by wet etching. In some cases, in order to adjust the height of the insulating film 712 embedded in the STI, the insulating film 712 may be slightly etched before the nitride film 704 is removed.
[0067]
Thereafter, a second floating gate polycrystalline silicon layer 713 is formed on the entire surface of the substrate. Further, a lithography process and etching of the floating gate isolation region 714 are performed on the STI region, and processing for separating the floating gate for each cell is performed (FIG. 13C).
[0068]
Next, a laminated insulating film 715 of, for example, an oxide film / nitride film / oxide film (ONO), which becomes an insulating film between the floating gate and the control gate, is formed on the floating gate 713 (FIG. 14A). Thereafter, only the peripheral circuit portion is shown.
[0069]
Next, the memory cell portion is covered with a resist by a photolithography process, the ONO film in the peripheral circuit portion, the first and second polycrystalline silicon for the floating gate are removed by dry etching, and the tunnel oxide film is removed by wet etching ( FIG. 14 (b)). Since the gate bird's beak is sufficiently formed during the wet etching, the upper end portion of the element region is protected and the oxide film can be prevented from dropping at the upper end portion.
[0070]
Next, a gate oxide film 716 having a necessary oxide film thickness, for example, 15 nm is formed in the peripheral circuit portion (FIG. 14C), and then a polycrystalline silicon layer 717 is formed thereon (FIG. 14D). ). The polycrystalline silicon layer 717 becomes a gate electrode of the peripheral circuit portion and a control gate of the memory cell.
[0071]
Next, although not shown in the figure, the peripheral transistors and the memory cell transistors are processed by gate processing, and then a diffusion layer is formed in the memory cell portion and the peripheral circuit portion as usual. The cell array is completed.
[0072]
The semiconductor memory device in which the bird's beak is greatly invaded only in the peripheral circuit portion is also realized by the process as described above.
[0073]
(Sixth embodiment)
15 to 17 are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the fifth embodiment of the present invention step by step. Unlike the first to fifth embodiments, the present embodiment does not form a large bird's beak at the upper end of the element region of the peripheral circuit section, but covers the STI side walls of the peripheral circuit section with an oxynitride film to provide STI buried insulation. When the film is etched back, the side surface of the element region is prevented from being exposed, thereby suppressing the drop of the gate electrode of the peripheral circuit portion to the side surface of the element region.
[0074]
Hereinafter, the manufacturing process will be described with reference to the drawings. FIG. 15 to FIG. 17A are applied to both the memory cell portion and the peripheral circuit portion, and FIG. 17B to FIG. It is a figure applied to a circuit part.
[0075]
First, a silicon oxide film 802 serving as a tunnel oxide film of a memory cell is formed on the entire surface of the silicon substrate 801, for example, 10 nm. Next, a 70 nm thick first polycrystalline silicon layer 803 serving as a lower layer of the floating gate is formed thereon (FIG. 15A).
[0076]
Further, usually, a silicon nitride film 804 is deposited to 200 nm, for example. Thereafter, a resist pattern in which a portion for forming the STI trench is opened is formed by a photolithography process, and the silicon nitride film is processed. Subsequently, using this nitride film as a mask, the first floating gate polycrystalline silicon, tunnel oxide film, and silicon substrate are sequentially processed by the RIE method. A shallow groove dug in the silicon substrate is an element isolation groove (STI) (FIG. 15B).
[0077]
Next, an oxidation, for example, a 10 nm thermal oxidation process is performed so as to minimize the amount of oxidation so that a bird's beak is not introduced so much at the interface between the first polycrystalline silicon serving as a floating gate and the silicon substrate. Thereby, a thermal oxide film 806 is formed (FIG. 15C).
[0078]
Next, a silicon oxide film 807 is deposited thereon, for example, by 20 nm by the CVD method. Thereafter, the silicon oxide films 806 and 807 are changed to thermal nitride films (FIG. 15 (D)). Specifically, for example, NH at 900 ° C. ₃ Treated for 60 minutes in an atmosphere, and further O at 900 ° C ₂ Treat for 60 minutes in atmosphere. By this treatment, the interface region between the silicon oxide film 806 and silicon and the surface region of the silicon oxide film 807 become an oxynitride film containing several percent of nitrogen.
[0079]
Next, for example, a plasma oxide film 812 is deposited in order to fill the inside of the STI (FIG. 16A). If the aspect ratio is high, it may be deposited using high density plasma (HDP) CVD. Next, the plasma oxide film is planarized by, eg, CMP (FIG. 16B).
[0080]
Next, the silicon nitride film 804 on the first floating gate polycrystalline silicon 803 is removed by wet etching. In some cases, the insulating film 812 may be slightly etched before the nitride film 804 is removed in order to adjust the height of the insulating film 812 embedded in the STI. Thereafter, a second floating gate polycrystalline silicon layer 813 is formed on the entire surface of the substrate. Further, a lithography process and etching of the floating gate isolation region 814 are performed on the STI region, and processing for separating the floating gate for each cell is performed (FIG. 16C).
[0081]
Next, on the floating gate 813, a laminated insulating film 815 of, for example, an oxide film / nitride film / oxide film (ONO) to be an insulating film between the floating gate and the control gate is formed (FIG. 17A). After this, only the portion that becomes the peripheral circuit is shown.
[0082]
Next, the memory cell portion is covered with a resist (not shown), the ONO film of the peripheral circuit portion, the first and second polycrystalline silicon layers 803 and 813 are removed by dry etching, and the tunnel oxide film 802 is removed by wet etching. (FIG. 17B). During this wet etching, the silicon sidewalls of the STI and the side surfaces of the first floating gate electrode 802 are covered with the oxynitride films 806 and 807 that are oxynitrided. Therefore, the etching speed of this portion is the etching speed of the tunnel oxide film 802. Will be slower. For this reason, the element region upper end side surface is not exposed.
[0083]
Next, a gate oxide film 816 having a necessary oxide film thickness, for example, 15 nm is formed in the peripheral circuit portion (FIG. 17C), and then a polycrystalline silicon layer 817 is formed thereon (FIG. 17D). . This polycrystalline silicon layer becomes the gate electrode of the peripheral circuit portion and the control gate of the memory cell.
[0084]
In the present embodiment, the silicon oxide film 806 is deposited on the inner wall of the STI by the oxidation process, and then the silicon oxide film 807 is deposited. However, the silicon oxide films 806 and 807 do not necessarily have to be two layers. A single-layer silicon oxide film by oxidation treatment may be used.
[0085]
Next, although not shown, the peripheral cell and the memory cell transistor are processed by a gate, and then a diffusion layer is formed in the memory cell and the peripheral circuit part as usual, and then a wiring process is performed, whereby a memory cell array Is completed.
[0086]
In the present embodiment, the side surface of the upper edge of the element region after forming the gate electrode of the peripheral circuit portion is covered with at least the oxynitride film formed on the inner wall of the STI. Does not occur.
[0087]
Although the present invention has been described based on the embodiments, the present invention is not limited to this, and various modifications can be made without departing from the spirit of the invention. For example, the peripheral circuit portion is not limited to the control circuit of the memory cell portion, but can include a CPU or the like.
[0088]
【The invention's effect】
According to the first aspect of the present invention (the invention described in the first to fifth embodiments), the bird's beak is not formed so large between the active region of the memory cell and the silicon substrate, and the peripheral circuit portion is not formed. Since a large bird's beak can be formed, the characteristic variation of the memory cell can be reduced. On the other hand, since the bird's beak is formed in the peripheral circuit, the occurrence of the kink characteristic of the MOSFET can be prevented, and the increase in standby current consumption can be suppressed.
[0089]
In the second aspect of the present invention (the invention described in the sixth embodiment), since the STI inner wall is covered with the silicon oxynitride film, the element is removed when the tunnel oxide film is peeled off in the peripheral circuit portion. It is possible to suppress a decrease in the thickness of the insulating film at the upper end of the region, and similarly, it is possible to prevent the occurrence of kink characteristics of the MOSFET and to suppress an increase in standby current consumption.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing stepwise a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a step following FIG.
3 is a cross-sectional view showing a step that follows FIG. 2. FIG.
4 is a cross-sectional view showing a step that follows FIG. 3. FIG.
FIG. 5 is a sectional view showing a step following FIG.
FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the invention.
FIG. 7 is a cross-sectional view showing stepwise a manufacturing method of a semiconductor memory device according to a third embodiment of the present invention.
8 is a cross-sectional view showing a step that follows the step in FIG.
FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fourth embodiment of the present invention in stages.
10 is a cross-sectional view showing a step that follows FIG. 9. FIG.
FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to a fifth embodiment of the present invention in stages.
12 is a cross-sectional view showing a step that follows FIG.
13 is a cross-sectional view showing a step that follows the step shown in FIG. 12. FIG.
FIG. 14 is a cross-sectional view showing a step that follows the step of FIG.
FIG. 15 is a cross-sectional view showing a step-by-step method of manufacturing a semiconductor memory device according to a sixth embodiment of the present invention.
16 is a cross-sectional view showing a step that follows the step of FIG.
17 is a cross-sectional view showing a step that follows FIG. 16. FIG.
FIG. 18 is a cross-sectional view showing a conventional method of manufacturing a semiconductor memory device in stages.
FIG. 19 is a cross-sectional view for explaining a parasitic transistor generated in a conventional semiconductor memory device.
FIG. 20 is a cross-sectional view for explaining a method of forming a bird's beak and a problem thereof in a conventional semiconductor memory device.
[Explanation of symbols]
301 ... silicon substrate
302 ... Tunnel oxide film
303 ... 1st polycrystalline silicon layer
304, 308 ... Silicon nitride film
305 ... STI groove
306 ... Silicon oxide film
307: CVD oxide film
309 ... Photoresist
310 ... Peripheral circuit part Bird's beak
311... STI buried insulating film
312 ... Second polycrystalline silicon layer
313: Floating gate isolation region
314: Insulating film between gate electrodes
315 ... Peripheral gate insulating film
316 ... polycrystalline silicon for gate electrode

Claims (6)

A method of manufacturing a nonvolatile semiconductor memory device having an element region formed by trench-type element isolation and having a memory cell portion having a floating gate and a peripheral circuit portion thereof,
Forming a polycrystalline silicon layer on the silicon substrate via an insulating film;
In order to form an element region, the polycrystalline silicon layer, the insulating film, and the silicon substrate are etched in a self-aligned manner to form a plurality of element isolation grooves having a bottom in the silicon substrate and surrounding the element region. When,
A step of rounding each end of the surface where the element region and the polycrystalline silicon layer face each other by oxidation;
Coating only the memory cell portion with an oxidation-resistant film;
After the formation of the oxidation resistant film, oxidation is added to form a bird's beak-like oxide film thicker than the memory cell portion between the end portions of the surface of the peripheral circuit portion where the silicon substrate and the polycrystalline silicon layer face each other. And a process of
A method of manufacturing a nonvolatile semiconductor memory device, comprising:   After the deposition of the oxidation resistant film, before the oxidation of the peripheral circuit portion, in the memory cell portion, the oxidation resistance film is left only on the side surface of the floating gate and the inner wall of the element isolation trench. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a step of selectively removing the conductive film.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein after the oxidation of the peripheral circuit portion, the oxidation resistant film covering the memory cell portion is removed. A method of manufacturing a nonvolatile semiconductor memory device having an element region formed by trench-type element isolation and having a memory cell portion having a floating gate and a peripheral circuit portion thereof,
Forming a polycrystalline silicon layer on the silicon substrate via an insulating film;
Etching only the peripheral circuit portion, the polycrystalline silicon layer and the insulating film, the silicon substrate in a self-aligning manner, and forming a first element isolation groove;
Forming a bird's beak-like oxide film by oxidizing each end of the surface where the element region and the first polycrystalline silicon layer face each other in the peripheral circuit portion;
Etching the polycrystalline silicon layer, the insulating film, and the silicon substrate of the memory cell portion in a self-aligned manner to form a second element isolation groove;
After the formation of the second element isolation trench, the end portions of the surfaces of the memory cell portion where the element region and the polycrystalline silicon layer face each other are oxidized to form a bird's beak shape thinner than the bird's beak-like oxide film formed in the peripheral circuit portion. Forming an oxide film;
A method for manufacturing a nonvolatile semiconductor device, comprising: A method of manufacturing a nonvolatile semiconductor memory having an element region formed by trench type element isolation and having a floating gate and a peripheral circuit portion thereof,
Forming an oxidation-resistant film on the silicon substrate via an insulating film;
Selectively removing the oxidation-resistant film and the insulating film in the memory cell portion;
Forming a tunnel oxide film in the memory cell portion and nitriding the tunnel oxide film to form an oxynitride film;
Forming a polycrystalline silicon layer on the upper portion of the tunnel oxynitride film in the memory cell portion and the upper portion of the oxidation resistant film in the peripheral circuit portion;
Etching the polycrystalline silicon and the silicon substrate in a self-aligned manner to form a groove for element isolation in the memory cell portion and the peripheral circuit portion;
A step of forming a bird's beak-like oxide film at the end of each surface where the element region and polycrystalline silicon face each other by oxidation after forming the element isolation trench, and forming a bird's beak-like oxide film thicker than the memory cell portion in the peripheral circuit portion When,
A method for manufacturing a nonvolatile semiconductor device, comprising: A method of manufacturing a nonvolatile semiconductor memory device having an element region formed by trench-type element isolation and having a memory cell portion having a floating gate and a peripheral circuit portion thereof,
Forming a polycrystalline silicon layer on the silicon substrate via an insulating film;
Etching the polycrystalline silicon layer and the silicon substrate in a self-aligned manner to form an element region;
A step of rounding edges of respective faces of the element region and polycrystalline silicon by oxidation;
Covering only the memory cell portion with a silicon film;
The silicon film covering the memory cell part is converted into an oxide film by adding oxidation after covering the silicon film, and the memory cell part between the end parts of the peripheral surface of the silicon substrate and the polycrystalline silicon layer facing each other. Forming a thicker bird's beak-like oxide film;
A method of manufacturing a nonvolatile semiconductor memory device, comprising:

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