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JP3827407B2 - Semiconductor mounting substrate - Google Patents

Semiconductor mounting substrate Download PDF

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Publication number
JP3827407B2
JP3827407B2 JP17857097A JP17857097A JP3827407B2 JP 3827407 B2 JP3827407 B2 JP 3827407B2 JP 17857097 A JP17857097 A JP 17857097A JP 17857097 A JP17857097 A JP 17857097A JP 3827407 B2 JP3827407 B2 JP 3827407B2
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Japan
Prior art keywords
semiconductor
substrate
chip
semiconductor device
mounting
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JPH1126627A (en
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淳介 田中
守次 森田
浩太郎 朝比奈
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Mitsui Chemicals Inc
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Mitsui Chemicals Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Adhesives Or Adhesive Processes (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、生産性に優れ、はんだ付け時に生じるポップコーン現象が発生しにくいボールグリッドアレイ（以下、ＢＧＡと称する）半導体装置及びそれを搭載する基板に関し、特に、回路配線を有する基板上に半導体チップが搭載され、該半導体チップの電極と前記回路配線とを電気的に接続し、少なくとも前記半導体チップが樹脂で封止され、前記半導体チップが搭載された面と反対側の面に複数のはんだバンプが設けられているボールグリッドアレイ半導体装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
近年の半導体装置の高機能化に伴い、面付実装型パッケージの外部リードの数は増大する傾向にある。これらの半導体装置の代表例がＱＦＰ（Quad Flat Pakage）である。ＱＦＰは半導体装置の側面に外部リードを設けているため、外部リードの間隔を狭くしたとしても、外部リードの数の増大によりパッケージサイズは大型化の傾向にある。これに対して、近年、開発された面付実装型パッケージがＢＧＡ半導体装置である。このＢＧＡ半導体装置は、図１に示すように、回路配線を有する基板１の片側の面の面２に半導体チップ３を、搭載し、基板１と半導体チップを金ワイヤ等４で電気的に接続し、基板１の半導体チップを搭載した面２を封止樹脂５で封止している。また、基板１の半導体チップを搭載した面の反対側の面６に、半導体チップと電気的に接続した複数の電極７を形成し、電極７上にはんだバンプ８を設けて外部電極としている。このはんだバンプ８は、面６上にアレイ状に配置されているため、ＱＦＰと比較するとより多くの外部電極が設けられ、また、同じ外部電極数なら、ＱＦＰよりもパッケージサイズが小さくできるという特徴を有する。このＢＧＡ半導体装置を、実装基板上に位置決めして搭載し、実装基板とパッケージを加熱することによりはんだバンプ８をリフローし、実装基板上の電極と接続する。
前記ＢＧＡ半導体装置に関する技術については、米国特許第５，２４１，１３３号に記載されている。
【０００３】
【発明が解決しようとする課題】
このＢＧＡ半導体装置の問題点としては、IEEE TRANSACTIONS ON COPONENTS,PACKAGING,AND MANUFACTURING TECHNOLOGY-PART B,vol 18,No3,pp491〜495,1995 に記載されているような、はんだリフロー時のポップコーン現象がある。ポップコーン現象とは、半導体装置が吸湿し、リフロー時の温度により、吸湿した水分が気化し、半導体装置内にクラックが発生する現象である。このポップコーン現象を防ぐためには、防湿梱包を行ったり、はんだリフローする前に乾燥する必要があり、ポップコーン現象が起きない半導体装置が要求されている。本発明は、ポップコーン現象の発生しにくいＢＧＡ半導体装置、半導体搭載用基板、さらには、生産性に優れた半導体搭載用基板を提供するものである。
【０００４】
【課題を解決するための手段】
上記、問題点を解決するために、本発明者らは、上記課題を解決するため、鋭意研究を重ねた結果、半導体チップが搭載される回路基板において、半導体チップが搭載される部分に予め接着剤層が設けられており、この接着剤層が、基板のスルーホールを塞がない構造を有させることにより、ＢＧＡ半導体装置におけるポップコーン現象を起しにくくすることを見出し、本発明を完成することにいたった。
【０００５】
すなわち、本発明は、（１）半導体チップが搭載される回路配線を有する基板において、半導体チップが搭載される部分に銅メッキが施されたスルーホールを有し、このスルーホールのチップ搭載側の逆側が開口しており、さらに半導体チップが搭載される部分に、熱可塑性樹脂からなる接着剤層がスルーホールを塞がないように設けられている半導体搭載用基板、
（２） （１）に記載の接着剤層が、熱可塑性樹脂の他に金属または無機フィラーを含む半導体搭載用基板、
（３） （１）または（２）に記載の半導体搭載用基板を用いることを特徴とする半導体装置、
を提供するものである。
【０００６】
【発明の実施の形態】
ポップコーン現象が発生する原因としては、半導体チップ下の接着剤層部分に入った水分が、はんだリフロー時の温度により、気化し、その発生圧力により、クラックが発生するものと考えられている。本発明においては、回路基板のチップ搭載にスルーホールがあり、かつ、このスルーホール部が塞がれていないため、はんだリフロー時に発生する水蒸気がこのスルーホールを通じて、外部に容易に逃げる事ができ、チップ下に圧力が発生しないために、クラックが生じにくくなっているものと考えられる。
【０００７】
本発明で、使用される接着剤用の熱可塑性樹脂としては、ポリエーテルスルホン、ポリスルホン、ポリフェニレンスルフィド、ポリエーテルエーテルケトン、ポリイミド、ポリエーテルイミド、ポリアミドイミド、芳香族ポリアミド、ポリパラバン酸、ポリフェニレンエーテル等が挙げられる。これらは、単独でも又は２種以上混合して用いても差し支えない。
【０００８】
又、接着剤の熱伝導率を上げたり、電気伝導性を出すために、熱可塑性樹脂に金属または無機フィラーを混合することができる。本発明で使用される金属または無機フィラーとしては、一般的に知られているもの、即ち、金、銀、白金、パラジウム、アルミニウム、スズ、鉛、亜鉛、ニッケル、カーボン、鉄、銅、アルミナ、窒化アルミニウム、窒化ホウ素、酸化スズ、酸化鉄、酸化銅、タルク、雲母、カオリナイト、炭酸カルシウム、シリカ、酸化チタン等が挙げられる。これらは、単独でもまたは２種以上混合して用いても差し支えない。
【０００９】
熱可塑性樹脂からなる接着剤は、有機溶剤に溶かしたペースト状、または、押し出し成形またはキャスト法により成形したフィルム状である。ペースト状の場合は、回路基板状にスクリーン印刷または、ディスペンサー、またはスタンピングにより塗布した後、溶剤を乾燥させて、接着剤付き回路基板を得ることができる。又、フィルム状の場合は、フィルムを所定の大きさにした後、回路基板へ熱圧着することにより、接着剤付き回路基板を得ることができる。
【００１０】
一方、半導体チップの接着剤として、一般的に使用される、エポキシ樹脂等の熱硬化性樹脂タイプの接着剤を用いた場合、チップを接着する際に、気泡を除去するために、スクラブの操作が必要で、接着の際に、スルーホール部を埋めてしまい、ポップコーン現象に対する効果が得られない。
【００１１】
以下、本発明を図面（図１）を参照しながら詳細に説明する。
半導体チップが搭載される回路配線板を製造する方法は一般的なプリント配線板の製造方法で行われる。即ち、特に限定されるものではないが、ガラスエポキシ銅張積層板、ガラス変性ポリイミド銅張積層板、ガラスポリイミド銅張積層板、ガラスＢＴレジン銅張積層板、ガラスポリフェニレンオキサイド樹脂銅張積層板、アラミド樹脂銅張積層板、ポリイミド樹脂銅張積層板等の絶縁樹脂基板１を、ドリルにより孔明け後、銅メッキを施し、スルーホール１０を形成する。その後、パターニングにより所定の配線回路を形成し、絶縁性樹脂組成物からなるソルダーレジスト皮膜１１を形成する。この際、ソルダーレジスト皮膜がチップが搭載される部分のスルーホールを覆わないようにする。このようにして、回路配線板を製造した後、前述の方法により、熱可塑性樹脂からなる接着剤層９を形成した後、所定の大きさに外形加工を行い、半導体チップが搭載される回路配線基板を得ることができる。
【００１２】
本発明の回路配線基板を用いて、半導体装置を製造する場合、半導体チップ３を、接着剤層に熱圧着する。熱圧着する条件は、使用する接着剤に依存して一概に決められないが、一般的には、温度が２００〜４００℃であり、圧力は0.01〜20kg/cm2、時間は１〜120秒である。
チップを接着後、ワイヤボンディング４によりチップと基板の電気的接続を行ない、封止樹脂５をトランスファーモールドまたはポッティングにより、封止することにより、ＢＧＡ半導体装置を得ることができる。
【００１３】
【実施例】
以下、実施例として本発明のより具体的な実施の様態を、図面を参照しながら説明する。
実施例１
絶縁基板として、三菱ガス化学製のＢＴ−ＨＬ８３０、厚み０．５mmtのガラスＢＴレジン銅張積層板を使用して、図２、３、４に示すような基板を作製した。孔は、0.2mm径のドリルにより加工し、銅メッキを施し、スルーホール１０を形成した。ランド径は0.4ｍｍφである。外形寸法は、20mm角であり、チップが搭載される部分は銅箔１２がそのまま残されており、その大きさは、9mm角である。チップが搭載される部分以外は、ソルダーレジスト皮膜として、太陽インキ社のPSR4000、１１をコーティングした。次に、熱可塑性樹脂接着剤であるテクノアルファ社製のペーストタイプであるステイスティック１８１をスクリーン印刷により約40μm塗布９した（図５）後、150℃、３０分間乾燥して、接着剤付き半導体搭載用基板を得た。８mm角、厚さ0.4mmの半導体チップ３を５kg/cm2、温度200℃の条件で熱圧着した（図６）。チップ下のスルーホール１０は接着剤により塞がれることはなかった。その後、液状封止材である日立化成社製のCEC1400をポッティング、硬化し、半導体装置を得た。この半導体装置の１０個を８５℃、８５％ＲＨの恒温恒湿槽内で４８時間吸湿させた後、240℃のはんだ槽に３０秒間浸漬するはんだ耐熱性試験を行なった後、超音波顕微鏡により、半導体装置内の剥離またはクラックを観察したところ、剥離またはクラックは認められなかった。
【００１４】
実施例２
熱可塑性接着剤層として、ポリイミドタイプのフィルムである三井東圧化学社製のレグルス−ＵＡＴを、実施例１で示した基板に温度280℃、圧力５kg/cm2、時間２０秒の条件で張付けた後、半導体チップを温度３００℃、圧力１０kg/cm2、時間１０秒の条件で接着した後は、実施例１と同様な組み立て、試験を行なったところ、半導体装置内に剥離またはクラックは認められなかった。
【００１５】
比較例１
実施例１と同様の基板を用い、接着剤として、銀入りエポキシ樹脂であるエイブルスティック社のエイブルスボンド ８４L-1LMにより、チップを接着した。接着後の断面を図７に示すが、チップ下のスルーホール１０'は接着剤が入り、塞がれていた。実施例１と同様な評価を行ったところ、半導体装置１０個中、全てにクラックが発生した。
【００１６】
【発明の効果】
実施例および比較例にて説明したごとく、本発明による半導体チップ搭載用の基板は、熱可塑性樹脂からなる接着剤層をあらかじめ、設けることにより、はんだリフロー時に発生する水蒸気を外部に抜けやすい構造を得ることができ、ポップコーン現象を起こしにくい、ＢＧＡ半導体装置として、有効なものである。
【図面の簡単な説明】
【図１】本発明のＢＧＡ半導体装置の構成を示す断面図
【図２】本発明の半導体搭載用基板の回路配線を行なった後の断面図
【図３】本発明の半導体搭載用基板において、ソルダーレジスト皮膜を施した後の断面図
【図４】本発明の半導体搭載用基板（図２）をチップ搭載側から見た平面図
【図５】本発明の半導体搭載用基板において、熱可塑性樹脂からなる接着剤層を設けた後の断面図
【図６】本発明の半導体搭載用基板に半導体チップを搭載した後の断面図
【図７】半導体搭載用基板に熱硬化性樹脂からなる接着剤を用いて、半導体チップを搭載した後の断面図
【符号の説明】
１ 基板
２ 基板の半導体チップを搭載する面
３ 半導体チップ
４ 金線
５ 封止樹脂
６ 基板のはんだバンプを設ける面
７ 基板上の電極
８ はんだバンプ
９ 接着剤層
10 スルーホール
11 ソルダーレジスト皮膜
12 半導体チップを搭載する銅箔[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ball grid array (hereinafter referred to as BGA) semiconductor device which is excellent in productivity and hardly causes popcorn phenomenon that occurs during soldering, and a substrate on which the ball grid array (hereinafter referred to as BGA) is mounted. Is mounted, electrically connects the electrodes of the semiconductor chip and the circuit wiring, and at least the semiconductor chip is sealed with a resin, and a plurality of solder bumps are provided on a surface opposite to the surface on which the semiconductor chip is mounted. The present invention relates to a technique that is effective when applied to a ball grid array semiconductor device provided with the.
[0002]
[Prior art]
The number of external leads of the surface mount package tends to increase as the functionality of the semiconductor device increases in recent years. A typical example of these semiconductor devices is QFP (Quad Flat Pakage). Since QFP has external leads on the side surface of the semiconductor device, the package size tends to increase due to the increase in the number of external leads even if the interval between the external leads is narrowed. On the other hand, a surface-mounted package developed in recent years is a BGA semiconductor device. In this BGA semiconductor device, as shown in FIG. 1, a semiconductor chip 3 is mounted on one surface 2 of a substrate 1 having circuit wiring, and the substrate 1 and the semiconductor chip are electrically connected by a gold wire 4 or the like. The surface 2 on which the semiconductor chip of the substrate 1 is mounted is sealed with a sealing resin 5. A plurality of electrodes 7 electrically connected to the semiconductor chip are formed on the surface 6 of the substrate 1 opposite to the surface on which the semiconductor chip is mounted, and solder bumps 8 are provided on the electrodes 7 as external electrodes. Since the solder bumps 8 are arranged in an array on the surface 6, more external electrodes are provided compared to the QFP, and the package size can be made smaller than the QFP if the number of external electrodes is the same. Have The BGA semiconductor device is positioned and mounted on the mounting board, and the solder bumps 8 are reflowed by heating the mounting board and the package, and are connected to the electrodes on the mounting board.
The technology relating to the BGA semiconductor device is described in US Pat. No. 5,241,133.
[0003]
[Problems to be solved by the invention]
As a problem of this BGA semiconductor device, there is a popcorn phenomenon at the time of solder reflow as described in IEEE TRANSACTIONS ON COPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART B, vol 18, No3, pp491-495,1995 . The popcorn phenomenon is a phenomenon in which the semiconductor device absorbs moisture, and the moisture absorbed by the semiconductor device is vaporized due to the temperature during reflow, causing cracks in the semiconductor device. In order to prevent this popcorn phenomenon, it is necessary to dry before moisture-proof packaging or solder reflow, and a semiconductor device that does not cause popcorn phenomenon is required. The present invention provides a BGA semiconductor device, a semiconductor mounting substrate, and a semiconductor mounting substrate with excellent productivity that are less likely to cause popcorn.
[0004]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present inventors have made extensive studies in order to solve the above problems, and as a result, in the circuit board on which the semiconductor chip is mounted, the semiconductor chip is bonded in advance. An adhesive layer is provided, and it is found that the adhesive layer has a structure that does not block the through hole of the substrate, thereby making it difficult for the popcorn phenomenon in the BGA semiconductor device to occur, and the present invention is completed. I went to.
[0005]
That is, according to the present invention, (1) a substrate having a circuit wiring on which a semiconductor chip is mounted has a through hole plated with copper in a portion on which the semiconductor chip is mounted, A semiconductor mounting substrate in which the opposite side is open and an adhesive layer made of a thermoplastic resin is provided in a portion where the semiconductor chip is mounted so as not to block the through hole ,
(2) The board | substrate for semiconductor mounting in which the adhesive bond layer as described in (1) contains a metal or an inorganic filler other than a thermoplastic resin,
(3) A semiconductor device using the semiconductor mounting substrate according to (1) or (2),
Is to provide.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
As a cause of the popcorn phenomenon, it is considered that moisture entering the adhesive layer portion under the semiconductor chip is vaporized due to the temperature during solder reflow, and cracks are generated due to the generated pressure. In the present invention, since there is a through hole in the chip mounting of the circuit board and the through hole portion is not blocked, water vapor generated during solder reflow can easily escape to the outside through the through hole. It is considered that cracks are hardly generated because no pressure is generated under the chip.
[0007]
Examples of the thermoplastic resin for the adhesive used in the present invention include polyethersulfone, polysulfone, polyphenylene sulfide, polyetheretherketone, polyimide, polyetherimide, polyamideimide, aromatic polyamide, polyparabanic acid, polyphenylene ether, and the like. Is mentioned. These may be used alone or in combination of two or more.
[0008]
Moreover, in order to raise the heat conductivity of an adhesive agent or to take out electrical conductivity, a metal or an inorganic filler can be mixed with a thermoplastic resin. The metal or inorganic filler used in the present invention is generally known, that is, gold, silver, platinum, palladium, aluminum, tin, lead, zinc, nickel, carbon, iron, copper, alumina, Examples thereof include aluminum nitride, boron nitride, tin oxide, iron oxide, copper oxide, talc, mica, kaolinite, calcium carbonate, silica, and titanium oxide. These may be used alone or in combination of two or more.
[0009]
The adhesive made of a thermoplastic resin is in the form of a paste dissolved in an organic solvent, or in the form of a film formed by extrusion or casting. In the case of a paste, a circuit board with an adhesive can be obtained by applying it to the circuit board by screen printing, dispenser, or stamping and then drying the solvent. In the case of a film, a circuit board with an adhesive can be obtained by making the film a predetermined size and then thermocompression bonding to the circuit board.
[0010]
On the other hand, when using a thermosetting resin type adhesive such as epoxy resin, which is commonly used as an adhesive for semiconductor chips, scrub operation to remove bubbles when bonding chips Is necessary, and the through-hole portion is filled at the time of bonding, and the effect on the popcorn phenomenon cannot be obtained.
[0011]
Hereinafter, the present invention will be described in detail with reference to the drawings (FIG. 1).
A method of manufacturing a circuit wiring board on which a semiconductor chip is mounted is performed by a general printed wiring board manufacturing method. That is, although not particularly limited, glass epoxy copper clad laminate, glass modified polyimide copper clad laminate, glass polyimide copper clad laminate, glass BT resin copper clad laminate, glass polyphenylene oxide resin copper clad laminate, An insulating resin substrate 1 such as an aramid resin copper clad laminate or a polyimide resin copper clad laminate is drilled with a drill, and then plated with copper to form a through hole 10. Thereafter, a predetermined wiring circuit is formed by patterning, and a solder resist film 11 made of an insulating resin composition is formed. At this time, the solder resist film is made not to cover the through hole where the chip is mounted. In this way, after the circuit wiring board is manufactured, the adhesive layer 9 made of thermoplastic resin is formed by the above-described method, and then the outer shape is processed to a predetermined size, and the circuit wiring on which the semiconductor chip is mounted A substrate can be obtained.
[0012]
When manufacturing a semiconductor device using the circuit wiring board of the present invention, the semiconductor chip 3 is thermocompression bonded to the adhesive layer. The conditions for thermocompression bonding are not generally determined depending on the adhesive used, but in general, the temperature is 200 to 400 ° C., the pressure is 0.01 to 20 kg / cm 2 , and the time is 1 to 120 seconds. It is.
After the chip is bonded, the chip and the substrate are electrically connected by wire bonding 4, and the sealing resin 5 is sealed by transfer molding or potting to obtain a BGA semiconductor device.
[0013]
【Example】
Hereinafter, more specific embodiments of the present invention will be described as examples with reference to the drawings.
Example 1
As an insulating substrate, BT-HL830 manufactured by Mitsubishi Gas Chemical Co., Ltd. and a glass BT resin copper-clad laminate having a thickness of 0.5 mmt were used to produce substrates as shown in FIGS. The hole was machined with a 0.2 mm diameter drill and plated with copper to form a through hole 10. The land diameter is 0.4 mmφ. The external dimensions are 20 mm square, and the copper foil 12 is left as it is in the portion where the chip is mounted, and the size is 9 mm square. Except for the part where the chip is mounted, PSR4000 and 11 of Taiyo Ink Co. were coated as a solder resist film. Next, a paste stick 181 made by Techno Alpha, which is a thermoplastic resin adhesive, was applied 9 by screen printing 9 to about 40 μm (FIG. 5), and then dried at 150 ° C. for 30 minutes, and a semiconductor with adhesive A mounting substrate was obtained. An 8 mm square and 0.4 mm thick semiconductor chip 3 was thermocompression bonded under the conditions of 5 kg / cm 2 and a temperature of 200 ° C. (FIG. 6). The through hole 10 under the chip was not blocked by the adhesive. Thereafter, CEC1400 manufactured by Hitachi Chemical Co., Ltd., which is a liquid sealing material, was potted and cured to obtain a semiconductor device. Ten semiconductor devices were absorbed in a constant temperature and humidity chamber at 85 ° C. and 85% RH for 48 hours, and then subjected to a solder heat resistance test immersed in a solder bath at 240 ° C. for 30 seconds. When the peeling or crack in the semiconductor device was observed, no peeling or crack was observed.
[0014]
Example 2
Regulus-UAT made by Mitsui Toatsu Chemical Co., Ltd., which is a polyimide type film, is applied as a thermoplastic adhesive layer to the substrate shown in Example 1 at a temperature of 280 ° C., a pressure of 5 kg / cm 2 , and a time of 20 seconds. After bonding the semiconductor chip under the conditions of a temperature of 300 ° C., a pressure of 10 kg / cm 2 , and a time of 10 seconds, the same assembly and test as in Example 1 were conducted. As a result, peeling or cracks were observed in the semiconductor device. I couldn't.
[0015]
Comparative Example 1
The same substrate as in Example 1 was used, and the chip was bonded by Ablesbond 84L-1LM manufactured by Able Stick Co., Ltd., which is an epoxy resin containing silver, as an adhesive. FIG. 7 shows a cross-section after bonding. The through-hole 10 ′ under the chip was filled with an adhesive and blocked. When the same evaluation as in Example 1 was performed, cracks occurred in all 10 semiconductor devices.
[0016]
【The invention's effect】
As described in the examples and comparative examples, the substrate for mounting a semiconductor chip according to the present invention has a structure that allows water vapor generated during solder reflow to easily escape to the outside by providing an adhesive layer made of a thermoplastic resin in advance. It is effective as a BGA semiconductor device that can be obtained and hardly causes the popcorn phenomenon.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a BGA semiconductor device of the present invention. FIG. 2 is a cross-sectional view after circuit wiring of a semiconductor mounting substrate of the present invention. FIG. 4 is a cross-sectional view after applying a solder resist film. FIG. 4 is a plan view of the semiconductor mounting substrate of the present invention (FIG. 2) as viewed from the chip mounting side. FIG. 6 is a cross-sectional view after mounting a semiconductor chip on the semiconductor mounting substrate of the present invention. FIG. 7 is an adhesive made of a thermosetting resin on the semiconductor mounting substrate. Sectional view after mounting a semiconductor chip using
DESCRIPTION OF SYMBOLS 1 Board | substrate 2 The surface which mounts the semiconductor chip of a board | substrate 3 Semiconductor chip 4 Gold wire 5 Sealing resin 6 The surface which provides the solder bump of a board | substrate 7 The electrode 8 on a board | substrate Solder bump 9 Adhesive layer
10 Through hole
11 Solder resist film
12 Copper foil for mounting semiconductor chips

Claims (3)

半導体チップが搭載される回路配線を有する基板において、半導体チップが搭載される部分に銅メッキが施されたスルーホールを有し、このスルーホールのチップ搭載側の逆側が開口しており、さらに半導体チップが搭載される部分に、熱可塑性樹脂からなる接着剤層がスルーホールを塞がないように設けられていることを特徴とする半導体搭載用基板。A substrate having circuit wiring on which a semiconductor chip is mounted has a through hole plated with copper in a portion on which the semiconductor chip is mounted, and the opposite side of the through hole on the chip mounting side is opened, and further, the semiconductor A semiconductor mounting substrate, wherein an adhesive layer made of a thermoplastic resin is provided on a portion where a chip is mounted so as not to block a through hole . 請求項１に記載の接着剤層が、熱可塑性樹脂の他に金属または無機フィラーを含むことを特徴とする半導体搭載用基板。The substrate for mounting a semiconductor, wherein the adhesive layer according to claim 1 contains a metal or an inorganic filler in addition to the thermoplastic resin. 請求項１または２に記載の半導体搭載用基板を用いることを特徴とする半導体装置。A semiconductor device comprising the semiconductor mounting substrate according to claim 1.
JP17857097A 1997-07-03 1997-07-03 Semiconductor mounting substrate Expired - Lifetime JP3827407B2 (en)

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Application Number Priority Date Filing Date Title
JP17857097A JP3827407B2 (en) 1997-07-03 1997-07-03 Semiconductor mounting substrate

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JP3827407B2 true JP3827407B2 (en) 2006-09-27

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JP3485509B2 (en) * 1999-10-28 2004-01-13 シャープ株式会社 Flip chip type semiconductor device and manufacturing method thereof
JP4659802B2 (en) * 2007-09-25 2011-03-30 シャープ株式会社 Insulating wiring board, semiconductor package using the same, and manufacturing method of insulating wiring board
JP5230580B2 (en) * 2009-11-09 2013-07-10 パナソニック株式会社 Semiconductor device and mounting method thereof

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