JP3812209B2 - Active matrix substrate, electro-optical device, and manufacturing method of active matrix substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix substrate on which transistors are formed, an electro-optical device using the active matrix substrate, and a method for manufacturing the active matrix substrate. More specifically, the present invention relates to a technique for forming a film quality inspection region for performing a film quality inspection of a film constituting a transistor.
[0002]
[Prior art]
A typical active matrix substrate in which transistors and signal wirings are formed on a substrate is an active matrix substrate used for a liquid crystal display device (electro-optical device). Among the active matrix substrates, those with a built-in drive circuit have a plurality of pixels arranged in a matrix corresponding to the intersections of the plurality of scanning lines and the plurality of data lines arranged on the insulating substrate. Each pixel is formed with a pixel switching thin film transistor (hereinafter referred to as TFT) connected to the scanning line and the data line, and a pixel electrode. A data line driving circuit for supplying an image signal to each of a plurality of data lines and a scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines are configured in an outer region of the pixel portion on the insulating substrate. ing. These drive circuits are formed by a plurality of TFTs.
[0003]
Among these TFTs, for example, a pixel switching TFT 50 includes a gate electrode 3a formed simultaneously with the scanning line and a source as a part of the data line 30, as shown in FIGS. A source region 1f, 1d in which the electrode 6a is electrically connected through the first contact hole 4a of the first interlayer insulating film 4, and a drain electrode 6d composed of an aluminum film or the like formed simultaneously with the data line 30 Have drain regions 1g and 1e electrically connected through the second contact hole 4d of the first interlayer insulating film 4. A second interlayer insulating film 7 is formed on the upper side of the first interlayer insulating film 4, and the pixel electrode is connected via the third contact hole 8 a formed in the second interlayer insulating film 7. 9a is electrically connected to the drain electrode 6d. Such a structure is basically the same for the TFT formed in the drive circuit.
[0004]
Here, the active matrix substrate is subjected to various inspections after the TFT 50 and the like are formed using a semiconductor process. Various analyzes are performed on those determined to be defective in this inspection, and the results are fed back. For example, the impurity concentration of the source / drain regions, the crystallinity of the channel region 1a, and the like are analyzed. In performing such an analysis, conventionally, the pixel switching TFT 50 or the driving circuit TFT is rastered from the surface side, and the second interlayer insulating film 7, the first interlayer insulating film 4, the gate electrode 3a, The gate insulating film 2 is removed in this order to expose the channel region 1a or the source / drain region, and then elemental analysis by SIMS (secondary ion mass spectrometry) and analysis by X-ray are performed.
[0005]
[Problems to be solved by the invention]
However, when the source / drain region and the channel region 1a are analyzed, the second interlayer insulating film 7, the first interlayer insulating film 4, the gate electrode 3a, and the gate insulating film 2 are removed as in the prior art. However, there is a problem that it takes a considerable time for the removal. That is, although the film thickness of the portion to be inspected is, for example, about 500 angstroms to 1000 angstroms, it is 4000 angstroms after removing the 1 μm interlayer insulating film until the film quality inspection is performed. It is necessary to remove the gate electrode 3a. Further, even when rastering is performed over such a time, the channel region 1a of the TFT 50 is as small as about 100 μm square at most, so that there is a problem that high-precision investigation cannot be performed.
[0006]
In view of the above problems, an object of the present invention is to provide an active matrix substrate capable of easily and accurately inspecting the film quality of a transistor such as a TFT, and an electro-optical device using the active matrix substrate. is there.
[0007]
Another object of the present invention is to form a film quality inspection region having a history similar to that of a channel region and a gate insulating film of a transistor without increasing the number of steps, thereby enabling more accurate film quality inspection to be efficiently performed. An object of the present invention is to provide a method for manufacturing an active matrix substrate.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, an active matrix substrate of the present invention is an active matrix substrate in which transistors and signal wirings are formed on a substrate, and at least a region of the substrate on which the transistors and signal wirings are not formed. In one place, a semiconductor film for film quality inspection of the same layer as the semiconductor film used in the transistor is provided, and the inspection area side interlayer insulation of the same layer as the interlayer insulating film formed in the upper layer of the semiconductor film for film quality inspection The film quality inspection region is characterized in that the film quality inspection semiconductor film is exposed through an opening provided in the film.
[0009]
In the present invention, since a film quality inspection region including a semiconductor film for film quality inspection of the same layer as the semiconductor film used in the transistor is formed, if this film quality inspection region is analyzed, the source / drain region and channel region of the transistor are Film quality inspections such as elemental analysis and crystallinity analysis on the semiconductor film can be performed. Here, since the film quality inspection region is exposed from the opening of the inspection region side interlayer insulating film in the same layer as the interlayer insulating film, the inspection can be started immediately, unlike the case of inspecting on the transistor side, There is no need to remove the interlayer insulating film and the gate electrode. Therefore, the film quality inspection can be performed quickly and easily. Further, even if it is formed large in the film quality inspection region, it does not affect the transistor characteristics of the transistor. Therefore, various analyzes can be performed with high accuracy by forming a large film quality inspection region.
[0010]
In the present invention, the semiconductor film for film quality inspection is, for example, in the same layer as the source / drain region of the transistor, and the same impurity as the source / drain region is introduced at the same concentration.
[0011]
In order to manufacture an active matrix substrate having such a configuration, for example, a semiconductor film used for the transistor and a gate insulating film are formed in this order, and at the same time the film quality inspection semiconductor film and After forming the inspection region side gate insulating film in this order, the following steps are performed. That is, after forming a conductive film for forming the gate electrode of the transistor, patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side, and the gate insulation A step of selectively introducing impurities into the semiconductor film through the film to form source / drain regions of the transistor and simultaneously introducing impurities into the film quality inspection semiconductor film through the inspection region side gate insulating film; Forming the interlayer insulating film on the surface side of the gate electrode and simultaneously forming the inspection region side interlayer insulating film on the surface side of the inspection region side gate insulating film on the inspection region side; and the interlayer insulation A contact hole for the MIS transistor is formed in the film, and at the same time, in the film quality inspection region, the inspection region side interlayer insulating film and the Forming the opening in 査領 frequency side gate insulating film performing the step of exposing the film quality inspection for a semiconductor film.
[0012]
According to such a manufacturing method, since the semiconductor film for film quality inspection follows a history substantially the same as the source / drain region of the transistor, even when the semiconductor film for film quality inspection is an inspection object, higher accuracy is achieved. Thus, the film quality of the source / drain regions of the transistor can be inspected. In addition, since the film quality inspection region can be formed by using the process for manufacturing the transistor as it is, the number of processes does not increase.
[0013]
In the present invention, the source / drain region of the transistor may have a low concentration source / drain region and a high concentration source / drain region. In this case, the semiconductor film for film quality inspection is the same layer as the source / drain region of one of the low concentration source / drain region and the high concentration source / drain region, and is the same as the source / drain region. These regions may be formed as regions where the same impurity is introduced at the same concentration.
[0014]
In manufacturing an active matrix substrate having such a configuration, for example, a semiconductor film used for the transistor and a gate insulating film are formed in this order, and at the same time, the film quality inspection semiconductor film and the region to be the film quality inspection region are formed. After forming the inspection region side gate insulating film in this order, the following steps are performed. That is, after forming a conductive film for forming the gate electrode of the transistor, patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side, and the gate insulation A high-concentration impurity and a low-concentration impurity are selectively introduced into the semiconductor film through the film to form the low-concentration source / drain region and the high-concentration source / drain region of the transistor, and at the same time the inspection region side A step of introducing one of the low-concentration impurity and the high-concentration impurity into the film quality inspection semiconductor film through the gate insulating film; and simultaneously with forming the interlayer insulating film on the surface side of the gate electrode Forming the inspection region side interlayer insulating film on the inspection region side gate insulating film on the surface side of the inspection region side; and Forming a contact hole for the transistor in the film and simultaneously forming the opening in the inspection region side interlayer insulating film and the inspection region side gate insulating film in the film quality inspection region to expose the semiconductor film for film quality inspection; I do.
[0015]
In the present invention, when the source / drain region of the transistor has a low-concentration source / drain region and a high-concentration source / drain region, the semiconductor film for film quality inspection is the low-concentration source / drain region. And the same layer as the low concentration source / drain region, the same impurity as the low concentration source / drain region is introduced at the same concentration, the same layer as the high concentration source / drain region, and It is preferable to include a second film quality inspection semiconductor film into which the same impurity as the high concentration source / drain region is introduced at the same concentration. With this configuration, even when the source / drain region of the transistor has a low concentration source / drain region and a high concentration source / drain region, each region can be inspected.
[0016]
In manufacturing an active matrix substrate having such a configuration, for example, a semiconductor film used for the transistor and a gate insulating film are formed in this order, and at the same time, the film quality inspection semiconductor film and the region to be the film quality inspection region are formed. After forming the inspection region side gate insulating film in this order, the following steps are performed. That is, after forming a conductive film for forming the gate electrode of the transistor, patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side, and the gate insulation A high-concentration impurity and a low-concentration impurity are selectively introduced into the semiconductor film through the film to form the low-concentration source / drain region and the high-concentration source / drain region of the transistor, and at the same time the inspection region side The first film quality inspection semiconductor film and the second film quality inspection semiconductor are formed by selectively introducing the low concentration impurity and the high concentration impurity into the film quality inspection semiconductor film through a gate insulating film. Forming a film; forming the interlayer insulating film on the surface side of the gate electrode; Forming the inspection region side interlayer insulating film on the surface side of the film; and simultaneously forming the contact hole for the transistor in the interlayer insulating film in the film quality inspection region, the inspection region side interlayer insulating film and the inspection region side gate Forming the opening in the insulating film and exposing the semiconductor film for film quality inspection.
[0017]
According to such a manufacturing method, the first film quality inspection semiconductor film and the second film quality inspection semiconductor film have substantially the same history as the low concentration source / drain region and the high concentration source / drain region of the transistor, respectively. Therefore, even when the semiconductor film for film quality inspection is an inspection object, the film quality of the source / drain region of the transistor can be inspected with higher accuracy. In addition, since the film quality inspection region can be formed by directly using the process for manufacturing the transistor, the number of processes does not increase.
[0018]
In the present invention, when the semiconductor film for film quality inspection is used for inspection of the source / drain region of the transistor, the film quality inspection area is preferably formed in an area larger than the source / drain region of the transistor.
[0019]
In the present invention, the semiconductor film for film quality inspection may be formed for inspection of the channel region of the transistor. That is, the semiconductor film for film quality inspection is formed as the same layer as the channel region of the transistor and as a low concentration region in which the same intrinsic semiconductor film as the channel region or the same impurity is channel-doped at the same concentration. May be.
[0020]
In this case, it is preferable to form the film quality inspection region with an area larger than the channel region of the transistor.
[0021]
In manufacturing an active matrix substrate having such a configuration, for example, a semiconductor film used for the transistor and a gate insulating film are formed in this order, and at the same time, the film quality inspection semiconductor film and the region to be the film quality inspection region are formed. After forming the inspection region side gate insulating film in this order, the following steps are performed. That is, after forming a conductive film for forming the gate electrode of the transistor, patterning the conductive film to form the gate electrode and simultaneously removing the conductive film from the film quality inspection region side, and the film quality inspection Forming a source / drain region of the transistor by selectively introducing impurities into the semiconductor film through the gate insulating film with the semiconductor film covered with a mask; and the transistor in the interlayer insulating film At the same time as forming a contact hole for the film quality inspection region, the step of forming the opening in the inspection region side interlayer insulating film and the inspection region side gate insulating film to expose the film quality inspection semiconductor film is performed.
[0022]
According to such a manufacturing method, since the semiconductor film for film quality inspection follows a history substantially the same as the channel region of the transistor, even when the semiconductor film for film quality inspection is an inspection object, with higher accuracy, The film quality of the channel region of the transistor can be inspected. In addition, since the film quality inspection region can be formed by directly using the process for manufacturing the transistor, the number of processes does not increase.
[0023]
In any of the above forms, the film quality inspection region is, for example, 1 mm. ² It is preferable to have the above area. In this way, the film quality inspection region is considerably larger than the channel region of the transistor, for example, about 1 mm. ² When formed to have the above area, elemental inspection by SIMS can be performed with high accuracy, and the crystallinity of the semiconductor film for film quality inspection (channel region) is also inspected using Raman scattering analysis and the like. it can. Therefore, when a transistor such as a thin film transistor is formed from a polycrystalline semiconductor film obtained by performing a crystallization process on an amorphous semiconductor film, an effective inspection can be performed.
[0024]
In the present invention, if the transistor is a thin film transistor, a pixel switching thin film transistor connected to a scanning line and a data line and a pixel electrode connected to the thin film transistor are formed in a matrix on the substrate. An electro-optical device such as a liquid crystal display device by forming a scanning line driving circuit and a data line driving circuit for outputting signals to the scanning lines and the data lines, and a plurality of signal wirings for supplying signals to the driving circuits. Active matrix substrates can be formed. That is, an electro-optical device such as a liquid crystal display device can be configured by sandwiching an electro-optical material such as liquid crystal between the active matrix substrate (active matrix substrate) and the counter substrate on which the counter electrode is formed. it can. In such a case, the film quality inspection region is formed in at least one of the regions on the substrate where the pixel portion, the scanning line driving circuit, the data line driving circuit, and the signal wiring are not formed. Will be.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0026]
[Embodiment 1]
(Overall configuration of electro-optical device)
FIG. 1 is a plan view of the electro-optical device according to the present embodiment as viewed from the counter substrate side. FIG. 2 is a cross-sectional view of the electro-optical device when cut along the line HH ′ in FIG. 1.
[0027]
As shown in FIGS. 1 and 2, an electro-optical device 300 used for a projection display device or the like is an active matrix substrate in which pixel electrodes 9a are formed in a matrix on the surface of an insulating substrate 10 such as quartz glass or heat-resistant glass. 200 (active matrix substrate), a counter substrate 100 having a counter electrode 32 formed on the surface of an insulating substrate 41 such as quartz glass or heat-resistant glass, and a liquid crystal sealed and sandwiched as an electro-optical material between these substrates 39. The active matrix substrate 200 and the counter substrate 100 are bonded to each other with a predetermined gap (cell gap) by a gap material-containing sealing material 59 formed along the outer periphery of the counter substrate 100. In addition, a liquid crystal sealing region 40 is defined between the active matrix substrate 200 and the counter substrate 100 by a gap material-containing sealing material 59, and the liquid crystal 39 is sealed in the liquid crystal sealing region 40.
[0028]
The counter substrate 100 is smaller than the active matrix substrate 200, and the peripheral portion of the active matrix substrate 200 is bonded so as to protrude from the outer peripheral edge of the counter substrate 100. Therefore, the driving circuit (scanning line driving circuit 70 and data line driving circuit 60) and the input / output terminal 45 of the active matrix substrate 200 are exposed from the counter substrate 100. Here, since the sealing material 59 is partially interrupted, the liquid crystal injection port 241 is configured by the interrupted portion. Therefore, after the counter substrate 100 and the active matrix substrate 200 are bonded together, the liquid crystal 39 can be injected under reduced pressure from the liquid crystal injection port 241 if the inner region of the sealant 59 is in a reduced pressure state. The liquid crystal injection port 241 may be blocked with a sealant 242. In the active matrix substrate 200, a light shielding film 55 for cutting off the image display region 11 is formed inside the region where the sealing material 59 is formed. Further, a light shielding film 57 is formed on the counter substrate 100 in a region corresponding to the boundary region of each pixel electrode 9 a of the active matrix substrate 200.
[0029]
Note that a polarizing plate (not shown) or the like is placed in a predetermined direction on the light incident side surface or the light emission side of the counter substrate 100 and the active matrix substrate 200 according to the normally white mode / normally black mode. Be placed.
[0030]
In the electro-optical device 300 configured as described above, in the active matrix substrate 200, a pixel is generated by an image signal applied to the pixel electrode 9a via a data line (not shown) and a pixel switching TFT (described later). The alignment state of the liquid crystal 39 is controlled for each pixel between the electrode 9a and the counter electrode 32, and a predetermined image corresponding to the image signal is displayed. Therefore, in the active matrix substrate 200, it is necessary to supply an image signal to the pixel electrode 9a via the data line and the TFT 50 and to apply a predetermined potential to the counter electrode 32 as well. Therefore, in the electro-optical device 300, a portion of the surface of the active matrix substrate 200 facing each corner portion of the counter substrate 100 is used for vertical conduction made of an aluminum film or the like with the aid of a data line forming process. A first electrode 47 is formed. On the other hand, in each corner portion of the counter substrate 100, a second electrode 48 for vertical conduction made of an ITO (Indium Tin Oxide) film or the like is formed using the process of forming the counter electrode 4. Further, the first electrode 47 and the second electrode 48 for vertical conduction are electrically connected by a conductive material 56 in which conductive particles such as silver powder or gold-plated fiber are mixed with an epoxy resin adhesive component. is doing. Therefore, in the electro-optical device 300, the active matrix substrate can be obtained by connecting the flexible wiring substrate 99 only to the active matrix substrate 200 without connecting the flexible wiring substrate or the like to each of the active matrix substrate 200 and the counter substrate 100. A predetermined signal can be input to both 200 and the counter substrate 100.
[0031]
(Overall configuration of active matrix substrate)
FIG. 3 is a block diagram schematically showing the configuration of the active matrix substrate used in the electro-optical device 300.
[0032]
As shown in FIG. 3, in the active matrix substrate 200 with a built-in driving circuit according to this embodiment, pixel electrodes 9a connected to a plurality of scanning lines 20 and a plurality of data lines 30 intersecting each other are formed on a matrix. Configured. The scanning line 20 is composed of a tantalum film, an aluminum film, an aluminum alloy film, and the like, and the data line 30 is composed of an aluminum film, an aluminum alloy film, or the like, and each is a single layer or a stacked layer. An area where these pixel electrodes 9 a are formed is an image display area 11.
[0033]
A data line driving circuit 60 that supplies an image signal to each of the plurality of data lines 30 is configured in an outer region (peripheral portion) of the image display region 11 on the insulating substrate 10. Further, a scanning line driving circuit 70 that supplies a scanning signal for pixel selection to each scanning line 20 is configured at each of both ends of the scanning line 20. These driving circuits are configured using driving circuit TFTs formed simultaneously with pixel switching TFTs.
[0034]
The data line driving circuit 60 includes an X-side shift register circuit, a sample hold circuit 66 having a TFT as an analog switch that operates based on a signal output from the X-side shift register circuit, and each image signal developed in six phases. Six image signal lines 67 corresponding to are configured. In this example, in the data line driving circuit 60, the X-side shift register circuit is configured in four phases, and a start signal, a clock signal, and its inverted clock signal are externally input via the input / output terminal 45 on the X side. The data line driving circuit 60 is driven by these signals supplied to the shift register circuit. Accordingly, in the sample and hold circuit 66, each TFT operates based on the signal output from the X-side shift register circuit, and the image signal supplied via the image signal line 67 is transferred to the data line 30 at a predetermined timing. It is possible to capture and supply to each pixel electrode 9a.
[0035]
On the other hand, the scanning line driving circuit 70 is supplied with a start signal, a clock signal, and its inverted clock signal from the outside through terminals, and the scanning line driving circuit 70 is driven by these signals.
[0036]
In the active matrix substrate 200 of the present embodiment, a constant power source, a modulated image signal (image signal), various drive signals, etc. are input to the side portion of the insulating substrate 10 on the data line drive circuit 60 side. A large number of input / output terminals 45 made of a conductive film such as a metal film such as a film, a metal silicide film, or an ITO film are formed. From these input / output terminals 45, a scanning line driving circuit 60 and a data line driving circuit 70 are provided. A plurality of signal wirings 73 and 74 made of a low-resistance metal film such as an aluminum film for driving are respectively routed.
[0037]
(Pixel and TFT structure)
FIG. 4 is an equivalent circuit diagram of a pixel of the active matrix substrate shown in FIG. FIGS. 5A and 5B are pixel switching TFTs formed in the pixel of FIG. 3, respectively, and a cross-sectional view taken along the line CC ′ of a film quality inspection region described later with reference to FIG. It is sectional drawing which expands and shows some of them.
[0038]
As shown in FIG. 4, a pixel switching TFT 50 connected to the scanning line 20 and the data line 30 is formed on the pixel electrode 9a. In addition, a capacitor line 75 may be formed toward each pixel electrode 9a, and an applied capacitor (holding capacitor) may be formed in each pixel electrode 9a using the capacitor line 75.
[0039]
As shown in FIGS. 5A and 5B, the TFT 50 includes a gate electrode 3 a formed simultaneously with the scanning line 20 and a source electrode 6 a as a part of the data line 30 formed of the first interlayer insulating film 4. A high-concentration source region 1d that is electrically connected via the first contact hole 4a and a drain electrode 6d composed of an aluminum film or the like formed simultaneously with the data line 30 are formed in the second interlayer insulating film 4. High-concentration drain region 1e electrically connected through the contact hole 4d. Further, a second interlayer insulating film 7 is formed on the upper layer side of the first interlayer insulating film 4, and through the third contact hole 8a formed in the second interlayer insulating film 7, The pixel electrode 9a is electrically connected to the drain electrode 6d. In this embodiment, the TFT 50 has an LDD structure, and has a low-concentration source region 1f and a low-concentration drain region 1g in a portion facing the end of the gate electrode 3a.
[0040]
In this embodiment, the second interlayer insulating film 7 includes an insulating film 71 obtained by baking a coating film of perhydropolysilazane or a composition containing the same, and a thickness of about 500 angstroms to about 15000 angstroms formed by a CVD method or the like. It has a two-layer structure with an insulating film 72 made of a silicon oxide film. Here, perhydropolysilazane is a kind of inorganic polysilazane, and is a coating type coating material that is converted into a silicon oxide film by baking in the atmosphere. For example, polysilazane manufactured by Tonen Corporation is-(SiH ₂ It is an inorganic polymer having NH)-as a unit, and is soluble in an organic solvent such as xylene. Therefore, after applying an organic solvent solution of this inorganic polymer (for example, 20% xylene solution) as a coating solution by spin coating (for example, 2000 lrpm, 20 seconds), and baking in the air at a temperature of 450 ° C., moisture and A dense amorphous silicon oxide film equivalent to or better than a silicon oxide film formed by a CVD method by reacting with oxygen can be obtained. Therefore, the insulating film 71 (silicon oxide film) formed by this method can be used as an interlayer insulating film, and can flatten unevenness caused by the drain electrode 6d. Therefore, it is possible to prevent the alignment state of the liquid crystal from being disturbed due to the unevenness.
[0041]
(Film quality inspection area)
The active matrix substrate 200 thus formed is subjected to electrical inspection after forming each component using a semiconductor process. Moreover, about what was determined to be a defect in this inspection process, various analyzes are performed, and the results are fed back. For example, the impurity distribution in the source / drain region of the TFT 50 is inspected, and the result is fed back.
[0042]
In order to perform such inspection, as shown in FIGS. 1 and 3, the active matrix substrate 200 of this embodiment includes a pixel portion 11, a scanning line driving circuit 70, a data line driving circuit 60, and signal wirings 73 and 74. A rectangular film quality inspection region 80 having a side of about 1 mm is formed in a corner portion where the above is not formed (lower right portion in FIGS. 1 and 3).
[0043]
As shown in FIGS. 6A and 6B, the film quality inspection region 80 is in the same layer as the channel region 1a of the TFT 50 and the semiconductor film 1h constituting the source / drain region, and has a high concentration source / drain. A film quality inspection semiconductor film 1c (silicon film) is formed in which the same impurities as the regions (high concentration source region 1d and high concentration drain region 1e) are introduced at the same concentration. Further, in the film quality inspection region 80, the film quality inspection semiconductor film 1c is an opening penetrating the inspection region side gate insulating film 2c in the same layer as the gate insulating film 2 and the interlayer insulating films 4, 71, 72 on the inspection region side. It is exposed from the part 8c. Here, the semiconductor film 1c for film quality inspection is formed to have a considerably larger area than the source / drain regions (the high concentration source region 1d and the high concentration drain region 1e) of the TFT 50. Further, the semiconductor film 1c for film quality inspection is formed in a region including the region where the opening 8c is formed, and is slightly larger than the opening area of the opening 8c.
[0044]
As described above, the active matrix substrate 200 of this embodiment includes the film quality inspection semiconductor film 1c in the same layer as the high-concentration source region 1d and the high-concentration drain region 1e of the TFT 50 and having the same impurity introduced at the same concentration. Since the film quality inspection region 80 is formed, if elemental analysis is performed on the film quality inspection semiconductor film 1c in the film quality inspection region 80, the impurity concentration distribution of the high concentration source region 1d and the high concentration drain region 1e of the TFT 50, etc. Film quality inspection can be performed. Moreover, since the film quality inspection region 80 is exposed from the opening 8c penetrating the inspection region side gate insulating film 2c and the interlayer insulating films 4, 71, 72, the inspection can be started immediately, and the inspection is performed on the TFT 50 side. Unlike the case, the interlayer insulating films 4, 71, 72, the gate electrode 3a, and the gate insulating film 2 do not need to be removed. Therefore, the film quality inspection can be performed quickly and easily. Further, even if the film quality inspection region 80 is formed large, the transistor characteristics of the TFT 50 are not affected. Therefore, by forming a large film quality inspection region 80, elemental analysis in the depth direction can be performed with high accuracy while rastering a part (not shown) of the film quality inspection region 80 in the analysis by SIMS. Can do. Moreover, the film quality inspection region 80 has a considerably larger area than the high concentration source region 1d and the high concentration drain region of the TFT 50, for example, about 1 mm. ² In addition to the elemental analysis by SIMS, the crystallinity of the film quality inspection semiconductor film 1c (semiconductor film 1h) can be inspected by using crystal analysis by X-ray, Raman scattering analysis, or the like. Therefore, it is effective to inspect the TFT 50 formed from the polycrystalline semiconductor film 1h obtained by performing the crystallization process on the amorphous semiconductor film.
[0045]
Furthermore, in this embodiment, the film quality inspection region 80 is formed at a position protruding from the counter substrate 100 in the active matrix substrate 200, as can be seen from FIG. Therefore, not only in the stage of the active matrix substrate 200 but also after the electro-optical device 300 is assembled by bonding the active matrix substrate 200 and the counter substrate 100 and the lighting inspection or the like is performed, the film quality in the film quality inspection region 80. An inspection can also be performed.
[0046]
(Method for manufacturing active matrix substrate 200)
A method of manufacturing the active matrix substrate 200 while forming such a film quality inspection region 80 will be described with reference to FIGS. Each of these figures is a process sectional view showing a method of manufacturing the active matrix substrate 200 of the present embodiment. In each figure, the left side portion shows a cross section of the pixel TFT portion, and the right side portion shows C in FIG. A cross section taken along the line -C '(cross section of the film quality inspection region 80) is shown.
[0047]
First, as shown in FIG. 6A, a base protective film (not shown) formed directly on the surface of a transparent insulating substrate 10 made of a glass substrate, for example, non-crisp glass or quartz, or on the surface of the insulating substrate 10. 6), a semiconductor film 1 made of a polysilicon film having a thickness of about 200 angstroms to about 2000 angstroms, preferably about 1000 angstroms, is formed on the entire surface by a low pressure CVD method or the like, as shown in FIG. Then, it is patterned by using a photolithography technique to form an island-shaped semiconductor film 1h (active layer) in the pixel TFT portion. Further, an island-shaped film quality inspection semiconductor film 1 c is formed in the film quality inspection region 80.
[0048]
The semiconductor film 1 is formed by depositing an amorphous silicon film by a low temperature process and then crystallizing it by a method such as laser annealing to obtain a polysilicon film.
[0049]
Next, as shown in FIG. 6C, a silicon oxide film having a thickness of about 500 angstroms to about 1500 angstroms is formed on the entire surface of the insulating substrate 10 by a CVD method or the like under a temperature condition of about 400 ° C., for example. As a result, the gate insulating film 2 is formed on the surface of the island-shaped semiconductor film 1h in the pixel TFT portion, and the inspection region-side gate insulating film 2c is formed on the surface of the island-shaped film quality inspection semiconductor film 1c in the film quality inspection region 80. Is done.
[0050]
Next, as shown in FIG. 6D, after a tantalum film 3 (conductive film) for forming a gate electrode or the like is formed on the entire surface of the insulating substrate 10, the tantalum film 3 is patterned using a photolithography technique. As shown in FIG. 6E, the gate electrode 3a is formed on the pixel TFT portion side. Further, the tantalum film 3 is completely removed from the film quality inspection region 80.
[0051]
Next, as shown in FIG. 6F, on the side of the pixel TFT portion and the N-channel TFT portion of the driver circuit, about 0.1 × 10 6 using the gate electrode 3a as a mask. ¹³ / Cm ² ~ About 10 × 10 ¹³ / Cm ² The low concentration source region 1f and the low concentration drain region 1g are formed in a self-aligned manner with respect to the gate electrode 3a on the side of the pixel TFT portion. . Here, since it is located directly under the gate electrode 3a, the portion where the impurity ions are not introduced becomes the channel region 1a. At this time, in the film quality inspection region 80, a low concentration impurity is introduced as in the low concentration source region 1f and the low concentration drain region 1g.
[0052]
Next, as shown in FIG. 7A, in the pixel TFT portion, a resist mask RM1 wider than the gate electrode 3a is formed, and high-concentration impurity ions (phosphorus ions) are about 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² Then, a high concentration source region 1d and a high concentration drain region 1e are formed. Also at this time, high-concentration impurities are introduced into the film quality inspection region 80 as in the high-concentration source region 1d and the high-concentration drain region 1e.
[0053]
Instead of these impurity introduction steps, a high concentration impurity (phosphorus ion) is implanted in a state where a resist mask RM1 wider than the gate electrode 3a is formed without implanting a low concentration impurity, and a source region having an offset structure and A drain region may be formed. Needless to say, a high concentration impurity (phosphorus ion) may be implanted on the gate electrode 3a to form a source region and a drain region having a self-aligned structure.
[0054]
Although not shown, in order to form the P-channel TFT portion of the peripheral drive circuit, the pixel portion, the film quality inspection region 80 and the N-channel TFT portion are covered and protected with a resist, and the gate electrode is used as a mask. 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² By implanting boron ions at a dose of P, source / drain regions of the P channel are formed in a self-aligned manner. As in the formation of the N-channel TFT portion, the gate electrode is used as a mask and about 0.1 × 10 ¹³ / Cm ² ~ About 10 × 10 ¹³ / Cm ² After introducing a low concentration impurity (boron ion) at a dose of a low concentration region in the polysilicon film, a mask wider than the gate electrode is formed to form a high concentration impurity (boron ion). About 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² The source region and drain region of the LDD structure (lightly doped drain structure) may be formed by implanting with a dose amount of Alternatively, a source region and a drain region having an offset structure may be formed by implanting high concentration impurities (phosphorus ions) in a state where a mask wider than the gate electrode is formed without implanting low concentration impurities. By these ion implantation processes, CMOS can be realized, and the peripheral drive circuit can be built in the same substrate.
[0055]
Next, as shown in FIG. 7B, a silicon oxide film or an NSG film (boron) is formed on the surface side of the gate electrode 3a and the inspection region side gate insulating film 2c by a CVD method or the like under a temperature condition of about 400 ° C., for example. The first interlayer insulating film 4 made of silicate glass film not containing phosphorus or the like is formed with a film thickness of about 3000 angstroms to 15000 angstroms.
[0056]
Next, a resist mask RM2 for forming contact holes and openings is formed in the first interlayer insulating film 4 by using a photolithography technique.
[0057]
Next, as shown in FIG. 7C, the portion corresponding to the source region 1d and the drain region 1e in the first interlayer insulating film 4 on the pixel TFT portion side, and the first on the film quality inspection region 80 side. In the interlayer insulating film 4, contact holes 4a and 4d and an opening 4c are respectively formed in a part corresponding to the film quality inspection semiconductor film 1c. As a result, in the film quality inspection region 80, the film quality inspection semiconductor film 1c is exposed. Then, the resist mask RM2 is removed.
[0058]
Next, as shown in FIG. 7D, an aluminum film 6 for forming a source electrode or the like is formed on the surface side of the first interlayer insulating film 4 by sputtering or the like.
[0059]
Next, a resist mask RM3 for patterning the aluminum film 6 is formed using a photolithography technique.
[0060]
Next, as shown in FIG. 7E, the aluminum film 6 is patterned, and in the pixel TFT portion, as a part of the data line 30, it is electrically connected to the high concentration source region 1d through the first contact hole 4a. A source electrode 6a made of an aluminum film to be connected and a drain electrode 6d electrically connected to the high concentration drain region 1e through the second contact hole 4d are formed. On the other hand, in the film quality inspection region 80, the aluminum film 6 is completely removed, and the film quality inspection semiconductor film 1c is exposed. Then, the resist mask RM3 is removed.
[0061]
Next, as shown in FIG. 8A, an insulating film 71 obtained by baking a coating film of perhydropolysilazane or a composition containing the same on the surface side of the source electrode 6a, the drain electrode 6d, and the semiconductor film 1c for film quality inspection. Form. Further, an insulating film 72 made of a silicon oxide film having a thickness of about 500 angstroms to about 15000 angstroms is formed on the surface of the insulating film 71 by a CVD method using TEOS under a temperature condition of about 400 ° C., for example. These insulating films 71 and 72 form a second interlayer insulating film 7.
[0062]
Next, a resist mask RM4 for forming contact holes and openings is formed in the second interlayer insulating film 7 by using a photolithography technique.
[0063]
Next, as shown in FIG. 8B, with respect to the insulating films 71 and 72 constituting the second interlayer insulating film 7, a third portion made of contact holes 71a and 72a is formed in a portion corresponding to the drain electrode 6d. Contact hole 8a is formed. At this time, in the film quality inspection region 80, the openings 71c and 72c are formed in the insulating films 71 and 72 constituting the second interlayer insulating film 7, and the opening 8c that exposes the film quality inspection semiconductor film 1c is formed. To do. Then, the resist mask RM4 is removed.
[0064]
Next, as shown in FIG. 8C, an ITO film 9 (Indium Tin Oxide) having a thickness of about 400 angstroms to about 2000 angstroms to form a drain electrode is formed on the surface side of the second interlayer insulating film 7. ) Is formed by sputtering or the like.
[0065]
Next, a resist mask RM5 for patterning the ITO film 9 is formed by using a photolithography technique.
[0066]
Then, the ITO film 9 is patterned using the resist mask RM5. As a result, as shown in FIGS. 5A and 5B, a pixel electrode 9a that is electrically connected to the drain electrode 6d through the third contact hole 8a is formed in the pixel TFT portion. In the film quality inspection region 80, the ITO film 9 is completely removed, and the film quality inspection semiconductor film 6c is exposed from the opening 8c.
[0067]
Therefore, thereafter, the film quality inspection of the film quality inspection semiconductor film 1c can be immediately performed through the opening 8c. Moreover, since the film quality inspection semiconductor film 1c follows a history substantially the same as that of the high concentration source region 1d and the high concentration drain region 1e of the TFT 50, even when the film quality inspection semiconductor film 1h is an inspection target, The film quality of the high concentration source region 1d and the high concentration drain region 1e of the TFT 50 can be inspected with high accuracy. Furthermore, since the film quality inspection region 80 can be formed using the process of manufacturing the TFT 50 as it is, the number of processes does not increase.
[0068]
[Embodiment 2]
In the first embodiment, a low concentration impurity is introduced into the film quality inspection semiconductor film 1c in the step shown in FIG. 6F, and then a high concentration is added to the film quality inspection semiconductor film 1c in the step shown in FIG. By introducing this impurity, the semiconductor film 1c for film quality inspection was made a region in which the same impurity as the high concentration source region 1d and the high concentration drain region 1e was introduced at the same concentration.
[0069]
In this embodiment, after introducing low concentration impurities into the film quality inspection semiconductor film 1c in the step shown in FIG. 6F, in the step shown in FIG. 7A, as shown in FIG. If 80 is also covered with the resist mask RM1, the film quality inspection semiconductor film 1c can be a region into which the same impurity as the low concentration source region 1f and the low concentration drain region 1g is introduced at the same concentration. Accordingly, if the semiconductor film 1c for film quality inspection is analyzed in the inspection region 80, the film quality inspection can be performed on the low concentration source region 1f and the low concentration drain region 1g of the TFT 50. In addition, since the film quality inspection semiconductor film 1c follows substantially the same history as that of the low concentration source region 1f and the low concentration drain region 1g of the TFT 50, even when the film quality inspection semiconductor film 1c is an inspection target, The film quality of the low concentration source region 1f and the low concentration drain region of the TFT 50 can be inspected with high accuracy. Furthermore, in this case as well, the film quality inspection region 80 can be formed using the process of manufacturing the TFT 50 as it is, so that the number of processes does not increase.
[0070]
[Embodiment 3]
In the first embodiment, after introducing low concentration impurities into the film quality inspection semiconductor film 1c in the step shown in FIG. 6F, the entire film quality inspection semiconductor film 1c is formed in the step shown in FIG. By introducing high-concentration impurities, the entire semiconductor film 1c for film quality inspection is made a region into which the same impurities as the high-concentration source region 1d and the high-concentration drain region 1e are introduced at the same concentration. After introducing low concentration impurities into the film quality inspection semiconductor film 1c in the step shown in FIG. 7A, in the step shown in FIG. 7A, only a part of the film quality inspection region 80 is resisted as shown in FIG. If covered with the mask RM1, as shown in FIG. 10B, the same impurity as the low concentration source region 1f and the low concentration drain region 1g is introduced into the film quality inspection semiconductor film 1c at the same concentration. 1 Film quality inspection semiconductor film 1c Thus, the second semiconductor film 1c ″ for film quality inspection into which the same impurity as that of the high concentration source region 1d and the high concentration drain region 1e is introduced at the same concentration can be formed. When the first film quality inspection semiconductor film 1c ′ and the second film quality inspection semiconductor film 1c ″ are analyzed, the film quality inspection for the high concentration source region 1d and the high concentration drain region 1e of the TFT 50 and the low concentration source region 1f are performed. In addition, the film quality inspection for the low concentration drain region 1g can be performed. In addition, the film quality inspection semiconductor film 1c (the first film quality inspection semiconductor film 1c ′ and the second film quality inspection semiconductor film 1c ″) are respectively a low concentration source / drain region and a high concentration source / drain region of the TFT 50. The film quality of the source / drain region of the TFT 50 can be inspected with higher accuracy even when the film quality inspection semiconductor film 1c is the inspection object. Since the film quality inspection region 80 can be formed using the process of manufacturing the TFT 50 as it is, the number of processes does not increase.
[0071]
[Embodiment 4]
In the first to third embodiments, impurities are introduced into the film quality inspection semiconductor film 1c so that the film quality inspection semiconductor film 1c is used for the inspection of the source / drain regions of the TFT 50. FIG. In both of the steps shown in FIG. 7A and the step shown in FIG. 7A, as shown in FIG. 9, if the film quality inspection region 80 is covered with the resist mask RM1, as shown in FIG. 1c is an intrinsic region into which no impurity is introduced. Therefore, if the film quality inspection semiconductor film 1c is analyzed in the inspection region 80, the film quality inspection for the channel region 1a of the TFT 50 can be performed. Also in this case, since the film quality inspection region 80 can be formed using the process of manufacturing the TFT 50 as it is, the number of processes does not increase.
[0072]
When manufacturing the TFT 50, an extremely low concentration impurity may be channel-doped in the steps shown in FIGS. 6A to 6C. In this case, the film quality inspection semiconductor film 1c is formed as a region where the same impurity as the channel region 1c is channel-doped at the same concentration.
[0073]
[Embodiment 5]
In any of the above-described first to fourth embodiments, the film quality inspection region 80 is formed in one place for one active matrix substrate 200. However, as shown in FIG. The film quality inspection regions 80 ′ and 80 ″ may be formed as described above. In this case, the same impurity is introduced at the same concentration into each of the film quality inspection semiconductor films 1c in the film quality inspection regions 80 ′ and 80 ″. However, for example, of the plurality of film quality inspection regions 1c, the film quality inspection semiconductor film 1c in a certain film quality inspection region 80 ′ is used for film quality inspection of the channel region 1a of the TFT 50 without introducing impurities. Impurities may be introduced into the film quality inspection semiconductor film 1c in the other film quality inspection region 80 ″ to be used for film quality inspection of the source / drain regions of the TFT 50.
[0074]
[Other embodiments]
In the above embodiment, the present invention is applied to the active matrix substrate used for assembling the electro-optical device. However, when manufacturing the active matrix substrate, the present invention is applied to a test substrate for confirming the process conditions through the test. May be applied.
[0075]
Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention can be applied not only to the above-described various liquid crystal display devices but also to electroluminescence and plasm display devices. Furthermore, the present invention can be applied to the case where an SOI (Silicon On Insulator) substrate or an SOS (Silicon On Sapphire) substrate is used.
[0076]
【The invention's effect】
As described above, in the present invention, since the film quality inspection region including the semiconductor film for film quality inspection of the same layer as the semiconductor film used for the transistor is formed, if this film quality inspection region is analyzed, Film quality inspection such as elemental analysis and crystallinity analysis on the semiconductor film constituting the drain region and the channel region can be performed. Here, since the film quality inspection region is exposed from the opening of the inspection region side interlayer insulating film in the same layer as the interlayer insulating film, the inspection can be started immediately, unlike the case of inspecting on the transistor side, There is no need to remove the interlayer insulating film and the gate electrode. Therefore, the film quality inspection can be performed quickly and easily. Further, even if it is formed large in the film quality inspection region, it does not affect the transistor characteristics of the transistor. Therefore, various analyzes can be performed with high accuracy by forming a large film quality inspection region.
[Brief description of the drawings]
FIG. 1 is a plan view of an electro-optical device according to a first embodiment of the present invention as viewed from a counter substrate side.
2 is a cross-sectional view of the electro-optical device when cut along the line HH ′ of FIG. 1;
3 is a block diagram of an active matrix substrate used in the electro-optical device shown in FIG.
4 is an equivalent circuit diagram of a pixel on the active matrix substrate shown in FIG. 3. FIG.
5A and 5B are cross-sectional views taken along the line CC ′ of the pixel TFT portion formed on the active matrix substrate of the electro-optical device shown in FIG. 1 and the film quality inspection region of FIG. It is sectional drawing which expands and shows some of them.
6 is a process cross-sectional view illustrating the manufacturing method of the active matrix substrate shown in FIG. 3; FIG.
7 is a process cross-sectional view of each process performed following the process shown in FIG. 6; FIG.
FIG. 8 is a process cross-sectional view of each process performed following the process shown in FIG. 7;
FIG. 9 is a cross-sectional view of a high-concentration impurity process when forming a film quality inspection region for inspecting a low-concentration source / drain region of a TFT on an active matrix substrate according to Embodiment 2 of the present invention.
FIGS. 10A and 10B are diagrams for testing both a low concentration source / drain region and a high concentration source / drain region of a TFT with respect to the active matrix substrate according to the third embodiment of the present invention. FIG. 6 is a cross-sectional view of a high-concentration impurity process when forming a film quality inspection region, and a cross-sectional view of a film quality inspection region formed using this process.
FIG. 11 is a cross-sectional view showing a configuration of a film quality inspection region with respect to a channel region of a TFT in an active matrix substrate according to Embodiment 4 of the present invention.
FIG. 12 is a cross-sectional view showing a configuration of film quality inspection regions formed at a plurality of locations on an active matrix substrate according to Embodiment 5 of the present invention.
[Explanation of symbols]
1a channel region
1c, 1c ′, 1c ″ Semiconductor film for film quality inspection
2 Gate insulation film
2c Inspection region side gate insulating film
3a Gate electrode
4 First interlayer insulating film
4a First contact hole
4d second contact hole
5b, 8b Cutting hole
6d drain electrode
7 Second interlayer insulating film
8a Third contact hole
8c opening
9a Pixel electrode
11 Image display area
20 scan lines
30 data lines
50 TFT
60 Data line drive circuit
70 Scanning line drive circuit
71 Insulating film using polysilazane
72 Insulating film formed by CVD method
72, 73 Signal wiring
80, 80 ', 80 "film quality inspection area
200 Active matrix substrate
200 Counter substrate
300 Electro-optical device

Claims (14)

In an active matrix substrate in which transistors and signal wirings are formed on a substrate,
A film quality inspection semiconductor film in the same layer as the semiconductor film used in the transistor is provided in at least one of the regions on the substrate where the transistor and the signal wiring are not formed, and the film quality inspection semiconductor film An active matrix comprising a film quality inspection region in which the film quality inspection semiconductor film is exposed through an opening provided in an inspection region side interlayer insulating film in the same layer as the interlayer insulating film formed on the upper layer substrate.   2. The active layer according to claim 1, wherein the semiconductor film for film quality inspection is in the same layer as the source / drain region of the transistor, and the same impurity as the source / drain region is introduced at the same concentration. Matrix substrate. 2. The source / drain region of the transistor according to claim 1, comprising a low concentration source / drain region and a high concentration source / drain region.
The semiconductor film for film quality inspection is in the same layer as one of the low-concentration source / drain region and the high-concentration source / drain region, and the same impurity as the source / drain region has the same concentration. An active matrix substrate characterized by being introduced in (1). 2. The source / drain region of the transistor according to claim 1, comprising a low concentration source / drain region and a high concentration source / drain region.
The semiconductor film for film quality inspection is the same layer as the low concentration source / drain region, and the first film quality inspection semiconductor film into which the same impurity as the low concentration source / drain region is introduced at the same concentration ,
A second film quality inspection semiconductor film having the same layer as the high-concentration source / drain region and the same impurity as the high-concentration source / drain region is introduced at the same concentration. Active matrix substrate.   5. The active matrix substrate according to claim 1, wherein the film quality inspection region where the film quality inspection semiconductor film is formed has a larger area than a source / drain region of the transistor.   2. The semiconductor film for film quality inspection according to claim 1, wherein the semiconductor film for film quality inspection is in the same layer as the channel region of the transistor and is the same intrinsic semiconductor film as the channel region or a low concentration region in which the same impurity is channel-doped at the same concentration. An active matrix substrate characterized by the above.   8. The active matrix substrate according to claim 7, wherein the film quality inspection region has a larger area than a channel region of the transistor. The active matrix substrate according to claim 1, wherein the film quality inspection region has an area of 1 mm ² or more. 9. The transistor according to claim 1, wherein the transistor is a thin film transistor, and a thin film transistor for pixel switching connected to a scanning line and a data line and a pixel electrode connected to the thin film transistor are formed in a matrix on the substrate. A pixel portion, a scanning line driving circuit and a data line driving circuit for outputting a signal to the scanning line and the data line, and a plurality of the signal wirings for supplying a signal to the driving circuit are formed,
The film quality inspection region is formed in at least one of the regions on the substrate where the pixel portion, the scanning line driving circuit, the data line driving circuit, and the signal wiring are not formed. Active matrix substrate.   An electro-optical device, wherein an electro-optical material is sandwiched between an active matrix substrate defined in claim 9 and a counter substrate. 3. A method of manufacturing an active matrix substrate as defined in claim 2, wherein a semiconductor film and a gate insulating film used for the transistor are formed in this order, and at the same time, the film quality inspection semiconductor film and the inspection area with respect to the area to be the film quality inspection area. Forming a side gate insulating film in this order;
Forming a conductive film for forming a gate electrode of the transistor, then patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side;
Impurities are selectively introduced into the semiconductor film through the gate insulating film to form source / drain regions of the transistor, and at the same time, impurities are introduced into the film quality inspection semiconductor film through the inspection region side gate insulating film. Introducing the process;
Forming the interlayer insulating film on the surface side of the gate electrode and simultaneously forming the inspection region side interlayer insulating film on the surface side of the inspection region side gate insulating film on the inspection region side;
At the same time as forming a contact hole for the transistor in the interlayer insulating film, the opening is formed in the inspection region side interlayer insulating film and the inspection region side gate insulating film in the film quality inspection region to expose the semiconductor film for film quality inspection The process of
And a method for manufacturing an active matrix substrate. 4. A method of manufacturing an active matrix substrate as defined in claim 3, wherein a semiconductor film and a gate insulating film used for the transistor are formed in this order, and at the same time, the film quality inspection semiconductor film and the inspection region with respect to the region to be the film quality inspection region. Forming a side gate insulating film in this order;
Forming a conductive film for forming a gate electrode of the transistor, then patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side;
The low-concentration source / drain region and the high-concentration source / drain region of the transistor are formed simultaneously by selectively introducing high-concentration impurities and low-concentration impurities into the semiconductor film through the gate insulating film. Introducing one of the low-concentration impurity and the high-concentration impurity into the semiconductor film for film quality inspection via the inspection region-side gate insulating film;
Forming the interlayer insulating film on the surface side of the gate electrode and simultaneously forming the inspection region side interlayer insulating film on the surface side of the inspection region side gate insulating film on the inspection region side;
At the same time as forming a contact hole for the transistor in the interlayer insulating film, the opening is formed in the inspection region side interlayer insulating film and the inspection region side gate insulating film in the film quality inspection region to expose the semiconductor film for film quality inspection The process of
And a method for manufacturing an active matrix substrate. 5. A method of manufacturing an active matrix substrate as defined in claim 4, wherein a semiconductor film and a gate insulating film used for the transistor are formed in this order and at the same time the film quality inspection semiconductor film and the inspection region with respect to the region to be the film quality inspection region. Forming a side gate insulating film in this order;
Forming a conductive film for forming a gate electrode of the transistor, then patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side;
The low-concentration source / drain region and the high-concentration source / drain region of the transistor are formed simultaneously by selectively introducing high-concentration impurities and low-concentration impurities into the semiconductor film through the gate insulating film. The first film quality inspection semiconductor film and the second film quality are obtained by selectively introducing the low concentration impurity and the high concentration impurity into the film quality inspection semiconductor film via the inspection region side gate insulating film. Forming a semiconductor film for inspection;
Forming the interlayer insulating film on the surface side of the gate electrode and simultaneously forming the inspection region side interlayer insulating film on the surface side of the inspection region side gate insulating film on the inspection region side;
At the same time as forming a contact hole for the transistor in the interlayer insulating film, the opening is formed in the inspection region side interlayer insulating film and the inspection region side gate insulating film in the film quality inspection region to expose the semiconductor film for film quality inspection The process of
And a method for manufacturing an active matrix substrate. 8. A method of manufacturing an active matrix substrate as defined in claim 7, wherein a semiconductor film and a gate insulating film used for the transistor are formed in this order, and at the same time, the film quality inspection semiconductor film and the inspection region with respect to the region to be the film quality inspection region. Forming a side gate insulating film in this order;
Forming a conductive film for forming a gate electrode of the transistor, then patterning the conductive film to form the gate electrode, and simultaneously removing the conductive film from the film quality inspection region side;
Forming a source / drain region of the transistor by selectively introducing impurities into the semiconductor film through the gate insulating film in a state in which the semiconductor film for film quality inspection is covered with a mask;
Forming the interlayer insulating film on the surface side of the gate electrode and simultaneously forming the inspection region side interlayer insulating film on the surface side of the inspection region side gate insulating film on the inspection region side;
At the same time as forming a contact hole for the transistor in the interlayer insulating film, the opening is formed in the inspection region side interlayer insulating film and the inspection region side gate insulating film in the film quality inspection region to expose the semiconductor film for film quality inspection The process of
And a method for manufacturing an active matrix substrate.

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